1436 lines
52 KiB
C
1436 lines
52 KiB
C
/**
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* @file sdrv_etimer_lld.c
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* @brief Semidrive ETIMER driver source file.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#include <types.h>
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#include "common.h"
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#include "reg.h"
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#include "sdrv_etimer.h"
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/**
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* @brief sdrv etimer read reg.
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*
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* @param[in] base reg base
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* @param[in] offset reg offset
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* @return return reg val
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*/
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static inline uint32_t sdrv_etimer_lld_readl(uint32_t base, uint32_t offset)
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{
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return readl(base + offset);
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}
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/**
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* @brief sdrv etimer write reg.
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*
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* @param[in] base reg base
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* @param[in] offset reg offset
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* @param[in] val reg val
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*/
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static inline void sdrv_etimer_lld_writel(uint32_t base, uint32_t offset,
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uint32_t val)
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{
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writel(val, (base + offset));
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}
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void sdrv_etimer_lld_clk_cfg(uint32_t base, clk_set_t *cfg)
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{
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uint32_t clk_set = 0;
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clk_set = ETMR_FV_TIM_CLK_CONFIG_DIV_NUM(cfg->div_num);
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clk_set |= ETMR_FV_TIM_CLK_CONFIG_SRC_CLK_SEL(cfg->src_clk_sel);
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clk_set |= ETMR_BM_TIM_CLK_CONFIG_CLK_CHANGE_UPD;
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sdrv_etimer_lld_writel(base, ETMR_TIM_CLK_CONFIG_OFF, clk_set);
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while (sdrv_etimer_lld_readl(base, ETMR_TIM_CLK_CONFIG_OFF) &
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ETMR_BM_TIM_CLK_CONFIG_CLK_CHANGE_UPD)
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;
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}
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void sdrv_etimer_lld_clk_mon_en(uint32_t base, bool enable)
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{
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uint32_t clk_mon;
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clk_mon = ETMR_BM_CLK_MON_EN_CMP_SET;
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enable ? (clk_mon |= ETMR_BM_CLK_MON_EN_EN_P)
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: (clk_mon |= ETMR_BM_CLK_MON_EN_EN_N);
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sdrv_etimer_lld_writel(base, ETMR_CLK_MON_EN_OFF, clk_mon);
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}
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static void sdrv_etimer_lld_basic_cnt_upd(uint32_t base,
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sdrv_etimer_cnt_id_e cnt_x,
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bool init_flag, bool ovf_flag)
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{
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if (cnt_x > SDRV_ETIMR_CNT_G1) {
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return;
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}
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uint32_t cnt_cfg;
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cnt_cfg = sdrv_etimer_lld_readl(base, ETMR_CNT_CFG_OFF(cnt_x));
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if (init_flag) {
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cnt_cfg |= ETMR_BM_CNT_CFG_INIT_UPD;
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}
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if (ovf_flag) {
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cnt_cfg |= ETMR_BM_CNT_CFG_OVF_UPD;
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}
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sdrv_etimer_lld_writel(base, ETMR_CNT_CFG_OFF(cnt_x), cnt_cfg);
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}
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static void sdrv_etimer_lld_local_cnt_upd(uint32_t base,
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sdrv_etimer_cnt_id_e cnt_x,
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bool init_flag, bool ovf_flag)
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{
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if (cnt_x <= SDRV_ETIMR_CNT_G1) {
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return;
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}
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uint32_t lcnt_cfg;
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lcnt_cfg = sdrv_etimer_lld_readl(base, ETMR_CNT_CFG_OFF(cnt_x));
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if (init_flag) {
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lcnt_cfg |= ETMR_BM_LCNT_CFG_INIT_UPD;
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}
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if (ovf_flag) {
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lcnt_cfg |= ETMR_BM_LCNT_CFG_OVF_UPD;
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}
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sdrv_etimer_lld_writel(base, ETMR_CNT_CFG_OFF(cnt_x), lcnt_cfg);
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}
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void sdrv_etimer_lld_cnt_upd(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
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bool init_flag, bool ovf_flag)
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{
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switch (cnt_x) {
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case SDRV_ETIMR_CNT_G0:
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case SDRV_ETIMR_CNT_G1:
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sdrv_etimer_lld_basic_cnt_upd(base, cnt_x, init_flag, ovf_flag);
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break;
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case SDRV_ETIMR_LCNT_A:
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case SDRV_ETIMR_LCNT_B:
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case SDRV_ETIMR_LCNT_C:
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case SDRV_ETIMR_LCNT_D:
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sdrv_etimer_lld_local_cnt_upd(base, cnt_x, init_flag, ovf_flag);
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break;
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default:
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return;
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}
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uint32_t cnt_cfg = sdrv_etimer_lld_readl(base, ETMR_CNT_CFG_OFF(cnt_x));
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/* Wait until the update flag takes effect */
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while ((cnt_cfg & ETMR_BM_CNT_CFG_INIT_UPD) ||
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(cnt_cfg & ETMR_BM_CNT_CFG_OVF_UPD)) {
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cnt_cfg = sdrv_etimer_lld_readl(base, ETMR_CNT_CFG_OFF(cnt_x));
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}
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}
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void sdrv_etimer_lld_cnt_ovf(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
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uint32_t val)
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{
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sdrv_etimer_lld_writel(base, ETMR_CNT_OVF_OFF(cnt_x), val);
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sdrv_etimer_lld_cnt_upd(base, cnt_x, false, true);
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}
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void sdrv_etimer_lld_cnt_init(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
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uint32_t val)
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{
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sdrv_etimer_lld_writel(base, ETMR_CNT_INIT_OFF(cnt_x), val);
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sdrv_etimer_lld_cnt_upd(base, cnt_x, true, false);
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}
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void sdrv_etimer_lld_cnt_en(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
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bool enable)
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{
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sdrv_etimer_lld_writel(base, ETMR_CNT_EN_OFF(cnt_x), enable);
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}
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uint32_t sdrv_etimer_lld_get_cnt_value(uint32_t base,
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sdrv_etimer_cnt_id_e cnt_x)
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{
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uint32_t cnt_value = 0;
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cnt_value = sdrv_etimer_lld_readl(base, ETMR_CNT_OFF(cnt_x));
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return cnt_value;
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}
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uint32_t sdrv_etimer_lld_get_cpt0_cnt0(uint32_t base,
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sdrv_etimer_chn_id_e etimer_id)
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{
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uint32_t cpt0_cnt0_value = 0;
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cpt0_cnt0_value =
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sdrv_etimer_lld_readl(base, ETMR_CPT_CPT0_CNT0_OFF(etimer_id));
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return cpt0_cnt0_value;
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}
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uint32_t sdrv_etimer_lld_get_cpt0_cnt1(uint32_t base,
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sdrv_etimer_chn_id_e etimer_id)
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{
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uint32_t cpt0_cnt1_value = 0;
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cpt0_cnt1_value =
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sdrv_etimer_lld_readl(base, ETMR_CPT_CPT0_CNT1_OFF(etimer_id));
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return cpt0_cnt1_value;
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}
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uint32_t sdrv_etimer_lld_get_cpt1_cnt0(uint32_t base,
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sdrv_etimer_chn_id_e etimer_id)
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{
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uint32_t cpt1_cnt0_value = 0;
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cpt1_cnt0_value =
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sdrv_etimer_lld_readl(base, ETMR_CPT_CPT1_CNT0_OFF(etimer_id));
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return cpt1_cnt0_value;
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}
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uint32_t sdrv_etimer_lld_get_cpt1_cnt1(uint32_t base,
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sdrv_etimer_chn_id_e etimer_id)
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{
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uint32_t cpt1_cnt1_value = 0;
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cpt1_cnt1_value =
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sdrv_etimer_lld_readl(base, ETMR_CPT_CPT1_CNT1_OFF(etimer_id));
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return cpt1_cnt1_value;
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}
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void sdrv_etimer_lld_cnt_frc_rld(uint32_t base, sdrv_etimer_cnt_id_e cnt_x)
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{
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uint32_t cnt_cfg;
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cnt_cfg = sdrv_etimer_lld_readl(base, ETMR_CNT_CFG_OFF(cnt_x));
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cnt_cfg |= ETMR_BM_CNT_CFG_FRC_RLD;
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sdrv_etimer_lld_writel(base, ETMR_CNT_CFG_OFF(cnt_x), cnt_cfg);
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}
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void sdrv_etimer_lld_lcnt_sig_en(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
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bool enable)
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{
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if (cnt_x <= SDRV_ETIMR_CNT_G1) {
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return;
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}
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uint32_t lcnt_cfg;
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lcnt_cfg = sdrv_etimer_lld_readl(base, ETMR_CNT_CFG_OFF(cnt_x));
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enable ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_SIG_EN)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_SIG_EN);
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sdrv_etimer_lld_writel(base, ETMR_CNT_CFG_OFF(cnt_x), lcnt_cfg);
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}
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void sdrv_etimer_lld_basic_cnt_cfg(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
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basic_cnt_config_t *cfg)
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{
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if (cnt_x > SDRV_ETIMR_CNT_G1) {
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return;
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}
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uint32_t cnt_cfg = 0;
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(cfg->con_mode) ? (cnt_cfg |= ETMR_BM_CNT_CFG_CON_MODE)
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: (cnt_cfg &= ~ETMR_BM_CNT_CFG_CON_MODE);
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(cfg->ovf_rst_dis) ? (cnt_cfg |= ETMR_BM_CNT_CFG_OVF_RST_DIS)
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: (cnt_cfg &= ~ETMR_BM_CNT_CFG_OVF_RST_DIS);
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(cfg->ce_en) ? (cnt_cfg |= ETMR_BM_CNT_CFG_CE_EN)
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: (cnt_cfg &= ~ETMR_BM_CNT_CFG_CE_EN);
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cnt_cfg |= ETMR_FV_CNT_CFG_INTERVAL(cfg->interval);
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cnt_cfg |= ETMR_FV_CNT_CFG_CLR_TRIG_SEL(cfg->clr_trig_sel);
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cnt_cfg |= ETMR_FV_CNT_CFG_SET_TRIG_SEL(cfg->set_trig_sel);
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cnt_cfg |= ETMR_FV_CNT_CFG_SET_UPD_SEL(cfg->set_upd_sel);
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if ((cnt_x == SDRV_ETIMR_CNT_G0) && (cfg->cascade_mode)) {
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cnt_cfg |= ETMR_BM_CNT_G0_CFG_CASCADE_MODE;
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}
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(cfg->frc_rld) ? (cnt_cfg |= ETMR_BM_CNT_CFG_FRC_RLD)
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: (cnt_cfg &= ~ETMR_BM_CNT_CFG_FRC_RLD);
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sdrv_etimer_lld_writel(base, ETMR_CNT_CFG_OFF(cnt_x), cnt_cfg);
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}
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void sdrv_etimer_lld_local_cnt_cfg(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
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local_cnt_config_t *cfg)
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{
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if (cnt_x <= SDRV_ETIMR_CNT_G1) {
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return;
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}
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uint32_t lcnt_cfg = 0;
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(cfg->con_mode) ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_CON_MODE)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_CON_MODE);
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(cfg->no_stop_ovf_mode) ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_NO_STOP_OVF_MODE)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_NO_STOP_OVF_MODE);
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lcnt_cfg |= ETMR_FV_LCNT_CFG_SET_TRIG_SEL(cfg->set_trig_sel);
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lcnt_cfg |= ETMR_FV_LCNT_CFG_SET_UPD_SEL(cfg->set_upd_sel);
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lcnt_cfg |= ETMR_FV_LCNT_CFG_CLR_TRIG_SEL(cfg->clr_trig_sel);
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lcnt_cfg |= ETMR_FV_LCNT_CFG_INTERVAL(cfg->interval);
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lcnt_cfg |= ETMR_FV_LCNT_CFG_SIG_TRIG_SEL(cfg->sig_trig_sel);
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(cfg->ce_en) ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_CE_EN)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_CE_EN);
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(cfg->cpt0_clr_en) ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_CPT0_CLR_EN)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_CPT0_CLR_EN);
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(cfg->cpt1_clr_en) ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_CPT1_CLR_EN)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_CPT1_CLR_EN);
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(cfg->start_by_first_cpt)
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? (lcnt_cfg |= ETMR_BM_LCNT_CFG_START_BY_FIRST_CPT)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_START_BY_FIRST_CPT);
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(cfg->sig_en) ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_SIG_EN)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_SIG_EN);
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(cfg->delta_time_en) ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_DELTA_TIME_EN)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_DELTA_TIME_EN);
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(cfg->ovf_rst_dis) ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_OVF_RST_DIS)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_OVF_RST_DIS);
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(cfg->frc_rld) ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_FRC_RLD)
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: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_FRC_RLD);
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sdrv_etimer_lld_writel(base, ETMR_CNT_CFG_OFF(cnt_x), lcnt_cfg);
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}
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void sdrv_etimer_lld_int_en(uint32_t base, uint32_t bit_mask, bool enable)
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{
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uint32_t val_sta = sdrv_etimer_lld_readl(base, ETMR_INT_STA_EN_OFF);
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uint32_t val_sig = sdrv_etimer_lld_readl(base, ETMR_INT_SIG_EN_OFF);
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val_sta = enable ? (val_sta | bit_mask) : (val_sta & (~bit_mask));
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val_sig = enable ? (val_sig | bit_mask) : (val_sig & (~bit_mask));
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sdrv_etimer_lld_writel(base, ETMR_INT_STA_EN_OFF, val_sta);
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sdrv_etimer_lld_writel(base, ETMR_INT_SIG_EN_OFF, val_sig);
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}
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void sdrv_etimer_lld_int_enable(uint32_t base, uint32_t int_sel)
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{
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sdrv_etimer_lld_writel(base, ETMR_INT_STA_EN_OFF, int_sel);
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sdrv_etimer_lld_writel(base, ETMR_INT_SIG_EN_OFF, int_sel);
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}
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void sdrv_etimer_lld_cor_int_enable(uint32_t base, uint32_t int_sel)
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{
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sdrv_etimer_lld_writel(base, ETMR_COR_ERR_INT_STA_EN_OFF, int_sel);
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sdrv_etimer_lld_writel(base, ETMR_COR_ERR_INT_SIG_EN_OFF, int_sel);
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}
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void sdrv_etimer_lld_unc_int_enable(uint32_t base, uint32_t int_sel)
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{
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sdrv_etimer_lld_writel(base, ETMR_UNC_ERR_INT_STA_EN_OFF, int_sel);
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sdrv_etimer_lld_writel(base, ETMR_UNC_ERR_INT_SIG_EN_OFF, int_sel);
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}
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uint32_t sdrv_etimer_lld_get_int_status(uint32_t base)
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{
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uint32_t int_sta = sdrv_etimer_lld_readl(base, ETMR_INT_STA_OFF);
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return int_sta;
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}
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void sdrv_etimer_lld_clear_int_status(uint32_t base, uint32_t int_sta)
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{
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sdrv_etimer_lld_writel(base, ETMR_INT_STA_OFF, int_sta);
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}
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uint32_t sdrv_etimer_lld_get_cor_int_status(uint32_t base)
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{
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uint32_t int_sta = sdrv_etimer_lld_readl(base, ETMR_COR_ERR_INT_STA_OFF);
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return int_sta;
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}
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void sdrv_etimer_lld_clear_cor_int_status(uint32_t base, uint32_t int_sta)
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{
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sdrv_etimer_lld_writel(base, ETMR_COR_ERR_INT_STA_OFF, int_sta);
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}
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uint32_t sdrv_etimer_lld_get_unc_int_status(uint32_t base)
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{
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uint32_t int_sta = sdrv_etimer_lld_readl(base, ETMR_UNC_ERR_INT_STA_OFF);
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return int_sta;
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}
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void sdrv_etimer_lld_clear_unc_int_status(uint32_t base, uint32_t int_sta)
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{
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sdrv_etimer_lld_writel(base, ETMR_UNC_ERR_INT_STA_OFF, int_sta);
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}
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uint32_t sdrv_etimer_lld_get_fusa_cor_int_status(uint32_t base)
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{
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uint32_t int_sta =
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sdrv_etimer_lld_readl(base, ETMR_FUSA_COR_ERR_INT_STA_OFF);
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return int_sta;
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}
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void sdrv_etimer_lld_clear_fusa_cor_int_status(uint32_t base, uint32_t int_sta)
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{
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sdrv_etimer_lld_writel(base, ETMR_FUSA_COR_ERR_INT_STA_OFF, int_sta);
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}
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uint32_t sdrv_etimer_lld_get_fusa_unc_int_status(uint32_t base)
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{
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uint32_t int_sta =
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sdrv_etimer_lld_readl(base, ETMR_FUSA_UNC_ERR_INT_STA_OFF);
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return int_sta;
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}
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void sdrv_etimer_lld_clear_fusa_unc_int_status(uint32_t base, uint32_t int_sta)
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{
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sdrv_etimer_lld_writel(base, ETMR_FUSA_UNC_ERR_INT_STA_OFF, int_sta);
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}
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void sdrv_etimer_lld_dma_chn_cfg(uint32_t base, sdrv_etimer_chn_id_e ch,
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chn_etimer_dma_ctrl_t *config)
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{
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uint32_t dma_chn_ctrl = sdrv_etimer_lld_readl(base, ETMR_CHN_DMA_CTRL_OFF);
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dma_chn_ctrl &= ~ETMR_FM_CHN_DMA_CTRL_CHN_SEL(ch);
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dma_chn_ctrl |= ETMR_FV_CHN_DMA_CTRL_CHN_SEL(config->block_sel, ch);
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(config->chn_sig_mask)
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? (dma_chn_ctrl |= ETMR_BM_CHN_DMA_CTRL_CHN_SIG_MASK(ch))
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: (dma_chn_ctrl &= ~ETMR_BM_CHN_DMA_CTRL_CHN_SIG_MASK(ch));
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(config->bit_mode)
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? (dma_chn_ctrl |= ETMR_BM_CHN_DMA_CTRL_CHN_16BIT_MODE(ch))
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: (dma_chn_ctrl &= ~ETMR_BM_CHN_DMA_CTRL_CHN_16BIT_MODE(ch));
|
|
|
|
if (config->chn_en) {
|
|
dma_chn_ctrl |= ETMR_BM_CHN_DMA_CTRL_CHN_EN(ch);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CHN_DMA_CTRL_OFF, dma_chn_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_dma_wml(uint32_t base, sdrv_etimer_chn_id_e chn,
|
|
uint32_t value)
|
|
{
|
|
uint32_t dma_wml_chn = sdrv_etimer_lld_readl(base, ETMR_DMA_WML_OFF);
|
|
dma_wml_chn &= ~ETMR_FM_DMA_WML_CHN(chn);
|
|
dma_wml_chn |= ETMR_FV_DMA_WML_CHN(value, chn);
|
|
sdrv_etimer_lld_writel(base, ETMR_DMA_WML_OFF, dma_wml_chn);
|
|
}
|
|
|
|
void sdrv_etimer_lld_config_dma_ctrl(uint32_t base, uint32_t trig_sel)
|
|
{
|
|
uint32_t dma_ctl = 0;
|
|
dma_ctl |= ETMR_FV_CONFIG_DMA_CTL_TRIG_SEL(trig_sel);
|
|
dma_ctl |= ETMR_BM_CONFIG_DMA_CTL_EN;
|
|
sdrv_etimer_lld_writel(base, ETMR_CONFIG_DMA_CTL_OFF, dma_ctl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_out_mode(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
etimer_cmp_event_mode_t *mode)
|
|
{
|
|
uint32_t cmp_mode = 0;
|
|
cmp_mode |= ETMR_FV_CMP_EVENT_OUT_MODE_CMP00(mode->cmp_00_out);
|
|
cmp_mode |= ETMR_FV_CMP_EVENT_OUT_MODE_CMP01(mode->cmp_01_out);
|
|
cmp_mode |= ETMR_FV_CMP_EVENT_OUT_MODE_CMP10(mode->cmp_10_out);
|
|
cmp_mode |= ETMR_FV_CMP_EVENT_OUT_MODE_CMP11(mode->cmp_11_out);
|
|
cmp_mode |= ETMR_FV_CMP_EVENT_OUT_MODE_CMP0_OVF(mode->cmp_0_ovf_out);
|
|
cmp_mode |= ETMR_FV_CMP_EVENT_OUT_MODE_CMP1_OVF(mode->cmp_1_ovf_out);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_EVENT_OUT_MODE_OFF(etimer_id),
|
|
cmp_mode);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_val(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_cmp_event_e group, uint32_t val)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_VAL_OFF(etimer_id, group), val);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_pulse_wid0_set(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
etimer_cmp_pulse_wid0_t *wid0)
|
|
{
|
|
uint32_t cmp_pulse_wid0 = 0;
|
|
cmp_pulse_wid0 |= ETMR_FV_CMP_PULSE_WID0_CMP00(wid0->cmp_00_pluse);
|
|
cmp_pulse_wid0 |= ETMR_FV_CMP_PULSE_WID0_CMP01(wid0->cmp_01_pluse);
|
|
cmp_pulse_wid0 |= ETMR_FV_CMP_PULSE_WID0_CMP10(wid0->cmp_10_pluse);
|
|
cmp_pulse_wid0 |= ETMR_FV_CMP_PULSE_WID0_CMP11(wid0->cmp_11_pluse);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_PULSE_WID0_OFF(etimer_id),
|
|
cmp_pulse_wid0);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_pulse_wid1_set(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
etimer_cmp_pulse_wid1_t *wid1)
|
|
{
|
|
uint32_t cmp_pulse_wid1 = 0;
|
|
cmp_pulse_wid1 |= ETMR_FV_CMP_PULSE_WID1_CMP1_OVF(wid1->cmp_1_ovf_pluse);
|
|
cmp_pulse_wid1 |= ETMR_FV_CMP_PULSE_WID1_CMP0_OVF(wid1->cmp_0_ovf_pluse);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_PULSE_WID1_OFF(etimer_id),
|
|
cmp_pulse_wid1);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_val_upd(uint32_t base, sdrv_etimer_chn_id_e etimer_id)
|
|
{
|
|
uint32_t cmp_upd = sdrv_etimer_lld_readl(base, ETMR_CMP_CTRL_OFF);
|
|
cmp_upd |= ETMR_BM_CMP_CTRL_CMP_VAL_UPD(etimer_id);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CTRL_OFF, cmp_upd);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_init_status(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
etimer_cmp_init_status_t *init_sta)
|
|
{
|
|
uint32_t cmp_init_status = sdrv_etimer_lld_readl(base, ETMR_CMP_CTRL_OFF);
|
|
|
|
if (init_sta->init_status_x0) {
|
|
cmp_init_status |= ETMR_BM_CMP_CTRL_CMP_X0_INIT_STATUS(etimer_id);
|
|
}
|
|
else {
|
|
cmp_init_status &= ~ETMR_BM_CMP_CTRL_CMP_X0_INIT_STATUS(etimer_id);
|
|
}
|
|
|
|
if (init_sta->init_status_x1) {
|
|
cmp_init_status |= ETMR_BM_CMP_CTRL_CMP_X1_INIT_STATUS(etimer_id);
|
|
}
|
|
else {
|
|
cmp_init_status &= ~ETMR_BM_CMP_CTRL_CMP_X1_INIT_STATUS(etimer_id);
|
|
}
|
|
|
|
cmp_init_status |= ETMR_BM_CMP_CTRL_CMP_X0_INIT_UPD(etimer_id);
|
|
cmp_init_status |= ETMR_BM_CMP_CTRL_CMP_X1_INIT_UPD(etimer_id);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CTRL_OFF, cmp_init_status);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_cfg(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
cmp_config_t *cfg)
|
|
{
|
|
uint32_t cmp_cfg = 0;
|
|
|
|
if (cfg->ce_en) {
|
|
cmp_cfg |= ETMR_BM_CMP_CONFIG_CE_EN;
|
|
}
|
|
|
|
cmp_cfg |= ((ETMR_BM_CMP_CONFIG_OUT_MODE(cfg->out_mode)) |
|
|
(ETMR_BM_CMP_CONFIG_CON_MODE(cfg->con_mode)) |
|
|
(ETMR_FV_CMP_CONFIG_CMP_MODE(cfg->cmp_mode)));
|
|
cmp_cfg |= (ETMR_FV_CMP_CONFIG_CNT_SEL(cfg->cnt_sel) |
|
|
ETMR_FV_CMP_CONFIG_CE_TRIG_SEL(cfg->ce_trig_sel) |
|
|
ETMR_FV_CMP_CONFIG_SET_TRIG_SEL(cfg->set_trig_sel) |
|
|
ETMR_FV_CMP_CONFIG_CLR_TRIG_SEL(cfg->clr_trig_sel));
|
|
cmp_cfg |= (ETMR_BM_CMP_CONFIG_RLD_TRIG_MODE(cfg->rld_trig_mode) |
|
|
ETMR_BM_CMP_CONFIG_SW_RLD_MODE(cfg->sw_rld_mode));
|
|
cmp_cfg |= ETMR_FV_CMP_CONFIG_REFRESH_INTVAL(cfg->ref_interval);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CONFIG_OFF(etimer_id), cmp_cfg);
|
|
}
|
|
|
|
uint32_t sdrv_etimer_lld_get_cmp_mode(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id)
|
|
{
|
|
uint32_t cmp_cfg =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_CONFIG_OFF(etimer_id));
|
|
return ((cmp_cfg & ETMR_FM_CMP_CONFIG_CMP_MODE) >> 2);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_sw_rld(uint32_t base, sdrv_etimer_chn_id_e etimer_id)
|
|
{
|
|
uint32_t cmp_cfg =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_CONFIG_OFF(etimer_id));
|
|
cmp_cfg |= ETMR_BM_CMP_CONFIG_SW_RLD_SET;
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CONFIG_OFF(etimer_id), cmp_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_en(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t cmp_ctrl = sdrv_etimer_lld_readl(base, ETMR_CMP_CTRL_OFF);
|
|
enable ? (cmp_ctrl |= ETMR_BM_CMP_CTRL_CMP_EN(etimer_id))
|
|
: (cmp_ctrl &= ~ETMR_BM_CMP_CTRL_CMP_EN(etimer_id));
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CTRL_OFF, cmp_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_config_set(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id)
|
|
{
|
|
uint32_t cmp_ctrl = sdrv_etimer_lld_readl(base, ETMR_CMP_CTRL_OFF);
|
|
cmp_ctrl |= ETMR_BM_CMP_CTRL_CMP_CONFIG_SET(etimer_id);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CTRL_OFF, cmp_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_cfg(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
cpt_config_t *cfg)
|
|
{
|
|
uint32_t cpt_cfg = 0;
|
|
(cfg->ce_en) ? (cpt_cfg |= ETMR_BM_CPT_CONFIG_CE_EN)
|
|
: (cpt_cfg &= ~ETMR_BM_CPT_CONFIG_CE_EN);
|
|
(cfg->con_mode) ? (cpt_cfg |= ETMR_BM_CPT_CONFIG_CON_MODE)
|
|
: (cpt_cfg &= ~ETMR_BM_CPT_CONFIG_CON_MODE);
|
|
(cfg->dual_mode) ? (cpt_cfg |= ETMR_BM_CPT_CONFIG_DUAL_MODE)
|
|
: (cpt_cfg &= ~ETMR_BM_CPT_CONFIG_DUAL_MODE);
|
|
cpt_cfg |= (ETMR_FV_CPT_CONFIG_CPT0_TRIG_MODE(cfg->cpt0_trig_mode) |
|
|
ETMR_FV_CPT_CONFIG_CPT1_TRIG_MODE(cfg->cpt1_trig_mode));
|
|
cpt_cfg |= (ETMR_FV_CPT_CONFIG_CNT_SEL(cfg->cnt_sel) |
|
|
ETMR_FV_CPT_CONFIG_CE_TRIG_SEL(cfg->ce_trig_sel));
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_CONFIG_OFF(etimer_id), cpt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_config_set(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id)
|
|
{
|
|
uint32_t cpt_ctrl = sdrv_etimer_lld_readl(base, ETMR_CPT_CTRL_OFF);
|
|
cpt_ctrl |= ETMR_BM_CPT_CTRL_CPT_CONFIG_SET(etimer_id);
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_CTRL_OFF, cpt_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_en(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t cpt_ctrl = sdrv_etimer_lld_readl(base, ETMR_CPT_CTRL_OFF);
|
|
enable ? (cpt_ctrl |= ETMR_BM_CPT_CTRL_CPT_EN(etimer_id))
|
|
: (cpt_ctrl &= ~(ETMR_BM_CPT_CTRL_CPT_EN(etimer_id)));
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_CTRL_OFF, cpt_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_dti_ctrl_cfg(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_dti_ctrl_e ctrl_mode)
|
|
{
|
|
uint32_t dti_ctrl =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id));
|
|
|
|
switch (ctrl_mode) { // fill bit
|
|
case SDRV_ETIMR_CMP_0_NO_CHANGE:
|
|
dti_ctrl &= ~ETMR_BM_CMP_DTI_CTRL_CMP0_POL;
|
|
break;
|
|
|
|
case SDRV_ETIMR_CMP_0_INVERT:
|
|
dti_ctrl |= ETMR_BM_CMP_DTI_CTRL_CMP0_POL;
|
|
break;
|
|
|
|
case SDRV_ETIMR_CMP_1_NO_CHANGE:
|
|
dti_ctrl &= ~ETMR_BM_CMP_DTI_CTRL_CMP1_POL;
|
|
break;
|
|
|
|
case SDRV_ETIMR_CMP_1_INVERT:
|
|
dti_ctrl |= ETMR_BM_CMP_DTI_CTRL_CMP1_POL;
|
|
break;
|
|
|
|
case SDRV_ETIMR_CMP_1_SAME_0:
|
|
dti_ctrl |= ETMR_BM_CMP_DTI_CTRL_CMP1_SAME_CMP0;
|
|
dti_ctrl &= ~ETMR_BM_CMP_DTI_CTRL_CMP1_INV_CMP0;
|
|
break;
|
|
|
|
case SDRV_ETIMR_CMP_1_INVERT_0:
|
|
dti_ctrl &= ~ETMR_BM_CMP_DTI_CTRL_CMP1_SAME_CMP0;
|
|
dti_ctrl |= ETMR_BM_CMP_DTI_CTRL_CMP1_INV_CMP0;
|
|
break;
|
|
|
|
default:
|
|
return;
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id), dti_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_dti_wid(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
uint16_t wid0, uint16_t wid1)
|
|
{
|
|
uint32_t dti_wid =
|
|
(ETMR_FV_CMP_DTI_WID_DT0_WID(wid0)) | ETMR_FV_CMP_DTI_WID_DT1_WID(wid1);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_DTI_WID_OFF(etimer_id), dti_wid);
|
|
}
|
|
|
|
void sdrv_etimer_lld_dti_ctrl_en(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t dti_ctrl =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id));
|
|
enable ? (dti_ctrl |= ETMR_BM_CMP_DTI_CTRL_EN)
|
|
: (dti_ctrl &= ~ETMR_BM_CMP_DTI_CTRL_EN);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id), dti_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_fs_status_set(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_cmp_group_e group, bool enable)
|
|
{
|
|
uint32_t dti_ctrl =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id));
|
|
|
|
if (SDRV_ETIMR_CMP_OUT_0 == group) {
|
|
enable ? (dti_ctrl |= ETMR_BM_CMP_DTI_CTRL_CMP0_FS_STATUS)
|
|
: (dti_ctrl &= ~ETMR_BM_CMP_DTI_CTRL_CMP0_FS_STATUS);
|
|
}
|
|
else if (SDRV_ETIMR_CMP_OUT_1 == group) {
|
|
enable ? (dti_ctrl |= ETMR_BM_CMP_DTI_CTRL_CMP1_FS_STATUS)
|
|
: (dti_ctrl &= ~ETMR_BM_CMP_DTI_CTRL_CMP1_FS_STATUS);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id), dti_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_input_sel(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_trig_set_clr_e val)
|
|
{
|
|
uint32_t input_sel =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_INPUT_SEL_OFF(etimer_id));
|
|
|
|
if (SDRV_ETIMR_TRIG_SEL_SET == sel) {
|
|
input_sel &= ~ETMR_FM_CMP_INPUT_SEL_SET_SEL;
|
|
input_sel |= ETMR_FV_CMP_INPUT_SEL_SET_SEL(val);
|
|
}
|
|
else if (SDRV_ETIMR_TRIG_SEL_CLR == sel) {
|
|
input_sel &= ~ETMR_FM_CMP_INPUT_SEL_CLR_SEL;
|
|
input_sel |= ETMR_FV_CMP_INPUT_SEL_CLR_SEL(val);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_INPUT_SEL_OFF(etimer_id), input_sel);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_trig_cfg(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_cmp_event_trig_e val)
|
|
{
|
|
uint32_t cmp_cfg =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_CONFIG_OFF(etimer_id));
|
|
|
|
if (SDRV_ETIMR_TRIG_SEL_SET == sel) {
|
|
cmp_cfg &= ~ETMR_FM_CMP_CONFIG_SET_TRIG_SEL;
|
|
cmp_cfg |= ETMR_FV_CMP_CONFIG_SET_TRIG_SEL(val);
|
|
}
|
|
else if (SDRV_ETIMR_TRIG_SEL_CLR == sel) {
|
|
cmp_cfg &= ~ETMR_FM_CMP_CONFIG_CLR_TRIG_SEL;
|
|
cmp_cfg |= ETMR_FV_CMP_CONFIG_CLR_TRIG_SEL(val);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CONFIG_OFF(etimer_id), cmp_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_lcnt_trig_cfg(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_cmp_event_trig_e val)
|
|
{
|
|
uint32_t lcnt_cfg = sdrv_etimer_lld_readl(base, ETMR_CNT_CFG_OFF(cnt_x));
|
|
|
|
if (SDRV_ETIMR_TRIG_SEL_SET == sel) {
|
|
lcnt_cfg &= ~ETMR_FM_LCNT_CFG_SET_TRIG_SEL;
|
|
lcnt_cfg |= ETMR_FV_LCNT_CFG_SET_TRIG_SEL(val);
|
|
}
|
|
else if (SDRV_ETIMR_TRIG_SEL_CLR == sel) {
|
|
lcnt_cfg &= ~ETMR_FM_LCNT_CFG_CLR_TRIG_SEL;
|
|
lcnt_cfg |= ETMR_FV_LCNT_CFG_CLR_TRIG_SEL(val);
|
|
}
|
|
else if (SDRV_ETIMR_TRIG_SEL_SIG == sel) {
|
|
lcnt_cfg &= ~ETMR_FM_LCNT_CFG_SIG_TRIG_SEL;
|
|
lcnt_cfg |= ETMR_FV_LCNT_CFG_SIG_TRIG_SEL(val);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CNT_CFG_OFF(cnt_x), lcnt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_lcnt_ovf_rst_en(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
|
|
bool enable)
|
|
{
|
|
uint32_t lcnt_cfg = sdrv_etimer_lld_readl(base, ETMR_CNT_CFG_OFF(cnt_x));
|
|
enable ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_OVF_RST_DIS)
|
|
: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_OVF_RST_DIS);
|
|
sdrv_etimer_lld_writel(base, ETMR_CNT_CFG_OFF(cnt_x), lcnt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_lcnt_cpt_clr_en(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
|
|
sdrv_etimer_cpt_clr_e cpt_event,
|
|
bool enable)
|
|
{
|
|
uint32_t lcnt_cfg = sdrv_etimer_lld_readl(base, ETMR_CNT_CFG_OFF(cnt_x));
|
|
|
|
if (cpt_event == SDRV_ETIMR_LCNT_CPT_0_CLR) {
|
|
enable ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_CPT0_CLR_EN)
|
|
: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_CPT0_CLR_EN);
|
|
}
|
|
else {
|
|
enable ? (lcnt_cfg |= ETMR_BM_LCNT_CFG_CPT1_CLR_EN)
|
|
: (lcnt_cfg &= ~ETMR_BM_LCNT_CFG_CPT1_CLR_EN);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CNT_CFG_OFF(cnt_x), lcnt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cnt_input_sel(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_trig_set_clr_e val)
|
|
{
|
|
if (cnt_x > SDRV_ETIMR_CNT_G1) {
|
|
return;
|
|
}
|
|
|
|
uint32_t input_sel =
|
|
sdrv_etimer_lld_readl(base, ETMR_CNT_INPUT_SEL_OFF(cnt_x));
|
|
|
|
if (SDRV_ETIMR_TRIG_SEL_CLR == sel) {
|
|
input_sel &= ~ETMR_FM_CNT_INPUT_SEL_CLR_SEL;
|
|
input_sel |= ETMR_FV_CNT_INPUT_SEL_CLR_SEL(val);
|
|
}
|
|
else if (SDRV_ETIMR_TRIG_SEL_SET == sel) {
|
|
input_sel &= ~ETMR_FM_CNT_INPUT_SEL_SET_SEL;
|
|
input_sel |= ETMR_FV_CNT_INPUT_SEL_SET_SEL(val);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CNT_INPUT_SEL_OFF(cnt_x), input_sel);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_input_set_clr_sel(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_trig_set_clr_e val)
|
|
{
|
|
uint32_t cpt_input =
|
|
sdrv_etimer_lld_readl(base, ETMR_CPT_INPUT_SEL_OFF(etimer_id));
|
|
|
|
if (SDRV_ETIMR_TRIG_SEL_SET == sel) {
|
|
cpt_input &= ~ETMR_FM_CPT_INPUT_SEL_SET_SEL;
|
|
cpt_input |= ETMR_FV_CPT_INPUT_SEL_SET_SEL(val);
|
|
}
|
|
else if (SDRV_ETIMR_TRIG_SEL_CLR == sel) {
|
|
cpt_input &= ~ETMR_FM_CPT_INPUT_SEL_CLR_SEL;
|
|
cpt_input |= ETMR_FV_CPT_INPUT_SEL_CLR_SEL(val);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_INPUT_SEL_OFF(etimer_id), cpt_input);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_input_sig_sel(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_trig_sig_e val)
|
|
{
|
|
if (SDRV_ETIMR_TRIG_SEL_SIG != sel) {
|
|
return;
|
|
}
|
|
|
|
uint32_t cpt_input =
|
|
sdrv_etimer_lld_readl(base, ETMR_CPT_INPUT_SEL_OFF(etimer_id));
|
|
cpt_input &= ~ETMR_FM_CPT_INPUT_SEL_SIG_SEL;
|
|
cpt_input |= ETMR_FV_CPT_INPUT_SEL_SIG_SEL(val);
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_INPUT_SEL_OFF(etimer_id), cpt_input);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_input_dir_sel(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_trig_dir_e val)
|
|
{
|
|
if (SDRV_ETIMR_TRIG_SEL_DIR != sel) {
|
|
return;
|
|
}
|
|
|
|
uint32_t cpt_input =
|
|
sdrv_etimer_lld_readl(base, ETMR_CPT_INPUT_SEL_OFF(etimer_id));
|
|
cpt_input &= ~ETMR_FM_CPT_INPUT_SEL_DIR_SEL;
|
|
cpt_input |= ETMR_FV_CPT_INPUT_SEL_DIR_SEL(val);
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_INPUT_SEL_OFF(etimer_id), cpt_input);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_trig_cfg(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_cmp_event_trig_e val)
|
|
{
|
|
uint32_t cpt_cfg =
|
|
sdrv_etimer_lld_readl(base, ETMR_CPT_CONFIG_OFF(etimer_id));
|
|
|
|
if (SDRV_ETIMR_TRIG_SEL_SET == sel) {
|
|
cpt_cfg &= ~ETMR_FM_CMP_CONFIG_SET_TRIG_SEL;
|
|
cpt_cfg |= ETMR_FV_CMP_CONFIG_SET_TRIG_SEL(val);
|
|
}
|
|
else if (SDRV_ETIMR_TRIG_SEL_CLR == sel) {
|
|
cpt_cfg &= ~ETMR_FM_CMP_CONFIG_CLR_TRIG_SEL;
|
|
cpt_cfg |= ETMR_FV_CMP_CONFIG_CLR_TRIG_SEL(val);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_CONFIG_OFF(etimer_id), cpt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cnt_trig_gen(uint32_t base, uint32_t trigger)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_CNT_EXT_SW_TRIG_OFF, trigger);
|
|
}
|
|
|
|
void sdrv_etimer_lld_sw_trig_ctrl(uint32_t base,
|
|
sdrv_etimer_sw_trig_sel_e trig_sel,
|
|
sdrv_etimer_sw_trig_typr_e trig_type)
|
|
{
|
|
uint32_t sw_trig = sdrv_etimer_lld_readl(base, ETMR_SW_TRIG_CTRL_OFF);
|
|
sw_trig |= ETMR_BM_SW_TRIG_CTRL_SW_TRIG0_CTRL0(trig_sel, trig_type);
|
|
sdrv_etimer_lld_writel(base, ETMR_SW_TRIG_CTRL_OFF, sw_trig);
|
|
}
|
|
|
|
void sdrv_etimer_lld_sw_trig_pulse(uint32_t base,
|
|
sdrv_etimer_sw_trig_sel_e trig_sel,
|
|
uint32_t value)
|
|
{
|
|
uint32_t trig_pul0 = sdrv_etimer_lld_readl(base, ETMR_SW_TRIG_PULSE0_OFF);
|
|
uint32_t trig_pul1 = sdrv_etimer_lld_readl(base, ETMR_SW_TRIG_PULSE1_OFF);
|
|
|
|
switch (trig_sel) {
|
|
case SDRV_ETIMR_SW_TRIG0:
|
|
trig_pul0 &= ~ETMR_FM_SW_TRIG_PULSE0_TRIG0_WIDTH;
|
|
trig_pul0 |= ETMR_FV_SW_TRIG_PULSE0_TRIG0_WIDTH(value);
|
|
break;
|
|
|
|
case SDRV_ETIMR_SW_TRIG1:
|
|
trig_pul0 &= ~ETMR_FM_SW_TRIG_PULSE0_TRIG1_WIDTH;
|
|
trig_pul0 |= ETMR_FV_SW_TRIG_PULSE0_TRIG1_WIDTH(value);
|
|
break;
|
|
|
|
case SDRV_ETIMR_SW_TRIG2:
|
|
trig_pul1 &= ~ETMR_FM_SW_TRIG_PULSE1_TRIG2_WIDTH;
|
|
trig_pul1 |= ETMR_FV_SW_TRIG_PULSE1_TRIG2_WIDTH(value);
|
|
break;
|
|
|
|
case SDRV_ETIMR_SW_TRIG3:
|
|
trig_pul1 &= ~ETMR_FM_SW_TRIG_PULSE1_TRIG3_WIDTH;
|
|
trig_pul1 |= ETMR_FV_SW_TRIG_PULSE1_TRIG3_WIDTH(value);
|
|
break;
|
|
|
|
default:
|
|
return;
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_SW_TRIG_PULSE0_OFF, trig_pul0);
|
|
sdrv_etimer_lld_writel(base, ETMR_SW_TRIG_PULSE1_OFF, trig_pul1);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_sse_ctrl(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
const sdrv_etimer_sse_ctrl_t *cfg)
|
|
{
|
|
uint32_t cmp_sse =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_SSE_CTRL_OFF(etimer_id));
|
|
uint32_t sse_mode = cfg->sse_mode[0] << 0 | cfg->sse_mode[1] << 1 |
|
|
cfg->sse_mode[2] << 2 | cfg->sse_mode[3] << 3 |
|
|
cfg->sse_mode[4] << 4;
|
|
cmp_sse &= ~ETMR_FM_CMP_SSE_CTRL_SSE_MODE;
|
|
cmp_sse |= ETMR_FV_CMP_SSE_CTRL_SSE_MODE(sse_mode);
|
|
uint32_t sse_edge = cfg->edge_sel[0] << 0 | cfg->edge_sel[1] << 2 |
|
|
cfg->edge_sel[2] << 4 | cfg->edge_sel[3] << 6 |
|
|
cfg->edge_sel[4] << 8;
|
|
cmp_sse &= ~ETMR_FM_CMP_SSE_CTRL_EDGE_SEL;
|
|
cmp_sse |= ETMR_FV_CMP_SSE_CTRL_EDGE_SEL(sse_edge);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_SSE_CTRL_OFF(etimer_id), cmp_sse);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_sse_en(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t cmp_sse =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_SSE_CTRL_OFF(etimer_id));
|
|
enable ? (cmp_sse |= ETMR_BM_CMP_SSE_CTRL_SSE_EN)
|
|
: (cmp_sse &= ~ETMR_BM_CMP_SSE_CTRL_SSE_EN);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_SSE_CTRL_OFF(etimer_id), cmp_sse);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_fault_det_en(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t cmp_sse =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_SSE_CTRL_OFF(etimer_id));
|
|
enable ? (cmp_sse |= ETMR_BM_CMP_SSE_CTRL_SSE_FAULT_DET_EN)
|
|
: (cmp_sse &= ~ETMR_BM_CMP_SSE_CTRL_SSE_FAULT_DET_EN);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_SSE_CTRL_OFF(etimer_id), cmp_sse);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_fault_det_set(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_cmp_fault_det_e fault_det)
|
|
{
|
|
uint32_t cmp_sse =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_SSE_CTRL_OFF(etimer_id));
|
|
cmp_sse &= ~ETMR_FM_CMP_SSE_CTRL_SSE_SO_DET_FAULT;
|
|
cmp_sse |= ETMR_FV_CMP_SSE_CTRL_SSE_SO_DET_FAULT(fault_det);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_SSE_CTRL_OFF(etimer_id), cmp_sse);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_sse_val(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
uint32_t value)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_SSE_REG_OFF(etimer_id), value);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_sse_ctrl(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
const sdrv_etimer_sse_ctrl_t *cfg)
|
|
{
|
|
uint32_t cpt_sse =
|
|
sdrv_etimer_lld_readl(base, ETMR_CPT_SSE_CTRL_OFF(etimer_id));
|
|
uint32_t sse_mode = cfg->sse_mode[0] << 0 | cfg->sse_mode[1] << 1 |
|
|
cfg->sse_mode[2] << 2 | cfg->sse_mode[3] << 3 |
|
|
cfg->sse_mode[4] << 4;
|
|
cpt_sse &= ~ETMR_FM_CPT_SSE_CTRL_SSE_MODE;
|
|
cpt_sse |= ETMR_FV_CPT_SSE_CTRL_SSE_MODE(sse_mode);
|
|
uint32_t sse_edge = cfg->edge_sel[0] << 0 | cfg->edge_sel[1] << 2 |
|
|
cfg->edge_sel[2] << 4 | cfg->edge_sel[3] << 6 |
|
|
cfg->edge_sel[4] << 8;
|
|
cpt_sse &= ~ETMR_FM_CPT_SSE_CTRL_EDGE_SEL;
|
|
cpt_sse |= ETMR_FV_CPT_SSE_CTRL_EDGE_SEL(sse_edge);
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_SSE_CTRL_OFF(etimer_id), cpt_sse);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_quad_ctrl(uint32_t base, quad_ctrl_t *quad_ctrl)
|
|
{
|
|
uint32_t cpt_sse = sdrv_etimer_lld_readl(base, ETMR_CPT_SSE_CTRL_OFF(0));
|
|
cpt_sse &= ~ETMR_FM_CPT_SSE_CTRL_QUAD_SET_SEL;
|
|
cpt_sse |= ETMR_FV_CPT_SSE_CTRL_QUAD_SET_SEL(quad_ctrl->quad_set_sel);
|
|
cpt_sse &= ~ETMR_FM_CPT_SSE_CTRL_QUAD_CLR_SEL;
|
|
cpt_sse |= ETMR_FV_CPT_SSE_CTRL_QUAD_CLR_SEL(quad_ctrl->quad_clr_sel);
|
|
(quad_ctrl->quad_home_pol)
|
|
? (cpt_sse |= ETMR_BM_CPT_SSE_CTRL_QUAD_HOME_POL)
|
|
: (cpt_sse &= ~ETMR_BM_CPT_SSE_CTRL_QUAD_HOME_POL);
|
|
(quad_ctrl->quad_index_pol)
|
|
? (cpt_sse |= ETMR_BM_CPT_SSE_CTRL_QUAD_INDEX_POL)
|
|
: (cpt_sse &= ~ETMR_BM_CPT_SSE_CTRL_QUAD_INDEX_POL);
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_SSE_CTRL_OFF(0), cpt_sse);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_quad_en(uint32_t base, bool enable)
|
|
{
|
|
uint32_t cpt_sse = sdrv_etimer_lld_readl(base, ETMR_CPT_SSE_CTRL_OFF(0));
|
|
enable ? (cpt_sse |= ETMR_BM_CPT_SSE_CTRL_QUAD_MODE_EN)
|
|
: (cpt_sse &= ~ETMR_BM_CPT_SSE_CTRL_QUAD_MODE_EN);
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_SSE_CTRL_OFF(0), cpt_sse);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_sse_en(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t cpt_sse =
|
|
sdrv_etimer_lld_readl(base, ETMR_CPT_SSE_CTRL_OFF(etimer_id));
|
|
enable ? (cpt_sse |= ETMR_BM_CPT_SSE_CTRL_SSE_EN)
|
|
: (cpt_sse &= ~ETMR_BM_CPT_SSE_CTRL_SSE_EN);
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_SSE_CTRL_OFF(etimer_id), cpt_sse);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_sse_val(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
uint32_t value)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_SSE_REG_OFF(etimer_id), value);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_flt_cfg(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
flt_config_t *cfg)
|
|
{
|
|
if (((cfg->pos_band_wid < 2) || (cfg->pos_band_wid > 17)) &&
|
|
((cfg->pos_band_wid == SDRV_ETIMR_FLT_POSEEDGE) ||
|
|
(cfg->pos_band_wid == SDRV_ETIMR_FLT_BOTHEDGE))) {
|
|
return;
|
|
}
|
|
|
|
if (((cfg->neg_band_wid < 2) || (cfg->neg_band_wid > 17)) &&
|
|
((cfg->pos_band_wid == SDRV_ETIMR_FLT_NEGEEDGE) ||
|
|
(cfg->pos_band_wid == SDRV_ETIMR_FLT_BOTHEDGE))) {
|
|
return;
|
|
}
|
|
|
|
uint32_t flt_cfg = 0;
|
|
flt_cfg |= ETMR_FV_CPT_X0_FLT_FLT_EDGE_SEL(cfg->flt_edge_sel);
|
|
|
|
if (cfg->flt_edge_sel == SDRV_ETIMR_FLT_POSEEDGE) {
|
|
flt_cfg |= ETMR_FV_CPT_X0_FLT_POS_BAND_WID(
|
|
cfg->pos_band_wid - 2); /* 0-15 indicate 2-17 sample interval */
|
|
}
|
|
else if (cfg->flt_edge_sel == SDRV_ETIMR_FLT_NEGEEDGE) {
|
|
flt_cfg |= ETMR_FV_CPT_X0_FLT_NEG_BAND_WID(
|
|
cfg->neg_band_wid - 2); /* 0-15 indicate 2-17 sample interval */
|
|
}
|
|
else {
|
|
flt_cfg |= ETMR_FV_CPT_X0_FLT_POS_BAND_WID(
|
|
cfg->pos_band_wid - 2); /* 0-15 indicate 2-17 sample interval */
|
|
flt_cfg |= ETMR_FV_CPT_X0_FLT_NEG_BAND_WID(
|
|
cfg->neg_band_wid - 2); /* 0-15 indicate 2-17 sample interval */
|
|
}
|
|
|
|
flt_cfg |= ETMR_FV_CPT_X0_FLT_SMPL_INTVAL(cfg->sample_intval);
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_X0_FLT_OFF(etimer_id), flt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cpt_flt_en(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t flt_cfg =
|
|
sdrv_etimer_lld_readl(base, ETMR_CPT_X0_FLT_OFF(etimer_id));
|
|
enable ? (flt_cfg |= ETMR_BM_CPT_X0_FLT_FLT_EN)
|
|
: (flt_cfg &= ~ETMR_BM_CPT_X0_FLT_FLT_EN);
|
|
sdrv_etimer_lld_writel(base, ETMR_CPT_X0_FLT_OFF(etimer_id), flt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_fault_flt_cfg(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
flt_config_t *cfg)
|
|
{
|
|
if (((cfg->pos_band_wid < 2) || (cfg->pos_band_wid > 17)) &&
|
|
((cfg->pos_band_wid == SDRV_ETIMR_FLT_POSEEDGE) ||
|
|
(cfg->pos_band_wid == SDRV_ETIMR_FLT_BOTHEDGE))) {
|
|
return;
|
|
}
|
|
|
|
if (((cfg->neg_band_wid < 2) || (cfg->neg_band_wid > 17)) &&
|
|
((cfg->pos_band_wid == SDRV_ETIMR_FLT_NEGEEDGE) ||
|
|
(cfg->pos_band_wid == SDRV_ETIMR_FLT_BOTHEDGE))) {
|
|
return;
|
|
}
|
|
|
|
uint32_t flt_cfg = 0;
|
|
flt_cfg |= ETMR_FV_FAULT_X_FLT_FLT_EDGE_SEL(cfg->flt_edge_sel);
|
|
flt_cfg |= ETMR_FV_FAULT_X_FLT_POS_BAND_WID(
|
|
cfg->pos_band_wid - 2); /* 0-15 indicate 2-17 sample interval */
|
|
flt_cfg |= ETMR_FV_FAULT_X_FLT_NEG_BAND_WID(
|
|
cfg->neg_band_wid - 2); /* 0-15 indicate 2-17 sample interval */
|
|
flt_cfg |= ETMR_FV_FAULT_X_FLT_SMPL_INTVAL(cfg->sample_intval);
|
|
sdrv_etimer_lld_writel(base, ETMR_FAULT_X_FLT_OFF(etimer_id), flt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_fault_flt_en(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t flt_cfg =
|
|
sdrv_etimer_lld_readl(base, ETMR_FAULT_X_FLT_OFF(etimer_id));
|
|
enable ? (flt_cfg |= ETMR_BM_FAULT_X_FLT_FLT_EN)
|
|
: (flt_cfg &= ~ETMR_BM_FAULT_X_FLT_FLT_EN);
|
|
sdrv_etimer_lld_writel(base, ETMR_FAULT_X_FLT_OFF(etimer_id), flt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cnt_snap_shot(uint32_t base, sdrv_etimer_cnt_id_e cnt_x,
|
|
uint32_t val)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_CNT_SNAP_SHOT_SEL_OFF(cnt_x), val);
|
|
}
|
|
|
|
void sdrv_etimer_lld_output_snap_shot(uint32_t base, uint32_t val)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_SNAP_SHOT_O_SEL_OFF, val);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_fault_ctrl(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_cmp_fault_e fault_idx,
|
|
cmp_fault_ctrl_t *cfg)
|
|
{
|
|
uint32_t fault_ctrl = 0;
|
|
(cfg->fault_pol)
|
|
? (fault_ctrl |= ETMR_BM_CMP_FAULT_EVENT_CTRL_FAULT_X_POL(fault_idx))
|
|
: (fault_ctrl &= ~ETMR_BM_CMP_FAULT_EVENT_CTRL_FAULT_X_POL(fault_idx));
|
|
(cfg->fault_clr_mode)
|
|
? (fault_ctrl |=
|
|
ETMR_BM_CMP_FAULT_EVENT_CTRL_FAULT_X_CLR_MODE(fault_idx))
|
|
: (fault_ctrl &=
|
|
~ETMR_BM_CMP_FAULT_EVENT_CTRL_FAULT_X_CLR_MODE(fault_idx));
|
|
sdrv_etimer_lld_writel(base, ETMR_ETMR_CMP_FAULT_EVENT_CTRL_OFF(etimer_id),
|
|
fault_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_fault_en(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_cmp_fault_e fault_idx,
|
|
bool enable)
|
|
{
|
|
uint32_t fault_ctrl = sdrv_etimer_lld_readl(
|
|
base, ETMR_ETMR_CMP_FAULT_EVENT_CTRL_OFF(etimer_id));
|
|
enable
|
|
? (fault_ctrl |= ETMR_BM_CMP_FAULT_EVENT_CTRL_FAULT_X_EN(fault_idx))
|
|
: (fault_ctrl &= ~ETMR_BM_CMP_FAULT_EVENT_CTRL_FAULT_X_EN(fault_idx));
|
|
sdrv_etimer_lld_writel(base, ETMR_ETMR_CMP_FAULT_EVENT_CTRL_OFF(etimer_id),
|
|
fault_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_fault_clr(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_cmp_fault_e fault_idx)
|
|
{
|
|
uint32_t fault_ctrl = sdrv_etimer_lld_readl(
|
|
base, ETMR_ETMR_CMP_FAULT_EVENT_CTRL_OFF(etimer_id));
|
|
fault_ctrl |= ETMR_BM_CMP_FAULT_EVENT_CTRL_FAULT_X_CLR(fault_idx);
|
|
sdrv_etimer_lld_writel(base, ETMR_ETMR_CMP_FAULT_EVENT_CTRL_OFF(etimer_id),
|
|
fault_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_offset(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
uint32_t val)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_ETMR_CMP_OFFSET_OFF(etimer_id), val);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_eid(uint32_t base, sdrv_etimer_cmp_event_e cmp_event,
|
|
uint32_t val)
|
|
{
|
|
uint32_t cmp_eid = sdrv_etimer_lld_readl(base, ETMR_CMP_A_EID_OFF);
|
|
cmp_eid &= ~ETMR_FM_CMP_A_EID_CMP(cmp_event);
|
|
cmp_eid |= ETMR_FV_CMP_A_EID_CMP(val, cmp_event);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_A_EID_OFF, cmp_eid);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_eid_upd(uint32_t base)
|
|
{
|
|
uint32_t cmp_ctrl = sdrv_etimer_lld_readl(base, ETMR_CMP_CTRL_OFF);
|
|
cmp_ctrl |= ETMR_BM_CMP_CTRL_CMP_A_EID_UPD;
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CTRL_OFF, cmp_ctrl);
|
|
}
|
|
|
|
void sdrv_etimer_lld_sw_rst(uint32_t base, uint32_t val)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_SW_RST_OFF, val);
|
|
}
|
|
|
|
void sdrv_etimer_lld_set_sync_dis(uint32_t base, uint32_t val)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_SYNC_DIS_OFF, val);
|
|
}
|
|
|
|
void sdrv_etimer_lld_ext_output_dir_sel(uint32_t base,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_ext_out_dir_e val)
|
|
{
|
|
if (sel != SDRV_ETIMR_TRIG_SEL_DIR) {
|
|
return;
|
|
}
|
|
|
|
uint32_t ext_out = sdrv_etimer_lld_readl(base, ETMR_EXT_OUTPUT_SEL_OFF);
|
|
ext_out &= ~ETMR_FM_EXT_OUTPUT_SEL_DIR_SEL;
|
|
ext_out |= ETMR_FV_EXT_OUTPUT_SEL_DIR_SEL(val);
|
|
sdrv_etimer_lld_writel(base, ETMR_EXT_OUTPUT_SEL_OFF, ext_out);
|
|
}
|
|
|
|
void sdrv_etimer_lld_ext_output_set_clr_sel(uint32_t base,
|
|
sdrv_etimer_trig_sel_e sel,
|
|
sdrv_etimer_ext_out_set_clr_e val)
|
|
{
|
|
uint32_t ext_out = sdrv_etimer_lld_readl(base, ETMR_EXT_OUTPUT_SEL_OFF);
|
|
|
|
if (sel == SDRV_ETIMR_TRIG_SEL_SET) {
|
|
ext_out &= ~ETMR_FM_EXT_OUTPUT_SEL_SET_SEL;
|
|
ext_out |= ETMR_FV_EXT_OUTPUT_SEL_SET_SEL(val);
|
|
}
|
|
else if (sel == SDRV_ETIMR_TRIG_SEL_CLR) {
|
|
ext_out &= ~ETMR_FM_EXT_OUTPUT_SEL_CLR_SEL;
|
|
ext_out |= ETMR_FV_EXT_OUTPUT_SEL_CLR_SEL(val);
|
|
}
|
|
else {
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_EXT_OUTPUT_SEL_OFF, ext_out);
|
|
}
|
|
|
|
uint32_t sdrv_etimer_lld_get_fifo_req_sta(uint32_t base)
|
|
{
|
|
uint32_t fifo_req_sta =
|
|
sdrv_etimer_lld_readl(base, ETMR_FIFO_REQ_STATUS_OFF);
|
|
return fifo_req_sta;
|
|
}
|
|
|
|
uint32_t sdrv_etimer_lld_get_fifo_val(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id)
|
|
{
|
|
uint32_t fifo_val = sdrv_etimer_lld_readl(base, ETMR_FIFO_OFF(etimer_id));
|
|
return fifo_val;
|
|
}
|
|
|
|
uint32_t sdrv_etimer_lld_get_fifo_sta(uint32_t base)
|
|
{
|
|
uint32_t fifo_sta = sdrv_etimer_lld_readl(base, ETMR_FIFO_STA_OFF);
|
|
return fifo_sta;
|
|
}
|
|
|
|
void sdrv_etimer_lld_clear_fifo(uint32_t base, sdrv_etimer_chn_id_e etimer_id)
|
|
{
|
|
uint32_t fifo_sta = sdrv_etimer_lld_get_fifo_sta(base);
|
|
|
|
for (uint8_t i = 0;
|
|
i < (ETMR_GFV_FIFO_STA_FIFO_ENTRIES(fifo_sta, etimer_id)); i++) {
|
|
sdrv_etimer_lld_get_fifo_val(base, etimer_id);
|
|
}
|
|
}
|
|
|
|
uint32_t sdrv_etimer_lld_get_sig_status(uint32_t base)
|
|
{
|
|
uint32_t sig_status = sdrv_etimer_lld_readl(base, ETMR_SIGNAL_STATUS_OFF);
|
|
return sig_status;
|
|
}
|
|
|
|
void sdrv_etimer_lld_set_self_test(uint32_t base, bool enable)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_SELFTEST_MODE_OFF, enable);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_dti_cbc(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
#if CONFIG_E3 || CONFIG_D3
|
|
|
|
if (IS_1P1)
|
|
#endif
|
|
{
|
|
uint8_t index = 0;
|
|
|
|
for (index = 0; index < 4; index++) {
|
|
if (APB_ETMR1_BASE + 0x10000 * index == base)
|
|
break;
|
|
}
|
|
|
|
RMWREG32(ETMR_CBC_ZERO_VECTOR_BY_SCR_ADDR,
|
|
ETMR_CBC_POS(index, etimer_id), 1, enable);
|
|
}
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_dti_zero_vector(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
#if CONFIG_E3 || CONFIG_D3
|
|
|
|
if (IS_1P1)
|
|
#endif
|
|
{
|
|
uint8_t index = 0;
|
|
|
|
for (index = 0; index < 4; index++) {
|
|
if (APB_ETMR1_BASE + 0x10000 * index == base)
|
|
break;
|
|
}
|
|
|
|
RMWREG32(ETMR_CBC_ZERO_VECTOR_BY_SCR_ADDR,
|
|
ETMR_ZERO_VECTOR_POS(index, etimer_id), 1, enable);
|
|
}
|
|
}
|
|
|
|
#if CONFIG_E3L
|
|
void sdrv_etimer_lld_cmp_sw_frc_dis(paddr_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_output_e sub_chnl, bool en)
|
|
{
|
|
uint8_t index = 0;
|
|
|
|
for (index = 0; index < 2; index++) {
|
|
if (APB_ETMR1_BASE + 0x10000 * index == base)
|
|
break;
|
|
}
|
|
|
|
RMWREG32(ETMR_CBC_ZERO_VECTOR_BY_SCR_ADDR, ETMR_SW_FRC_DIS_POS(index, etimer_id, sub_chnl),
|
|
1, en);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cnt_center_align_en(uint32_t base,
|
|
sdrv_etimer_cnt_id_e cnt_x,
|
|
bool enable)
|
|
{
|
|
uint32_t cnt_reg_addr = 0;
|
|
|
|
if (cnt_x <= SDRV_ETIMR_CNT_G1) {
|
|
cnt_reg_addr = ETMR_CNT_CFG_OFF(cnt_x);
|
|
}
|
|
else {
|
|
cnt_reg_addr = ETMR_LCNT_CFG1_OFF(cnt_x - 2);
|
|
}
|
|
|
|
uint32_t cnt_cfg = sdrv_etimer_lld_readl(base, cnt_reg_addr);
|
|
|
|
if (cnt_x <= SDRV_ETIMR_CNT_G1) {
|
|
enable ? (cnt_cfg |= ETMR_BM_CNT_CFG_CENTER_ALIGN_MODE)
|
|
: (cnt_cfg &= ~ETMR_BM_CNT_CFG_CENTER_ALIGN_MODE);
|
|
}
|
|
else {
|
|
enable ? (cnt_cfg |= ETMR_BM_LCNT_CFG_CENTER_ALIGN_MODE)
|
|
: (cnt_cfg &= ~ETMR_BM_LCNT_CFG_CENTER_ALIGN_MODE);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, cnt_reg_addr, cnt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cnt_center_align_cfg(uint32_t base,
|
|
sdrv_etimer_cnt_id_e cnt_x,
|
|
cnt_center_align_config_t *cfg)
|
|
{
|
|
uint32_t cnt_reg_addr = 0;
|
|
|
|
if (cnt_x <= SDRV_ETIMR_CNT_G1) {
|
|
cnt_reg_addr = ETMR_CNT_CFG_OFF(cnt_x);
|
|
}
|
|
else {
|
|
cnt_reg_addr = ETMR_LCNT_CFG1_OFF(cnt_x - 2);
|
|
}
|
|
|
|
uint32_t cnt_cfg = sdrv_etimer_lld_readl(base, cnt_reg_addr);
|
|
|
|
if (cnt_x <= SDRV_ETIMR_CNT_G1) {
|
|
cnt_cfg &= ~ETMR_FM_CNT_CFG_CENTER_ALIGN_OVF_SEL;
|
|
cnt_cfg &= ~ETMR_FM_CNT_CFG_CENTER_ALIGN_CE_SEL;
|
|
cnt_cfg |= ETMR_FV_CNT_CFG_CENTER_ALIGN_OVF_SEL(cfg->ovf_sel);
|
|
cnt_cfg |= ETMR_FV_CNT_CFG_CENTER_ALIGN_CE_SEL(cfg->ce_sel);
|
|
}
|
|
else {
|
|
cnt_cfg &= ~ETMR_FM_LCNT_CFG_CENTER_ALIGN_OVF_SEL;
|
|
cnt_cfg &= ~ETMR_FM_LCNT_CFG_CENTER_ALIGN_CE_SEL;
|
|
cnt_cfg |= ETMR_FV_LCNT_CFG_CENTER_ALIGN_OVF_SEL(cfg->ovf_sel);
|
|
cnt_cfg |= ETMR_FV_LCNT_CFG_CENTER_ALIGN_CE_SEL(cfg->ce_sel);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, cnt_reg_addr, cnt_cfg);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_center_align_en(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t cmp_cfg1 =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_CONFIG1_OFF(etimer_id));
|
|
enable ? (cmp_cfg1 |= ETMR_BM_CMP_CENTER_ALIGN_MODE)
|
|
: (cmp_cfg1 &= ~ETMR_BM_CMP_CENTER_ALIGN_MODE);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CONFIG1_OFF(etimer_id), cmp_cfg1);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_center_align_cfg(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
cmp_center_align_config_t *cfg)
|
|
{
|
|
uint32_t cmp_cfg1 = 0;
|
|
cmp_cfg1 |= ETMR_FV_CMP_CENTER_ALIGN_CE_SEL(cfg->ce_sel);
|
|
cmp_cfg1 |= ETMR_FV_CMP_CENTER_ALIGN_CMP00_IRQ_SEL(cfg->cmp00_irq);
|
|
cmp_cfg1 |= ETMR_FV_CMP_CENTER_ALIGN_CMP01_IRQ_SEL(cfg->cmp01_irq);
|
|
cmp_cfg1 |= ETMR_FV_CMP_CENTER_ALIGN_CMP10_IRQ_SEL(cfg->cmp10_irq);
|
|
cmp_cfg1 |= ETMR_FV_CMP_CENTER_ALIGN_CMP11_IRQ_SEL(cfg->cmp11_irq);
|
|
cmp_cfg1 |= ETMR_FV_CMP_CENTER_ALIGN_RLD_SEL(cfg->rld_sel);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_CONFIG1_OFF(etimer_id), cmp_cfg1);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_cen_ali_int_enable(uint32_t base, uint32_t int_sel)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_CENTER_ALIGN_CMP_INT_STA_EN_OFF, int_sel);
|
|
sdrv_etimer_lld_writel(base, ETMR_CENTER_ALIGN_CMP_INT_SIG_EN_OFF, int_sel);
|
|
}
|
|
|
|
uint32_t sdrv_etimer_lld_get_cmp_cen_ali_int_status(uint32_t base)
|
|
{
|
|
uint32_t int_sta =
|
|
sdrv_etimer_lld_readl(base, ETMR_CENTER_ALIGN_CMP_INT_STA_OFF);
|
|
return int_sta;
|
|
}
|
|
|
|
void sdrv_etimer_lld_clear_cmp_cen_ali_int_status(uint32_t base,
|
|
uint32_t int_sta)
|
|
{
|
|
sdrv_etimer_lld_writel(base, ETMR_CENTER_ALIGN_CMP_INT_STA_OFF, int_sta);
|
|
}
|
|
|
|
uint32_t sdrv_etimer_lld_get_cmp_fault_sta(uint32_t base)
|
|
{
|
|
uint32_t fault_sta =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_FAULT_EVENT_STA_OFF);
|
|
return fault_sta;
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_frc_idle(uint32_t base, sdrv_etimer_chn_id_e etimer_id,
|
|
sdrv_etimer_cmp_group_e group, bool enable)
|
|
{
|
|
uint32_t cmp_idle =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id));
|
|
|
|
if (SDRV_ETIMR_CMP_OUT_0 == group) {
|
|
enable ? (cmp_idle |= ETMR_BM_CMP_CMP0_IDLE_STA)
|
|
: (cmp_idle &= ~ETMR_BM_CMP_CMP0_IDLE_STA);
|
|
}
|
|
else if (SDRV_ETIMR_CMP_OUT_1 == group) {
|
|
enable ? (cmp_idle |= ETMR_BM_CMP_CMP1_IDLE_STA)
|
|
: (cmp_idle &= ~ETMR_BM_CMP_CMP1_IDLE_STA);
|
|
}
|
|
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id), cmp_idle);
|
|
}
|
|
|
|
void sdrv_etimer_lld_cmp_sw_trig_idle(uint32_t base,
|
|
sdrv_etimer_chn_id_e etimer_id,
|
|
bool enable)
|
|
{
|
|
uint32_t cmp_idle =
|
|
sdrv_etimer_lld_readl(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id));
|
|
enable ? (cmp_idle |= ETMR_BM_CMP_SW_TRIG_FRC)
|
|
: (cmp_idle &= ~ETMR_BM_CMP_SW_TRIG_FRC);
|
|
sdrv_etimer_lld_writel(base, ETMR_CMP_DTI_CTRL_OFF(etimer_id), cmp_idle);
|
|
}
|
|
|
|
#endif
|