763 lines
24 KiB
C
763 lines
24 KiB
C
/**
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* dwc_eth.c
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*
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* Copyright (c) 2021 Semidrive Semiconductor.
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* All rights reserved.
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*
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* Description: dw eth mac drv
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*
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* Revision History:
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* -----------------
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*/
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#include <stdlib.h>
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#include <string.h>
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#include "debug.h"
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#include "param.h"
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#include "armv7-r/barriers.h"
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#include "armv7-r/cache.h"
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#include "irq_num.h"
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#include "irq.h"
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#include "sdrv_mac_lld.h"
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#include "sdrv_eth.h"
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#include "phy/phy.h"
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#include "app/app_frm_signal.h"
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/* Eth frame header and crc length. */
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#define ETH_FRAME_HEADER_LEN (6 + 6 + 2)
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#define ETH_FRAME_OVERHEAD_LEN (ETH_FRAME_HEADER_LEN + 4)
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#if !CONFIG_ETH_USE_HEAP
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#define MAX_ETH_CNT 2
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#ifndef CONFIG_ARCH_CACHE_LINE
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#define CONFIG_ARCH_CACHE_LINE 32
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#endif
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typedef struct {
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struct eqos_desc desc;
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} __ALIGNED(EQOS_DESCRIPTOR_ALIGN) eqos_desc_t;
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struct eqos_data {
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bool used;
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dwc_eth_dev_t dev;
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struct eqos_priv eqos;
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eqos_desc_t descs[EQOS_DESCRIPTORS_NUM];
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uint8_t rx_dma_buf[EQOS_RX_BUFFER_SIZE] __ALIGNED(CONFIG_ARCH_CACHE_LINE);
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uint8_t tx_dma_buf[EQOS_TX_BUFFER_SIZE] __ALIGNED(CONFIG_ARCH_CACHE_LINE);
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};
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static struct eqos_data g_eqos_data[MAX_ETH_CNT];
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#endif
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static void *eqos_alloc_descs(struct eqos_priv *eqos, unsigned int num)
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{
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/* Align dma descriptors base address & size to cache line to avoid
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* descriptors corrupted by cacahe line invalidation needed by other
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* address, if descriptors has not been wrote to ram.
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*/
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eqos->desc_size = ALIGN(sizeof(struct eqos_desc),
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(unsigned int)EQOS_DESCRIPTOR_ALIGN);
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#if !CONFIG_ETH_USE_HEAP
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return containerof(eqos, struct eqos_data, eqos)->descs;
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#else
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#if __GNUC__
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return (void *)memalign(eqos->desc_size, num * eqos->desc_size);
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#else
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return aligned_alloc(eqos->desc_size, num * eqos->desc_size);
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#endif
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#endif
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}
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#if CONFIG_ETH_USE_HEAP
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static void eqos_free_descs(void *descs)
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{
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free(descs);
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}
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#endif
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static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos, unsigned int num,
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bool rx)
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{
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void *desc = (uint8_t *)eqos->descs +
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((rx ? EQOS_DESCRIPTORS_TX : 0) + num) * eqos->desc_size;
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return desc;
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}
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/**
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* @brief Init the Controller DMA Block
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*/
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static inline void mac_init_dma(uint32_t regbase, struct eqos_priv *eqos)
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{
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uint8_t ch_cnt = 0U;
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dwmac_dma_bus_init(regbase, DMA_AXI_MAX_OSR_LIMIT | DMA_SYS_BUS_AAL |
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DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | DMA_AXI_BLEN4);
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for (ch_cnt = 0; ch_cnt < ETH_MAX_DMA_CHANNEL; ch_cnt++) {
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// DMA Control
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dwmac_dma_init_channel(regbase, 0, ch_cnt, eqos->dsl);
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// rx ring length
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dwmac_set_rx_ring_len(regbase, EQOS_DESCRIPTORS_RX - 1, ch_cnt);
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// init_rx_chan
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dwmac_dma_init_rx_chan(regbase, (paddr_t)eqos_get_desc(eqos, 0, true),
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EQOS_MAX_PACKET_SIZE, ch_cnt);
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// rx bufsize
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dwmac_set_bfsize(regbase, 2048, ch_cnt);
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// tx ring length
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dwmac_set_tx_ring_len(regbase, EQOS_DESCRIPTORS_TX - 1, ch_cnt);
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// init_tx_chan
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dwmac_dma_init_tx_chan(regbase, (paddr_t)eqos_get_desc(eqos, 0, false),
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ch_cnt);
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// set tx tail ptr to next address after the last tx descriptor, so that
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// dma will never suspend.
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dwmac_set_tx_tail_ptr(regbase, (uint32_t)eqos_get_desc(eqos, EQOS_DESCRIPTORS_TX, false),
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ch_cnt);
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// set rx tail ptr to next address after the last tx descriptor, so that
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// dma will never suspend.
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dwmac_set_rx_tail_ptr(regbase,
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(paddr_t)eqos_get_desc(eqos, EQOS_DESCRIPTORS_RX, true),
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ch_cnt);
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dwmac_enable_dma_irq(regbase, ch_cnt, false, false);
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}
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}
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/**
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* @brief Init the Controller MTL Block
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*/
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static inline void mac_init_mtl(uint32_t regbase)
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{
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uint8_t ch_cnt = 0U;
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dwmac_prog_mtl_rx_algorithms(regbase, MTL_RX_ALGORITHM_SP);
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dwmac_prog_mtl_tx_algorithms(regbase, MTL_OPERATION_SCHALG_WRR);
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for (ch_cnt = 0; ch_cnt < ETH_MAX_DMA_CHANNEL; ch_cnt++) {
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// rx mtl map with dma
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dwmac_map_mtl_dma(regbase, ch_cnt, ch_cnt);
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dwmac_rx_queue_enable(regbase, MTL_QUEUE_MODE_DCB, ch_cnt);
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dwmac_dma_tx_chan_op_mode(regbase, ch_cnt, SF_MODE, 10240, MTL_QUEUE_MODE_DCB);
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dwmac_dma_rx_chan_op_mode(regbase, ch_cnt, SF_MODE, 10240, MTL_QUEUE_MODE_DCB);
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}
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}
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static inline void mac_start(uint32_t regbase, bool start)
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{
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uint8_t ch_cnt = 0U;
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for (ch_cnt = 0; ch_cnt < ETH_MAX_DMA_CHANNEL; ch_cnt++) {
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if (start) {
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// start rx
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dwmac_dma_start_rx(regbase, ch_cnt);
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// start tx
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dwmac_dma_start_tx(regbase, ch_cnt);
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}
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else {
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// stop rx
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dwmac_dma_stop_rx(regbase, ch_cnt);
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// stop tx
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dwmac_dma_stop_tx(regbase, ch_cnt);
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}
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}
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}
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static void eth_mac_init(dwc_eth_config_t *cfg, struct eqos_priv *eqos)
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{
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//DMA core sw reset
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dwmac_dma_reset(cfg->base);
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uint32_t skip_len = eqos->desc_size - sizeof(struct eqos_desc);
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uint8_t bus_width = cfg->dma_bus_width ? cfg->dma_bus_width : 64;
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eqos->dsl = skip_len * 8 / bus_width;
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//DMA init
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mac_init_dma(cfg->base, eqos);
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//MTL init
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mac_init_mtl(cfg->base);
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//core init
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phy_speed_t speed = (cfg->phy[0].phy_addr == ~0) ?
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PHY_SPEED_1000 : cfg->phy[0].speed;
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dwmac_core_init(cfg->base, cfg->mtu, speed, cfg->mac_addr);
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dwmac_mac_rx_queue_mcbc_routing(cfg->base, 0);
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}
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static inline void set_phyif_mode(dwc_eth_config_t *cfg)
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{
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if (cfg->set_phy_intf)
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cfg->set_phy_intf(cfg->base, cfg->phy_intf_mode);
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}
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static inline void config_eth_clk(dwc_eth_config_t *cfg)
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{
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if (cfg->timer_sec_clk)
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sdrv_ckgen_set_rate(cfg->timer_sec_clk, 125000000);
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if (cfg->phy_ref_clk)
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sdrv_ckgen_set_rate(cfg->phy_ref_clk, 125000000);
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if (cfg->rmii_clk)
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sdrv_ckgen_set_rate(cfg->rmii_clk, 50000000);
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if (cfg->tx_clk)
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sdrv_ckgen_set_rate(cfg->tx_clk, 250000000);
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}
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static inline void reset_eth(dwc_eth_config_t *cfg)
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{
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if (cfg->rst)
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sdrv_rstgen_reset(cfg->rst);
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}
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static err_t dwc_eth_init(struct net_driver_s *dev)
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{
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int ret = 0;
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int i;
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dwc_eth_dev_t *eth_dev = (dwc_eth_dev_t *)dev->d_private;
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dwc_eth_config_t *cfg = eth_dev->config;
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struct eqos_priv *eqos;
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if (eth_dev->init)
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return 0;
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else
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eth_dev->init = true;
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//set SCR ethernet operating mode, e.g. RGMII, SGMII, etc.
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set_phyif_mode(cfg);
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//set ethernet Clk
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config_eth_clk(cfg);
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//ethernet reset
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reset_eth(cfg);
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#if !CONFIG_ETH_USE_HEAP
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struct eqos_data *eqosd = containerof(eth_dev, struct eqos_data, dev);
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eqos = &eqosd->eqos;
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#else
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eqos = (struct eqos_priv *)malloc(sizeof(struct eqos_priv));
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ASSERT(eqos);
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memset(eqos, 0, sizeof(struct eqos_priv));
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#endif
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eqos->descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_NUM);
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if (!eqos->descs) {
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ssdk_printf(SSDK_INFO, "%s: eqos_alloc_descs() failed\n", __func__);
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ret = -1;
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}
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eqos->tx_desc_idx = 0;
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eqos->rx_desc_idx = 0;
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#if !CONFIG_ETH_USE_HEAP
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eqos->tx_dma_buf = eqosd->tx_dma_buf;
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eqos->rx_dma_buf = eqosd->rx_dma_buf;
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#else
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/* Align tx dma buf base address & size to cache line to avoid tx
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* dma buf corrupted by cacahe line invalidation needed by other
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* address, if tx dma buf data has not been wrote to ram.
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*/
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#if __GNUC__
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eqos->tx_dma_buf = (void *)memalign(CONFIG_ARCH_CACHE_LINE,
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EQOS_TX_BUFFER_SIZE);
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#else
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eqos->tx_dma_buf = (void *)aligned_alloc(CONFIG_ARCH_CACHE_LINE,
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EQOS_TX_BUFFER_SIZE);
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#endif
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ASSERT(eqos->tx_dma_buf);
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memset(eqos->tx_dma_buf, 0, EQOS_TX_BUFFER_SIZE);
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/* rx dma buf base address & size should be cache line aligned.
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* Otherwise data before or after rx dma buf may locate in same
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* cache line with rx dma buf, when invalidate rx dma buf cache,
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* heap data before or after rx dma buf may be corrupted.
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*/
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#if __GNUC__
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eqos->rx_dma_buf = (void *)memalign(CONFIG_ARCH_CACHE_LINE,
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EQOS_RX_BUFFER_SIZE);
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#else
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eqos->rx_dma_buf = (void *)aligned_alloc(CONFIG_ARCH_CACHE_LINE,
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EQOS_RX_BUFFER_SIZE);
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#endif
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ASSERT(eqos->rx_dma_buf);
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memset(eqos->rx_dma_buf, 0, EQOS_RX_BUFFER_SIZE);
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#endif
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//init phy
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phy_init(ð_dev->phy_bus);
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//init mac
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eth_mac_init(cfg, eqos);
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// set up dma tx/rx descriptors
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memset(eqos->descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_NUM);
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for (i = 0; i < EQOS_DESCRIPTORS_TX; i++) {
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struct eqos_desc *tx_desc = eqos_get_desc(eqos, i, false);
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arch_clean_cache_range((addr_t)tx_desc, sizeof(struct eqos_desc));
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}
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for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
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struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true);
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rx_desc->des0 = (paddr_t)eqos->rx_dma_buf +
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(i * EQOS_MAX_PACKET_SIZE);
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DMB;
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rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_IOC | EQOS_DESC3_BUF1V;
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arch_clean_cache_range((addr_t)rx_desc, sizeof(struct eqos_desc));
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arch_invalidate_cache_range((addr_t)((char *)eqos->rx_dma_buf +
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(i * EQOS_MAX_PACKET_SIZE)), EQOS_MAX_PACKET_SIZE);
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}
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//enable rx/tx
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mac_start(cfg->base, true);
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eqos->started = true;
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eth_dev->eqos = eqos;
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return ret;
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}
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static inline void eqos_rx_lock(struct eqos_priv *eqos)
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{
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EQOS_RX_LOCK(eqos);
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}
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static inline void eqos_rx_unlock(struct eqos_priv *eqos)
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{
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EQOS_RX_UNLOCK(eqos);
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}
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static inline void eqos_tx_lock(struct eqos_priv *eqos)
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{
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EQOS_TX_LOCK(eqos);
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}
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static inline void eqos_tx_unlock(struct eqos_priv *eqos)
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{
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EQOS_TX_UNLOCK(eqos);
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}
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static err_t dwc_eth_txavail(struct net_driver_s *dev, struct pbuf *p)
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{
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int i, ret = 0;
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struct eqos_desc *tx_desc;
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uint8_t *tx_buf;
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uint32_t offset = 0;
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struct pbuf *q = NULL;
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dwc_eth_dev_t *eth_dev = (dwc_eth_dev_t *)dev->d_private;
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dwc_eth_config_t *cfg = eth_dev->config;
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struct eqos_priv *eqos = eth_dev->eqos;
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if (p->tot_len > (cfg->mtu + ETH_FRAME_HEADER_LEN)) {
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ssdk_printf(SSDK_INFO, "eth tx len > MTU, %d\n", p->tot_len);
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return -1;
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}
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eqos_tx_lock(eqos);
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tx_desc = eqos_get_desc(eqos, eqos->tx_desc_idx, false);
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for (i = 0; i < 100000; i++) {
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arch_invalidate_cache_range((addr_t)tx_desc, sizeof(struct eqos_desc));
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if ((tx_desc->des3 & EQOS_DESC3_OWN) == 0) {
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goto start_tx;
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}
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}
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ssdk_printf(SSDK_INFO, "%s: Previous tX on desc %d timeout\n", __func__,
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eqos->tx_desc_idx);
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ret = -1;
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goto tx_out;
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start_tx:
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tx_buf = (uint8_t *)eqos->tx_dma_buf +
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eqos->tx_desc_idx * EQOS_MAX_PACKET_SIZE;
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//copy data to pbuf
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for (q = p; q != NULL; q = q->next) {
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memcpy((uint8_t *)(tx_buf + offset),
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(uint8_t *)((uint8_t *)q->payload), q->len);
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offset += q->len;
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}
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arch_clean_cache_range((addr_t)tx_buf, p->tot_len);
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eqos->tx_desc_idx ++;
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eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
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tx_desc->des0 = (paddr_t)tx_buf;
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tx_desc->des1 = 0;
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tx_desc->des2 = p->tot_len;
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/*
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* Make sure that if HW sees the _OWN write below, it will see all the
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* writes to the rest of the descriptor too.
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*/
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DMB;
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tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | (p->tot_len);
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arch_clean_cache_range((addr_t)tx_desc, sizeof(struct eqos_desc));
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dwmac_set_tx_tail_ptr(cfg->base,
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(uint32_t)eqos_get_desc(eqos, EQOS_DESCRIPTORS_TX, false),
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0);
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tx_out:
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eqos_tx_unlock(eqos);
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return ret;
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}
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static uint32_t dwc_eth_getmac(struct net_driver_s *dev, void *buf, uint32_t max_len)
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{
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dwc_eth_dev_t *eth_dev = (dwc_eth_dev_t *)dev->d_private;
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uint8_t *mac_addr = eth_dev->config->mac_addr;
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if (mac_addr == NULL) {
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mac_addr = dwmac_get_default_mac_addr();
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}
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memcpy(buf, (void *)mac_addr, max_len);
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return max_len;
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}
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static uint32_t dwc_eth_getmtu(struct net_driver_s *dev)
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{
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dwc_eth_dev_t *eth_dev = (dwc_eth_dev_t *)dev->d_private;
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return eth_dev->config->mtu;
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}
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static int dwc_eth_rx_poll(struct net_driver_s *dev)
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{
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struct eqos_desc *rx_desc;
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uint32_t length = 0;
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uint8_t *recbuf;
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struct pbuf *rx_pbuf = NULL;
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dwc_eth_dev_t *eth_dev = (dwc_eth_dev_t *)dev->d_private;
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dwc_eth_config_t *cfg = eth_dev->config;
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struct eqos_priv *eqos = eth_dev->eqos;
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eqos_rx_lock(eqos);
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rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true);
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arch_invalidate_cache_range((addr_t)rx_desc, sizeof(struct eqos_desc));
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if (rx_desc->des3 & EQOS_DESC3_OWN) {
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eqos_rx_unlock(eqos);
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return -1;
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}
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/*
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* Make sure reading des3 before dma buffer.
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* Avoid speculative reading of buffer before des3 own bit cleared.
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*/
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DMB;
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recbuf = (uint8_t *)eqos->rx_dma_buf + (eqos->rx_desc_idx *
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EQOS_MAX_PACKET_SIZE);
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length = rx_desc->des3 & 0x7FFF;
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arch_invalidate_cache_range((addr_t)((char *)recbuf), length);
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if (length <= (cfg->mtu + ETH_FRAME_OVERHEAD_LEN)) {
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rx_pbuf = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
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if (rx_pbuf) {
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uint32_t offset = 0;
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struct pbuf *q = NULL;
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|
||
for (q = rx_pbuf; q != NULL; q = q->next) {
|
||
memcpy( (uint8_t *)((uint8_t *)q->payload ), ((uint8_t *)recbuf + offset),
|
||
q->len);
|
||
offset += q->len;
|
||
}
|
||
}
|
||
}
|
||
else {
|
||
ssdk_printf(SSDK_INFO, "len > 1500! desc3 = 0x%x\n", rx_desc->des3);
|
||
}
|
||
|
||
//free packet
|
||
rx_desc->des0 = (paddr_t)recbuf;
|
||
rx_desc->des1 = 0;
|
||
rx_desc->des2 = 0;
|
||
/*
|
||
* Make sure DMA observes new des3 value after observing
|
||
* new des0 & des1 & des2 value under any condition, especially
|
||
* when des3 located in a different cache line and the cache line
|
||
* is automatically evicted due to corresponding cache set full.
|
||
*/
|
||
DMB;
|
||
rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_IOC | EQOS_DESC3_BUF1V;
|
||
arch_clean_cache_range((addr_t)rx_desc, sizeof(struct eqos_desc));
|
||
|
||
dwmac_set_rx_tail_ptr(cfg->base,
|
||
(uint32_t)eqos_get_desc(eqos, EQOS_DESCRIPTORS_RX, true),
|
||
0);
|
||
eqos->rx_desc_idx++;
|
||
eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
|
||
|
||
eqos_rx_unlock(eqos);
|
||
|
||
if (rx_pbuf)
|
||
netdev_input(dev, rx_pbuf);
|
||
|
||
return length;
|
||
}
|
||
|
||
static inline void __dwc_eth_enable_dma_rx_int(dwc_eth_dev_t *dwc_eth)
|
||
{
|
||
for (int chn = 0; chn < ETH_MAX_DMA_CHANNEL; chn++) {
|
||
dwmac_enable_dma_rx_int(dwc_eth->config->base, chn, true);
|
||
}
|
||
}
|
||
|
||
__UNUSED static inline void __dwc_eth_disable_dma_rx_int(dwc_eth_dev_t *dwc_eth)
|
||
{
|
||
for (int chn = 0; chn < ETH_MAX_DMA_CHANNEL; chn++) {
|
||
dwmac_enable_dma_rx_int(dwc_eth->config->base, chn, false);
|
||
}
|
||
}
|
||
|
||
void dwc_eth_enable_dma_rx_int(struct net_driver_s *dev, dma_rx_int_cb_t callback)
|
||
{
|
||
ASSERT(dev);
|
||
dwc_eth_dev_t *dwc_eth = dev->d_private;
|
||
|
||
dwc_eth->rx_cb = callback;
|
||
__dwc_eth_enable_dma_rx_int(dwc_eth);
|
||
}
|
||
|
||
/**
|
||
* @brief try to read rx packet and send the packet to lwip stack.
|
||
* Should be called in thread context.
|
||
* If enable DMA rx interrupt, i.e. poll is false, this function
|
||
* should be called after DMA rx interrupt triggered. DMA rx
|
||
* interrupt will be disabled in ISR, and re-enabled in this
|
||
* function after reading out all rx packets, this is helpful to
|
||
* avoid too much rx interrupt.
|
||
*
|
||
* @param [in] dev eth device
|
||
* @param [in] poll true for polling read, false for interrupt read
|
||
* @return int total length of rx packets or -1 if rx nothing
|
||
*/
|
||
int dwc_eth_rx(struct net_driver_s *dev, bool poll)
|
||
{
|
||
ASSERT(dev);
|
||
|
||
int rx_pkt_len = 0;
|
||
int len;
|
||
|
||
do {
|
||
len = dwc_eth_rx_poll(dev);
|
||
if (len != -1)
|
||
rx_pkt_len += len;
|
||
}
|
||
while (len != -1);
|
||
|
||
if (!poll) {
|
||
dwc_eth_dev_t *dwc_eth = dev->d_private;
|
||
/* After reading all packets out, re-enable eth dma rx
|
||
* interrupt which had been disabled in rx int service
|
||
* routine. This strategy can avoid too much eth interrupt.
|
||
*/
|
||
__dwc_eth_enable_dma_rx_int(dwc_eth);
|
||
}
|
||
|
||
return rx_pkt_len ? rx_pkt_len : -1;
|
||
}
|
||
|
||
static int dwc_eth_irq_handler(uint32_t irq, void *arg)
|
||
{
|
||
struct net_driver_s *dev = arg;
|
||
dwc_eth_dev_t *dwc_eth = dev->d_private;
|
||
uint32_t reg_base = dwc_eth->config->base;
|
||
uint32_t status = dwmac_get_dma_int_status(reg_base);
|
||
uint32_t sub_sts, detail;
|
||
uint8_t chn = (irq == ENET1_SBD_INTR_NUM) ? 1 : 2;
|
||
|
||
ssdk_printf(SSDK_DEBUG, "%s int status 0x%x\n", __func__, status);
|
||
if (!status) {
|
||
return -1;
|
||
}
|
||
|
||
irq_state_t state = enter_critical_section();//20250426 <20><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6><CFB1><EFBFBD>
|
||
|
||
if (status & (1 << 17)) {
|
||
/* MAC interrupt */
|
||
sub_sts = dwmac_get_mac_int_status(reg_base);
|
||
ssdk_printf(SSDK_EMERG, "%s %d mac int status 0x%x\n", __func__, irq, sub_sts);
|
||
if (sub_sts & (1 << 0)) {
|
||
/* RGMII/SMII PHY link status changed. Read of MAC_PHYIF_Control_Status
|
||
* register will clear the interrupt status.
|
||
*/
|
||
detail = dwmac_get_mac_phyif_control_status(reg_base);
|
||
if (detail & (1 << 19))
|
||
ssdk_printf(SSDK_EMERG, "ETH%d phy link up\n", chn);
|
||
else
|
||
ssdk_printf(SSDK_EMERG, "ETH%d phy link down\n", chn);
|
||
}
|
||
if (sub_sts & (3 << 1)) {
|
||
/* TBI/RTBI/SGMII PHY link status changed, or TBI/RTBI/SGMII PHY
|
||
* auto-negotiation is completed. Read of MAC_AN_Status register
|
||
* will clear the interrupt status.
|
||
*/
|
||
detail = dwmac_get_mac_an_status(reg_base);
|
||
ssdk_printf(SSDK_EMERG, "ETH%d mac an status 0x%x\n",
|
||
chn, detail);
|
||
}
|
||
if (sub_sts & (1 << 4)) {
|
||
/* A magic packet or Wake-on-LAN packet is received.
|
||
* Read of MAC_PMT_Control_Status register will clear
|
||
* the interrupt status.
|
||
*/
|
||
detail = dwmac_get_mac_pmt_control_status(reg_base);
|
||
ssdk_printf(SSDK_EMERG, "ETH%d mac pmt ctrl status 0x%x\n",
|
||
chn, detail);
|
||
}
|
||
if (sub_sts & (1 << 5)) {
|
||
/* LPI state entry or exit in the MAC Transmitter or Receiver.
|
||
* Read of MAC_LPI_Control_Status register will clear the
|
||
* interrupt status.
|
||
*/
|
||
detail = dwmac_get_mac_lpi_control_status(reg_base);
|
||
ssdk_printf(SSDK_EMERG, "ETH%d mac lpi ctrl status 0x%x\n",
|
||
chn, detail);
|
||
}
|
||
}
|
||
|
||
if (status & (1 << 16)) {
|
||
/* MTL interrupt */
|
||
sub_sts = dwmac_get_mtl_int_status(reg_base);
|
||
if (sub_sts & 0xFFFFFF00) {
|
||
ssdk_printf(SSDK_EMERG, "ETH%d mtl int status 0x%x\n",
|
||
chn, sub_sts);
|
||
ASSERT(0);
|
||
}
|
||
for (int i = 0; i < ETH_MAX_DMA_CHANNEL; i++) {
|
||
if (sub_sts & (1 << i)) {
|
||
detail = dwmac_get_mtl_q_int_status(reg_base, i);
|
||
dwmac_clr_mtl_q_int_status(reg_base, i, detail);
|
||
if (detail & (1 << 16))
|
||
ssdk_printf(SSDK_WARNING, "ETH%d mtl queue %d rx overflow\n",
|
||
chn, i);
|
||
if (detail & (1 << 1))
|
||
ssdk_printf(SSDK_WARNING, "ETH%d mtl queue %d ABS updated\n",
|
||
chn, i);
|
||
if (detail & (1 << 1))
|
||
ssdk_printf(SSDK_WARNING, "ETH%d mtl queue %d tx underflow\n",
|
||
chn, i);
|
||
}
|
||
}
|
||
}
|
||
|
||
if (status & 0x7F) {
|
||
/* DMA interrupt */
|
||
for (int chn = 0; chn < ETH_MAX_DMA_CHANNEL; chn++) {
|
||
sub_sts = dwmac_get_dma_chn_status(reg_base, chn);
|
||
dwmac_clear_dma_chn_int_status(reg_base, chn);
|
||
if (sub_sts & BIT(6)) {
|
||
/* DMA rx interrupt */
|
||
ssdk_printf(SSDK_DEBUG, "%s: chn %d rx int\n", __func__, chn);
|
||
dwmac_enable_dma_rx_int(reg_base, chn, false);
|
||
if (dwc_eth->rx_cb)
|
||
dwc_eth->rx_cb(dev);
|
||
}
|
||
if (sub_sts & BIT(0)) {
|
||
/* DMA tx interrupt */
|
||
ssdk_printf(SSDK_DEBUG, "%s: chn %d tx int\n", __func__, chn);
|
||
/* Nothing to do for now. */
|
||
}
|
||
}
|
||
}
|
||
exit_critical_section(state);//20250426 <20><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6><CFB1><EFBFBD>
|
||
return 0;
|
||
}
|
||
|
||
static int dwc_eqos_mdio_read(phy_bus_t *bus, uint32_t phyaddr,
|
||
uint32_t devaddr, uint32_t reg)
|
||
{
|
||
dwc_eth_dev_t *dwc_eth_dev = containerof(bus, dwc_eth_dev_t, phy_bus);
|
||
uint32_t reg_base = dwc_eth_dev->config->base;
|
||
|
||
return mac_mdio_read(reg_base, phyaddr, devaddr, reg);
|
||
}
|
||
|
||
static int dwc_eqos_mdio_write(phy_bus_t *bus, uint32_t phyaddr,
|
||
uint32_t devaddr, uint32_t reg, uint32_t data)
|
||
{
|
||
dwc_eth_dev_t *dwc_eth_dev = containerof(bus, dwc_eth_dev_t, phy_bus);
|
||
uint32_t reg_base = dwc_eth_dev->config->base;
|
||
|
||
return mac_mdio_write(reg_base, phyaddr, devaddr, reg, data);
|
||
}
|
||
|
||
static phy_bus_ops_t g_dwc_eqos_mdio_ops = {
|
||
.mdio_read = dwc_eqos_mdio_read,
|
||
.mdio_write = dwc_eqos_mdio_write
|
||
};
|
||
|
||
static void dwc_eth_phy_bus_init(phy_bus_t *bus)
|
||
{
|
||
list_initialize(&bus->phy_dev_list);
|
||
bus->ref_cnt = 0;
|
||
bus->ops = &g_dwc_eqos_mdio_ops;
|
||
}
|
||
|
||
static dwc_eth_dev_t *alloc_dwc_eth_device(void)
|
||
{
|
||
#if !CONFIG_ETH_USE_HEAP
|
||
for (int i = 0; i < MAX_ETH_CNT; i++) {
|
||
if (!g_eqos_data[i].used) {
|
||
g_eqos_data[i].used = true;
|
||
return &g_eqos_data[i].dev;
|
||
}
|
||
}
|
||
|
||
return NULL;
|
||
#else
|
||
return (dwc_eth_dev_t *)malloc(sizeof(dwc_eth_dev_t));
|
||
#endif
|
||
}
|
||
|
||
int dwc_eth_probe(struct net_driver_s *dev, dwc_eth_config_t *cfg)
|
||
{
|
||
ASSERT(dev && cfg);
|
||
|
||
dev->d_init = dwc_eth_init;
|
||
dev->d_txavail = dwc_eth_txavail;
|
||
dev->d_getmac = dwc_eth_getmac;
|
||
dev->d_getmtu = dwc_eth_getmtu;
|
||
|
||
dwc_eth_dev_t *dw_eth_dev = alloc_dwc_eth_device();
|
||
ASSERT(dw_eth_dev);
|
||
dw_eth_dev->init = false;
|
||
dw_eth_dev->config = cfg;
|
||
dev->d_private = dw_eth_dev;
|
||
|
||
dev->d_ipaddr.addr = (cfg->ip[3] << 24) | (cfg->ip[2] << 16) |
|
||
(cfg->ip[1] << 8) | cfg->ip[0];
|
||
dev->d_netmask.addr = (cfg->mask[3] << 24) | (cfg->mask[2] << 16) |
|
||
(cfg->mask[1] << 8) | cfg->mask[0];
|
||
dev->d_gateway.addr = (1 << 24) | (cfg->ip[2] << 16) |
|
||
(cfg->ip[1] << 8) | cfg->ip[0];
|
||
|
||
dwc_eth_phy_bus_init(&dw_eth_dev->phy_bus);
|
||
|
||
for (int i = 0; cfg->phy[i].phy_addr != ~0; i++) {
|
||
phy_dev_register(&dw_eth_dev->phy_bus, &cfg->phy[i]);
|
||
}
|
||
|
||
int ret = netdev_register(dev, NET_LL_ETHERNET);
|
||
|
||
irq_attach(cfg->irq_num, dwc_eth_irq_handler, dev);
|
||
irq_enable(cfg->irq_num);
|
||
|
||
return ret;
|
||
}
|