/*********************************************************************
*                    SEGGER Microcontroller GmbH                     *
*        Solutions for real time microcontroller applications        *
**********************************************************************
*                                                                    *
*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
*                                                                    *
* Internet: www.segger.com Support: support@segger.com               *
*                                                                    *
**********************************************************************
----------------------------------------------------------------------
Purpose : 
---------------------------END-OF-HEADER------------------------------
*/

/*********************************************************************
*
*       ResetTarget
*/
//void ResetTarget(void) {
//  In case cores 1-3 are reset, we do nothing, 
//  as we would lose connection to these cores, when resetting the device
//  as a reset disables the clock to them.
//}

/*********************************************************************
*
*       InitTarget
*/
int ConfigTargetSettings(void) {
  JLINK_SYS_Report("----------JLinkScript ConfigTargetSettings----------");
  JLINK_CPU                       = CORTEX_R5;
  JLINK_CORESIGHT_CoreBaseAddr    = 0xF2081000;
}

//static void disable_watchdog(U32 Addr) {
//  int ret;
//  ret = JLINK_MEM_ReadU32(Addr);
//  ret = ret & (~2);
//  JLINK_MEM_WriteU32(Addr, ret);
//}
//
//int AfterResetTarget(void){
//  JLINK_SYS_Report("----------JLinkScript AfterResetTarget----------");
//  disable_watchdog(0xF07E0000);
//  disable_watchdog(0xF07F0000);
//  disable_watchdog(0xF2100000);
//  disable_watchdog(0xF2110000);
//  disable_watchdog(0xF0BE0000);
//  disable_watchdog(0xF0BF0000);
//  disable_watchdog(0xF31F0000);
//  return 0;
//}