/** * @file g2dlite_reg.h * @brief SemiDrive G2DLite REG header file. * * @copyright Copyright (c) 2022 Semidrive Semiconductor. * All rights reserved. */ #ifndef G2DLITE_REG_H__ #define G2DLITE_REG_H__ #define REG(x) (x) #define G2D_RA000 REG(0x0) #define G2D_SHIFT31_RA000 31 #define G2D_MASK31_RA000 1UL << G2D_SHIFT31_RA000 #define G2D_SHIFT00_RA000 0 #define G2D_MASK00_RA000 1 << G2D_SHIFT00_RA000 #define G2D_RA004 REG(0x4) #define G2D_SHIFT00_RA004 0 #define G2D_MASK00_RA004 1 << G2D_SHIFT00_RA004 #define G2D_RA00C REG(0xc) #define G2D_SHIFT16_RA00C 16 #define G2D_MASK16_RA00C 0xFFFFUL << G2D_SHIFT16_RA00C #define G2D_SHIFT00_RA00C 0 #define G2D_MASK00_RA00C 0xFFFF << G2D_SHIFT00_RA00C #define G2D_RA010 REG(0x10) #define G2D_SHIFT02_RA010 2 #define G2D_MASK02_RA010 \ 0x3FFFFFFF << G2D_SHIFT02_RA010 #define G2D_RA014 REG(0x14) #define G2D_SHIFT00_RA014 0 #define G2D_MASK00_RA014 \ 0xFF << G2D_SHIFT00_RA014 #define G2D_RA018 REG(0x18) #define G2D_SHIFT00_RA018 0 #define G2D_MASK00_RA018 \ 0xFFFF << G2D_SHIFT00_RA018 #define G2D_RA01C REG(0x1c) #define G2D_SHIFT03_RA01C 3 #define G2D_MASK03_RA01C \ 1 << G2D_SHIFT03_RA01C #define G2D_SHIFT00_RA01C 0 #define G2D_MASK00_RA01C \ 0x7 << G2D_SHIFT00_RA01C #define G2D_RA020 REG(0x20) #define G2D_RA024 REG(0x24) #define G2D_SHIFT06_RA020 6 #define G2D_MASK06_RA020 1 << G2D_SHIFT06_RA020 #define G2D_SHIFT05_RA020 5 #define G2D_MASK05_RA020 1 << G2D_SHIFT05_RA020 #define G2D_SHIFT04_RA020 4 #define G2D_MASK04_RA020 1 << G2D_SHIFT04_RA020 #define G2D_SHIFT03_RA020 3 #define G2D_MASK03_RA020 1 << G2D_SHIFT03_RA020 #define G2D_SHIFT02_RA020 2 #define G2D_MASK02_RA020 1 << G2D_SHIFT02_RA020 #define G2D_SHIFT01_RA020 1 #define G2D_MASK01_RA020 1 << G2D_SHIFT01_RA020 #define G2D_SHIFT00_RA020 0 #define G2D_MASK00_RA020 1 << G2D_SHIFT00_RA020 #define G2D_RA030 REG(0x30) #define G2D_SHIFT31_RA030 31 #define G2D_MASK31_RA030 1 << G2D_SHIFT31_RA030 #define G2D_SHIFT00_RA030 0 #define G2D_MASK00_RA030 0x3FF << G2D_SHIFT00_RA030 /* RDMA */ #define CHN_JMP 0x20 #define CHN_COUNT 5 #define G2D_RB000(i) (REG(0x1000) + CHN_JMP * i) #define G2D_SHIFT00_RB000 0 #define G2D_MASK00_RB000 (0xFFFF << G2D_SHIFT00_RB000) #define G2D_RB004(i) (REG(0x1004) + CHN_JMP * i) #define G2D_SHIFT00_RB004 0 #define G2D_MASK00_RB004 (0xFFFF << G2D_SHIFT00_RB004) #define G2D_RB008(i) (REG(0x1008) + CHN_JMP * i) #define G2D_SHIFT00_RB008 0 #define G2D_MASK00_RB008 (0xFFFF << G2D_SHIFT00_RB008) #define G2D_RB00C(i) (REG(0x100c) + CHN_JMP * i) #define G2D_SHIFT16_RB00C 16 #define G2D_MASK16_RB00C 0x3f << G2D_SHIFT16_RB00C #define G2D_SHIFT08_RB00C 8 #define G2D_MASK08_RB00C 0x3f << G2D_SHIFT08_RB00C #define G2D_SHIFT00_RB00C 0 #define G2D_MASK00_RB00C 0x3f << G2D_SHIFT00_RB00C #define G2D_RB010(i) (REG(0x1010) + CHN_JMP * i) #define G2D_SHIFT03_RB010 3 #define G2D_MASK03_RB010 1 << G2D_SHIFT03_RB010 #define G2D_SHIFT00_RB010 0 #define G2D_MASK00_RB010 0x7 << G2D_SHIFT00_RB010 #define G2D_RB014(i) (REG(0x1014) + CHN_JMP * i) #define G2D_SHIFT00_RB014 0 #define G2D_MASK00_RB014 0xFFFFF << G2D_SHIFT00_RB014 #define G2D_RB018(i) (REG(0x1018) + CHN_JMP * i) #define G2D_SHIFT04_RB018 4 #define G2D_MASK04_RB018 0x3 << G2D_SHIFT04_RB018 #define G2D_SHIFT00_RB018 0 #define G2D_MASK00_RB018 0xF << G2D_SHIFT00_RB018 #define G2D_RB400 REG(0x1400) #define G2D_SHIFT01_RB400 1 #define G2D_MASK01_RB400 1 << G2D_SHIFT01_RB400 #define G2D_SHIFT00_RB400 0 #define G2D_MASK00_RB400 1 << G2D_SHIFT00_RB400 #define G2D_RB500 REG(0x1500) #define G2D_RB504 REG(0x1504) #define G2D_RB508 REG(0x1508) #define G2D_RB50C REG(0x150c) #define G2D_RB510 REG(0x1510) #define G2D_RB520 REG(0x1520) #define G2D_RB524 REG(0x1524) #define G2D_SHIFT04_RB520 4 #define G2D_MASK04_RB520 1UL << G2D_SHIFT04_RB520 #define G2D_SHIFT03_RB520 3 #define G2D_MASK03_RB520 1UL << G2D_SHIFT03_RB520 #define G2D_SHIFT02_RB520 2 #define G2D_MASK02_RB520 1UL << G2D_SHIFT02_RB520 #define G2D_SHIFT01_RB520 1 #define G2D_MASK01_RB520 1UL << G2D_SHIFT01_RB520 #define G2D_SHIFT00_RB520 0 #define G2D_MASK00_RB520 1UL << G2D_SHIFT00_RB520 #define G2D_RB540 REG(0x1540) #define G2D_SHIFT00_RB540 0 #define G2D_MASK00_RB540 0x1F << G2D_SHIFT00_RB540 #define G2D_RB544 REG(0x1544) #define G2D_SHIFT16_RB544 16 #define G2D_MASK16_RB544 0xFFFF << G2D_SHIFT16_RB544 #define G2D_SHIFT00_RB544 0 #define G2D_MASK00_RB544 0xFFFF << G2D_SHIFT00_RB544 /* GP */ #define G2D_RC000 REG(0x2000) #define G2D_SHIFT24_RC000 24 #define G2D_MASK24_RC000 0xF << G2D_SHIFT24_RC000 #define G2D_SHIFT16_RC000 16 #define G2D_MASK16_RC000 0xF << G2D_SHIFT16_RC000 #define G2D_SHIFT08_RC000 8 #define G2D_MASK08_RC000 0x1F << G2D_SHIFT08_RC000 #define G2D_SHIFT00_RC000 0 #define G2D_MASK00_RC000 0xF << G2D_SHIFT00_RC000 #define G2D_RC004 REG(0x2004) #define G2D_SHIFT16_RC004 16 #define G2D_MASK16_RC004 0x7 << G2D_SHIFT16_RC004 #define G2D_SHIFT12_RC004 12 #define G2D_MASK12_RC004 0xF << G2D_SHIFT12_RC004 #define G2D_SHIFT09_RC004 9 #define G2D_MASK09_RC004 0x7 << G2D_SHIFT09_RC004 #define G2D_SHIFT08_RC004 8 #define G2D_MASK08_RC004 1 << G2D_SHIFT08_RC004 #define G2D_SHIFT07_RC004 7 #define G2D_MASK07_RC004 1 << G2D_SHIFT07_RC004 #define G2D_SHIFT05_RC004 5 #define G2D_MASK05_RC004 0x3 << G2D_SHIFT05_RC004 #define G2D_SHIFT02_RC004 2 #define G2D_MASK02_RC004 0x7 << G2D_SHIFT02_RC004 #define G2D_SHIFT00_RC004 0 #define G2D_MASK00_RC004 0x3 << G2D_SHIFT00_RC004 #define G2D_RC008 REG(0x2008) #define G2D_SHIFT16_RC008 16 #define G2D_MASK16_RC008 0xFFFFUL << G2D_SHIFT16_RC008 #define G2D_SHIFT00_RC008 0 #define G2D_MASK00_RC008 0xFFFF << G2D_SHIFT00_RC008 #define G2D_RC00C REG(0x200c) #define G2D_SHIFT00_RC00C 0 #define G2D_MASK00_RC00C 0xFFFFFFFF << G2D_SHIFT00_RC00C #define G2D_RC010 REG(0x2010) #define G2D_SHIFT00_RC010 0 #define G2D_MASK00_RC010 0xFF << G2D_SHIFT00_RC010 #define G2D_RC014 REG(0x2014) #define G2D_SHIFT00_RC014 0 #define G2D_MASK00_RC014 0xFFFFFFFF << G2D_SHIFT00_RC014 #define G2D_RC018 REG(0x2018) #define G2D_SHIFT00_RC018 0 #define G2D_MASK00_RC018 0xFF << G2D_SHIFT00_RC018 #define G2D_RC01C REG(0x201c) #define G2D_SHIFT00_RC01C 0 #define G2D_MASK00_RC01C 0xFFFFFFFF << G2D_SHIFT00_RC01C #define G2D_RC020 REG(0x2020) #define G2D_SHIFT00_RC020 0 #define G2D_MASK00_RC020 0xFF << G2D_SHIFT00_RC020 #define G2D_RC02C REG(0x202c) #define G2D_SHIFT00_RC02C 0 #define G2D_MASK00_RC02C 0x3FFFFUL << G2D_SHIFT00_RC02C #define G2D_RC030 REG(0x2030) #define G2D_SHIFT00_RC030 0 #define G2D_MASK00_RC030 0x3FFFFUL << G2D_SHIFT00_RC030 #define G2D_RC034 REG(0x2034) #define G2D_SHIFT00_RC034 0 #define G2D_MASK00_RC034 0x3FFFFUL << G2D_SHIFT00_RC034 #define G2D_RC040 REG(0x2040) #define FRM_Y_SHIFT 16 #define FRM_Y_MASK 0xFFFFUL << FRM_Y_SHIFT #define FRM_X_SHIFT 0 #define FRM_X_MASK 0xFFFFUL << FRM_X_SHIFT #define G2D_RC044 REG(0x2044) #define G2D_SHIFT31_RC044 31 #define G2D_MASK31_RC044 0x1UL << G2D_SHIFT31_RC044 #define G2D_SHIFT06_RC044 6 #define G2D_MASK06_RC044 0x3 << G2D_SHIFT06_RC044 #define G2D_SHIFT04_RC044 4 #define G2D_MASK04_RC044 0x3 << G2D_SHIFT04_RC044 #define G2D_SHIFT03_RC044 3 #define G2D_MASK03_RC044 \ 0x1 << G2D_SHIFT03_RC044 #define G2D_SHIFT02_RC044 2 #define G2D_MASK02_RC044 \ 0x1 << G2D_SHIFT02_RC044 #define G2D_SHIFT01_RC044 1 #define G2D_MASK01_RC044 \ 0x1 << G2D_SHIFT01_RC044 #define G2D_SHIFT00_RC044 0 #define G2D_MASK00_RC044 0x1 << G2D_SHIFT00_RC044 #define G2D_RC100 REG(0x2100) #define G2D_SHIFT00_RC100 0 #define G2D_MASK00_RC100 0x1 << G2D_SHIFT00_RC100 #define G2D_RC104 REG(0x2104) #define G2D_SHIFT16_RC104 16 #define G2D_MASK16_RC104 0xFFFF << G2D_SHIFT16_RC104 #define G2D_SHIFT00_RC104 0 #define G2D_MASK00_RC104 0xFFFF << G2D_SHIFT00_RC104 #define G2D_RC108 REG(0x2108) #define G2D_SHIFT16_RC108 16 #define G2D_MASK16_RC108 0xFFFFUL << G2D_SHIFT16_RC108 #define G2D_SHIFT00_RC108 0 #define G2D_MASK00_RC108 0xFFFF << G2D_SHIFT00_RC108 #define G2D_RC120 REG(0x2120) #define G2D_SHIFT00_RC120 0 #define G2D_MASK00_RC120 0x1 << G2D_SHIFT00_RC120 /*GP CSC*/ #define G2D_RC200 REG(0x2200) #define G2D_SHIFT02_RC200 2 #define G2D_MASK02_RC200 0x1 << G2D_SHIFT02_RC200 #define G2D_SHIFT01_RC200 1 #define G2D_MASK01_RC200 0x1 << G2D_SHIFT01_RC200 #define G2D_SHIFT00_RC200 0 #define G2D_MASK00_RC200 0x1 << G2D_SHIFT00_RC200 #define G2D_RC204 REG(0x2204) #define G2D_SHIFT16_RC204 16 #define G2D_MASK16_RC204 0x3FFF << G2D_SHIFT16_RC204 #define G2D_SHIFT00_RC204 0 #define G2D_MASK00_RC204 0x3FFF << G2D_SHIFT00_RC204 #define G2D_RC208 REG(0x2208) #define G2D_SHIFT16_RC208 16 #define G2D_MASK16_RC208 0x3FFF << G2D_SHIFT16_RC208 #define G2D_SHIFT00_RC208 0 #define G2D_MASK00_RC208 0x3FFF << G2D_SHIFT00_RC208 #define G2D_RC20C REG(0x220c) #define G2D_SHIFT16_RC20C 16 #define G2D_MASK16_RC20C 0x3FFF << G2D_SHIFT16_RC20C #define G2D_SHIFT00_RC20C 0 #define G2D_MASK00_RC20C 0x3FFF << G2D_SHIFT00_RC20C #define G2D_RC210 REG(0x2210) #define G2D_SHIFT16_RC210 16 #define G2D_MASK16_RC210 0x3FFF << G2D_SHIFT16_RC210 #define G2D_SHIFT00_RC210 0 #define G2D_MASK00_RC210 0x3FFF << G2D_SHIFT00_RC210 #define G2D_RC214 REG(0x2214) #define G2D_SHIFT16_RC214 16 #define G2D_MASK16_RC214 0x3FFF << G2D_SHIFT16_RC214 #define G2D_SHIFT00_RC214 0 #define G2D_MASK00_RC214 0x3FFF << G2D_SHIFT00_RC214 #define G2D_RC218 REG(0x2218) #define G2D_SHIFT16_RC218 16 #define G2D_MASK16_RC218 0x3FFF << G2D_SHIFT16_RC218 #define G2D_SHIFT00_RC218 0 #define G2D_MASK00_RC218 0x3FFF << G2D_SHIFT00_RC218 #define G2D_RC21C REG(0x221c) #define G2D_SHIFT16_RC21C 16 #define G2D_MASK16_RC21C 0x3FF << G2D_SHIFT16_RC21C #define G2D_SHIFT00_RC21C 0 #define G2D_MASK00_RC21C 0x3FF << G2D_SHIFT00_RC21C #define G2D_RC220 REG(0x2220) #define G2D_SHIFT00_RC220 0 #define G2D_MASK00_RC220 0x3FF << G2D_SHIFT00_RC220 #define G2D_RC300 REG(0x2300) #define G2D_SHIFT08_RC300 8 #define G2D_MASK08_RC300 0xF << G2D_SHIFT08_RC300 #define G2D_SHIFT04_RC300 4 #define G2D_MASK04_RC300 1 << G2D_SHIFT04_RC300 #define G2D_SHIFT03_RC300 3 #define G2D_MASK03_RC300 1 << G2D_SHIFT03_RC300 #define G2D_SHIFT02_RC300 2 #define G2D_MASK02_RC300 1 << G2D_SHIFT02_RC300 #define G2D_SHIFT01_RC300 1 #define G2D_MASK01_RC300 1 << G2D_SHIFT01_RC300 #define G2D_SHIFT00_RC300 0 #define G2D_MASK00_RC300 1 << G2D_SHIFT00_RC300 #define G2D_RC304 REG(0x2304) #define G2D_SHIFT19_RC304 19 #define G2D_MASK19_RC304 1 << G2D_SHIFT19_RC304 #define G2D_SHIFT00_RC304 0 #define G2D_MASK00_RC304 0x7FFFF << G2D_SHIFT00_RC304 #define G2D_RC308 REG(0x2308) #define G2D_SHIFT19_RC308 19 #define G2D_MASK19_RC308 0x7 << G2D_SHIFT19_RC308 #define G2D_SHIFT00_RC308 0 #define G2D_MASK00_RC308 0x7FFFF << G2D_SHIFT00_RC308 #define G2D_RC30C REG(0x230c) #define G2D_SHIFT00_RC30C 0 #define G2D_MASK00_RC30C 0xFFFF << G2D_SHIFT00_RC30C #define G2D_RC400 REG(0x2400) #define G2D_SHIFT04_RC400 4 #define G2D_MASK04_RC400 0xF << G2D_SHIFT04_RC400 #define G2D_SHIFT03_RC400 3 #define G2D_MASK03_RC400 1 << G2D_SHIFT03_RC400 #define G2D_SHIFT02_RC400 2 #define G2D_MASK02_RC400 1 << G2D_SHIFT02_RC400 #define G2D_SHIFT00_RC400 0 #define G2D_MASK00_RC400 0x3 << G2D_SHIFT00_RC400 #define G2D_RC404 REG(0x2404) #define G2D_SHIFT00_RC404 0 #define G2D_MASK00_RC404 0xFFFF << G2D_SHIFT00_RC404 #define G2D_RC408 REG(0x2408) #define G2D_SHIFT00_RC408 0 #define G2D_MASK00_RC408 0x1FFFFF << G2D_SHIFT00_RC408 #define G2D_RC40C REG(0x240c) #define G2D_RC410 REG(0x2410) #define G2D_SHIFT18_RC40C 18 #define G2D_MASK18_RC40C 0x3 << G2D_SHIFT18_RC40C #define G2D_SHIFT00_RC40C 0 #define G2D_MASK00_RC40C \ 0X3FFFF << G2D_SHIFT00_RC40C #define G2D_RC414 REG(0x2414) #define G2D_SHIFT02_RC414 2 #define G2D_MASK02_RC414 1 << G2D_SHIFT02_RC414 #define G2D_SHIFT01_RC414 1 #define G2D_MASK01_RC414 1 << G2D_SHIFT01_RC414 #define G2D_SHIFT00_RC414 0 #define G2D_MASK00_RC414 1 << G2D_SHIFT00_RC414 #define G2D_RCF00 REG(0x2f00) #define G2D_SHIFT00_RCF00 0 #define G2D_MASK00_RCF00 1 << G2D_SHIFT00_RCF00 /* SP */ #define G2D_RD000 REG(0x5000) /* SHIFT MASK define see G2D_GP_XX area */ #define G2D_RD004 REG(0x5004) #define G2D_RD008 REG(0x5008) #define G2D_RD00C REG(0x500c) #define G2D_RD010 REG(0x5010) #define G2D_RD02C REG(0x502c) #define G2D_RD040 REG(0x5040) /* SHIFT MASK define see G2D_GP_XX area */ /* RLE */ #define G2D_RD100 REG(0x5100) #define G2D_SHIFT00_RD100 0 #define G2D_MASK00_RD100 0xFFFFFF << G2D_SHIFT00_RD100 #define G2D_RD110 REG(0x5110) #define G2D_SHIFT00_RD110 0 #define G2D_MASK00_RD110 0xFFFFFFFF << G2D_SHIFT00_RD110 #define G2D_RD120 REG(0x5120) #define G2D_SHIFT01_RD120 1 #define G2D_MASK01_RD120 0x3 << G2D_SHIFT01_RD120 #define G2D_SHIFT00_RD120 0 #define G2D_MASK00_RD120 0x1 << G2D_SHIFT00_RD120 #define G2D_RD130 REG(0x5130) #define G2D_RD134 REG(0x5134) #define G2D_RD138 REG(0x5138) #define G2D_RD13C REG(0x513c) #define G2D_RD140 REG(0x5140) #define G2D_RD144 REG(0x5144) #define G2D_SHIFT03_RD140 3 #define G2D_MASK03_RD140 0x1 << G2D_SHIFT03_RD140 #define G2D_SHIFT02_RD140 2 #define G2D_MASK02_RD140 0x1 << G2D_SHIFT02_RD140 #define G2D_SHIFT01_RD140 1 #define G2D_MASK01_RD140 0x1 << G2D_SHIFT01_RD140 #define G2D_SHIFT00_RD140 0 #define G2D_MASK00_RD140 0x1 << G2D_SHIFT00_RD140 /* CLUT */ #define G2D_RD200 REG(0x5200) #define G2D_SHIFT18_RD200 18 #define G2D_MASK18_RD200 0x1 << G2D_SHIFT18_RD200 #define G2D_SHIFT17_RD200 17 #define G2D_MASK17_RD200 0x1 << G2D_SHIFT17_RD200 #define G2D_SHIFT16_RD200 16 #define G2D_MASK16_RD200 0x1 << G2D_SHIFT16_RD200 #define G2D_SHIFT08_RD200 8 #define G2D_MASK08_RD200 0xFF << G2D_SHIFT08_RD200 #define G2D_SHIFT00_RD200 0 #define G2D_MASK00_RD200 0xF << G2D_SHIFT00_RD200 #define G2D_RD204 REG(0x5204) #define G2D_SHIFT16_RD204 16 #define G2D_MASK16_RD204 0x1 << G2D_SHIFT16_RD204 #define G2D_SHIFT08_RD204 8 #define G2D_MASK08_RD204 0xFF << G2D_SHIFT08_RD204 #define G2D_SHIFT00_RD204 0 #define G2D_MASK00_RD204 0xF << G2D_SHIFT00_RD204 #define G2D_RD208 REG(0x5208) #define G2D_SHIFT17_RD208 17 #define G2D_MASK17_RD208 0x1 << G2D_SHIFT17_RD208 #define G2D_SHIFT16_RD208 16 #define G2D_MASK16_RD208 0x1 << G2D_SHIFT16_RD208 #define G2D_SHIFT08_RD208 8 #define G2D_MASK08_RD208 0xFF << G2D_SHIFT08_RD208 #define G2D_SHIFT00_RD208 0 #define G2D_MASK00_RD208 0xF << G2D_SHIFT00_RD208 #define G2D_RD20C REG(0x520c) #define G2D_SHIFT17_RD20C 17 #define G2D_MASK17_RD20C 0x1 << G2D_SHIFT17_RD20C #define G2D_SHIFT16_RD20C 16 #define G2D_MASK16_RD20C 0x1 << G2D_SHIFT16_RD20C #define G2D_SHIFT08_RD20C 8 #define G2D_MASK08_RD20C 0xFF << G2D_SHIFT08_RD20C #define G2D_SHIFT00_RD20C 0 #define G2D_MASK00_RD20C 0xF << G2D_SHIFT00_RD20C #define G2D_RD210 REG(0x5210) #define G2D_SHIFT03_RD210 3 #define G2D_MASK03_RD210 0x1 << G2D_SHIFT03_RD210 #define G2D_SHIFT02_RD210 2 #define G2D_MASK02_RD210 0x1 << G2D_SHIFT02_RD210 #define G2D_SHIFT01_RD210 1 #define G2D_MASK01_RD210 0x1 << G2D_SHIFT01_RD210 #define G2D_SHIFT00_RD210 0 #define G2D_MASK00_RD210 0x1 << G2D_SHIFT00_RD210 /* SP_SDW_CTRL */ #define G2D_RDF00 REG(0x5f00) #define G2D_SHIFT00_RDF00 0 #define G2D_MASK00_RDF00 0x1 << G2D_SHIFT00_RDF00 /*MLC*/ #define MLC_LAYER_JMP 0x30 #define MLC_LAYER_COUNT 2 #define MLC_PATH_JMP 0x4 #define MLC_PATH_COUNT 3 #define G2D_RE000(i) (REG(0x7000) + MLC_LAYER_JMP * i) #define G2D_SHIFT08_RE000 8 #define G2D_MASK08_RE000 0x3F << G2D_SHIFT08_RE000 #define G2D_SHIFT07_RE000 7 #define G2D_MASK07_RE000 0x1 << G2D_SHIFT07_RE000 #define G2D_SHIFT06_RE000 6 #define G2D_MASK06_RE000 0x1 << G2D_SHIFT06_RE000 #define G2D_SHIFT05_RE000 5 #define G2D_MASK05_RE000 0x1 << G2D_SHIFT05_RE000 #define G2D_SHIFT04_RE000 4 #define G2D_MASK04_RE000 0x1 << G2D_SHIFT04_RE000 #define G2D_SHIFT03_RE000 3 #define G2D_MASK03_RE000 0x1 << G2D_SHIFT03_RE000 #define G2D_SHIFT02_RE000 2 #define G2D_MASK02_RE000 0x1 << G2D_SHIFT02_RE000 #define G2D_SHIFT01_RE000 1 #define G2D_MASK01_RE000 0x1 << G2D_SHIFT01_RE000 #define G2D_SHIFT00_RE000 0 #define G2D_MASK00_RE000 0x1 << G2D_SHIFT00_RE000 #define G2D_RE004(i) (REG(0x7004) + MLC_LAYER_JMP * i) #define G2D_SHIFT00_RE004 0 #define G2D_MASK00_RE004 0x1FFFF << G2D_SHIFT00_RE004 #define G2D_RE008(i) (REG(0x7008) + MLC_LAYER_JMP * i) #define G2D_SHIFT00_RE008 0 #define G2D_MASK00_RE008 0x1FFFF << G2D_SHIFT00_RE008 #define G2D_RE00C(i) (REG(0x700c) + MLC_LAYER_JMP * i) #define G2D_SHIFT16_RE00C 16 #define G2D_MASK16_RE00C 0xFFFFUL << G2D_SHIFT16_RE00C #define G2D_SHIFT00_RE00C 0 #define G2D_MASK00_RE00C 0xFFFF << G2D_SHIFT00_RE00C #define G2D_RE010(i) (REG(0x7010) + MLC_LAYER_JMP * i) #define G2D_RE014(i) (REG(0x7014) + MLC_LAYER_JMP * i) #define G2D_SHIFT16_RE010 16 #define G2D_MASK16_RE010 0xFFFF << G2D_SHIFT16_RE010 #define G2D_SHIFT00_RE010 0 #define G2D_MASK00_RE010 0xFFFF << G2D_SHIFT00_RE010 #define G2D_RE018(i) (REG(0x7018) + MLC_LAYER_JMP * i) #define G2D_SHIFT00_RE018 0 #define G2D_MASK00_RE018 0xFF << G2D_SHIFT00_RE018 #define G2D_RE01C(i) (REG(0x701c) + MLC_LAYER_JMP * i) #define G2D_SHIFT00_RE01C 0 #define G2D_MASK00_RE01C 0xFF << G2D_SHIFT00_RE01C #define G2D_RE020(i) (REG(0x7020) + MLC_LAYER_JMP * i) #define G2D_RE024(i) (REG(0x7024) + MLC_LAYER_JMP * i) #define G2D_RE028(i) (REG(0x7028) + MLC_LAYER_JMP * i) #define G2D_SHIFT16_RE020 16 #define G2D_MASK16_RE020 0x3FF << G2D_SHIFT16_RE020 #define G2D_SHIFT00_RE020 0 #define G2D_MASK00_RE020 0x3FF << G2D_SHIFT00_RE020 #define G2D_RE02C(i) (REG(0x702c) + MLC_LAYER_JMP * i) #define G2D_SHIFT00_RE02C 0 #define G2D_MASK00_RE02C 0xFFFFFFFF << G2D_SHIFT00_RE02C #define G2D_RE200(i) (REG(0x7200) + MLC_PATH_JMP * i) #define G2D_SHIFT29_RE200 29 #define G2D_MASK29_RE200 0x1 << G2D_SHIFT29_RE200 #define G2D_SHIFT28_RE200 28 #define G2D_MASK28_RE200 0x1 << G2D_SHIFT28_RE200 #define G2D_SHIFT20_RE200 20 #define G2D_MASK20_RE200 0x1F << G2D_SHIFT20_RE200 #define G2D_SHIFT16_RE200 16 #define G2D_MASK16_RE200 0xF << G2D_SHIFT16_RE200 #define G2D_SHIFT12_RE200 12 #define G2D_MASK12_RE200 0x7 << G2D_SHIFT12_RE200 #define G2D_SHIFT08_RE200 8 #define G2D_MASK08_RE200 0x7 << G2D_SHIFT08_RE200 #define G2D_SHIFT04_RE200 4 #define G2D_MASK04_RE200 0x7 << G2D_SHIFT04_RE200 #define G2D_SHIFT00_RE200 0 #define G2D_MASK00_RE200 0xF << G2D_SHIFT00_RE200 #define G2D_RE220 REG(0x7220) #define G2D_SHIFT08_RE220 8 #define G2D_MASK08_RE220 0xFF << G2D_SHIFT08_RE220 #define G2D_SHIFT07_RE220 7 #define G2D_MASK07_RE220 0x1 << G2D_SHIFT07_RE220 #define G2D_SHIFT04_RE220 4 #define G2D_MASK04_RE220 0x7 << G2D_SHIFT04_RE220 #define G2D_SHIFT02_RE220 2 #define G2D_MASK02_RE220 0x1 << G2D_SHIFT02_RE220 #define G2D_SHIFT01_RE220 1 #define G2D_MASK01_RE220 0x1 << G2D_SHIFT01_RE220 #define G2D_SHIFT00_RE220 0 #define G2D_MASK00_RE220 0x1 << G2D_SHIFT00_RE220 #define G2D_RE224 REG(0x7224) #define G2D_SHIFT20_RE224 20 #define G2D_MASK20_RE224 0x3FF << G2D_SHIFT20_RE224 #define G2D_SHIFT10_RE224 10 #define G2D_MASK10_RE224 0x3FF << G2D_SHIFT10_RE224 #define G2D_SHIFT00_RE224 0 #define G2D_MASK00_RE224 0x3FF << G2D_SHIFT00_RE224 #define G2D_RE228 REG(0x7228) #define G2D_SHIFT00_RE228 0 #define G2D_MASK00_RE228 0xFFFFFFFF << G2D_SHIFT00_RE228 #define G2D_RE230 REG(0x7230) #define G2D_SHIFT20_RE230 20 #define G2D_MASK20_RE230 0x3FF << G2D_SHIFT20_RE230 #define G2D_SHIFT10_RE230 10 #define G2D_MASK10_RE230 0x3FF << G2D_SHIFT10_RE230 #define G2D_SHIFT00_RE230 0 #define G2D_MASK00_RE230 0x3FF << G2D_SHIFT00_RE230 #define G2D_RE234 REG(0x7234) #define G2D_SHIFT00_RE234 0 #define G2D_MASK00_RE234 0xFFFF << G2D_SHIFT00_RE234 #define G2D_RE240 REG(0x7240) #define G2D_SHIFT12_RE240 12 #define G2D_MASK12_RE240 0x1 << G2D_SHIFT12_RE240 #define G2D_SHIFT11_RE240 11 #define G2D_MASK11_RE240 0x1 << G2D_SHIFT11_RE240 #define G2D_SHIFT10_RE240 10 #define G2D_MASK10_RE240 0x1 << G2D_SHIFT10_RE240 #define G2D_SHIFT09_RE240 9 #define G2D_MASK09_RE240 0x1 << G2D_SHIFT09_RE240 #define G2D_SHIFT08_RE240 8 #define G2D_MASK08_RE240 0x1 << G2D_SHIFT08_RE240 #define G2D_SHIFT07_RE240 7 #define G2D_MASK07_RE240 0x1 << G2D_SHIFT07_RE240 #define G2D_SHIFT06_RE240 6 #define G2D_MASK06_RE240 0x1 << G2D_SHIFT06_RE240 #define G2D_SHIFT05_RE240 5 #define G2D_MASK05_RE240 0x1 << G2D_SHIFT05_RE240 #define G2D_SHIFT04_RE240 4 #define G2D_MASK04_RE240 0x1 << G2D_SHIFT04_RE240 #define G2D_SHIFT03_RE240 3 #define G2D_MASK03_RE240 0x1 << G2D_SHIFT03_RE240 #define G2D_SHIFT02_RE240 2 #define G2D_MASK02_RE240 0x1 << G2D_SHIFT02_RE240 #define G2D_SHIFT01_RE240 1 #define G2D_MASK01_RE240 0x1 << G2D_SHIFT01_RE240 #define G2D_SHIFT00_RE240 0 #define G2D_MASK00_RE240 0x1 << G2D_SHIFT00_RE240 #define G2D_RE244 REG(0x7244) #define G2D_SHIFT27_RE244 27 #define G2D_MASK27_RE244 0x1 << G2D_SHIFT27_RE244 #define G2D_SHIFT26_RE244 26 #define G2D_MASK26_RE244 0x1 << G2D_SHIFT26_RE244 #define G2D_SHIFT25_RE244 25 #define G2D_MASK25_RE244 0x1 << G2D_SHIFT25_RE244 #define G2D_SHIFT24_RE244 24 #define G2D_MASK24_RE244 0x1 << G2D_SHIFT24_RE244 #define G2D_SHIFT23_RE244 23 #define G2D_MASK23_RE244 0x1 << G2D_SHIFT23_RE244 #define G2D_SHIFT22_RE244 22 #define G2D_MASK22_RE244 0x1 << G2D_SHIFT22_RE244 #define G2D_SHIFT21_RE244 21 #define G2D_MASK21_RE244 0x1 << G2D_SHIFT21_RE244 #define G2D_SHIFT20_RE244 20 #define G2D_MASK20_RE244 0x1 << G2D_SHIFT20_RE244 #define G2D_SHIFT19_RE244 19 #define G2D_MASK19_RE244 0x1 << G2D_SHIFT19_RE244 #define G2D_SHIFT18_RE244 18 #define G2D_MASK18_RE244 0x1 << G2D_SHIFT18_RE244 #define G2D_SHIFT17_RE244 17 #define G2D_MASK17_RE244 0x1 << G2D_SHIFT17_RE244 #define G2D_SHIFT16_RE244 16 #define G2D_MASK16_RE244 0x1 << G2D_SHIFT16_RE244 #define G2D_SHIFT12_RE244 12 #define G2D_MASK12_RE244 0x1 << G2D_SHIFT12_RE244 #define G2D_SHIFT11_RE244 11 #define G2D_MASK11_RE244 0x1 << G2D_SHIFT11_RE244 #define G2D_SHIFT10_RE244 10 #define G2D_MASK10_RE244 0x1 << G2D_SHIFT10_RE244 #define G2D_SHIFT09_RE244 9 #define G2D_MASK09_RE244 0x1 << G2D_SHIFT09_RE244 #define G2D_SHIFT08_RE244 8 #define G2D_MASK08_RE244 0x1 << G2D_SHIFT08_RE244 #define G2D_SHIFT07_RE244 7 #define G2D_MASK07_RE244 0x1 << G2D_SHIFT07_RE244 #define G2D_SHIFT06_RE244 6 #define G2D_MASK06_RE244 0x1 << G2D_SHIFT06_RE244 #define G2D_SHIFT05_RE244 5 #define G2D_MASK05_RE244 0x1 << G2D_SHIFT05_RE244 #define G2D_SHIFT04_RE244 4 #define G2D_MASK04_RE244 0x1 << G2D_SHIFT04_RE244 #define G2D_SHIFT03_RE244 3 #define G2D_MASK03_RE244 0x1 << G2D_SHIFT03_RE244 #define G2D_SHIFT02_RE244 2 #define G2D_MASK02_RE244 0x1 << G2D_SHIFT02_RE244 #define G2D_SHIFT01_RE244 1 #define G2D_MASK01_RE244 0x1 << G2D_SHIFT01_RE244 #define G2D_SHIFT00_RE244 0 #define G2D_MASK00_RE244 0x1 << G2D_SHIFT00_RE244 /*AP*/ #define G2D_RF000 REG(0x9000) #define G2D_SHIFT00_RF000 0 #define G2D_MASK00_RF000 0xF << G2D_SHIFT00_RF000 #define G2D_RF004 REG(0x9004) #define G2D_SHIFT16_RF004 16 #define G2D_MASK16_RF004 0x7 << G2D_SHIFT16_RF004 #define G2D_SHIFT08_RF004 8 #define G2D_MASK08_RF004 0x7 << G2D_SHIFT08_RF004 #define G2D_SHIFT00_RF004 0 #define G2D_MASK00_RF004 0x1 << G2D_SHIFT00_RF004 #define G2D_RF008 REG(0x9008) #define G2D_SHIFT16_RF008 16 #define G2D_MASK16_RF008 0xFFFFUL << G2D_SHIFT16_RF008 #define G2D_SHIFT00_RF008 0 #define G2D_MASK00_RF008 0xFFFF << G2D_SHIFT00_RF008 #define G2D_RF00C REG(0x900c) #define G2D_SHIFT00_RF00C 0 #define G2D_MASK00_RF00C 0xFFFFFFFF << G2D_SHIFT00_RF00C #define G2D_RF010 REG(0x9010) #define G2D_SHIFT00_RF010 0 #define G2D_MASK00_RF010 0xFFFFFFFF << G2D_SHIFT00_RF010 #define G2D_RF02C REG(0x902c) #define G2D_SHIFT00_RF02C 0 #define G2D_MASK00_RF02C 0x3FFFF << G2D_SHIFT00_RF02C #define G2D_RF040 REG(0x9040) #define G2D_SHIFT16_RF040 16 #define G2D_MASK16_RF040 0xFFFF << G2D_SHIFT16_RF040 #define G2D_SHIFT00_RF040 0 #define G2D_MASK00_RF040 0xFFFF << G2D_SHIFT00_RF040 /* AP_SDW_CTRL */ #define G2D_RFF00 REG(0x9f00) #define G2D_SHIFT00_RFF00 0 #define G2D_MASK00_RFF00 0x1 << G2D_SHIFT00_RFF00 /*wdma*/ #define WCHN_JUMP 0x20 #define WCHN_COUNT 3 #define G2D_RG000(i) (REG(0xa000) + WCHN_JUMP * i) #define G2D_SHIFT00_RG000 0 #define G2D_MASK00_RG000 0xFFFF << G2D_SHIFT00_RG000 #define G2D_RG004(i) (REG(0xa004) + WCHN_JUMP * i) #define G2D_SHIFT00_RG004 0 #define G2D_MASK00_RG004 0xFFFF << G2D_SHIFT00_RG004 #define G2D_RG008(i) (REG(0xa008) + WCHN_JUMP * i) #define G2D_SHIFT00_RG008 0 #define G2D_MASK00_RG008 0xFFFF << G2D_SHIFT00_RG008 #define G2D_RG00C(i) (REG(0xa00c) + WCHN_JUMP * i) #define G2D_SHIFT16_RG00C 16 #define G2D_MASK16_RG00C 0x3F << G2D_SHIFT16_RG00C #define G2D_SHIFT08_RG00C 8 #define G2D_MASK08_RG00C 0x3F << G2D_SHIFT08_RG00C #define G2D_SHIFT00_RG00C 0 #define G2D_MASK00_RG00C 0x3F << G2D_SHIFT00_RG00C #define G2D_RG010(i) (REG(0xa010) + WCHN_JUMP * i) #define G2D_SHIFT03_RG010 3 #define G2D_MASK03_RG010 1 << G2D_SHIFT03_RG010 #define G2D_SHIFT00_RG010 0 #define G2D_MASK00_RG010 0x7 << G2D_SHIFT00_RG010 #define G2D_RG014(i) (REG(0xa014) + WCHN_JUMP * i) #define G2D_SHIFT00_RG014 0 #define G2D_MASK00_RG014 0xFFFFF << G2D_SHIFT00_RG014 #define G2D_RG018(i) (REG(0xa018) + WCHN_JUMP * i) #define G2D_SHIFT07_RG018 7 #define G2D_MASK07_RG018 1 << G2D_SHIFT07_RG018 #define G2D_SHIFT06_RG018 6 #define G2D_MASK06_RG018 1 << G2D_SHIFT06_RG018 #define G2D_SHIFT04_RG018 4 #define G2D_MASK04_RG018 0x3 << G2D_SHIFT04_RG018 #define G2D_SHIFT00_RG018 0 #define G2D_MASK00_RG018 0xF << G2D_SHIFT00_RG018 #define G2D_RG400 REG(0xa400) #define G2D_SHIFT01_RG400 1 #define G2D_MASK01_RG400 1 << G2D_SHIFT01_RG400 #define G2D_SHIFT00_RG400 0 #define G2D_MASK00_RG400 1 << G2D_SHIFT00_RG400 #define G2D_RG500 REG(0xa500) #define G2D_SHIFT02_RG500 2 #define G2D_MASK02_RG500 1 << G2D_SHIFT02_RG500 #define G2D_SHIFT01_RG500 1 #define G2D_MASK01_RG500 1 << G2D_SHIFT01_RG500 #define G2D_SHIFT00_RG500 0 #define G2D_MASK00_RG500 1 << G2D_SHIFT00_RG500 #define G2D_RG504 REG(0xa504) #define G2D_SHIFT02_RG504 2 #define G2D_MASK02_RG504 1 << G2D_SHIFT02_RG504 #define G2D_SHIFT01_RG504 1 #define G2D_MASK01_RG504 1 << G2D_SHIFT01_RG504 #define G2D_SHIFT00_RG504 0 #define G2D_MASK00_RG504 1 << G2D_SHIFT00_RG504 #define G2D_RG508 REG(0xa508) #define G2D_SHIFT02_RG508 2 #define G2D_MASK02_RG508 1 << G2D_SHIFT02_RG508 #define G2D_SHIFT01_RG508 1 #define G2D_MASK01_RG508 1 << G2D_SHIFT01_RG508 #define G2D_SHIFT00_RG508 0 #define G2D_MASK00_RG508 1 << G2D_SHIFT00_RG508 #define G2D_RG50C REG(0xa50c) #define G2D_SHIFT02_RG50C 2 #define G2D_MASK02_RG50C 1 << G2D_SHIFT02_RG50C #define G2D_SHIFT01_RG50C 1 #define G2D_MASK01_RG50C 1 << G2D_SHIFT01_RG50C #define G2D_SHIFT00_RG50C 0 #define G2D_MASK00_RG50C 1 << G2D_SHIFT00_RG50C #define G2D_RG510 REG(0xa510) #define G2D_SHIFT02_RG510 2 #define G2D_MASK02_RG510 1 << G2D_SHIFT02_RG510 #define G2D_SHIFT01_RG510 1 #define G2D_MASK01_RG510 1 << G2D_SHIFT01_RG510 #define G2D_SHIFT00_RG510 0 #define G2D_MASK00_RG510 1 << G2D_SHIFT00_RG510 #define G2D_RG520 REG(0xa520) #define G2D_SHIFT02_RG520 2 #define G2D_MASK02_RG520 1 << G2D_SHIFT02_RG520 #define G2D_SHIFT01_RG520 1 #define G2D_MASK01_RG520 1 << G2D_SHIFT01_RG520 #define G2D_SHIFT00_RG520 0 #define G2D_MASK00_RG520 1 << G2D_SHIFT00_RG520 #define G2D_RG524 REG(0xa524) #define G2D_SHIFT02_RG524 2 #define G2D_MASK02_RG524 1 << G2D_SHIFT02_RG524 #define G2D_SHIFT01_RG524 1 #define G2D_MASK01_RG524 1 << G2D_SHIFT01_RG524 #define G2D_SHIFT00_RG524 0 #define G2D_MASK00_RG524 1 << G2D_SHIFT00_RG524 #define G2D_RG540 REG(0xa540) #define G2D_SHIFT00_RG540 0 #define G2D_MASK00_RG540 0x1F << G2D_SHIFT00_RG540 #define G2D_RG544 REG(0xa544) #define G2D_SHIFT16_RG544 16 #define G2D_MASK16_RG544 0xFFFF << G2D_SHIFT16_RG544 #define G2D_SHIFT00_RG544 0 #define G2D_MASK00_RG544 0xFFFF << G2D_SHIFT00_RG544 /*W-PIPE*/ #define G2D_RH000 REG(0xb000) #define G2D_SHIFT16_RH000 16 #define G2D_MASK16_RH000 0x7 << G2D_SHIFT16_RH000 #define G2D_SHIFT12_RH000 12 #define G2D_MASK12_RH000 1 << G2D_SHIFT12_RH000 #define G2D_SHIFT10_RH000 10 #define G2D_MASK10_RH000 0x3 << G2D_SHIFT10_RH000 #define G2D_SHIFT09_RH000 9 #define G2D_MASK09_RH000 1 << G2D_SHIFT09_RH000 #define G2D_SHIFT08_RH000 8 #define G2D_MASK08_RH000 1 << G2D_SHIFT08_RH000 #define G2D_SHIFT06_RH000 6 #define G2D_MASK06_RH000 0x3 << G2D_SHIFT06_RH000 #define G2D_SHIFT04_RH000 4 #define G2D_MASK04_RH000 0x3 << G2D_SHIFT04_RH000 #define G2D_SHIFT03_RH000 3 #define G2D_MASK03_RH000 1 << G2D_SHIFT03_RH000 #define G2D_SHIFT02_RH000 2 #define G2D_MASK02_RH000 1 << G2D_SHIFT02_RH000 #define G2D_SHIFT01_RH000 1 #define G2D_MASK01_RH000 1 << G2D_SHIFT01_RH000 #define G2D_SHIFT00_RH000 0 #define G2D_MASK00_RH000 1 << G2D_SHIFT00_RH000 #define G2D_RH004 REG(0xb004) #define G2D_SHIFT24_RH004 24 #define G2D_MASK24_RH004 0xF << G2D_SHIFT24_RH004 #define G2D_SHIFT16_RH004 16 #define G2D_MASK16_RH004 0xF << G2D_SHIFT16_RH004 #define G2D_SHIFT08_RH004 8 #define G2D_MASK08_RH004 0x1F << G2D_SHIFT08_RH004 #define G2D_SHIFT00_RH004 0 #define G2D_MASK00_RH004 0xF << G2D_SHIFT00_RH004 #define G2D_RH008 REG(0xb008) #define G2D_SHIFT09_RH008 9 #define G2D_MASK09_RH008 1 << G2D_SHIFT09_RH008 #define G2D_SHIFT08_RH008 8 #define G2D_MASK08_RH008 1 << G2D_SHIFT08_RH008 #define G2D_SHIFT06_RH008 6 #define G2D_MASK06_RH008 0x3 << G2D_SHIFT06_RH008 #define G2D_SHIFT04_RH008 4 #define G2D_MASK04_RH008 \ 0x3 << G2D_SHIFT04_RH008 #define G2D_SHIFT02_RH008 2 #define G2D_MASK02_RH008 0x3 << G2D_SHIFT02_RH008 #define G2D_SHIFT00_RH008 0 #define G2D_MASK00_RH008 \ 0x3 << G2D_SHIFT00_RH008 #define G2D_RH010 REG(0xb010) #define G2D_SHIFT00_RH010 0 #define G2D_MASK00_RH010 0xFFFFFFFF << G2D_SHIFT00_RH010 #define G2D_RH014 REG(0xb014) #define G2D_SHIFT00_RH014 0 #define G2D_MASK00_RH014 0xFF << G2D_SHIFT00_RH014 #define G2D_RH018 REG(0xb018) #define G2D_SHIFT00_RH018 0 #define G2D_MASK00_RH018 0xFFFFFFFF << G2D_SHIFT00_RH018 #define G2D_RH01C REG(0xb01c) #define G2D_SHIFT00_RH01C 0 #define G2D_MASK00_RH01C 0xFF << G2D_SHIFT00_RH01C #define G2D_RH020 REG(0xb020) #define G2D_SHIFT00_RH020 0 #define G2D_MASK00_RH020 0xFFFFFFFF << G2D_SHIFT00_RH020 #define G2D_RH024 REG(0xb024) #define G2D_SHIFT00_RH024 0 #define G2D_MASK00_RH024 0xFF << G2D_SHIFT00_RH024 #define G2D_RH028 REG(0xb028) #define G2D_SHIFT00_RH028 0 #define G2D_MASK00_RH028 0x3FFFF << G2D_SHIFT00_RH028 #define G2D_RH02C REG(0xb02c) #define G2D_SHIFT00_RH02C 0 #define G2D_MASK00_RH02C 0x3FFFF << G2D_SHIFT00_RH02C #define G2D_RH030 REG(0xb030) #define G2D_SHIFT00_RH030 0 #define G2D_MASK00_RH030 0x3FFFF << G2D_SHIFT00_RH030 #define G2D_RH040 REG(0xb040) #define G2D_SHIFT02_RH040 2 #define G2D_MASK02_RH040 1 << G2D_SHIFT02_RH040 #define G2D_SHIFT01_RH040 1 #define G2D_MASK01_RH040 1 << G2D_SHIFT01_RH040 #define G2D_SHIFT00_RH040 0 #define G2D_MASK00_RH040 1 << G2D_SHIFT00_RH040 #define G2D_RH044 REG(0xb044) #define G2D_SHIFT16_RH044 16 #define G2D_MASK16_RH044 0x3FFF << G2D_SHIFT16_RH044 #define G2D_SHIFT00_RH044 0 #define G2D_MASK00_RH044 0x3FFF << G2D_SHIFT00_RH044 #define G2D_RH048 REG(0xb048) #define G2D_SHIFT16_RH048 16 #define G2D_MASK16_RH048 0x3FFF << G2D_SHIFT16_RH048 #define G2D_SHIFT00_RH048 0 #define G2D_MASK00_RH048 0x3FFF << G2D_SHIFT00_RH048 #define G2D_RH04C REG(0xb04c) #define G2D_SHIFT16_RH04C 16 #define G2D_MASK16_RH04C 0x3FFF << G2D_SHIFT16_RH04C #define G2D_SHIFT00_RH04C 0 #define G2D_MASK00_RH04C 0x3FFF << G2D_SHIFT00_RH04C #define G2D_RH050 REG(0xb050) #define G2D_SHIFT16_RH050 16 #define G2D_MASK16_RH050 0x3FFF << G2D_SHIFT16_RH050 #define G2D_SHIFT00_RH050 0 #define G2D_MASK00_RH050 0x3FFF << G2D_SHIFT00_RH050 #define G2D_RH054 REG(0xb054) #define G2D_SHIFT16_RH054 16 #define G2D_MASK16_RH054 0x3FFF << G2D_SHIFT16_RH054 #define G2D_SHIFT00_RH054 0 #define G2D_MASK00_RH054 0x3FFF << G2D_SHIFT00_RH054 #define G2D_RH058 REG(0xb058) #define G2D_SHIFT16_RH058 16 #define G2D_MASK16_RH058 0x3FFF << G2D_SHIFT16_RH058 #define G2D_SHIFT00_RH058 0 #define G2D_MASK00_RH058 0x3FFF << G2D_SHIFT00_RH058 #define G2D_RH05C REG(0xb05c) #define G2D_SHIFT16_RH05C 16 #define G2D_MASK16_RH05C 0x3FF << G2D_SHIFT16_RH05C #define G2D_SHIFT00_RH05C 0 #define G2D_MASK00_RH05C 0x3FF << G2D_SHIFT00_RH05C #define G2D_RH060 REG(0xb060) #define G2D_SHIFT00_RH060 0 #define G2D_MASK00_RH060 0x3FF << G2D_SHIFT00_RH060 #endif /* G2DLITE_REG_H__ */