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liumin
2025-11-07 09:57:14 +08:00
parent b598c1d479
commit 97bc808489
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596
middleware/usb/include/cpu.h Normal file
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/*
*********************************************************************************************************
* uC/CPU
* CPU CONFIGURATION & PORT LAYER
*
* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
*
* SPDX-License-Identifier: APACHE-2.0
*
* This software is subject to an open source license and is distributed by
* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* NOTICE
*
* Semidrive modified this file to adapt it for ssdk platform.
* The modifications are only intended for use with Semidrive chips.
* Copyright of all the modifications belongs to Semidrive Semiconductor.
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CPU PORT FILE
*
* ARMv7-R
* GNU C Compiler
*
* Filename : cpu.h
* Version : V1.32.01
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef CPU_MODULE_PRESENT
#define CPU_MODULE_PRESENT
/*
*********************************************************************************************************
* CPU INCLUDE FILES
*
* Note(s) : (1) The following CPU files are located in the following directories :
*
* (a) \<Your Product Application>\cpu_cfg.h
*
* (b) \<CPU-Compiler Directory>\cpu_def.h
*
* (c) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
*
* where
* <Your Product Application> directory path for Your Product's Application
* <CPU-Compiler Directory> directory path for common CPU-compiler software
* <cpu> directory name for specific CPU
* <compiler> directory name for specific compiler
*
* (2) Compiler MUST be configured to include the '\<CPU-Compiler Directory>\' directory the
* specific CPU-compiler directory, & '\<Your Product Application>\' as additional include
* path directories.
*
* (3) Since NO custom library modules are included, 'cpu.h' may ONLY use configurations from
* CPU configuration file 'cpu_cfg.h' that do NOT reference any custom library definitions.
*
* In other words, 'cpu.h' may use 'cpu_cfg.h' configurations that are #define'd to numeric
* constants or to NULL (i.e. NULL-valued #define's); but may NOT use configurations to
* custom library #define's (e.g. DEF_DISABLED or DEF_ENABLED).
*********************************************************************************************************
*/
#include <param.h>
#include <cpu_def.h>
#include <cpu_cfg.h> /* See Note #3. */
#include <armv7-r/barriers.h>
#include <armv7-r/cache.h>
#include <irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
*********************************************************************************************************
* CONFIGURE STANDARD DATA TYPES
*
* Note(s) : (1) Configure standard data types according to CPU-/compiler-specifications.
*
* (2) (a) (1) 'CPU_FNCT_VOID' data type defined to replace the commonly-used function pointer
* data type of a pointer to a function which returns void & has no arguments.
*
* (2) Example function pointer usage :
*
* CPU_FNCT_VOID FnctName;
*
* FnctName();
*
* (b) (1) 'CPU_FNCT_PTR' data type defined to replace the commonly-used function pointer
* data type of a pointer to a function which returns void & has a single void
* pointer argument.
*
* (2) Example function pointer usage :
*
* CPU_FNCT_PTR FnctName;
* void *p_obj
*
* FnctName(p_obj);
*********************************************************************************************************
*/
typedef void CPU_VOID;
typedef char CPU_CHAR; /* 8-bit character */
typedef unsigned char CPU_BOOLEAN; /* 8-bit boolean or logical */
typedef unsigned char CPU_INT08U; /* 8-bit unsigned integer */
typedef signed char CPU_INT08S; /* 8-bit signed integer */
typedef unsigned short CPU_INT16U; /* 16-bit unsigned integer */
typedef signed short CPU_INT16S; /* 16-bit signed integer */
typedef unsigned int CPU_INT32U; /* 32-bit unsigned integer */
typedef signed int CPU_INT32S; /* 32-bit signed integer */
typedef unsigned long long CPU_INT64U; /* 64-bit unsigned integer */
typedef signed long long CPU_INT64S; /* 64-bit signed integer */
typedef float CPU_FP32; /* 32-bit floating point */
typedef double CPU_FP64; /* 64-bit floating point */
typedef volatile CPU_INT08U CPU_REG08; /* 8-bit register */
typedef volatile CPU_INT16U CPU_REG16; /* 16-bit register */
typedef volatile CPU_INT32U CPU_REG32; /* 32-bit register */
typedef volatile CPU_INT64U CPU_REG64; /* 64-bit register */
typedef void (*CPU_FNCT_VOID)(void); /* See Note #2a. */
typedef void (*CPU_FNCT_PTR )(void *p_obj); /* See Note #2b. */
/*
*********************************************************************************************************
* CPU WORD CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_ADDR_SIZE & CPU_CFG_DATA_SIZE with CPU's word sizes :
*
* CPU_WORD_SIZE_08 8-bit word size
* CPU_WORD_SIZE_16 16-bit word size
* CPU_WORD_SIZE_32 32-bit word size
* CPU_WORD_SIZE_64 64-bit word size See Note #1a
*
* (a) 64-bit word size NOT currently supported.
*
* (2) Configure CPU_CFG_ENDIAN_TYPE with CPU's data-word-memory order :
*
* (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
* octet @ lowest memory address)
* (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
* octet @ lowest memory address)
*********************************************************************************************************
*/
/* Define CPU word sizes (see Note #1) : */
#define CPU_CFG_ADDR_SIZE CPU_WORD_SIZE_32 /* Defines CPU address word size (in octets). */
#define CPU_CFG_DATA_SIZE CPU_WORD_SIZE_32 /* Defines CPU data word size (in octets). */
#define CPU_CFG_DATA_SIZE_MAX CPU_WORD_SIZE_64 /* Defines CPU maximum word size (in octets). */
/* Defines CPU data word-memory order (see Note #2). */
#define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_LITTLE
/*
*********************************************************************************************************
* CONFIGURE CPU ADDRESS & DATA TYPES
*********************************************************************************************************
*/
/* CPU address type based on address bus size. */
#if (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_32)
typedef CPU_INT32U CPU_ADDR;
#elif (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_16)
typedef CPU_INT16U CPU_ADDR;
#else
typedef CPU_INT08U CPU_ADDR;
#endif
/* CPU data type based on data bus size. */
#if (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_32)
typedef CPU_INT32U CPU_DATA;
#elif (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_16)
typedef CPU_INT16U CPU_DATA;
#else
typedef CPU_INT08U CPU_DATA;
#endif
typedef CPU_DATA CPU_ALIGN; /* Defines CPU data-word-alignment size. */
typedef CPU_ADDR CPU_SIZE_T; /* Defines CPU standard 'size_t' size. */
/*
*********************************************************************************************************
* CPU STACK CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_STK_GROWTH in 'cpu.h' with CPU's stack growth order :
*
* (a) CPU_STK_GROWTH_LO_TO_HI CPU stack pointer increments to the next higher stack
* memory address after data is pushed onto the stack
* (b) CPU_STK_GROWTH_HI_TO_LO CPU stack pointer decrements to the next lower stack
* memory address after data is pushed onto the stack
*
* (2) Configure CPU_CFG_STK_ALIGN_BYTES with the highest minimum alignement required for
* cpu stacks.
*
* (a) ARM Procedure Calls Standard requires an 8 bytes stack alignment.
*********************************************************************************************************
*/
#define CPU_CFG_STK_GROWTH CPU_STK_GROWTH_HI_TO_LO /* Defines CPU stack growth order (see Note #1). */
#define CPU_CFG_STK_ALIGN_BYTES (8u) /* Defines CPU stack alignment in bytes. (see Note #2). */
typedef CPU_INT32U CPU_STK; /* Defines CPU stack data type. */
typedef CPU_ADDR CPU_STK_SIZE; /* Defines CPU stack size data type. */
/*
*********************************************************************************************************
* CRITICAL SECTION CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
*
* Enter/Exit critical sections by ...
*
* CPU_CRITICAL_METHOD_INT_DIS_EN Disable/Enable interrupts
* CPU_CRITICAL_METHOD_STATUS_STK Push/Pop interrupt status onto stack
* CPU_CRITICAL_METHOD_STATUS_LOCAL Save/Restore interrupt status to local variable
*
* (a) CPU_CRITICAL_METHOD_INT_DIS_EN is NOT a preferred method since it does NOT support
* multiple levels of interrupts. However, with some CPUs/compilers, this is the only
* available method.
*
* (b) CPU_CRITICAL_METHOD_STATUS_STK is one preferred method since it supports multiple
* levels of interrupts. However, this method assumes that the compiler provides C-level
* &/or assembly-level functionality for the following :
*
* ENTER CRITICAL SECTION :
* (1) Push/save interrupt status onto a local stack
* (2) Disable interrupts
*
* EXIT CRITICAL SECTION :
* (3) Pop/restore interrupt status from a local stack
*
* (c) CPU_CRITICAL_METHOD_STATUS_LOCAL is one preferred method since it supports multiple
* levels of interrupts. However, this method assumes that the compiler provides C-level
* &/or assembly-level functionality for the following :
*
* ENTER CRITICAL SECTION :
* (1) Save interrupt status into a local variable
* (2) Disable interrupts
*
* EXIT CRITICAL SECTION :
* (3) Restore interrupt status from a local variable
*
* (2) Critical section macro's most likely require inline assembly. If the compiler does NOT
* allow inline assembly in C source files, critical section macro's MUST call an assembly
* subroutine defined in a 'cpu_a.asm' file located in the following software directory :
*
* \<CPU-Compiler Directory>\<cpu>\<compiler>\
*
* where
* <CPU-Compiler Directory> directory path for common CPU-compiler software
* <cpu> directory name for specific CPU
* <compiler> directory name for specific compiler
*
* (3) (a) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need
* to be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured).
*
* (1) 'cpu_sr' local variable SHOULD be declared via the CPU_SR_ALLOC() macro which, if
* used, MUST be declared following ALL other local variables.
*
* Example :
*
* void Fnct (void)
* {
* CPU_INT08U val_08;
* CPU_INT16U val_16;
* CPU_INT32U val_32;
* CPU_SR_ALLOC(); MUST be declared after ALL other local variables
* :
* :
* }
*
* (b) Configure 'CPU_SR' data type with the appropriate-sized CPU data type large enough to
* completely store the CPU's/compiler's status word.
*********************************************************************************************************
*/
/* Configure CPU critical method (see Note #1) : */
#define CPU_CFG_CRITICAL_METHOD CPU_CRITICAL_METHOD_STATUS_LOCAL
typedef irq_state_t CPU_SR; /* Defines CPU status register size (see Note #3b). */
/* Allocates CPU status register word (see Note #3a). */
#if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
#define CPU_SR_ALLOC() CPU_SR cpu_sr = (CPU_SR)0
#else
#define CPU_SR_ALLOC()
#endif
#define CPU_INT_DIS() do { cpu_sr = arch_irq_save(); DSB; } while (0)
#define CPU_INT_EN() do { DSB; arch_irq_restore(cpu_sr); } while (0)
#ifdef CPU_CFG_INT_DIS_MEAS_EN
/* Disable interrupts, ... */
/* & start interrupts disabled time measurement.*/
#define CPU_CRITICAL_ENTER() do { CPU_INT_DIS(); \
CPU_IntDisMeasStart(); } while (0)
/* Stop & measure interrupts disabled time, */
/* ... & re-enable interrupts. */
#define CPU_CRITICAL_EXIT() do { CPU_IntDisMeasStop(); \
CPU_INT_EN(); } while (0)
#else
#define CPU_CRITICAL_ENTER() do { CPU_INT_DIS(); } while (0) /* Disable interrupts. */
#define CPU_CRITICAL_EXIT() do { CPU_INT_EN(); } while (0) /* Re-enable interrupts. */
#endif
/*
*********************************************************************************************************
* MEMORY BARRIERS CONFIGURATION
*
* Note(s) : (1) (a) Configure memory barriers if required by the architecture.
*
* CPU_MB Full memory barrier.
* CPU_RMB Read (Loads) memory barrier.
* CPU_WMB Write (Stores) memory barrier.
*
*********************************************************************************************************
*/
#define CPU_MB() DSB
#define CPU_RMB() DSB
#define CPU_WMB() DSB
/*
*********************************************************************************************************
* CACHE DEFINES
*********************************************************************************************************
*/
#if CONFIG_ARCH_WITH_CACHE
#define LEN_CACHE_ALIGN(len) ROUNDUP(len, CONFIG_ARCH_CACHE_LINE)
#else
#define LEN_CACHE_ALIGN(len) (len)
#endif
/*
* The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
* stack that meets the minimum architecture alignment requirements for DMA.
* Such a buffer is useful for DMA operations where flushing and invalidating
* the cache before and after a read and/or write operation is required for
* correct operations.
*
* When called the macro creates an array on the stack that is sized such
* that:
*
* 1) The beginning of the array can be advanced enough to be aligned.
*
* 2) The size of the aligned portion of the array is a multiple of the minimum
* architecture alignment required for DMA.
*
* 3) The aligned portion contains enough space for the original number of
* elements requested.
*
* The macro then creates a pointer to the aligned portion of this array and
* assigns to the pointer the address of the first element in the aligned
* portion of the array.
*
* Calling the macro as:
*
* ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
*
* Will result in something similar to saying:
*
* uint32_t buffer[1024];
*
* The following differences exist:
*
* 1) The resulting buffer is guaranteed to be aligned to the value of
* CONFIG_ARCH_CACHE_LINE.
*
* 2) The buffer variable created by the macro is a pointer to the specified
* type, and NOT an array of the specified type. This can be very important
* if you want the address of the buffer, which you probably do, to pass it
* to the DMA hardware. The value of &buffer is different in the two cases.
* In the macro case it will be the address of the pointer, not the address
* of the space reserved for the buffer. However, in the second case it
* would be the address of the buffer. So if you are replacing hard coded
* stack buffers with this macro you need to make sure you remove the & from
* the locations where you are taking the address of the buffer.
*
* Note that the size parameter is the number of array elements to allocate,
* not the number of bytes.
*
* This macro can not be used outside of function scope, or for the creation
* of a function scoped static buffer. It can not be used to create a cache
* line aligned global buffer.
*/
#if CONFIG_ARCH_WITH_CACHE
#define ALLOC_ALIGN_BUFFER(type, name, size, align) \
char __##name[ROUNDUP((size) * sizeof(type), align) \
+ (align - 1)]; \
\
type *name = (type *)ALIGN((uintptr_t)__##name, align)
#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \
ALLOC_ALIGN_BUFFER(type, name, size, CONFIG_ARCH_CACHE_LINE)
#else
#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \
type __##name[size]; \
\
type *name = __##name
#endif
/*
*********************************************************************************************************
* CPU COUNT ZEROS CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT to define count leading zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*
* (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*********************************************************************************************************
*/
/* Configure CPU count leading zeros bits ... */
#define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1a). */
/* Configure CPU count trailing zeros bits ... */
#define CPU_CFG_TRAIL_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1b). */
/*
*********************************************************************************************************
* FUNCTION PROTOTYPES
*
* Note(s) : (1) CPU_CntLeadZeros() prototyped/defined respectively in :
*
* (a) 'cpu.h'/'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-version function
*
* (b) 'cpu_core.h'/'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-version function otherwise
*
* See also 'cpu_core.h FUNCTION PROTOTYPES Note #2'.
*
* (2) CPU_PMU_xxx() functions are intended to manage the Event & Performanace Monitor unit (PMU).
*********************************************************************************************************
*/
void CPU_IntDis (void);
void CPU_IntEn (void);
CPU_SR CPU_SR_Save (void);
void CPU_SR_Restore (CPU_SR cpu_sr);
void CPU_WaitForInt (void);
void CPU_WaitForEvent (void);
/*
*********************************************************************************************************
* CONFIGURATION ERRORS
*********************************************************************************************************
*/
#ifndef CPU_CFG_ADDR_SIZE
#error "CPU_CFG_ADDR_SIZE not #define'd in 'cpu.h' "
#error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
#error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
#error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
#elif ((CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_08) && \
(CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_16) && \
(CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_32))
#error "CPU_CFG_ADDR_SIZE illegally #define'd in 'cpu.h' "
#error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
#error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
#error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
#endif
#ifndef CPU_CFG_DATA_SIZE
#error "CPU_CFG_DATA_SIZE not #define'd in 'cpu.h' "
#error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
#error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
#error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
#elif ((CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_08) && \
(CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_16) && \
(CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_32))
#error "CPU_CFG_DATA_SIZE illegally #define'd in 'cpu.h' "
#error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
#error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
#error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
#endif
#ifndef CPU_CFG_ENDIAN_TYPE
#error "CPU_CFG_ENDIAN_TYPE not #define'd in 'cpu.h' "
#error " [MUST be CPU_ENDIAN_TYPE_BIG ]"
#error " [ || CPU_ENDIAN_TYPE_LITTLE]"
#elif ((CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_BIG ) && \
(CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_LITTLE))
#error "CPU_CFG_ENDIAN_TYPE illegally #define'd in 'cpu.h' "
#error " [MUST be CPU_ENDIAN_TYPE_BIG ]"
#error " [ || CPU_ENDIAN_TYPE_LITTLE]"
#endif
#ifndef CPU_CFG_STK_GROWTH
#error "CPU_CFG_STK_GROWTH not #define'd in 'cpu.h' "
#error " [MUST be CPU_STK_GROWTH_LO_TO_HI]"
#error " [ || CPU_STK_GROWTH_HI_TO_LO]"
#elif ((CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_LO_TO_HI) && \
(CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_HI_TO_LO))
#error "CPU_CFG_STK_GROWTH illegally #define'd in 'cpu.h' "
#error " [MUST be CPU_STK_GROWTH_LO_TO_HI]"
#error " [ || CPU_STK_GROWTH_HI_TO_LO]"
#endif
#ifndef CPU_CFG_CRITICAL_METHOD
#error "CPU_CFG_CRITICAL_METHOD not #define'd in 'cpu.h' "
#error " [MUST be CPU_CRITICAL_METHOD_INT_DIS_EN ]"
#error " [ || CPU_CRITICAL_METHOD_STATUS_STK ]"
#error " [ || CPU_CRITICAL_METHOD_STATUS_LOCAL]"
#elif ((CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_INT_DIS_EN ) && \
(CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_STK ) && \
(CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_LOCAL))
#error "CPU_CFG_CRITICAL_METHOD illegally #define'd in 'cpu.h' "
#error " [MUST be CPU_CRITICAL_METHOD_INT_DIS_EN ]"
#error " [ || CPU_CRITICAL_METHOD_STATUS_STK ]"
#error " [ || CPU_CRITICAL_METHOD_STATUS_LOCAL]"
#endif
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#ifdef __cplusplus
}
#endif
#endif /* End of CPU module include. */

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/**
* @file cpu_cache.h
*
* Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*
* Description: CPU Cache header file for USB Device & Host.
*
* Revision History:
* -----------------
*/
#ifndef CPU_CACHE_MODULE_PRESENT
#define CPU_CACHE_MODULE_PRESENT
#include <cpu.h>
#include <cpu_cfg.h>
#include <armv7-r/cache.h>
/*
*********************************************************************************************************
* CACHE CONFIGURATION
*********************************************************************************************************
*/
#ifndef CPU_CFG_CACHE_MGMT_EN
#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
#endif
/*
*********************************************************************************************************
* CACHE OPERATIONS FUNCTION PROTOTYPES
*********************************************************************************************************
*/
static inline
void CPU_DCACHE_RANGE_FLUSH(void *addr_start,
CPU_ADDR len)
{
arch_clean_cache_range((addr_t)addr_start, len);
}
static inline
void CPU_DCACHE_RANGE_FLUSHINV(void *addr_start,
CPU_ADDR len)
{
arch_clean_invalidate_cache_range((addr_t)addr_start, len);
}
static inline
void CPU_DCACHE_RANGE_INV (void *addr_start,
CPU_ADDR len)
{
arch_invalidate_cache_range((addr_t)addr_start, len);
}
#endif

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middleware/usb/include/cpu_cfg.h Normal file
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/**
* @file cpu_cfg.h
*
* Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*
* Description: CPU Configuration file for USB Device & Host.
*
* Revision History:
* -----------------
*/
#ifndef CPU_CFG_MODULE_PRESENT
#define CPU_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
* CPU TIMESTAMP CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
*
* (a) CPU_CFG_TS_32_EN enable/disable 32-bit CPU timestamp feature
* (b) CPU_CFG_TS_64_EN enable/disable 64-bit CPU timestamp feature
*
* (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
*
* CPU_WORD_SIZE_08 8-bit word size
* CPU_WORD_SIZE_16 16-bit word size
* CPU_WORD_SIZE_32 32-bit word size
* CPU_WORD_SIZE_64 64-bit word size
*
* (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets
* (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word
* size SHOULD be configured (e.g. to 16-bits). However, the minimum supported word
* size for CPU timestamp timers is 8-bits.
*
* See also 'cpu_core.h FUNCTION PROTOTYPES CPU_TS_TmrRd() Note #2a'.
*********************************************************************************************************
*/
/* Configure CPU timestamp features (see Note #1) : */
#define CPU_CFG_TS_32_EN DEF_DISABLED
#define CPU_CFG_TS_64_EN DEF_DISABLED
/* DEF_DISABLED CPU timestamps DISABLED */
/* DEF_ENABLED CPU timestamps ENABLED */
/* Configure CPU timestamp timer word size ... */
/* ... (see Note #2) : */
#define CPU_CFG_TS_TMR_SIZE CPU_WORD_SIZE_32
/*
*********************************************************************************************************
* CACHE MANAGEMENT
*
* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache management API.
*
* (2) This option only enables the cache management functions.
* It does not enable any hardware caches, which should be configured in startup code.
* Caches must be configured and enabled by the time CPU_Init() is called.
*
* (3) This option is usually required for device drivers which use a DMA engine to transmit
* buffers that are located in cached memory.
*********************************************************************************************************
*/
/* Defines CPU data word-memory order (see Note #1). */
#if CONFIG_ARCH_WITH_CACHE
#define CPU_CFG_CACHE_MGMT_EN DEF_ENABLED
#else
#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
#endif
#endif

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/*
*********************************************************************************************************
* uC/CPU
* CPU CONFIGURATION & PORT LAYER
*
* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
*
* SPDX-License-Identifier: APACHE-2.0
*
* This software is subject to an open source license and is distributed by
* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* NOTICE
*
* Semidrive modified this file to adapt it for ssdk platform.
* The modifications are only intended for use with Semidrive chips.
* Copyright of all the modifications belongs to Semidrive Semiconductor.
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CORE CPU MODULE
*
* Filename : cpu_core.h
* Version : V1.32.01
*********************************************************************************************************
* Note(s) : (1) Assumes the following versions (or more recent) of software modules are included in
* the project build :
*
* (a) uC/LIB V1.38.02
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*
* Note(s) : (1) This core CPU header file is protected from multiple pre-processor inclusion through use of
* the core CPU module present pre-processor macro definition.
*********************************************************************************************************
*/
#ifndef CPU_CORE_MODULE_PRESENT /* See Note #1. */
#define CPU_CORE_MODULE_PRESENT
/*
*********************************************************************************************************
* EXTERNS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*
* Note(s) : (1) CPU-configuration software files are located in the following directories :
*
* (a) \<Your Product Application>\cpu_cfg.h
*
* (b) (1) \<CPU-Compiler Directory>\cpu_*.*
* (2) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
*
* where
* <Your Product Application> directory path for Your Product's Application
* <CPU-Compiler Directory> directory path for common CPU-compiler software
* <cpu> directory name for specific processor (CPU)
* <compiler> directory name for specific compiler
*
* (2) NO compiler-supplied standard library functions SHOULD be used.
*
* (a) Standard library functions are implemented in the custom library module(s) :
*
* \<Custom Library Directory>\lib_*.*
*
* where
* <Custom Library Directory> directory path for custom library software
*
* (3) Compiler MUST be configured to include as additional include path directories :
*
* (a) '\<Your Product Application>\' directory See Note #1a
*
* (b) (1) '\<CPU-Compiler Directory>\' directory See Note #1b1
* (2) '\<CPU-Compiler Directory>\<cpu>\<compiler>\' directory See Note #1b2
*
* (c) '\<Custom Library Directory>\' directory See Note #2a
*********************************************************************************************************
*/
#include <debug.h>
#include <cpu.h>
#include <lib_def.h>
#include <cpu_cfg.h>
/*
*********************************************************************************************************
* CPU CONFIGURATION
*
* Note(s) : (1) The following pre-processor directives correctly configure CPU parameters. DO NOT MODIFY.
*
* (2) CPU timestamp timer feature is required for :
*
* (a) CPU timestamps
* (b) CPU interrupts disabled time measurement
*
* See also 'cpu_cfg.h CPU TIMESTAMP CONFIGURATION Note #1'
* & 'cpu_cfg.h CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION Note #1'.
*********************************************************************************************************
*/
#ifdef CPU_CFG_TS_EN
#undef CPU_CFG_TS_EN
#endif
#if ((CPU_CFG_TS_32_EN == DEF_ENABLED) || \
(CPU_CFG_TS_64_EN == DEF_ENABLED))
#define CPU_CFG_TS_EN DEF_ENABLED
#else
#define CPU_CFG_TS_EN DEF_DISABLED
#endif
#if ((CPU_CFG_TS_EN == DEF_ENABLED) || \
(defined(CPU_CFG_INT_DIS_MEAS_EN)))
#define CPU_CFG_TS_TMR_EN DEF_ENABLED
#else
#define CPU_CFG_TS_TMR_EN DEF_DISABLED
#endif
/*
*********************************************************************************************************
* CACHE CONFIGURATION
*
* Note(s) : (1) The following pre-processor directives correctly configure CACHE parameters. DO NOT MODIFY.
*
**********************************************************************************************************
*/
#ifndef CPU_CFG_CACHE_MGMT_EN
#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
#endif
/*
*********************************************************************************************************
* DEFINES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* DATA TYPES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* CPU ERROR CODES
*********************************************************************************************************
*/
typedef enum cpu_err {
CPU_ERR_NONE = 0u,
CPU_ERR_NULL_PTR = 10u,
CPU_ERR_NAME_SIZE = 1000u,
CPU_ERR_TS_FREQ_INVALID = 2000u
} CPU_ERR;
/*
*********************************************************************************************************
* CPU TIMESTAMP DATA TYPES
*
* Note(s) : (1) CPU timestamp timer data type defined to the binary-multiple of 8-bit octets as configured
* by 'CPU_CFG_TS_TMR_SIZE' (see 'cpu_cfg.h CPU TIMESTAMP CONFIGURATION Note #2').
*********************************************************************************************************
*/
typedef CPU_INT32U CPU_TS32;
typedef CPU_INT64U CPU_TS64;
typedef CPU_TS32 CPU_TS; /* Req'd for backwards-compatibility. */
/*
*********************************************************************************************************
* CPU TIMESTAMP TIMER FREQUENCY DATA TYPE
*********************************************************************************************************
*/
typedef CPU_INT32U CPU_TS_TMR_FREQ;
/*
*********************************************************************************************************
* GLOBAL VARIABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MACRO'S
*********************************************************************************************************
*/
#ifndef CPU_SW_EXCEPTION /* See Note #2. */
#define CPU_SW_EXCEPTION(err_rtn_val) do { \
PANIC(); \
} while (0)
#endif
/*
*********************************************************************************************************
* FUNCTION PROTOTYPES
*
* Note(s) : (1) CPU interrupts disabled time measurement functions prototyped/defined only if
* CPU_CFG_INT_DIS_MEAS_EN #define'd in 'cpu_cfg.h'.
*
* (2) (a) CPU_CntLeadZeros() defined in :
*
* (1) 'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s)
*
* (b) CPU_CntTrailZeros() defined in :
*
* (1) 'cpu_a.asm', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s)
*********************************************************************************************************
*/
/* --------------- CPU TS FNCTS --------------- */
#if (CPU_CFG_TS_32_EN == DEF_ENABLED)
CPU_TS32 CPU_TS_Get32 (void);
#endif
#if (CPU_CFG_TS_64_EN == DEF_ENABLED)
CPU_TS64 CPU_TS_Get64 (void);
#endif
#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED) /* ------------- CPU TS TMR FNCTS ------------- */
CPU_TS_TMR_FREQ CPU_TS_TmrFreqGet (CPU_ERR *p_err);
void CPU_TS_TmrFreqSet (CPU_TS_TMR_FREQ freq_hz);
#endif
/* ----------- CPU CNT ZEROS FNCTS ------------ */
static inline
CPU_DATA CPU_CntLeadZeros32 (CPU_INT32U val)
{
return __builtin_clz(val);
}
static inline
CPU_DATA CPU_CntTrailZeros (CPU_DATA val)
{
return __builtin_ctz(val);
}
static inline
CPU_DATA CPU_CntTrailZeros08 (CPU_INT08U val)
{
return val ? __builtin_ctz(val) : 8;
}
static inline
CPU_DATA CPU_CntTrailZeros32 (CPU_INT32U val)
{
return __builtin_ctz(val);
}
/*
*********************************************************************************************************
* CONFIGURATION ERRORS
*********************************************************************************************************
*/
#ifndef CPU_CFG_TS_32_EN
#error "CPU_CFG_TS_32_EN not #define'd in 'cpu_cfg.h'"
#error " [MUST be DEF_DISABLED] "
#error " [ || DEF_ENABLED ] "
#elif ((CPU_CFG_TS_32_EN != DEF_DISABLED) && \
(CPU_CFG_TS_32_EN != DEF_ENABLED ))
#error "CPU_CFG_TS_32_EN illegally #define'd in 'cpu_cfg.h'"
#error " [MUST be DEF_DISABLED] "
#error " [ || DEF_ENABLED ] "
#endif
#ifndef CPU_CFG_TS_64_EN
#error "CPU_CFG_TS_64_EN not #define'd in 'cpu_cfg.h'"
#error " [MUST be DEF_DISABLED] "
#error " [ || DEF_ENABLED ] "
#elif ((CPU_CFG_TS_64_EN != DEF_DISABLED) && \
(CPU_CFG_TS_64_EN != DEF_ENABLED ))
#error "CPU_CFG_TS_64_EN illegally #define'd in 'cpu_cfg.h'"
#error " [MUST be DEF_DISABLED] "
#error " [ || DEF_ENABLED ] "
#endif
/* Correctly configured in 'cpu_core.h'; DO NOT MODIFY. */
#ifndef CPU_CFG_TS_EN
#error "CPU_CFG_TS_EN not #define'd in 'cpu_core.h'"
#error " [MUST be DEF_DISABLED] "
#error " [ || DEF_ENABLED ] "
#elif ((CPU_CFG_TS_EN != DEF_DISABLED) && \
(CPU_CFG_TS_EN != DEF_ENABLED ))
#error "CPU_CFG_TS_EN illegally #define'd in 'cpu_core.h'"
#error " [MUST be DEF_DISABLED] "
#error " [ || DEF_ENABLED ] "
#endif
/* Correctly configured in 'cpu_core.h'; DO NOT MODIFY. */
#ifndef CPU_CFG_TS_TMR_EN
#error "CPU_CFG_TS_TMR_EN not #define'd in 'cpu_core.h'"
#error " [MUST be DEF_DISABLED] "
#error " [ || DEF_ENABLED ] "
#elif ((CPU_CFG_TS_TMR_EN != DEF_DISABLED) && \
(CPU_CFG_TS_TMR_EN != DEF_ENABLED ))
#error "CPU_CFG_TS_TMR_EN illegally #define'd in 'cpu_core.h'"
#error " [MUST be DEF_DISABLED] "
#error " [ || DEF_ENABLED ] "
#elif (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
#ifndef CPU_CFG_TS_TMR_SIZE
#error "CPU_CFG_TS_TMR_SIZE not #define'd in 'cpu_cfg.h' "
#error " [MUST be CPU_WORD_SIZE_08 8-bit timer]"
#error " [ || CPU_WORD_SIZE_16 16-bit timer]"
#error " [ || CPU_WORD_SIZE_32 32-bit timer]"
#error " [ || CPU_WORD_SIZE_64 64-bit timer]"
#elif ((CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_08) && \
(CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_16) && \
(CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_32) && \
(CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_64))
#error "CPU_CFG_TS_TMR_SIZE illegally #define'd in 'cpu_cfg.h' "
#error " [MUST be CPU_WORD_SIZE_08 8-bit timer]"
#error " [ || CPU_WORD_SIZE_16 16-bit timer]"
#error " [ || CPU_WORD_SIZE_32 32-bit timer]"
#error " [ || CPU_WORD_SIZE_64 64-bit timer]"
#endif
#endif
/*
*********************************************************************************************************
* CPU PORT CONFIGURATION ERRORS
*********************************************************************************************************
*/
#ifndef CPU_CFG_ADDR_SIZE
#error "CPU_CFG_ADDR_SIZE not #define'd in 'cpu.h'"
#endif
#ifndef CPU_CFG_DATA_SIZE
#error "CPU_CFG_DATA_SIZE not #define'd in 'cpu.h'"
#endif
#ifndef CPU_CFG_DATA_SIZE_MAX
#error "CPU_CFG_DATA_SIZE_MAX not #define'd in 'cpu.h'"
#endif
/*
*********************************************************************************************************
* MODULE END
*
* Note(s) : (1) See 'cpu_core.h MODULE'.
*********************************************************************************************************
*/
#endif /* End of CPU core module include. */

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/*
*********************************************************************************************************
* uC/CPU
* CPU CONFIGURATION & PORT LAYER
*
* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
*
* SPDX-License-Identifier: APACHE-2.0
*
* This software is subject to an open source license and is distributed by
* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CPU CONFIGURATION DEFINES
*
* Filename : cpu_def.h
* Version : V1.32.01
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*
* Note(s) : (1) This CPU definition header file is protected from multiple pre-processor inclusion
* through use of the CPU definition module present pre-processor macro definition.
*********************************************************************************************************
*/
#ifndef CPU_DEF_MODULE_PRESENT
#define CPU_DEF_MODULE_PRESENT
/*
*********************************************************************************************************
* CORE CPU MODULE VERSION NUMBER
*
* Note(s) : (1) (a) The core CPU module software version is denoted as follows :
*
* Vx.yy.zz
*
* where
* V denotes 'Version' label
* x denotes major software version revision number
* yy denotes minor software version revision number
* zz denotes sub-minor software version revision number
*
* (b) The software version label #define is formatted as follows :
*
* ver = x.yyzz * 100 * 100
*
* where
* ver denotes software version number scaled as an integer value
* x.yyzz denotes software version number, where the unscaled integer
* portion denotes the major version number & the unscaled
* fractional portion denotes the (concatenated) minor
* version numbers
*********************************************************************************************************
*/
#define CPU_CORE_VERSION 13201u /* See Note #1. */
/*
*********************************************************************************************************
* CPU WORD CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_ADDR_SIZE & CPU_CFG_DATA_SIZE in 'cpu.h' with CPU's word sizes :
*
* CPU_WORD_SIZE_08 8-bit word size
* CPU_WORD_SIZE_16 16-bit word size
* CPU_WORD_SIZE_32 32-bit word size
* CPU_WORD_SIZE_64 64-bit word size
*
* (2) Configure CPU_CFG_ENDIAN_TYPE in 'cpu.h' with CPU's data-word-memory order :
*
* (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
* octet @ lowest memory address)
* (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
* octet @ lowest memory address)
*********************************************************************************************************
*/
/* ---------------------- CPU WORD SIZE ----------------------- */
#define CPU_WORD_SIZE_08 1u /* 8-bit word size (in octets). */
#define CPU_WORD_SIZE_16 2u /* 16-bit word size (in octets). */
#define CPU_WORD_SIZE_32 4u /* 32-bit word size (in octets). */
#define CPU_WORD_SIZE_64 8u /* 64-bit word size (in octets). */
/* ------------------ CPU WORD-ENDIAN ORDER ------------------- */
#define CPU_ENDIAN_TYPE_NONE 0u
#define CPU_ENDIAN_TYPE_BIG 1u /* Big- endian word order (see Note #1a). */
#define CPU_ENDIAN_TYPE_LITTLE 2u /* Little-endian word order (see Note #1b). */
/*
*********************************************************************************************************
* CPU STACK CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_STK_GROWTH in 'cpu.h' with CPU's stack growth order :
*
* (a) CPU_STK_GROWTH_LO_TO_HI CPU stack pointer increments to the next higher stack
* memory address after data is pushed onto the stack
* (b) CPU_STK_GROWTH_HI_TO_LO CPU stack pointer decrements to the next lower stack
* memory address after data is pushed onto the stack
*********************************************************************************************************
*/
/* ------------------ CPU STACK GROWTH ORDER ------------------ */
#define CPU_STK_GROWTH_NONE 0u
#define CPU_STK_GROWTH_LO_TO_HI 1u /* CPU stk incs towards higher mem addrs (see Note #1a). */
#define CPU_STK_GROWTH_HI_TO_LO 2u /* CPU stk decs towards lower mem addrs (see Note #1b). */
/*
*********************************************************************************************************
* CRITICAL SECTION CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
*
* Enter/Exit critical sections by ...
*
* CPU_CRITICAL_METHOD_INT_DIS_EN Disable/Enable interrupts
* CPU_CRITICAL_METHOD_STATUS_STK Push/Pop interrupt status onto stack
* CPU_CRITICAL_METHOD_STATUS_LOCAL Save/Restore interrupt status to local variable
*
* (a) CPU_CRITICAL_METHOD_INT_DIS_EN is NOT a preferred method since it does NOT support
* multiple levels of interrupts. However, with some CPUs/compilers, this is the only
* available method.
*
* (b) CPU_CRITICAL_METHOD_STATUS_STK is one preferred method since it supports multiple
* levels of interrupts. However, this method assumes that the compiler provides C-level
* &/or assembly-level functionality for the following :
*
* ENTER CRITICAL SECTION :
* (1) Push/save interrupt status onto a local stack
* (2) Disable interrupts
*
* EXIT CRITICAL SECTION :
* (3) Pop/restore interrupt status from a local stack
*
* (c) CPU_CRITICAL_METHOD_STATUS_LOCAL is one preferred method since it supports multiple
* levels of interrupts. However, this method assumes that the compiler provides C-level
* &/or assembly-level functionality for the following :
*
* ENTER CRITICAL SECTION :
* (1) Save interrupt status into a local variable
* (2) Disable interrupts
*
* EXIT CRITICAL SECTION :
* (3) Restore interrupt status from a local variable
*
* (2) Critical section macro's most likely require inline assembly. If the compiler does NOT
* allow inline assembly in C source files, critical section macro's MUST call an assembly
* subroutine defined in a 'cpu_a.asm' file located in the following software directory :
*
* \<CPU-Compiler Directory>\<cpu>\<compiler>\
*
* where
* <CPU-Compiler Directory> directory path for common CPU-compiler software
* <cpu> directory name for specific CPU
* <compiler> directory name for specific compiler
*
* (3) (a) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need
* to be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured).
*
* (1) 'cpu_sr' local variable SHOULD be declared via the CPU_SR_ALLOC() macro which,
* if used, MUST be declared following ALL other local variables (see any 'cpu.h
* CRITICAL SECTION CONFIGURATION Note #3a1').
*
* Example :
*
* void Fnct (void)
* {
* CPU_INT08U val_08;
* CPU_INT16U val_16;
* CPU_INT32U val_32;
* CPU_SR_ALLOC(); MUST be declared after ALL other local variables
* :
* :
* }
*
* (b) Configure 'CPU_SR' data type with the appropriate-sized CPU data type large enough to
* completely store the CPU's/compiler's status word.
*********************************************************************************************************
*/
/* --------------- CPU CRITICAL SECTION METHODS --------------- */
#define CPU_CRITICAL_METHOD_NONE 0u /* */
#define CPU_CRITICAL_METHOD_INT_DIS_EN 1u /* DIS/EN ints (see Note #1a). */
#define CPU_CRITICAL_METHOD_STATUS_STK 2u /* Push/Pop int status onto stk (see Note #1b). */
#define CPU_CRITICAL_METHOD_STATUS_LOCAL 3u /* Save/Restore int status to local var (see Note #1c). */
/*
*********************************************************************************************************
* MODULE END
*
* Note(s) : (1) See 'cpu_def.h MODULE'.
*********************************************************************************************************
*/
#endif /* End of CPU def module include. */

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/**
* @file lib_cfg.h
*
* Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*
* Description: Custom Library Configuration file for USB Device & Host.
*
* Revision History:
* -----------------
*/
#ifndef LIB_CFG_MODULE_PRESENT
#define LIB_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
*********************************************************************************************************
* MEMORY LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
* argument check feature :
*
* (a) When ENABLED, arguments received from any port interface provided by the developer
* or application are checked/validated.
*
* (b) When DISABLED, NO arguments received from any port interface provided by the developer
* or application are checked/validated.
*********************************************************************************************************
*/
/* External argument check. */
/* Indicates if arguments received from any port ... */
/* ... interface provided by the developer or ... */
/* ... application are checked/validated. */
#define LIB_MEM_CFG_ARG_CHK_EXT_EN DEF_DISABLED
#endif /* End of lib cfg module include. */

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middleware/usb/include/lib_math.h Normal file
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/**
* @file lib_math.h
*
* Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*
* Description: Mathematic library header file for USB Device & Host.
*
* Revision History:
* -----------------
*/
#ifndef LIB_MATH_MODULE_PRESENT
#define LIB_MATH_MODULE_PRESENT
#include <cpu.h>
#include <cpu_core.h>
#include <lib_def.h>
/*
*********************************************************************************************************
* MATH_IS_PWR2()
*
* Description : Determine if a value is a power of 2.
*
* Argument(s) : nbr Value.
*
* Return(s) : DEF_YES, 'nbr' is a power of 2.
*
* DEF_NO, 'nbr' is not a power of 2.
*
* Caller(s) : Application.
*
* Note(s) : none.
*********************************************************************************************************
*/
#define MATH_IS_PWR2(nbr) ((((nbr) != 0u) && (((nbr) & ((nbr) - 1u)) == 0u)) ? DEF_YES : DEF_NO)
/*
*********************************************************************************************************
* MATH_ROUND_INC_UP_PWR2()
*
* Description : Round value up to the next (power of 2) increment.
*
* Argument(s) : nbr Value to round.
*
* inc Increment to use. MUST be a power of 2.
*
* Return(s) : Rounded up value.
*
* Caller(s) : Application.
*
* Note(s) : none.
*********************************************************************************************************
*/
#define MATH_ROUND_INC_UP_PWR2(nbr, inc) (((nbr) & ~((inc) - 1)) + (((nbr) & ((inc) - 1)) == 0 ? 0 : (inc)))
/*
*********************************************************************************************************
* MATH_ROUND_INC_UP()
*
* Description : Round value up to the next increment.
*
* Argument(s) : nbr Value to round.
*
* inc Increment to use.
*
* Return(s) : Rounded up value.
*
* Caller(s) : Application.
*
* Note(s) : none.
*********************************************************************************************************
*/
#define MATH_ROUND_INC_UP(nbr, inc) (((nbr) + ((inc) - 1)) / (inc) * (inc))
#endif

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middleware/usb/include/lib_str.h Normal file
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/**
* @file lib_str.h
*
* Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*
* Description: String library header file for USB Device & Host.
*
* Revision History:
* -----------------
*/
#ifndef LIB_STR_MODULE_PRESENT
#define LIB_STR_MODULE_PRESENT
#include <string.h>
#include <cpu.h>
static inline
CPU_SIZE_T Str_Len (const CPU_CHAR *pstr)
{
return strlen(pstr);
}
static inline
CPU_CHAR *Str_Copy_N ( CPU_CHAR *pstr_dest,
const CPU_CHAR *pstr_src,
CPU_SIZE_T len_max)
{
return strncpy(pstr_dest, pstr_src, len_max);
}
CPU_CHAR *Str_FmtNbr_Int32U ( CPU_INT32U nbr,
CPU_INT08U nbr_dig,
CPU_INT08U nbr_base,
CPU_CHAR lead_char,
CPU_BOOLEAN lower_case,
CPU_BOOLEAN nul,
CPU_CHAR *pstr);
#endif

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/**
* @file usb_bsp_e3.h
* @brief usb board support header file.
*
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef USB_BSP_E3_H
#define USB_BSP_E3_H
#include <udelay/udelay.h>
#include <board.h>
#include "config.h"
#ifndef APB_USB0H_BASE
#define APB_USB0H_BASE APB_USB_BASE
#define APB_USB0D_BASE (APB_USB0H_BASE + 0x1000u)
#endif
#ifndef USB0_INTR_NUM
#define USB0_INTR_NUM USB_INTR_NUM
#endif
#if !CONFIG_OS
extern volatile uint32_t usb_tick_cnt;
void usb_tick_init(uint32_t btm_base, int btm_irq);
uint32_t usb_tick_get_us(void);
#endif
void usb_irq_init(void);
void usb_bsp_wait_pll_lock(void);
#ifdef CONFIG_USB_DEVICE
#include <Drivers/Renesas_USBHS/usbd_drv_renesas_usbhs.h>
extern USBD_DRV_BSP_API USBD_DrvBSP_TAISHAN_USB0;
static inline void USBD_BSP_DlyUs(CPU_INT32U us)
{
udelay(us);
}
#if USB_LOW_VBUS
uint16_t USBD_DrvGetVbInt(void *p_reg);
uint16_t USBD_DrvGetVbStatus(void *p_reg);
#endif
#endif
#ifdef CONFIG_USB_HOST
#include <HCD/EHCI/usbh_hcd_ehci.h>
#include <HCD/OHCI/usbh_hcd_ohci.h>
#define RUSB_OHCI_OFFSET 0x0u
#define RUSB_EHCI_OFFSET 0x100u
extern USBH_HC_BSP_API USB0H_EHCI_BSP_TAISHAN;
extern USBH_HC_BSP_API USB0H_OHCI_BSP_TAISHAN;
#endif
#ifdef CONFIG_USB_OTG
void USB0_BSP_OTG_ISR_Reg (CPU_FNCT_PTR isr_fnct, void *arg);
#endif
#endif