128 lines
3.4 KiB
C
128 lines
3.4 KiB
C
#include "MAIN.H"
|
||
ubyte idata WLBuf[32] _at_ 0x80;
|
||
// This function will generate a Watchdog Reset
|
||
// The reset will be generated in about 21 us
|
||
void CAN_setWDTReset(void)
|
||
{
|
||
SFR_PAGE(_su1, noSST); // switch to page1 without saving
|
||
MAIN_vUnlockProtecReg(); // open access to protected register
|
||
|
||
SET_RMAP();
|
||
WDTCON |= 0x04; // set WDTEN
|
||
WDTREL = 0xFF; //Watch dog timer reload register
|
||
WDTCON |= 0x03; // set WDTRS,set WDTIN
|
||
RESET_RMAP();
|
||
|
||
MAIN_vlockProtecReg(); // close access to protected register
|
||
SFR_PAGE(_su0, noSST); // switch to page0 with out saving
|
||
|
||
while(1);
|
||
}
|
||
|
||
|
||
void CAN_waitTransmit(ubyte RgMsgobj)
|
||
{
|
||
ulong i;
|
||
for(i=0;(i<6000)&&(!CAN_ubRequestMsgObj(RgMsgobj));i++)WDT_vRefresh();
|
||
}
|
||
|
||
|
||
// CAN Acknowledge Frame consist of 2 data bytes.
|
||
// The first data byte is the Acknowledge Code
|
||
// The second data byte is the valid data depending on the Acknowledge Code
|
||
// TX_MSGOBJ is set to one Message object only.
|
||
void CAN_sendAck(ubyte Ack0,ubyte Ack1)
|
||
{
|
||
ubyte Arrtmp[8] = {0};
|
||
//--------------------------------------------
|
||
Arrtmp[3] = Ack0;
|
||
Arrtmp[2] = Ack1;
|
||
|
||
CAN_vLoadData(TX_MSGOBJ, (ulong *)(Arrtmp)); // Add this Line
|
||
CAN_vTransmit(TX_MSGOBJ);
|
||
CAN_waitTransmit(TX_MSGOBJ);
|
||
}
|
||
|
||
|
||
|
||
|
||
// Flash_Wait does not take care of the timeout.
|
||
// In case programming / erasing fail, it will automatically reset the chip.
|
||
// (to be implemented)
|
||
void Flash_Wait(void)
|
||
{
|
||
ubyte ubCount0, ubCount1, ubCount2;
|
||
|
||
SYSCON0 = SYSCON0 & 0xFE;
|
||
SCU_PAGE = 0; // Mandatory
|
||
for (ubCount2=0; ubCount2 < 50; ubCount2++)
|
||
{
|
||
for (ubCount1=0; ubCount1 < 255; ubCount1++)
|
||
{
|
||
for (ubCount0=0; ubCount0 < 255; ubCount0++)
|
||
{
|
||
if (NMISR & 0x4)
|
||
{
|
||
NMISR &= ~0x04;
|
||
return;
|
||
}
|
||
}
|
||
}
|
||
}
|
||
CAN_setWDTReset();
|
||
}
|
||
|
||
|
||
|
||
void BootMain(void)
|
||
{
|
||
stCAN_SWObj StrBootRx;
|
||
ubyte ulCANData[8];
|
||
ubyte i;
|
||
|
||
//------------------------------------
|
||
if(CAN_ubNewData(RX_MSGOBJ))
|
||
{
|
||
CAN_vGetMsgObj(RX_MSGOBJ, &StrBootRx);
|
||
ulCANData[3] = StrBootRx.ulDATAL.ubDB[0];
|
||
ulCANData[2] = StrBootRx.ulDATAL.ubDB[1];
|
||
ulCANData[1] = StrBootRx.ulDATAL.ubDB[2];
|
||
ulCANData[0] = StrBootRx.ulDATAL.ubDB[3];
|
||
ulCANData[7] = StrBootRx.ulDATAH.ubDB[0];
|
||
ulCANData[6] = StrBootRx.ulDATAH.ubDB[1];
|
||
ulCANData[5] = StrBootRx.ulDATAH.ubDB[2];
|
||
ulCANData[4] = StrBootRx.ulDATAH.ubDB[3];
|
||
CAN_vReleaseObj(RX_MSGOBJ);
|
||
|
||
EA = 0;
|
||
TR2 = 0;
|
||
WDT_vDisable();//<2F><><EFBFBD><EFBFBD>WDT<44><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>boot<6F><74><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
|
||
//------------------------------------------------------------
|
||
if((ulCANData[0] == 0xaa) && (ulCANData[1] == 0xaa))//<2F><><EFBFBD><EFBFBD>
|
||
{
|
||
CAN_sendAck(ACKNOWLEDGE, 0x01);
|
||
CAN_setWDTReset();
|
||
}
|
||
//------------------------------------------------------------
|
||
else if((ulCANData[0] == 0x33) && (ulCANData[1] == 0x33))//<2F><><EFBFBD><EFBFBD>11
|
||
{
|
||
SCU_PAGE = 0;
|
||
NMISR = 0;
|
||
DFlErase(0x0, 0x0300);//<2F><><EFBFBD><EFBFBD>bank1 sector 8<><38>9
|
||
Flash_Wait(); // In case fail, the chip will generate WDT Reset
|
||
|
||
for(i=0;i<32;i++)
|
||
{
|
||
WLBuf[i] = 0;
|
||
}
|
||
WLBuf[0] = 0x11;//<2F><><EFBFBD>̱<EFBFBD>ʶ,0x6F00
|
||
DPH = 0x6F;
|
||
DPL = 0;
|
||
FlProg(&WLBuf[0]);
|
||
Flash_Wait(); // In case fail, the chip will generate WDT Reset
|
||
CAN_sendAck(ACKNOWLEDGE, 0x04);
|
||
}
|
||
//------------------------------------------------------------
|
||
else ;
|
||
}
|
||
} |