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liumin
2025-07-05 07:47:22 +08:00
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//****************************************************************************
// @Module Analog / Digital Converter (ADC)
// @Filename ADC.C
// @Project CL2.0.dav
//----------------------------------------------------------------------------
// @Controller Infineon XC886CLM-8FF
//
// @Compiler Keil
//
// @Codegenerator 1.3
//
// @Description: This file contains functions that use the ADC module.
//
//----------------------------------------------------------------------------
// @Date 2025/4/27 16:05:22
//
//****************************************************************************
// USER CODE BEGIN (ADC_General,1)
// USER CODE END
//****************************************************************************
// @Project Includes
//****************************************************************************
#include "MAIN.H"
// USER CODE BEGIN (ADC_General,2)
// USER CODE END
//****************************************************************************
// @Macros
//****************************************************************************
// USER CODE BEGIN (ADC_General,3)
// USER CODE END
//****************************************************************************
// @Defines
//****************************************************************************
// USER CODE BEGIN (ADC_General,4)
// USER CODE END
//****************************************************************************
// @Typedefs
//****************************************************************************
// USER CODE BEGIN (ADC_General,5)
// USER CODE END
//****************************************************************************
// @Imported Global Variables
//****************************************************************************
// USER CODE BEGIN (ADC_General,6)
// USER CODE END
//****************************************************************************
// @Global Variables
//****************************************************************************
// USER CODE BEGIN (ADC_General,7)
// USER CODE END
//****************************************************************************
// @External Prototypes
//****************************************************************************
// USER CODE BEGIN (ADC_General,8)
// USER CODE END
//****************************************************************************
// @Prototypes Of Local Functions
//****************************************************************************
// USER CODE BEGIN (ADC_General,9)
// USER CODE END
//****************************************************************************
// @Function void ADC_vInit(void)
//
//----------------------------------------------------------------------------
// @Description This is the initialization function of the ADC function
// library. It is assumed that the SFRs used by this library
// are in their reset state.
//
// Following SFR fields will be initialized:
// GLOBCTR - Global Control
// PRAR - Priority and Arbitration Register
// ETRCR - External Trigger Control Register
// CHCTRx - Channel Control Register x
// RCRx - Result Control Register x
//
//----------------------------------------------------------------------------
// @Returnvalue None
//
//----------------------------------------------------------------------------
// @Parameters None
//
//----------------------------------------------------------------------------
// @Date 2025/4/27
//
//****************************************************************************
// USER CODE BEGIN (ADC_Init,1)
// USER CODE END
void ADC_vInit(void)
{
// USER CODE BEGIN (ADC_Init,2)
// USER CODE END
/// -----------------------------------------------------------------------
/// Configuration of Global Control:
/// -----------------------------------------------------------------------
/// - the ADC module clock is enabled
/// - the ADC module clock = 24.00 MHz
///
/// - the result is 10 bits wide
/// --- Conversion Timing -----------------
/// - conversion time (CTC) = 17.38 us
/// - Configure global control functions
SFR_PAGE(_ad0, noSST); // switch to page 0
ADC_GLOBCTR = 0x30; // load global control register
/// -----------------------------------------------------------------------
/// Configuration of Priority and Arbitration:
/// -----------------------------------------------------------------------
/// - the priority of request source 0 is low
/// - the wait-for-start mode is selected for source 0
/// - the priority of request source 1 is high
/// - the wait-for-start mode is selected for source 1
/// - the arbitration started by pending conversion request is selected
/// - Arbitration Slot 0 is disabled
/// - Arbitration Slot 1 is enabled
ADC_PRAR = 0x94; // load Priority and Arbitration register
SFR_PAGE(_ad1, noSST); // switch to page 1
/// -----------------------------------------------------------------------
/// Configuration of Channel Control Registers:
/// -----------------------------------------------------------------------
/// Configuration of Channel 7
/// - the result register0 is selected
/// - the limit check 0 is selected
ADC_CHCTR7 = 0x00; // load channel control register
SFR_PAGE(_ad0, noSST); // switch to page 0
/// -----------------------------------------------------------------------
/// Configuration of Sample Time Control:
/// -----------------------------------------------------------------------
ADC_INPCR0 = 0x00; // load input class register
SFR_PAGE(_ad4, noSST); // switch to page 4
/// -----------------------------------------------------------------------
/// Configuration of Result Control Registers:
/// -----------------------------------------------------------------------
/// Configuration of Result Control Register 0
/// - the data reduction filter is disabled
/// - the event interrupt is disabled
/// - the wait-for-read mode is enabled
/// - the VF reset by read access to RESRxH/RESRAxH
ADC_RCR0 = 0xC0; // load result control register 0
/// Configuration of Result Control Register 1
/// - the data reduction filter is disabled
/// - the event interrupt is disabled
/// - the wait-for-read mode is disabled
/// - the VF unchaned by read access to RESRxH/RESRAxH
ADC_RCR1 = 0x00; // load result control register 1
/// Configuration of Result Control Register 2
/// - the data reduction filter is disabled
/// - the event interrupt is disabled
/// - the wait-for-read mode is disabled
/// - the VF unchaned by read access to RESRxH/RESRAxH
ADC_RCR2 = 0x00; // load result control register 2
/// Configuration of Result Control Register 3
/// - the data reduction filter is disabled
/// - the event interrupt is disabled
/// - the wait-for-read mode is disabled
/// - the VF unchaned by read access to RESRxH/RESRAxH
ADC_RCR3 = 0x00; // load result control register 3
SFR_PAGE(_ad5, noSST); // switch to page 5
/// -----------------------------------------------------------------------
/// Configuration of Channel Interrupt Node Pointer Register:
/// -----------------------------------------------------------------------
/// - the SR 0 line become activated if channel 0 interrupt is generated
/// - the SR 0 line become activated if channel 1 interrupt is generated
/// - the SR 0 line become activated if channel 2 interrupt is generated
/// - the SR 0 line become activated if channel 3 interrupt is generated
/// - the SR 0 line become activated if channel 4 interrupt is generated
/// - the SR 0 line become activated if channel 5 interrupt is generated
/// - the SR 0 line become activated if channel 6 interrupt is generated
/// - the SR 0 line become activated if channel 7 interrupt is generated
ADC_CHINPR = 0x00; // load channel interrupt node pointer
// register
/// -----------------------------------------------------------------------
/// Configuration of Event Interrupt Node Pointer Registers:
/// -----------------------------------------------------------------------
/// - the SR 0 line become activated if the event 0 interrupt is generated
/// - the SR 0 line become activated if the event 1 interrupt is generated
/// - the SR 0 line become activated if the event 4 interrupt is generated
/// - the SR 0 line become activated if the event 5 interrupt is generated
/// - the SR 0 line become activated if the event 6 interrupt is generated
/// - the SR 0 line become activated if the event 7 interrupt is generated
ADC_EVINPR = 0x00; // load event interrupt set flag register
SFR_PAGE(_ad0, noSST); // switch to page 0
/// -----------------------------------------------------------------------
/// Configuration of Limit Check Boundary:
/// -----------------------------------------------------------------------
ADC_LCBR = 0xB7; // load limit check boundary register
/// -----------------------------------------------------------------------
/// Configuration of External Trigger Control:
/// -----------------------------------------------------------------------
/// - the trigger input ETR00 is selected for Source 0
/// - the trigger input ETR10 is selected for Source 1
/// - the synchronizing stage is not in external trigger input REQTR0 path
/// - the synchronizing stage is not in external trigger input REQTR1 path
ADC_ETRCR = 0x00; // load external trigger control register
SFR_PAGE(_ad6, noSST); // switch to page 6
/// -----------------------------------------------------------------------
/// Configuration of Conversion Queue Mode Register:
/// -----------------------------------------------------------------------
/// - the gating line is permanently 0
/// - the external trigger is disabled
/// - the trigger mode 0 is selected
ADC_QMR0 = 0x00; // load queue mode register
/// -----------------------------------------------------------------------
/// Configuration of Conversion Request Mode Registers:
/// -----------------------------------------------------------------------
/// - the gating line is permanently 1
/// - the external trigger is disabled
/// - the source interrupt is disabled
/// - the autoscan functionality is disabled
ADC_CRMR1 = 0x01; // load conversion request mode register 1
SFR_PAGE(_ad0, noSST); // switch to page 0
ADC_GLOBCTR |= 0x80; // turn on Analog part
/// - ADC-Interrupt (EADC) remains disabled
// USER CODE BEGIN (ADC_Init,3)
// USER CODE END
} // End of function ADC_vInit
//****************************************************************************
// @Function void ADC_vSetLoadEvent(void)
//
//----------------------------------------------------------------------------
// @Description This function generates load event.
//
//----------------------------------------------------------------------------
// @Returnvalue None
//
//----------------------------------------------------------------------------
// @Parameters None
//
//----------------------------------------------------------------------------
// @Date 2025/4/27
//
//****************************************************************************
void ADC_vSetLoadEvent(void)
{
SFR_PAGE(_ad6, SST1); // switch to page 6
ADC_CRMR1 |= 0x40; // set LDEV
SFR_PAGE(_ad0, RST1); // restore the old ADC page
} // End of function ADC_vSetLoadEvent
//****************************************************************************
// @Function void ADC_vStartParReqChNum(ubyte ubChannelNum)
//
//----------------------------------------------------------------------------
// @Description This function strarts conversion request of analog
// channel.The possible values for the request channels are:
// Bit 4 = 1 -> analog channel 4 is requested for
// conversion
// Bit 5 = 1 -> analog channel 5 is requested for
// conversion
// Bit 6 = 1 -> analog channel 6 is requested for
// conversion
// Bit 7 = 1 -> analog channel 7 is requested for
// conversion
//
//----------------------------------------------------------------------------
// @Returnvalue None
//
//----------------------------------------------------------------------------
// @Parameters ubChannelNum:
// Name of the Valid Flag Register
//
//----------------------------------------------------------------------------
// @Date 2025/4/27
//
//****************************************************************************
void ADC_vStartParReqChNum(ubyte ubChannelNum)
{
SFR_PAGE(_ad6, SST1); // switch to page 6
ADC_CRPR1 |= ubChannelNum ; // requested channel number
SFR_PAGE(_ad0, RST1); // restore the old ADC page
} // End of function ADC_vStartParReqChNum
//****************************************************************************
// @Function ubyte ADC_ubBusy(void)
//
//----------------------------------------------------------------------------
// @Description This function checks the conversion state of the current
// ADC-channel by examination of the busy flag (BUSY). It
// returns '1' while a conversion is running.
//
//----------------------------------------------------------------------------
// @Returnvalue 1 if conversion is currently active, else 0
//
//----------------------------------------------------------------------------
// @Parameters None
//
//----------------------------------------------------------------------------
// @Date 2025/4/27
//
//****************************************************************************
ubyte ADC_ubBusy(void)
{
ubyte ubResult = 0;
SFR_PAGE(_ad0, SST1); // switch to page 0
ubResult = ADC_GLOBSTR & 0x01;
SFR_PAGE(_ad0, RST1); // restore the old ADC page
return(ubResult);
} // End of function ADC_ubBusy
//****************************************************************************
// @Function uword ADC_uwGetResultData0(void)
//
//----------------------------------------------------------------------------
// @Description This function reads the 8- or 10-bit conversion results
// from result register 0
//
//----------------------------------------------------------------------------
// @Returnvalue Conversion Result
//
//----------------------------------------------------------------------------
// @Parameters None
//
//----------------------------------------------------------------------------
// @Date 2025/4/27
//
//****************************************************************************
uword ADC_uwGetResultData0(void)
{
uword uwResult = 0;
SFR_PAGE(_ad2, SST1); // switch to page 2
if ( ADC_RESR0L & 0x10 ) // if Result Register0 contains valid data
{
// 10-bit conversion (without accumulation)
uwResult = ((ADC_RESR0L >> 6) & 0x03); // Result Register0 Low
uwResult = (((uword)(ADC_RESR0H << 2)) + uwResult); // Result Register0 High
}
SFR_PAGE(_ad0, RST1); // restore the old ADC page
return(uwResult);
} // End of function ADC_uwGetResultData0
// USER CODE BEGIN (ADC_General,10)
// USER CODE END

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//****************************************************************************
// @Module Analog / Digital Converter (ADC)
// @Filename ADC.H
// @Project CL2.0.dav
//----------------------------------------------------------------------------
// @Controller Infineon XC886CLM-8FF
//
// @Compiler Keil
//
// @Codegenerator 1.3
//
// @Description: This file contains all function prototypes and macros for
// the ADC module.
//
//----------------------------------------------------------------------------
// @Date 2025/4/27 16:05:22
//
//****************************************************************************
// USER CODE BEGIN (ADC_Header,1)
// USER CODE END
#ifndef _ADC_H_
#define _ADC_H_
//****************************************************************************
// @Project Includes
//****************************************************************************
// USER CODE BEGIN (ADC_Header,2)
// USER CODE END
//****************************************************************************
// @Macros
//****************************************************************************
// USER CODE BEGIN (ADC_Header,3)
// USER CODE END
//****************************************************************************
// @Defines
//****************************************************************************
// USER CODE BEGIN (ADC_Header,4)
// USER CODE END
#define CHANNEL_7 7
//****************************************************************************
// @Typedefs
//****************************************************************************
// USER CODE BEGIN (ADC_Header,5)
// USER CODE END
//****************************************************************************
// @Imported Global Variables
//****************************************************************************
// USER CODE BEGIN (ADC_Header,6)
// USER CODE END
//****************************************************************************
// @Global Variables
//****************************************************************************
// USER CODE BEGIN (ADC_Header,7)
// USER CODE END
//****************************************************************************
// @Prototypes Of Global Functions
//****************************************************************************
void ADC_vInit(void);
void ADC_vSetLoadEvent(void);
void ADC_vStartParReqChNum(ubyte ubChannelNum);
ubyte ADC_ubBusy(void);
uword ADC_uwGetResultData0(void);
// USER CODE BEGIN (ADC_Header,8)
// USER CODE END
//****************************************************************************
// @Interrupt Vectors
//****************************************************************************
// USER CODE BEGIN (ADC_Header,9)
// USER CODE END
#endif // ifndef _ADC_H_

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#ifndef _BOOT_H_
#define _BOOT_H_
#include "XC88x_FLADDR.H"
#define ArrXram ((ubyte volatile xdata *)0xf000)
#define DF_XramLenth 0x600
#define ArrBootCode ((ubyte volatile code *)0x7000)
#define DF_BootCodeLenth 0x600
#define ACKNOWLEDGE 0x55
#define BLOCK_ERROR 0xFF
#define TIMEOUT_ERROR 0xF0
#define PROTECTION_ERROR 0xFD
#define RX_MSGOBJ 5
#define TX_MSGOBJ 9 // Define the Message Object for Transmit (No FIFO// is supported for Transmit)
//---<2D>ⲿҪʹ<D2AA>ñ<EFBFBD><C3B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>---------------------------------------------------------------------
void BootMain(void);
void CAN_waitTransmit(ubyte RgMsgobj);
//+------------------------------------------------+
//| Global variables needed
//+------------------------------------------------+
// Buffer for the 32byte data before being written to eEPROM
extern unsigned char idata WLBuf[BYTES_PER_WORDLINE];
// Function to program the WLBuf to Flash Memory
bit ProgWL(unsigned char code *AdrBnkXSecYWLZ);
// Function to load the data from XDATA memory to WLBuf
void LoadXD2WLBuf(unsigned char xdata *address);
// Function to load the data from CODE memory to WLBuf
// This is used to copy data from one Flash location to another.
void LoadConst2WLBuf(unsigned char code *address);
// Function to load the data from CODE memory to XDATA memory
void LoadConst2XD(unsigned char xdata *dstaddress, unsigned char code *srcaddress, unsigned char length);
// Function to read a byte from CODE memory
unsigned char ReadConst(unsigned char code *address);
// All of the description of the functions below is done in XC88x_FLHANDER.ASM
// Erase Flash Sectors
// Required Stack Size = 12
extern bit PFlErase (unsigned char Bank0Sector, unsigned char Bank1Sector, unsigned char Bank2Sector);
extern bit DFlErase (unsigned int DFlash0Sector, unsigned int DFlash1Sector);
// Program Flash
// Required Stack Size = 12
extern bit FlProg(unsigned char idata *SrcBuf);
// Check if Flash is ready to read
// Bank = Bank Number to be checked
// Required Stack Size = 6
extern bit FlReady(unsigned char Bank);
// Abort the existing erase process
// Required Stack Size = 6
extern bit FlEraseAbort(void);
// Program / Remove Password.
// Detail is available in FLHANDLER.asm
extern bit FlProtect(unsigned char Password);
extern unsigned char _FlReadByte(void);
extern void FlExecute(unsigned char AddrH, unsigned char AddrL);
sfr MEM_DPH = 0x83;
sfr MEM_DPL = 0x82;
sfr MEM_NMICON = 0xBB;
sfr MEM_NMISR = 0xBC;
#endif

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#include "MAIN.H"
ubyte idata WLBuf[32] _at_ 0x80;
// This function will generate a Watchdog Reset
// The reset will be generated in about 21 us
void CAN_setWDTReset(void)
{
SFR_PAGE(_su1, noSST); // switch to page1 without saving
MAIN_vUnlockProtecReg(); // open access to protected register
SET_RMAP();
WDTCON |= 0x04; // set WDTEN
WDTREL = 0xFF; //Watch dog timer reload register
WDTCON |= 0x03; // set WDTRS,set WDTIN
RESET_RMAP();
MAIN_vlockProtecReg(); // close access to protected register
SFR_PAGE(_su0, noSST); // switch to page0 with out saving
while(1);
}
void CAN_waitTransmit(ubyte RgMsgobj)
{
ulong i;
for(i=0;(i<6000)&&(!CAN_ubRequestMsgObj(RgMsgobj));i++)WDT_vRefresh();
}
// CAN Acknowledge Frame consist of 2 data bytes.
// The first data byte is the Acknowledge Code
// The second data byte is the valid data depending on the Acknowledge Code
// TX_MSGOBJ is set to one Message object only.
void CAN_sendAck(ubyte Ack0,ubyte Ack1)
{
ubyte Arrtmp[8] = {0};
//--------------------------------------------
Arrtmp[3] = Ack0;
Arrtmp[2] = Ack1;
CAN_vLoadData(TX_MSGOBJ, (ulong *)(Arrtmp)); // Add this Line
CAN_vTransmit(TX_MSGOBJ);
CAN_waitTransmit(TX_MSGOBJ);
}
// Flash_Wait does not take care of the timeout.
// In case programming / erasing fail, it will automatically reset the chip.
// (to be implemented)
void Flash_Wait(void)
{
ubyte ubCount0, ubCount1, ubCount2;
SYSCON0 = SYSCON0 & 0xFE;
SCU_PAGE = 0; // Mandatory
for (ubCount2=0; ubCount2 < 50; ubCount2++)
{
for (ubCount1=0; ubCount1 < 255; ubCount1++)
{
for (ubCount0=0; ubCount0 < 255; ubCount0++)
{
if (NMISR & 0x4)
{
NMISR &= ~0x04;
return;
}
}
}
}
CAN_setWDTReset();
}
void BootMain(void)
{
stCAN_SWObj StrBootRx;
ubyte ulCANData[8];
ubyte i;
//------------------------------------
if(CAN_ubNewData(RX_MSGOBJ))
{
CAN_vGetMsgObj(RX_MSGOBJ, &StrBootRx);
ulCANData[3] = StrBootRx.ulDATAL.ubDB[0];
ulCANData[2] = StrBootRx.ulDATAL.ubDB[1];
ulCANData[1] = StrBootRx.ulDATAL.ubDB[2];
ulCANData[0] = StrBootRx.ulDATAL.ubDB[3];
ulCANData[7] = StrBootRx.ulDATAH.ubDB[0];
ulCANData[6] = StrBootRx.ulDATAH.ubDB[1];
ulCANData[5] = StrBootRx.ulDATAH.ubDB[2];
ulCANData[4] = StrBootRx.ulDATAH.ubDB[3];
CAN_vReleaseObj(RX_MSGOBJ);
EA = 0;
TR2 = 0;
WDT_vDisable();//<2F><><EFBFBD><EFBFBD>WDT<44><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>boot<6F><74><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
//------------------------------------------------------------
if((ulCANData[0] == 0xaa) && (ulCANData[1] == 0xaa))//<2F><><EFBFBD><EFBFBD>
{
CAN_sendAck(ACKNOWLEDGE, 0x01);
CAN_setWDTReset();
}
//------------------------------------------------------------
else if((ulCANData[0] == 0x33) && (ulCANData[1] == 0x33))//<2F><><EFBFBD><EFBFBD>11
{
SCU_PAGE = 0;
NMISR = 0;
DFlErase(0x0, 0x0300);//<2F><><EFBFBD><EFBFBD>bank1 sector 8<><38>9
Flash_Wait(); // In case fail, the chip will generate WDT Reset
for(i=0;i<32;i++)
{
WLBuf[i] = 0;
}
WLBuf[0] = 0x11;//<2F><><EFBFBD>̱<EFBFBD>ʶ,0x6F00
DPH = 0x6F;
DPL = 0;
FlProg(&WLBuf[0]);
Flash_Wait(); // In case fail, the chip will generate WDT Reset
CAN_sendAck(ACKNOWLEDGE, 0x04);
}
//------------------------------------------------------------
else ;
}
}