commit 224cea156bd5b0f37ba4eed4205c5393442ca2b6 Author: liumin Date: Tue Oct 21 21:25:35 2025 +0800 第一次提交计算机温控 diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..54a4f23 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,5 @@ +{ + "files.associations": { + "temperature.C": "cpp" + } +} \ No newline at end of file diff --git a/CAN.C b/CAN.C new file mode 100644 index 0000000..5aa54eb --- /dev/null +++ b/CAN.C @@ -0,0 +1,1356 @@ +//**************************************************************************** +// @Module MultiCAN Controller +// @Filename CAN.C +// @Project CL2.0.dav +//---------------------------------------------------------------------------- +// @Controller Infineon XC886CLM-8FF +// +// @Compiler Keil +// +// @Codegenerator 1.3 +// +// @Description: This file contains functions that use the CAN module. +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 07:12:29 +// +//**************************************************************************** + +// USER CODE BEGIN (CAN_General,1) + +// USER CODE END + + + +//**************************************************************************** +// @Project Includes +//**************************************************************************** + +#include "MAIN.H" + +// USER CODE BEGIN (CAN_General,2) + +// USER CODE END + + +//**************************************************************************** +// @Macros +//**************************************************************************** + + +// USER CODE BEGIN (CAN_General,3) + +// USER CODE END + + +//**************************************************************************** +// @Defines +//**************************************************************************** + +// USER CODE BEGIN (CAN_General,4) + +// USER CODE END + + +//**************************************************************************** +// @Typedefs +//**************************************************************************** + +// USER CODE BEGIN (CAN_General,5) + +// USER CODE END + + +//**************************************************************************** +// @Imported Global Variables +//**************************************************************************** + +// USER CODE BEGIN (CAN_General,6) + +// USER CODE END + + +//**************************************************************************** +// @Global Variables +//**************************************************************************** + + +// USER CODE BEGIN (CAN_General,7) + +// USER CODE END + + +//**************************************************************************** +// @External Prototypes +//**************************************************************************** + +// USER CODE BEGIN (CAN_General,8) + +// USER CODE END + + +//**************************************************************************** +// @Prototypes Of Local Functions +//**************************************************************************** + +// USER CODE BEGIN (CAN_General,9) + +// USER CODE END + + +//**************************************************************************** +// @Function void CAN_vInit(void) +// +//---------------------------------------------------------------------------- +// @Description This is the initialization function of the CAN function +// library. It is assumed that the SFRs used by this library +// are in their reset state. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters None +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 +// +//**************************************************************************** + +// USER CODE BEGIN (Init,1) + +// USER CODE END + +void CAN_vInit(void) +{ + + // USER CODE BEGIN (Init,2) + + // USER CODE END + + /// ----------------------------------------------------------------------- + /// Configuration of the Module Clock: + /// ----------------------------------------------------------------------- + /// - the CAN module clock = 48.00 MHz + /// - FCLK runs at 2 times the frequency of PCLK. + + /// - CMCON - Clock Control Register is Configured in MAIN_vInit + + // - wait until Panel has finished the initialisation + CAN_vWriteCANAddress(CAN_PANCTR); // Addressing CAN_PANCTR + CAN_DATA1 = CAN_PANCTR_BUSY; + while(CAN_DATA1 & CAN_PANCTR_BUSY){ // wait until Panel has finished the + // initialisation + CAN_ADCON &= ~0x01; + } + + /// ----------------------------------------------------------------------- + /// Configuration of CAN Node 0: + /// ----------------------------------------------------------------------- + + /// General Configuration of the Node 0: + /// - set INIT and CCE + + //-----------CAN_NCR0 = 0x00000041------------------------------------- + + CAN_vWriteCANAddress(CAN_NCR0); // Addressing CAN_NCR0 + CAN_DATA0 = 0x41; // load NODE 0 control register[7-0] + CAN_vWriteEN(D0_VALID+ADR_INC); // Data0 is Valid for transmission and + // Write is EnabledCAN Address pointing + // to the CAN_NSR0. + + // CAN Address pointing to the CAN_NIPR0 + CAN_ADCON = ADR_INC; // Auto Increment the current address(+1) + + /// - load NODE 0 interrupt pointer register + //-----------CAN_NIPR0 = 0x00000000------------------------------------- + + CAN_DATA0 = 0x00; // load NIPR0_LECINP, NIPR0_ALINP + CAN_DATA1 = 0x00; // load NIPR0_CFCINP, NIPR0_TRINP + CAN_vWriteEN(D0_VALID+D1_VALID+ADR_INC); // Data0 and Data1 are Valid for + // with Auto Increment + // transmission and Write is + // Enabled CAN Address pointing + // to the CAN_NPCR0 + + /// ----------------------------------------------------------------------- + /// Configuration of the used CAN Input Port Pins: + /// ----------------------------------------------------------------------- + /// - Pin P1.0 is used as RXDC0_0 input + + //-----------CAN_NPCR0 = 0x00000000------------------------------------- + /// - Loop-back mode is disabled + + CAN_DATA0 = 0x00; // Receive Select NPCR0_RXSEL + CAN_DATA1 = 0x00; // Loop-back mode is disabled + CAN_vWriteEN(D0_VALID+D1_VALID+ADR_INC); // Data0 & 1 are Valid for + // transmission and Write is + // Enabled with AutoIncrement + // CAN Address pointing to the + // CAN_NBTR0 + + + + /// Configuration of the Node 0 Baud Rate: + /// - required baud rate = 250.000 kbaud + /// - real baud rate = 252.632 kbaud + /// - sample point = 60.00 % + /// - there are 5 time quanta before sample point + /// - there are 4 time quanta after sample point + /// - the (re)synchronization jump width is 2 time quanta + + //-----------CAN_NBTR0 = 0x00003452------------------------------------- + + CAN_DATA0 = 0x52; // load NBTR0_SJW, BRP + CAN_DATA1 = 0x34; // load NBTR0_DIV8, TSEG2, TSEG1 + CAN_vWriteEN(D0_VALID+D1_VALID+ADR_INC); // Data0, 1 are valid for + // transmission and Write is + // Enabled with Auto + // Increment(+1) CAN Address + // pointing to the CAN_NECNT0 + + /// Configuration of the Node 0 Error Counter: + /// - the error warning threshold value (warning level) is 96 + + //-----------CAN_NECNT0 = 0x00600000------------------------------------- + + CAN_DATA2 = 0x60; // load NECNT0_EWRNLVL register + CAN_vWriteEN(D2_VALID+ADR_INC); // Data2 is Valid for transmission, Auto + // Increment current address(+1) and + // Write is Enabled CAN Address pointing + // to the CAN_NFCR0 + + /// Configuration of the Frame Counter: + /// - Frame Counter Mode: the counter is incremented upon the reception + /// and transmission of frames + /// - frame counter: 0x0000 + + + //-----------CAN_NFCR0 = 0x00000000------------------------------------- + + CAN_DATA0 = 0x00; // load NFCR0_CFCL + CAN_DATA1 = 0x00; // load NFCR0_CFCH + CAN_DATA2 = 0x00; // load NFCR0_CFCOV, CFCIE, CFMOD, CFSEL + CAN_vWriteEN(D0_VALID+D1_VALID+D2_VALID); // Data0, 1, 2 are valid for + // transmission and Write is + // Enabled + + /// ----------------------------------------------------------------------- + /// Configuration of CAN Node 1: + /// ----------------------------------------------------------------------- + + /// General Configuration of the Node 1: + /// - set INIT and CCE + + //-----------CAN_NCR1 = 0x00000041------------------------------------- + + CAN_vWriteCANAddress(CAN_NCR1); // Addressing CAN_NCR1 + CAN_DATA0 = 0x41; // load NODE 1 control register[7-0] + CAN_vWriteEN(D0_VALID+ADR_INC); // Data0 is Valid for transmission and + // Write is EnabledCAN Address pointing + // to the CAN_NSR1. + + /// ----------------------------------------------------------------------- + /// Configuration of the used CAN Output Port Pins: + /// ----------------------------------------------------------------------- + /// Pin P1.1 is used as TXDC0_0 Output + /// - NODE1 TXD Pin's are not used + + SFR_PAGE(_pp2, noSST); // switch to page 2 + P1_ALTSEL0 |= 0x02; // set AltSel0 + P1_ALTSEL1 |= 0x02; // set AltSel1 + + SFR_PAGE(_pp0, noSST); // switch to page 0 + P1_DIR |= 0x02; // set Direction as Output + + + /// ----------------------------------------------------------------------- + /// Configuration of the CAN Message Object List Structure: + /// ----------------------------------------------------------------------- + + CAN_vWriteCANAddress(CAN_PANCTR); // Addressing CAN_PANCTR + + /// Allocate MOs for list 1: + CAN_vSetListCommand(0x01080002); // MO8 for list 1 + CAN_vSetListCommand(0x01050002); // MO5 for list 1 + CAN_vSetListCommand(0x01060002); // MO6 for list 1 + CAN_vSetListCommand(0x01070002); // MO7 for list 1 + CAN_vSetListCommand(0x01090002); // MO9 for list 1 + CAN_vSetListCommand(0x010A0002); // MO10 for list 1 + + /// ----------------------------------------------------------------------- + /// Configuration of the CAN Message Objects 0 - 31: + /// ----------------------------------------------------------------------- + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 0: + /// ----------------------------------------------------------------------- + /// - message object 0 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 1: + /// ----------------------------------------------------------------------- + /// - message object 1 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 2: + /// ----------------------------------------------------------------------- + /// - message object 2 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 3: + /// ----------------------------------------------------------------------- + /// - message object 3 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 4: + /// ----------------------------------------------------------------------- + /// - message object 4 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 5: + /// ----------------------------------------------------------------------- + /// - message object 5 is valid + /// - message object is used as receive object + /// - this message object is assigned to list 1 (node 0) + + //--------------MOCTR5 = 0x00A00000--------------------------------------- + + CAN_vWriteCANAddress(CAN_MOCTR5); // Addressing MO5 control register + + CAN_vWriteAMData(0x00A00000); // load MO5 control register + + // CAN Address pointing to the CAN_MOAR5 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - priority class 3; transmit acceptance filtering is based on the list + /// order (like class 1) + /// - extended 29-bit identifier + /// - identifier 29-bit: 0x00000003 + + //--------------MOAR5 = 0xE0000003--------------------------------------- + + CAN_vWriteAMData(0xE0000003); // load MO5 arbitration register + + // CAN Address pointing to the CAN_MODATAH5 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MODATAH5 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO5 data register high + + // CAN Address pointing to the CAN_MODATAL5 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + //--------------MODATAL5 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO5 data register low + + // CAN Address pointing to the CAN_MOAMR5 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - only accept receive frames with matching IDE bit + /// - acceptance mask 29-bit: 0x1FFFFFFF + + //--------------CAN_MOAMR5 = 0x3FFFFFFF------------------------------------ + + CAN_vWriteAMData(0x3FFFFFFF); // load MO5 acceptance mask register + + // CAN Address pointing to the CAN_MOIPR5 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - use message pending register 0 bit position 5 + + //--------------MOIPR5 = 0x00000500--------------------------------------- + + CAN_vWriteAMData(0x00000500); // load MO5 interrupt pointer register + + // CAN Address pointing to the CAN_MOFGPR5 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MOFGPR5 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO5 FIFO/gateway pointer register + + // CAN Address pointing to the CAN_MOFCR5 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - this object is a STANDARD MESSAGE OBJECT + /// - 8 valid data bytes + + //--------------MOFCR5 = 0x08000000--------------------------------------- + + CAN_vWriteAMData(0x08000000); // load MO5 function control register + + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 6: + /// ----------------------------------------------------------------------- + /// - message object 6 is valid + /// - message object is used as transmit object + /// - this message object is assigned to list 1 (node 0) + + //--------------MOCTR6 = 0x0EA80000--------------------------------------- + + CAN_vWriteCANAddress(CAN_MOCTR6); // Addressing MO6 control register + + CAN_vWriteAMData(0x0EA80000); // load MO6 control register + + // CAN Address pointing to the CAN_MOAR6 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - priority class 3; transmit acceptance filtering is based on the list + /// order (like class 1) + /// - extended 29-bit identifier + /// - identifier 29-bit: 0x11000001 + + //--------------MOAR6 = 0xF1000001--------------------------------------- + + CAN_vWriteAMData(0xF1000001); // load MO6 arbitration register + + // CAN Address pointing to the CAN_MODATAH6 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MODATAH6 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO6 data register high + + // CAN Address pointing to the CAN_MODATAL6 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + //--------------MODATAL6 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO6 data register low + + // CAN Address pointing to the CAN_MOAMR6 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - only accept receive frames with matching IDE bit + /// - acceptance mask 29-bit: 0x1FFFFFFF + + //--------------CAN_MOAMR6 = 0x3FFFFFFF------------------------------------ + + CAN_vWriteAMData(0x3FFFFFFF); // load MO6 acceptance mask register + + // CAN Address pointing to the CAN_MOIPR6 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - use message pending register 0 bit position 6 + + //--------------MOIPR6 = 0x00000600--------------------------------------- + + CAN_vWriteAMData(0x00000600); // load MO6 interrupt pointer register + + // CAN Address pointing to the CAN_MOFGPR6 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MOFGPR6 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO6 FIFO/gateway pointer register + + // CAN Address pointing to the CAN_MOFCR6 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - this object is a STANDARD MESSAGE OBJECT + /// - 8 valid data bytes + + //--------------MOFCR6 = 0x08000000--------------------------------------- + + CAN_vWriteAMData(0x08000000); // load MO6 function control register + + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 7: + /// ----------------------------------------------------------------------- + /// - message object 7 is valid + /// - message object is used as receive object + /// - this message object is assigned to list 1 (node 0) + + //--------------MOCTR7 = 0x00A00000--------------------------------------- + + CAN_vWriteCANAddress(CAN_MOCTR7); // Addressing MO7 control register + + CAN_vWriteAMData(0x00A00000); // load MO7 control register + + // CAN Address pointing to the CAN_MOAR7 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - priority class 3; transmit acceptance filtering is based on the list + /// order (like class 1) + /// - extended 29-bit identifier + /// - identifier 29-bit: 0x11000002 + + //--------------MOAR7 = 0xF1000002--------------------------------------- + + CAN_vWriteAMData(0xF1000002); // load MO7 arbitration register + + // CAN Address pointing to the CAN_MODATAH7 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MODATAH7 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO7 data register high + + // CAN Address pointing to the CAN_MODATAL7 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + //--------------MODATAL7 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO7 data register low + + // CAN Address pointing to the CAN_MOAMR7 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - only accept receive frames with matching IDE bit + /// - acceptance mask 29-bit: 0x1FFFFFFF + + //--------------CAN_MOAMR7 = 0x3FFFFFFF------------------------------------ + + CAN_vWriteAMData(0x3FFFFFFF); // load MO7 acceptance mask register + + // CAN Address pointing to the CAN_MOIPR7 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - use message pending register 0 bit position 7 + + //--------------MOIPR7 = 0x00000700--------------------------------------- + + CAN_vWriteAMData(0x00000700); // load MO7 interrupt pointer register + + // CAN Address pointing to the CAN_MOFGPR7 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MOFGPR7 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO7 FIFO/gateway pointer register + + // CAN Address pointing to the CAN_MOFCR7 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - this object is a STANDARD MESSAGE OBJECT + /// - 8 valid data bytes + + //--------------MOFCR7 = 0x08000000--------------------------------------- + + CAN_vWriteAMData(0x08000000); // load MO7 function control register + + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 8: + /// ----------------------------------------------------------------------- + /// - message object 8 is valid + /// - message object is used as receive object + /// - this message object is assigned to list 1 (node 0) + + //--------------MOCTR8 = 0x00A00000--------------------------------------- + + CAN_vWriteCANAddress(CAN_MOCTR8); // Addressing MO8 control register + + CAN_vWriteAMData(0x00A00000); // load MO8 control register + + // CAN Address pointing to the CAN_MOAR8 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - priority class 3; transmit acceptance filtering is based on the list + /// order (like class 1) + /// - extended 29-bit identifier + /// - identifier 29-bit: 0x11000003 + + //--------------MOAR8 = 0xF1000003--------------------------------------- + + CAN_vWriteAMData(0xF1000003); // load MO8 arbitration register + + // CAN Address pointing to the CAN_MODATAH8 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MODATAH8 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO8 data register high + + // CAN Address pointing to the CAN_MODATAL8 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + //--------------MODATAL8 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO8 data register low + + // CAN Address pointing to the CAN_MOAMR8 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - only accept receive frames with matching IDE bit + /// - acceptance mask 29-bit: 0x1FFFFFFF + + //--------------CAN_MOAMR8 = 0x3FFFFFFF------------------------------------ + + CAN_vWriteAMData(0x3FFFFFFF); // load MO8 acceptance mask register + + // CAN Address pointing to the CAN_MOIPR8 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - use message pending register 0 bit position 8 + + //--------------MOIPR8 = 0x00000800--------------------------------------- + + CAN_vWriteAMData(0x00000800); // load MO8 interrupt pointer register + + // CAN Address pointing to the CAN_MOFGPR8 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MOFGPR8 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO8 FIFO/gateway pointer register + + // CAN Address pointing to the CAN_MOFCR8 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - this object is a STANDARD MESSAGE OBJECT + /// - 8 valid data bytes + + //--------------MOFCR8 = 0x08000000--------------------------------------- + + CAN_vWriteAMData(0x08000000); // load MO8 function control register + + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 9: + /// ----------------------------------------------------------------------- + /// - message object 9 is valid + /// - message object is used as transmit object + /// - this message object is assigned to list 1 (node 0) + + //--------------MOCTR9 = 0x0EA80000--------------------------------------- + + CAN_vWriteCANAddress(CAN_MOCTR9); // Addressing MO9 control register + + CAN_vWriteAMData(0x0EA80000); // load MO9 control register + + // CAN Address pointing to the CAN_MOAR9 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - priority class 3; transmit acceptance filtering is based on the list + /// order (like class 1) + /// - extended 29-bit identifier + /// - identifier 29-bit: 0x1FFFFFF0 + + //--------------MOAR9 = 0xFFFFFFF0--------------------------------------- + + CAN_vWriteAMData(0xFFFFFFF0); // load MO9 arbitration register + + // CAN Address pointing to the CAN_MODATAH9 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MODATAH9 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO9 data register high + + // CAN Address pointing to the CAN_MODATAL9 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + //--------------MODATAL9 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO9 data register low + + // CAN Address pointing to the CAN_MOAMR9 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - only accept receive frames with matching IDE bit + /// - acceptance mask 29-bit: 0x1FFFFFFF + + //--------------CAN_MOAMR9 = 0x3FFFFFFF------------------------------------ + + CAN_vWriteAMData(0x3FFFFFFF); // load MO9 acceptance mask register + + // CAN Address pointing to the CAN_MOIPR9 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - use message pending register 0 bit position 9 + + //--------------MOIPR9 = 0x00000900--------------------------------------- + + CAN_vWriteAMData(0x00000900); // load MO9 interrupt pointer register + + // CAN Address pointing to the CAN_MOFGPR9 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MOFGPR9 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO9 FIFO/gateway pointer register + + // CAN Address pointing to the CAN_MOFCR9 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - this object is a STANDARD MESSAGE OBJECT + /// - 8 valid data bytes + + //--------------MOFCR9 = 0x08000000--------------------------------------- + + CAN_vWriteAMData(0x08000000); // load MO9 function control register + + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 10: + /// ----------------------------------------------------------------------- + /// - message object 10 is valid + /// - message object is used as transmit object + /// - this message object is assigned to list 1 (node 0) + + //--------------MOCTR10 = 0x0EA80000--------------------------------------- + + CAN_vWriteCANAddress(CAN_MOCTR10); // Addressing MO10 control register + + CAN_vWriteAMData(0x0EA80000); // load MO10 control register + + // CAN Address pointing to the CAN_MOAR10 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - priority class 3; transmit acceptance filtering is based on the list + /// order (like class 1) + /// - extended 29-bit identifier + /// - identifier 29-bit: 0x11000000 + + //--------------MOAR10 = 0xF1000000--------------------------------------- + + CAN_vWriteAMData(0xF1000000); // load MO10 arbitration register + + // CAN Address pointing to the CAN_MODATAH10 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MODATAH10 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO10 data register high + + // CAN Address pointing to the CAN_MODATAL10 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + //--------------MODATAL10 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO10 data register low + + // CAN Address pointing to the CAN_MOAMR10 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - only accept receive frames with matching IDE bit + /// - acceptance mask 29-bit: 0x1FFFFFFF + + //--------------CAN_MOAMR10 = 0x3FFFFFFF------------------------------------ + + CAN_vWriteAMData(0x3FFFFFFF); // load MO10 acceptance mask register + + // CAN Address pointing to the CAN_MOIPR10 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - use message pending register 0 bit position 10 + + //--------------MOIPR10 = 0x00000A00--------------------------------------- + + CAN_vWriteAMData(0x00000A00); // load MO10 interrupt pointer register + + // CAN Address pointing to the CAN_MOFGPR10 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + + //--------------MOFGPR10 = 0x00000000--------------------------------------- + + CAN_vWriteAMData(0x00000000); // load MO10 FIFO/gateway pointer register + + // CAN Address pointing to the CAN_MOFCR10 + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + /// - this object is a STANDARD MESSAGE OBJECT + /// - 8 valid data bytes + + //--------------MOFCR10 = 0x08000000--------------------------------------- + + CAN_vWriteAMData(0x08000000); // load MO10 function control register + + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 11: + /// ----------------------------------------------------------------------- + /// - message object 11 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 12: + /// ----------------------------------------------------------------------- + /// - message object 12 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 13: + /// ----------------------------------------------------------------------- + /// - message object 13 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 14: + /// ----------------------------------------------------------------------- + /// - message object 14 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 15: + /// ----------------------------------------------------------------------- + /// - message object 15 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 16: + /// ----------------------------------------------------------------------- + /// - message object 16 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 17: + /// ----------------------------------------------------------------------- + /// - message object 17 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 18: + /// ----------------------------------------------------------------------- + /// - message object 18 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 19: + /// ----------------------------------------------------------------------- + /// - message object 19 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 20: + /// ----------------------------------------------------------------------- + /// - message object 20 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 21: + /// ----------------------------------------------------------------------- + /// - message object 21 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 22: + /// ----------------------------------------------------------------------- + /// - message object 22 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 23: + /// ----------------------------------------------------------------------- + /// - message object 23 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 24: + /// ----------------------------------------------------------------------- + /// - message object 24 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 25: + /// ----------------------------------------------------------------------- + /// - message object 25 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 26: + /// ----------------------------------------------------------------------- + /// - message object 26 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 27: + /// ----------------------------------------------------------------------- + /// - message object 27 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 28: + /// ----------------------------------------------------------------------- + /// - message object 28 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 29: + /// ----------------------------------------------------------------------- + /// - message object 29 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 30: + /// ----------------------------------------------------------------------- + /// - message object 30 is not valid + /// ----------------------------------------------------------------------- + /// Configuration of Message Object 31: + /// ----------------------------------------------------------------------- + /// - message object 31 is not valid + + /// ----------------------------------------------------------------------- + /// Configuration of the Interrupts: + /// ----------------------------------------------------------------------- + /// - CAN interrupt node 0 is disabled + /// - CAN interrupt node 1 is disabled + /// - CAN interrupt node 2 is disabled + /// - CAN interrupt node 3 is disabled + /// - CAN interrupt node 4 is disabled + /// - CAN interrupt node 5 is disabled + /// - CAN interrupt node 6 is disabled + /// - CAN interrupt node 7 is disabled + + + // ----------------------------------------------------------------------- + // Start the CAN Nodes: + // ----------------------------------------------------------------------- + + /// - -----------CAN_NCR0-------------------------------------------------------- + + CAN_vWriteCANAddress(CAN_NCR0); // Addressing CAN_NCR0 + CAN_vReadEN(); // Read Mode is Enabled + CAN_DATA0 &= ~0x41; // reset INIT and CCE + CAN_vWriteEN(D0_VALID); // Data0 is Valid for transmission and Write + // is Enabled + + + + // USER CODE BEGIN (Init,3) + + // USER CODE END + +} // End of function CAN_vInit + +//**************************************************************************** +// @Function void CAN_vWriteAMData(ulong ulValue) +// +//---------------------------------------------------------------------------- +// @Description This function writes 32-bit Data to CAN Data Register's +// 0-3respectively. +// Note: +// Write Process : +// ->Write the address of the MultiCAN kernel register to the +// CAN_ADL and CAN_ADH registers. +// use macro : CAN_vWriteCANAddress. +// ->Write the data to the +// CAN_DATA0/CAN_DATA1/CAN_DATA2/CAN_DATA3 registers. +// ->Write the register CAN_ADCON, including setting the valid +// bit of the data registers and setting register bit RWEN to +// 1. +// ->The valid data will be written to the MultiCAN kernel +// only once. Register bit BSY will become 1. +// ->When Register bit BSY becomes 0, the transmission is +// finished. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ulValue: +// 32-bit Data +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 +// +//**************************************************************************** + +// USER CODE BEGIN (WriteAMData,1) + +// USER CODE END + +void CAN_vWriteAMData(ulong ulValue) +{ + un_32bit ulData; + ulData.ulVal = ulValue; + + CAN_DATA0 = ulData.ubDB[3]; // load CAN Data Register 0 + CAN_DATA1 = ulData.ubDB[2]; // load CAN Data Register 1 + CAN_DATA2 = ulData.ubDB[1]; // load CAN Data Register 2 + CAN_DATA3 = ulData.ubDB[0]; // load CAN Data Register 3 + CAN_vWriteEN(ALL_DATA_VALID); // Writemode is Enabled +} // End of function CAN_vWriteAMData + +//**************************************************************************** +// @Function void CAN_vSetListCommand(ulong ulVal) +// +//---------------------------------------------------------------------------- +// @Description This function write's 32-bit Data to CAN_PANCTR Register. +// +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ulVal: +// 32-bit Data +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 +// +//**************************************************************************** + +// USER CODE BEGIN (SetListCommand,1) + +// USER CODE END + +void CAN_vSetListCommand(ulong ulVal) +{ + CAN_vWriteAMData(ulVal); // - load Panel Control Register + CAN_DATA1 = CAN_PANCTR_BUSY; + while(CAN_DATA1 & CAN_PANCTR_BUSY){ // wait until Panel has finished the + // initialisation + CAN_ADCON &= ~0x01; + } +} // End of function CAN_vSetListCommand + +//**************************************************************************** +// @Function void CAN_vGetMsgObj(ubyte ubObjNr, stCAN_SWObj *pstObj) +// +//---------------------------------------------------------------------------- +// @Description This function fills the forwarded SW message object with +// the content of the chosen HW message object. +// +// The structure of the SW message object is defined in the +// header file CAN.H (see stCAN_SWObj). +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object to be read (0-31) +// @Parameters *pstObj: +// Pointer on a message object to be filled by this function +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 +// +//**************************************************************************** + +// USER CODE BEGIN (GetMsgObj,1) + +// USER CODE END + +void CAN_vGetMsgObj(ubyte ubObjNr, stCAN_SWObj *pstObj) +{ +ubyte ubTemp; + + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + //----- get DLC ------------------------------------------------------- + + CAN_vWriteCANAddress(CAN_MOFCR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + + pstObj->ubMOdlc = CAN_DATA3;//MOFCRn[31-24] DLC + + //----- get MODATAL --------------------------------------------------- + CAN_vWriteCANAddress(CAN_MODATAL(ubObjNr)); + + CAN_vReadEN(); // Readmode is Enabled + pstObj->ulDATAL.ubDB[3] = CAN_DATA0; // Read CAN Data Register 0 + pstObj->ulDATAL.ubDB[2] = CAN_DATA1; // Read CAN Data Register 1 + pstObj->ulDATAL.ubDB[1] = CAN_DATA2; // Read CAN Data Register 2 + pstObj->ulDATAL.ubDB[0] = CAN_DATA3; // Read CAN Data Register 3 + + // CAN Address pointing to the CAN_MODATAH + CAN_ADCON = ADR_INC; + + //----- get MODATAH --------------------------------------------------- + + CAN_vReadEN(); // Readmode is Enabled + pstObj->ulDATAH.ubDB[3] = CAN_DATA0; // Read CAN Data Register 0 + pstObj->ulDATAH.ubDB[2] = CAN_DATA1; // Read CAN Data Register 1 + pstObj->ulDATAH.ubDB[1] = CAN_DATA2; // Read CAN Data Register 2 + pstObj->ulDATAH.ubDB[0] = CAN_DATA3; // Read CAN Data Register 3 + + //----- get DIR ------------------------------------------------------- + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + + if(CAN_DATA1 & 0x08) // if transmit object (MOSTAT_DIR) + { + pstObj->ubMOcfg = (pstObj->ubMOcfg | 0x08); // set DIR + } + + //----- get XID - Extended Identifier --------------------------------- + + // CAN Address pointing to the CAN_MOARn + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + CAN_vReadEN(); // ReadMode is Enabled + + if(CAN_DATA3 & 0x20) // if extended identifier + { + + //----- get XID - Extended Identifier (MOARn) ------------------------ + pstObj->ulID.ubDB[3] = CAN_DATA0; // MOARn[7-0] + pstObj->ulID.ubDB[2] = CAN_DATA1; // MOARn[15-8] + pstObj->ulID.ubDB[1] = CAN_DATA2; // MOARn[23-16] + pstObj->ulID.ubDB[0] = (CAN_DATA3 & 0x1f); // MOARn[31-24] + + // CAN Address pointing to the CAN_MODATAH + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MODATAL + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MOAMR + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + CAN_vReadEN(); // ReadMode is Enabled + + //----- get XID - Extended Acceptance Mask (MOAMRn) ----------------- + pstObj->ulMask.ubDB[3] = CAN_DATA0; // MOAMRn[7-0] + pstObj->ulMask.ubDB[2] = CAN_DATA1; // MOAMRn[15-8] + pstObj->ulMask.ubDB[1] = CAN_DATA2; // MOAMRn[23-16] + pstObj->ulMask.ubDB[0] = (CAN_DATA3 & 0x1f); // MOAMRn[31-24] + + pstObj->ubMOcfg = (pstObj->ubMOcfg | 0x04); // set IDE 29-bit + } + else // standard identifier + { + //----- get - ID - Standard Identifier (MOARn) --------------------- + pstObj->ulID.ubDB[3] = (CAN_DATA2 & 0xFC) >> 2; // MOARn[23-16] + pstObj->ulID.ubDB[2] = (CAN_DATA3 & 0x1f); // MOARn[31-24] + pstObj->ulID.ubDB[1] = 0x00; // MOARn[15-8] + pstObj->ulID.ubDB[0] = 0x00; // MOARn[15-8] + + ubTemp = 0; + ubTemp = ((pstObj->ulID.ubDB[2]) & 0x03) << 6; + pstObj->ulID.ubDB[2] = (pstObj->ulID.ubDB[2] >> 2); + pstObj->ulID.ubDB[3] = (pstObj->ulID.ubDB[3] + ubTemp); + + // CAN Address pointing to the CAN_MODATAH + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MODATAL + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MOAMR + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + CAN_vReadEN(); // ReadMode is Enabled + + //----- get - ID - Acceptance Mask (MOAMRn) ----------------------- + + pstObj->ulMask.ubDB[3] = (CAN_DATA2 & 0xFC) >> 2; // MOAMRn[23-16] + pstObj->ulMask.ubDB[2] = (CAN_DATA3 & 0x1f); // MOAMRn[31-24] + pstObj->ulMask.ubDB[1] = 0x00; // MOAMRn[15-8] + pstObj->ulMask.ubDB[0] = 0x00; // MOAMRn[15-8] + + ubTemp = 0; + ubTemp = ((pstObj->ulMask.ubDB[2]) & 0x03) << 6; + pstObj->ulMask.ubDB[2] = (pstObj->ulMask.ubDB[2] >> 2); + pstObj->ulMask.ubDB[3] = (pstObj->ulMask.ubDB[3] + ubTemp); + } + + //----- get CFCVAL - CAN Frame Counter Value (MOIPRn) ----------------- + + CAN_vWriteCANAddress(CAN_MOIPR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + + pstObj->uwCounter.ubDB[1] = CAN_DATA2; // MOIPRn[16-23] + pstObj->uwCounter.ubDB[0] = CAN_DATA3; // MOIPRn[31-24] + + CAN_popAMRegs(); // POP the CAN Access Mediator Register +} // End of function CAN_vGetMsgObj + +//**************************************************************************** +// @Function ubyte CAN_ubRequestMsgObj(ubyte ubObjNr) +// +//---------------------------------------------------------------------------- +// @Description If a TRANSMIT OBJECT is to be reconfigured it must first be +// accessed. The access to the transmit object is exclusive. +// This function checks whether the choosen message object is +// still executing a transmit request, or if the object can be +// accessed exclusively. +// After the message object is reserved, it can be +// reconfigured by using the function CAN_vConfigMsgObj or +// CAN_vLoadData. +// Both functions enable access to the object for the CAN +// controller. +// By calling the function CAN_vTransmit transfering of data +// is started. +// +//---------------------------------------------------------------------------- +// @Returnvalue 0 message object is busy (a transfer is active), else 1 +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object (0-31) +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 +// +//**************************************************************************** + +// USER CODE BEGIN (RequestMsgObj,1) + +// USER CODE END + +ubyte CAN_ubRequestMsgObj(ubyte ubObjNr) +{ +ubyte ubReturn = 0; + + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + + if((CAN_DATA1 & 0x01) == 0) // if reset TXRQ + { + CAN_vWriteCANData(0x00000020); // reset MSGVAL + ubReturn = 1; + } + CAN_popAMRegs(); // POP the CAN Access Mediator Register + +return(ubReturn); +} // End of function CAN_ubRequestMsgObj + +//**************************************************************************** +// @Function ubyte CAN_ubNewData(ubyte ubObjNr) +// +//---------------------------------------------------------------------------- +// @Description This function checks whether the selected RECEIVE OBJECT +// has received a new message. If so the function returns the +// value '1'. +// +//---------------------------------------------------------------------------- +// @Returnvalue 1 the message object has received a new message, else 0 +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object (0-31) +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 +// +//**************************************************************************** + +// USER CODE BEGIN (NewData,1) + +// USER CODE END + +ubyte CAN_ubNewData(ubyte ubObjNr) +{ +ubyte ubReturn = 0; + + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + if(CAN_DATA0 & 0x08) // if NEWDAT + { + ubReturn = 1; + } + CAN_popAMRegs(); // POP the CAN Access Mediator Register + +return(ubReturn); +} // End of function CAN_ubNewData + +//**************************************************************************** +// @Function void CAN_vTransmit(ubyte ubObjNr) +// +//---------------------------------------------------------------------------- +// @Description This function triggers the CAN controller to send the +// selected message. +// If the selected message object is a TRANSMIT OBJECT then +// this function triggers the sending of a data frame. If +// however the selected message object is a RECEIVE OBJECT +// this function triggers the sending of a remote frame. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object (0-31) +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 +// +//**************************************************************************** + +// USER CODE BEGIN (Transmit,1) + +// USER CODE END + +void CAN_vTransmit(ubyte ubObjNr) +{ + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); //Addressing CAN_MOCTR register + CAN_vWriteCANData(0x07200000); // set TXRQ,TXEN0,TXEN1,MSGVAL + + CAN_popAMRegs(); // POP the CAN Access Mediator Register + +} // End of function CAN_vTransmit + +//**************************************************************************** +// @Function void CAN_vLoadData(ubyte ubObjNr, ulong *ulpubData) +// +//---------------------------------------------------------------------------- +// @Description If a hardware TRANSMIT OBJECT has to be loaded with data +// but not with a new identifier, this function may be used +// instead of the function CAN_vConfigMsgObj. The message +// object should be accessed by calling the function +// CAN_ubRequestMsgObj before calling this function. This +// prevents the CAN controller from working with invalid data. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object to be configured (0-31) +// @Parameters *ulpubData: +// Pointer on a data buffer +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 +// +//**************************************************************************** + +// USER CODE BEGIN (LoadData,1) + +// USER CODE END + +void CAN_vLoadData(ubyte ubObjNr, ulong *ulpubData) +{ + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); // Addressing CAN_MOCTRn register + CAN_vWriteCANData(0x00080000); // Set NEWDATA + + // CAN Address pointing to the CAN_MOARn + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MODATAHn + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MODATALn + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + CAN_vWriteCANData(*ulpubData); // Loading CAN_MODATALn + + // CAN Address pointing to the CAN_MODATAH + CAN_ADCON = ADR_INC; // Auto Increment the current address(+1) + + ulpubData++; + + CAN_vWriteCANData(*ulpubData); // Loading CAN_MODATAHn + + // CAN Address pointing to the CAN_MOARn + CAN_ADCON = ADR_INC; // Auto Increment the current address(+1) + + // CAN Address pointing to the CAN_MOCTRn + CAN_ADCON = ADR_INC; // Auto Increment the current address(+1) + + CAN_vWriteCANData(0x00200040); // reset RTSEL, set MSGVAL + + CAN_popAMRegs(); // POP the CAN Access Mediator Register + +} // End of function CAN_vLoadData + +//**************************************************************************** +// @Function void CAN_vReleaseObj(ubyte ubObjNr) +// +//---------------------------------------------------------------------------- +// @Description This function resets the NEWDAT flag of the selected +// RECEIVE OBJECT, so that the CAN controller have access to +// it. This function must be called if the function +// CAN_ubNewData detects, that new data are present in the +// message object and the actual data have been read by +// calling the function CAN_vGetMsgObj. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object (0-31) +// +//---------------------------------------------------------------------------- +// @Date 2025/3/30 +// +//**************************************************************************** + +// USER CODE BEGIN (ReleaseObj,1) + +// USER CODE END + +void CAN_vReleaseObj(ubyte ubObjNr) +{ + + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); // Addressing CAN_MOCTRn register + CAN_vWriteCANData(0x00000008); // reset NEWDAT + + CAN_popAMRegs(); // POP the CAN Access Mediator Register +} // End of function CAN_vReleaseObj + + +// USER CODE BEGIN (CAN_General,10) + +// USER CODE END + diff --git a/CAN.H b/CAN.H new file mode 100644 index 0000000..b9cc6f6 --- /dev/null +++ b/CAN.H @@ -0,0 +1,762 @@ +//**************************************************************************** +// @Module MultiCAN Controller +// @Filename CAN.H +// @Project CL2.0.dav +//---------------------------------------------------------------------------- +// @Controller Infineon XC886CLM-8FF +// +// @Compiler Keil +// +// @Codegenerator 1.3 +// +// @Description: This file contains all function prototypes and macros for +// the CAN module. +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 20:45:35 +// +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,1) + +// USER CODE END + + + +#ifndef _CAN_H_ +#define _CAN_H_ + +//**************************************************************************** +// @Project Includes +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,2) + +// USER CODE END + + +//**************************************************************************** +// @Macros +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,3) + +// USER CODE END + + +//**************************************************************************** +// @Defines +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,4) + +// USER CODE END + + +//**************************************************************************** +// @Typedefs +//**************************************************************************** + + +//**************************************************************************** +// @Declaration of SFRs +//**************************************************************************** + + +#define CAN_LIST0 0x0040 +#define CAN_LIST1 0x0041 +#define CAN_LIST2 0x0042 +#define CAN_LIST3 0x0043 +#define CAN_LIST4 0x0044 +#define CAN_LIST5 0x0045 +#define CAN_LIST6 0x0046 +#define CAN_LIST7 0x0047 +#define CAN_MCR 0x0072 +#define CAN_MITR 0x0073 +#define CAN_MOAMR0 0x0403 +#define CAN_MOAMR1 0x040b +#define CAN_MOAMR10 0x0453 +#define CAN_MOAMR11 0x045B +#define CAN_MOAMR12 0x0463 +#define CAN_MOAMR13 0x046B +#define CAN_MOAMR14 0x0473 +#define CAN_MOAMR15 0x047B +#define CAN_MOAMR16 0x0483 +#define CAN_MOAMR17 0x048B +#define CAN_MOAMR18 0x0493 +#define CAN_MOAMR19 0x049B +#define CAN_MOAMR2 0x0413 +#define CAN_MOAMR20 0x04A3 +#define CAN_MOAMR21 0x04AB +#define CAN_MOAMR22 0x04B3 +#define CAN_MOAMR23 0x04BB +#define CAN_MOAMR24 0x04C3 +#define CAN_MOAMR25 0x04CB +#define CAN_MOAMR26 0x04D3 +#define CAN_MOAMR27 0x04DB +#define CAN_MOAMR28 0x04E3 +#define CAN_MOAMR29 0x04EB +#define CAN_MOAMR3 0x041B +#define CAN_MOAMR30 0x04F3 +#define CAN_MOAMR31 0x04FB +#define CAN_MOAMR4 0x0423 +#define CAN_MOAMR5 0x042B +#define CAN_MOAMR6 0x0433 +#define CAN_MOAMR7 0x043B +#define CAN_MOAMR8 0x0443 +#define CAN_MOAMR9 0x044B +#define CAN_MOAR0 0x0406 +#define CAN_MOAR1 0x040e +#define CAN_MOAR10 0x0456 +#define CAN_MOAR11 0x045E +#define CAN_MOAR12 0x0466 +#define CAN_MOAR13 0x046E +#define CAN_MOAR14 0x0476 +#define CAN_MOAR15 0x047E +#define CAN_MOAR16 0x0486 +#define CAN_MOAR17 0x048E +#define CAN_MOAR18 0x0496 +#define CAN_MOAR19 0x049E +#define CAN_MOAR2 0x0416 +#define CAN_MOAR20 0x04A6 +#define CAN_MOAR21 0x04AE +#define CAN_MOAR22 0x04B6 +#define CAN_MOAR23 0x04BE +#define CAN_MOAR24 0x04C6 +#define CAN_MOAR25 0x04CE +#define CAN_MOAR26 0x04D6 +#define CAN_MOAR27 0x04DE +#define CAN_MOAR28 0x04E6 +#define CAN_MOAR29 0x04EE +#define CAN_MOAR3 0x041E +#define CAN_MOAR30 0x04F6 +#define CAN_MOAR31 0x04FE +#define CAN_MOAR4 0x0426 +#define CAN_MOAR5 0x042E +#define CAN_MOAR6 0x0436 +#define CAN_MOAR7 0x043E +#define CAN_MOAR8 0x0446 +#define CAN_MOAR9 0x044E +#define CAN_MOCTR0 0x0407 +#define CAN_MOCTR1 0x040f +#define CAN_MOCTR10 0x0457 +#define CAN_MOCTR11 0x045F +#define CAN_MOCTR12 0x0467 +#define CAN_MOCTR13 0x046F +#define CAN_MOCTR14 0x0477 +#define CAN_MOCTR15 0x047F +#define CAN_MOCTR16 0x0487 +#define CAN_MOCTR17 0x048F +#define CAN_MOCTR18 0x0497 +#define CAN_MOCTR19 0x049F +#define CAN_MOCTR2 0x0417 +#define CAN_MOCTR20 0x04A7 +#define CAN_MOCTR21 0x04AF +#define CAN_MOCTR22 0x04B7 +#define CAN_MOCTR23 0x04BF +#define CAN_MOCTR24 0x04C7 +#define CAN_MOCTR25 0x04CF +#define CAN_MOCTR26 0x04D7 +#define CAN_MOCTR27 0x04DF +#define CAN_MOCTR28 0x04E7 +#define CAN_MOCTR29 0x04EF +#define CAN_MOCTR3 0x041F +#define CAN_MOCTR30 0x04F7 +#define CAN_MOCTR31 0x04FF +#define CAN_MOCTR4 0x0427 +#define CAN_MOCTR5 0x042F +#define CAN_MOCTR6 0x0437 +#define CAN_MOCTR7 0x043F +#define CAN_MOCTR8 0x0447 +#define CAN_MOCTR9 0x044F +#define CAN_MODATAH0 0x0405 +#define CAN_MODATAH1 0x040d +#define CAN_MODATAH10 0x0455 +#define CAN_MODATAH11 0x045D +#define CAN_MODATAH12 0x0465 +#define CAN_MODATAH13 0x046D +#define CAN_MODATAH14 0x0475 +#define CAN_MODATAH15 0x047D +#define CAN_MODATAH16 0x0485 +#define CAN_MODATAH17 0x048D +#define CAN_MODATAH18 0x0495 +#define CAN_MODATAH19 0x049D +#define CAN_MODATAH2 0x0415 +#define CAN_MODATAH20 0x04A5 +#define CAN_MODATAH21 0x04AD +#define CAN_MODATAH22 0x04B5 +#define CAN_MODATAH23 0x04BD +#define CAN_MODATAH24 0x04C5 +#define CAN_MODATAH25 0x04CD +#define CAN_MODATAH26 0x04D5 +#define CAN_MODATAH27 0x04DD +#define CAN_MODATAH28 0x04E5 +#define CAN_MODATAH29 0x04ED +#define CAN_MODATAH3 0x041D +#define CAN_MODATAH30 0x04F5 +#define CAN_MODATAH31 0x04FD +#define CAN_MODATAH4 0x0425 +#define CAN_MODATAH5 0x042D +#define CAN_MODATAH6 0x0435 +#define CAN_MODATAH7 0x043D +#define CAN_MODATAH8 0x0445 +#define CAN_MODATAH9 0x044D +#define CAN_MODATAL0 0x0404 +#define CAN_MODATAL1 0x040c +#define CAN_MODATAL10 0x0454 +#define CAN_MODATAL11 0x045C +#define CAN_MODATAL12 0x0464 +#define CAN_MODATAL13 0x046C +#define CAN_MODATAL14 0x0474 +#define CAN_MODATAL15 0x047C +#define CAN_MODATAL16 0x0484 +#define CAN_MODATAL17 0x048C +#define CAN_MODATAL18 0x0494 +#define CAN_MODATAL19 0x049C +#define CAN_MODATAL2 0x0414 +#define CAN_MODATAL20 0x04A4 +#define CAN_MODATAL21 0x04AC +#define CAN_MODATAL22 0x04B4 +#define CAN_MODATAL23 0x04BC +#define CAN_MODATAL24 0x04C4 +#define CAN_MODATAL25 0x04CC +#define CAN_MODATAL26 0x04D4 +#define CAN_MODATAL27 0x04DC +#define CAN_MODATAL28 0x04E4 +#define CAN_MODATAL29 0x04EC +#define CAN_MODATAL3 0x041C +#define CAN_MODATAL30 0x04F4 +#define CAN_MODATAL31 0x04FC +#define CAN_MODATAL4 0x0424 +#define CAN_MODATAL5 0x042C +#define CAN_MODATAL6 0x0434 +#define CAN_MODATAL7 0x043C +#define CAN_MODATAL8 0x0444 +#define CAN_MODATAL9 0x044C +#define CAN_MOFCR0 0x0400 +#define CAN_MOFCR1 0x0408 +#define CAN_MOFCR10 0x0450 +#define CAN_MOFCR11 0x0458 +#define CAN_MOFCR12 0x0460 +#define CAN_MOFCR13 0x0468 +#define CAN_MOFCR14 0x0470 +#define CAN_MOFCR15 0x0478 +#define CAN_MOFCR16 0x0480 +#define CAN_MOFCR17 0x0488 +#define CAN_MOFCR18 0x0490 +#define CAN_MOFCR19 0x0498 +#define CAN_MOFCR2 0x0410 +#define CAN_MOFCR20 0x04A0 +#define CAN_MOFCR21 0x04A8 +#define CAN_MOFCR22 0x04B0 +#define CAN_MOFCR23 0x04B8 +#define CAN_MOFCR24 0x04C0 +#define CAN_MOFCR25 0x04C8 +#define CAN_MOFCR26 0x04D0 +#define CAN_MOFCR27 0x04D8 +#define CAN_MOFCR28 0x04E0 +#define CAN_MOFCR29 0x04E8 +#define CAN_MOFCR3 0x0418 +#define CAN_MOFCR30 0x04F0 +#define CAN_MOFCR31 0x04F8 +#define CAN_MOFCR4 0x0420 +#define CAN_MOFCR5 0x0428 +#define CAN_MOFCR6 0x0430 +#define CAN_MOFCR7 0x0438 +#define CAN_MOFCR8 0x0440 +#define CAN_MOFCR9 0x0448 +#define CAN_MOFGPR0 0x0401 +#define CAN_MOFGPR1 0x0409 +#define CAN_MOFGPR10 0x0451 +#define CAN_MOFGPR11 0x0459 +#define CAN_MOFGPR12 0x0461 +#define CAN_MOFGPR13 0x0469 +#define CAN_MOFGPR14 0x0471 +#define CAN_MOFGPR15 0x0479 +#define CAN_MOFGPR16 0x0481 +#define CAN_MOFGPR17 0x0489 +#define CAN_MOFGPR18 0x0491 +#define CAN_MOFGPR19 0x0499 +#define CAN_MOFGPR2 0x0411 +#define CAN_MOFGPR20 0x04A1 +#define CAN_MOFGPR21 0x04A9 +#define CAN_MOFGPR22 0x04B1 +#define CAN_MOFGPR23 0x04B9 +#define CAN_MOFGPR24 0x04C1 +#define CAN_MOFGPR25 0x04C9 +#define CAN_MOFGPR26 0x04D1 +#define CAN_MOFGPR27 0x04D9 +#define CAN_MOFGPR28 0x04E1 +#define CAN_MOFGPR29 0x04E9 +#define CAN_MOFGPR3 0x0419 +#define CAN_MOFGPR30 0x04F1 +#define CAN_MOFGPR31 0x04F9 +#define CAN_MOFGPR4 0x0421 +#define CAN_MOFGPR5 0x0429 +#define CAN_MOFGPR6 0x0431 +#define CAN_MOFGPR7 0x0439 +#define CAN_MOFGPR8 0x0441 +#define CAN_MOFGPR9 0x0449 +#define CAN_MOIPR0 0x0402 +#define CAN_MOIPR1 0x040a +#define CAN_MOIPR10 0x0452 +#define CAN_MOIPR11 0x045A +#define CAN_MOIPR12 0x0462 +#define CAN_MOIPR13 0x046A +#define CAN_MOIPR14 0x0472 +#define CAN_MOIPR15 0x047A +#define CAN_MOIPR16 0x0482 +#define CAN_MOIPR17 0x048A +#define CAN_MOIPR18 0x0492 +#define CAN_MOIPR19 0x049A +#define CAN_MOIPR2 0x0412 +#define CAN_MOIPR20 0x04A2 +#define CAN_MOIPR21 0x04AA +#define CAN_MOIPR22 0x04B2 +#define CAN_MOIPR23 0x04BA +#define CAN_MOIPR24 0x04C2 +#define CAN_MOIPR25 0x04CA +#define CAN_MOIPR26 0x04D2 +#define CAN_MOIPR27 0x04DA +#define CAN_MOIPR28 0x04E2 +#define CAN_MOIPR29 0x04EA +#define CAN_MOIPR3 0x041a +#define CAN_MOIPR30 0x04F2 +#define CAN_MOIPR31 0x04FA +#define CAN_MOIPR4 0x0422 +#define CAN_MOIPR5 0x042a +#define CAN_MOIPR6 0x0432 +#define CAN_MOIPR7 0x043A +#define CAN_MOIPR8 0x0442 +#define CAN_MOIPR9 0x044A +#define CAN_MSID0 0x0050 +#define CAN_MSID1 0x0051 +#define CAN_MSIMASK 0x0070 +#define CAN_MSPND0 0x0048 +#define CAN_MSPND1 0x0049 +#define CAN_NBTR0 0x0084 +#define CAN_NBTR1 0x00C4 +#define CAN_NCR0 0x0080 +#define CAN_NCR1 0x00C0 +#define CAN_NECNT0 0x0085 +#define CAN_NECNT1 0x00C5 +#define CAN_NFCR0 0x0086 +#define CAN_NFCR1 0x00C6 +#define CAN_NIPR0 0x0082 +#define CAN_NIPR1 0x00C2 +#define CAN_NPCR0 0x0083 +#define CAN_NPCR1 0x00C3 +#define CAN_NSR0 0x0081 +#define CAN_NSR1 0x00C1 +#define CAN_PANCTR 0x0071 + + + //------------------------------------------------------------ + //-- CAN Message Object x ------------------------------------ + //------------------------------------------------------------ + //------------------------------------------------------------ + // Note: DAvE Ignores Lower Address Lines A[1:0] + // + // MO = Message Ojbect; n = 31-0 + // MO base = 400H + n * 20H + // + // Message Object 0 Address Map... + // __________ + // |MOCTRn | -> 0x0407 + // |----------| + // |MOARn | -> 0x0406 + // |----------| + // |MODATAHn | -> 0x0405 + // |----------| + // |MODATALn | -> 0x0404 + // |----------| + // |MOAMRn | -> 0x0403 + // |----------| + // |MOOIPRn | -> 0x0402 + // |----------| + // |MOFGPRn | -> 0x0401 + // |----------| + // |MOFCRn | -> 0x0400 + // |__________| + // + //------------------------------------------------------------ + //------------------------------------------------------------ + //-- CAN Message Object x ------------------------------------ + //------------------------------------------------------------ + #define MO_BASE 0x0400 + + //------------------------------------------------------------ + //-- CAN Message Object 0-31 ------------------------------------ + //------------------------------------------------------------ + + // Message Object Nr Function Control Register + #define CAN_MOFCR(Nr) (MO_BASE + (Nr * 8)) + + // Message Object Nr FIFO/Gateway Pointer Register + #define CAN_MOFGPR(Nr) (MO_BASE + 01 + (Nr * 8)) + + // Message Object Nr Interrupt Pointer Register + #define CAN_MOIPR(Nr) (MO_BASE + 02 + (Nr * 8)) + + // Message Object Nr Acceptance Mask Register + #define CAN_MOAMR(Nr) (MO_BASE + 03 + (Nr * 8)) + + // Message Object Nr Data Register Low + #define CAN_MODATAL(Nr) (MO_BASE + 04 + (Nr * 8)) + + // Message Object Nr Data Register High + #define CAN_MODATAH(Nr) (MO_BASE + 05 + (Nr * 8)) + + // Message Object Nr Arbitration Register + #define CAN_MOAR(Nr) (MO_BASE + 06 + (Nr * 8)) + + // Message Object Nr Control Register + #define CAN_MOCTR(Nr) (MO_BASE + 07 + (Nr * 8)) + + //------------------------------------------------------------ + //-- CAN Node Registers 0-1 ---------------------------------- + //------------------------------------------------------------ + + // Node x Error Counter Register + #define CAN_NECNT(Nr) (CAN_NECNT0 + (Nr * 0x40)) + + //**************************************************************************** + // @Defines + //**************************************************************************** + + // Panel Busy Flag +#define CAN_PANCTR_BUSY 0x01 + +// Message Object Status Register +#define MOSTAT_RXPND 0x01 +#define MOSTAT_TXPND 0x02 +#define MOSTAT_NEWDAT 0x08 +#define MOSTAT_MSGLST 0x10 +#define MOSTAT_RST_MNR 0x19 + + // MultiCAN Access Mediator Registers + + // ADCON Read is enabled +#define ADCON_R 0x00 + + // ADCON Write is enabled +#define ADCON_W 0x01 + + // Data Transmission Busy +#define CAN_ADCON_BSY 0x02 + + // Auto increment the current address(+1) +#define ADR_INC 0x04 + + // Auto increment the current address(+8) +#define ADR_INC8 0x0C + + // Auto decrement the current address(-1) +#define ADR_DEC 0x08 + + // CAN Data 0 Valid +#define D0_VALID 0x10 + + // CAN Data 1 Valid +#define D1_VALID 0x20 + + // CAN Data 2 Valid +#define D2_VALID 0x40 + + // CAN Data 3 Valid +#define D3_VALID 0x80 + + // CAN Data 0-3 Valid +#define ALL_DATA_VALID 0xF0 + + + /// ------------------------------------------------------------------------- + /// @Definition of a union for the CAN data structure + /// ------------------------------------------------------------------------- + + // The following data type used for converting 32-bit data to Four 8-bit data types + // and vica-versa. This is used for accessing MultiCAN Kernel to Access Mediator + // Registers. The data type has the following fields: + // + // 31 24 23 16 15 8 7 0 + // |------------------------------------------------| + // | DB0 | DB1 | DB2 | DB3 | + // |------------------------------------------------| + // | | + // | <------------------ ulVal -------------------> | + // + +typedef union ulValue { + ulong ulVal; // 32-bit Data Type + ubyte ubDB[4]; // Four 8-bit Data Type +} un_32bit; + + + // The following data type used for converting 16-bit data to Two 8-bit data types + // and vica-versa. The data type has the following fields: + // + // 15 8 7 0 + // |----------------------| + // | DB0 | DB1 | + // |----------------------| + // | | + // | <----- uwVal ------> | + // + +typedef union uwValue { + uword uwVal; // 16-bit Data Type + ubyte ubDB[2]; // Two 8-bit Data Type +} un_16bit; + + /// ------------------------------------------------------------------------- + /// @Definition of a structure for the CAN data + /// ------------------------------------------------------------------------- + + // The following data type serves as a software message object. Each access to + // a hardware message object has to be made by forward a pointer to a software + // message object (MCAN_SWObj). The data type has the following fields: + // + // ubMOdlc: + // this byte has the same structure as the message configuration register of a + // MOFCRn message object. It contains the ' Data Lenght Code (DLC)' + // + // 7 6 5 4 3 2 1 0 + // |------------------------------------------------| + // | 0 | DLC | + // |------------------------------------------------| + // + // ubMOcfg: + // this byte contains the 'Extended Identifier (IDE)', the 'Message Direction (DIR)', + // the 'Node Select (NODE)' And the 'Remote Monitoring Mode (RMM)' + // + // + // 7 6 5 4 3 2 1 0 + // |------------------------------------------------| + // | | DIR | XTD | NODE | RMM | + // |------------------------------------------------| + // + // ulID: + // this field is four bytes long and contains either the 11-bit identifier + // or the 29-bit identifier + // + // ulMask: + // this field is four bytes long and contains either the 11-bit mask + // or the 29-bit mask + // + // ulDATAL: + // contains the lowest 4 bytes of message object + // + // ulDATAH: + // contains the upper 4 bytes of message object + // + // uwCounter: + // this field is two bytes long and contains the counter value + // + +typedef struct +{ + ubyte ubMOdlc; // message object function control register[31-24] + ubyte ubMOcfg; // message object configuration + un_32bit ulID; // standard (11-bit)/extended (29-bit) identifier + un_32bit ulMask; // standard (11-bit)/extended (29-bit) mask + un_32bit ulDATAL; // 32-bit data Lower bytes + un_32bit ulDATAH; // 32-bit data Higher bytes + un_16bit uwCounter; // frame counter(MOIPRn[31-16] +}stCAN_SWObj; + + +// USER CODE BEGIN (CAN_Header,5) + +// USER CODE END + + +//**************************************************************************** +// @Imported Global Variables +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,6) + +// USER CODE END + + +//**************************************************************************** +// @Global Variables +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,7) + +// USER CODE END + + +//**************************************************************************** +// @Prototypes Of Global Functions +//**************************************************************************** + +void CAN_vInit(void); +void CAN_vGetMsgObj(ubyte ubObjNr, stCAN_SWObj *pstObj); +ubyte CAN_ubRequestMsgObj(ubyte ubObjNr); +ubyte CAN_ubNewData(ubyte ubObjNr); +void CAN_vTransmit(ubyte ubObjNr); +void CAN_vLoadData(ubyte ubObjNr, ulong *ulpubData); +void CAN_vReleaseObj(ubyte ubObjNr); +void CAN_vWriteAMData(ulong ulValue); +void CAN_vSetListCommand(ulong ulVal); + + +// USER CODE BEGIN (CAN_Header,8) + +// USER CODE END + + +//**************************************************************************** +// @Macro CAN_vReadEN() +// +//---------------------------------------------------------------------------- +// @Description This macro enables Read mode (CAN Address/Data Control +// Register). +// +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters None +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_vReadEN() CAN_ADCON = 0x00; while(CAN_ADCON & CAN_ADCON_BSY) + +//**************************************************************************** +// @Macro CAN_vWriteEN(ubyte ubDCtrl) +// +//---------------------------------------------------------------------------- +// @Description This macro enables Write mode (CAN Address/Data Control +// Register). +// +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubDCtrl: +// Data Control Flags +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_vWriteEN(ubDCtrl) CAN_ADCON = ((ubDCtrl) | ADCON_W); while(CAN_ADCON & CAN_ADCON_BSY) + +//**************************************************************************** +// @Macro CAN_vWriteCANAddress(uword uwAdr) +// +//---------------------------------------------------------------------------- +// @Description This macro writes 16-bit CAN address to CAN Address +// Register Low and High respectively. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters uwAdr: +// 16-bit Address +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_vWriteCANAddress(uwAdr) CAN_ADLH = uwAdr + +//**************************************************************************** +// @Macro CAN_vWriteCANData(ulong ulValue) +// +//---------------------------------------------------------------------------- +// @Description This macro writes 32-bit Data to CAN Data Register's +// 0-3respectively. +// Note: +// Write Process : +// ->Write the address of the MultiCAN kernel register to the +// CAN_ADL and CAN_ADH registers. +// use macro : CAN_vWriteCANAddress. +// ->Write the data to the +// CAN_DATA0/CAN_DATA1/CAN_DATA2/CAN_DATA3 registers. +// ->Write the register CAN_ADCON, including setting the valid +// bit of the data registers and setting register bit RWEN to +// 1. +// ->The valid data will be written to the MultiCAN kernel +// only once. Register bit BSY will become 1. +// ->When Register bit BSY becomes 0, the transmission is +// finished. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ulValue: +// 32-bit Data +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_vWriteCANData(ulValue) CAN_DATA01 = (ulValue & 0xFFFF); \ + CAN_DATA23 = (ulValue >> 16) & 0xFFFF; \ + CAN_vWriteEN(ALL_DATA_VALID) + +//**************************************************************************** +// @Macro CAN_pushAMRegs/_popAMRegs() +// +//---------------------------------------------------------------------------- +// @Description The macro CAN_pushAMRegs() PUSH the CAN Access Mediator +// Registers. +// The macro CAN_popAMRegs() POP the CAN Access Mediator +// Registers. +// Note: +// This macro is used in CAN ISR/Function's to protect Access +// Mediator Register +// MultiCAN Access Mediator Registers: +// ADL, ADH, DATA0, DATA1, DATA2, DATA3. +// +// The _push_/_pop_ routine inserts a PUSH/POP instruction +// into the program saving the contents of the Special +// Function Register(sfr) on the Stack. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters None +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_pushAMRegs() while(CAN_ADCON & CAN_ADCON_BSY); \ + _push_(CAN_ADL); _push_(CAN_ADH); \ + _push_(CAN_DATA0); _push_(CAN_DATA1); \ + _push_(CAN_DATA2); _push_(CAN_DATA3) + +#define CAN_popAMRegs() _pop_(CAN_DATA3); _pop_(CAN_DATA2); \ + _pop_(CAN_DATA1); _pop_(CAN_DATA0); \ + _pop_(CAN_ADH); _pop_(CAN_ADL) + +//**************************************************************************** +// @Interrupt Vectors +//**************************************************************************** + +// Shared interrupt vector definitions are defined in SHARED_INT.H + + +// USER CODE BEGIN (CAN_Header,9) + +// USER CODE END + + +#endif // ifndef _CAN_H_ diff --git a/CAN协议.xls b/CAN协议.xls new file mode 100644 index 0000000..53a81eb Binary files /dev/null and b/CAN协议.xls differ diff --git a/CL2.0.asm b/CL2.0.asm new file mode 100644 index 0000000..d5faaf0 --- /dev/null +++ b/CL2.0.asm @@ -0,0 +1,4129 @@ +;**************************************************************************** +; Filename CL2.0.asm +; Project CL2.0.dav +;---------------------------------------------------------------------------- +; Description This file contains the assembler formatted information +; about the actual project values. It will be used by your +; programming environment. +; +; PLEASE DO NOT MODIFY THIS FILE ! +; +;---------------------------------------------------------------------------- +; Date 2025/1/18 20:45:36 +; +;**************************************************************************** + + +; RMAP=x -CPU Accumulator Register +ACC_ACC0 SET 0 +ACC_ACC1 SET 0 +ACC_ACC2 SET 0 +ACC_ACC3 SET 0 +ACC_ACC4 SET 0 +ACC_ACC5 SET 0 +ACC_ACC6 SET 0 +ACC_ACC7 SET 0 + +; RMAP=0 PAGE=1-ADC Channel 0 Control Register +ADC_CHCTR0_LCC SET 0 +ADC_CHCTR0_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 1 Control Register +ADC_CHCTR1_LCC SET 0 +ADC_CHCTR1_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 2 Control Register +ADC_CHCTR2_LCC SET 0 +ADC_CHCTR2_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 3 Control Register +ADC_CHCTR3_LCC SET 0 +ADC_CHCTR3_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 4 Control Register +ADC_CHCTR4_LCC SET 0 +ADC_CHCTR4_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 5 Control Register +ADC_CHCTR5_LCC SET 0 +ADC_CHCTR5_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 6 Control Register +ADC_CHCTR6_LCC SET 0 +ADC_CHCTR6_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 7 Control Register +ADC_CHCTR7_LCC SET 0 +ADC_CHCTR7_RESRSEL SET 0 + +; RMAP=0 PAGE=5-ADC Channel Interrupt Clear Register +ADC_CHINCR_CHINC0 SET 0 +ADC_CHINCR_CHINC1 SET 0 +ADC_CHINCR_CHINC2 SET 0 +ADC_CHINCR_CHINC3 SET 0 +ADC_CHINCR_CHINC4 SET 0 +ADC_CHINCR_CHINC5 SET 0 +ADC_CHINCR_CHINC6 SET 0 +ADC_CHINCR_CHINC7 SET 0 + +; RMAP=0 PAGE=5-ADC Channel Interrupt Flag Register +ADC_CHINFR_CHINF0 SET 0 +ADC_CHINFR_CHINF1 SET 0 +ADC_CHINFR_CHINF2 SET 0 +ADC_CHINFR_CHINF3 SET 0 +ADC_CHINFR_CHINF4 SET 0 +ADC_CHINFR_CHINF5 SET 0 +ADC_CHINFR_CHINF6 SET 0 +ADC_CHINFR_CHINF7 SET 0 + +; RMAP=0 PAGE=5-ADC Channel Interrupt Node Pointer Register +ADC_CHINPR_CHINP0 SET 0 +ADC_CHINPR_CHINP1 SET 0 +ADC_CHINPR_CHINP2 SET 0 +ADC_CHINPR_CHINP3 SET 0 +ADC_CHINPR_CHINP4 SET 0 +ADC_CHINPR_CHINP5 SET 0 +ADC_CHINPR_CHINP6 SET 0 +ADC_CHINPR_CHINP7 SET 0 + +; RMAP=0 PAGE=5-ADC Channel Interrupt Set Register +ADC_CHINSR_CHINS0 SET 0 +ADC_CHINSR_CHINS1 SET 0 +ADC_CHINSR_CHINS2 SET 0 +ADC_CHINSR_CHINS3 SET 0 +ADC_CHINSR_CHINS4 SET 0 +ADC_CHINSR_CHINS5 SET 0 +ADC_CHINSR_CHINS6 SET 0 +ADC_CHINSR_CHINS7 SET 0 + +; RMAP=0 PAGE=6-ADC Source 1 Conversion Request Control Register +ADC_CRCR1_CH4 SET 0 +ADC_CRCR1_CH5 SET 0 +ADC_CRCR1_CH6 SET 0 +ADC_CRCR1_CH7 SET 0 + +; RMAP=0 PAGE=6-ADC Source 1 Conversion Request Mode Register +ADC_CRMR1_0 SET 0 +ADC_CRMR1_CLRPND SET 0 +ADC_CRMR1_ENGT SET 0 +ADC_CRMR1_ENSI SET 0 +ADC_CRMR1_ENTR SET 0 +ADC_CRMR1_LDEV SET 0 +ADC_CRMR1_RSV SET 0 +ADC_CRMR1_SCAN SET 0 + +; RMAP=0 PAGE=6-ADC Source 1 Conversion Request Pending Register +ADC_CRPR1_CHP4 SET 0 +ADC_CRPR1_CHP5 SET 0 +ADC_CRPR1_CHP6 SET 0 +ADC_CRPR1_CHP7 SET 0 + +; RMAP=0 PAGE=0-ADC External Trigger Control Register +ADC_ETRCR_ETRSEL0 SET 0 +ADC_ETRCR_ETRSEL1 SET 0 +ADC_ETRCR_SYNEN0 SET 0 +ADC_ETRCR_SYNEN1 SET 0 + +; RMAP=0 PAGE=5-ADC Event Interrupt Clear Register +ADC_EVINCR_EVINC0 SET 0 +ADC_EVINCR_EVINC1 SET 0 +ADC_EVINCR_EVINC4 SET 0 +ADC_EVINCR_EVINC5 SET 0 +ADC_EVINCR_EVINC6 SET 0 +ADC_EVINCR_EVINC7 SET 0 + +; RMAP=0 PAGE=5-ADC Event Interrupt Flag Register +ADC_EVINFR_EVINF0 SET 0 +ADC_EVINFR_EVINF1 SET 0 +ADC_EVINFR_EVINF4 SET 0 +ADC_EVINFR_EVINF5 SET 0 +ADC_EVINFR_EVINF6 SET 0 +ADC_EVINFR_EVINF7 SET 0 + +; RMAP=0 PAGE=5-ADC Event Interrupt Node Pointer Register +ADC_EVINPR_EVINP0 SET 0 +ADC_EVINPR_EVINP1 SET 0 +ADC_EVINPR_EVINP4 SET 0 +ADC_EVINPR_EVINP5 SET 0 +ADC_EVINPR_EVINP6 SET 0 +ADC_EVINPR_EVINP7 SET 0 + +; RMAP=0 PAGE=5-ADC Event Interrupt Set Flag Register +ADC_EVINSR_EVINS0 SET 0 +ADC_EVINSR_EVINS1 SET 0 +ADC_EVINSR_EVINS4 SET 0 +ADC_EVINSR_EVINS5 SET 0 +ADC_EVINSR_EVINS6 SET 0 +ADC_EVINSR_EVINS7 SET 0 + +; RMAP=0 PAGE=0-ADC Global Control Register +ADC_GLOBCTR_ANON SET 0 +ADC_GLOBCTR_CTC SET 3 +ADC_GLOBCTR_DW SET 0 + +; RMAP=0 PAGE=0-ADC Global Status Register +ADC_GLOBSTR_BUSY SET 0 +ADC_GLOBSTR_CHNR SET 0 +ADC_GLOBSTR_SAMPLE SET 0 + +; RMAP=0 PAGE=0-ADC Input Class 0 Register +ADC_INPCR0_STC SET 0 + +; RMAP=0 PAGE=0-ADC Limit Check Boundary Register +ADC_LCBR_BOUND0 SET 7 +ADC_LCBR_BOUND1 SET 11 + +; RMAP=0 -ADC Page Register +ADC_PAGE_OP SET 0 +ADC_PAGE_PAGE SET 0 +ADC_PAGE_STNR SET 0 + +; RMAP=0 PAGE=0-ADC Priority and Arbitration Register +ADC_PRAR_ARBM SET 0 +ADC_PRAR_ASEN0 SET 0 +ADC_PRAR_ASEN1 SET 0 +ADC_PRAR_CSM0 SET 0 +ADC_PRAR_CSM1 SET 0 +ADC_PRAR_PRIO0 SET 0 +ADC_PRAR_PRIO1 SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue 0 Register +ADC_Q0R0_ENSI SET 0 +ADC_Q0R0_EXTR SET 0 +ADC_Q0R0_REQCHNR SET 0 +ADC_Q0R0_RF SET 0 +ADC_Q0R0_V SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue Backup Register +ADC_QBUR0_ENSI SET 0 +ADC_QBUR0_EXTR SET 0 +ADC_QBUR0_REQCHNR SET 0 +ADC_QBUR0_RF SET 0 +ADC_QBUR0_V SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue Input Register +ADC_QINR0_ENSI SET 0 +ADC_QINR0_EXTR SET 0 +ADC_QINR0_REQCHNR SET 0 +ADC_QINR0_RF SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue Mode Register +ADC_QMR0_0 SET 0 +ADC_QMR0_CEV SET 0 +ADC_QMR0_CLRV SET 0 +ADC_QMR0_ENGT SET 0 +ADC_QMR0_ENTR SET 0 +ADC_QMR0_FLUSH SET 0 +ADC_QMR0_TREV SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue Status Register +ADC_QSR0_EMPTY SET 0 +ADC_QSR0_EV SET 0 +ADC_QSR0_FILL SET 0 +ADC_QSR0_RSV SET 0 + +; RMAP=0 PAGE=4-ADC Result 0 Control Register +ADC_RCR0_DRCTR SET 0 +ADC_RCR0_IEN SET 0 +ADC_RCR0_VFCTR SET 0 +ADC_RCR0_WFR SET 0 + +; RMAP=0 PAGE=4-ADC Result 1 Control Register +ADC_RCR1_DRCTR SET 0 +ADC_RCR1_IEN SET 0 +ADC_RCR1_VFCTR SET 0 +ADC_RCR1_WFR SET 0 + +; RMAP=0 PAGE=4-ADC Result 2 Control Register +ADC_RCR2_DRCTR SET 0 +ADC_RCR2_IEN SET 0 +ADC_RCR2_VFCTR SET 0 +ADC_RCR2_WFR SET 0 + +; RMAP=0 PAGE=4-ADC Result 3 Control Register +ADC_RCR3_DRCTR SET 0 +ADC_RCR3_IEN SET 0 +ADC_RCR3_VFCTR SET 0 +ADC_RCR3_WFR SET 0 + +; RMAP=0 PAGE=2-ADC Result 0 Register High +ADC_RESR0H_RESULT SET 0 + +; RMAP=0 PAGE=2-ADC Result 0 Register Low +ADC_RESR0L_CHNR SET 0 +ADC_RESR0L_DRC SET 0 +ADC_RESR0L_RESULT SET 0 +ADC_RESR0L_VF SET 0 + +; RMAP=0 PAGE=2-ADC Result 1 Register High +ADC_RESR1H_RESULT SET 0 + +; RMAP=0 PAGE=2-ADC Result 1 Register Low +ADC_RESR1L_CHNR SET 0 +ADC_RESR1L_DRC SET 0 +ADC_RESR1L_RESULT SET 0 +ADC_RESR1L_VF SET 0 + +; RMAP=0 PAGE=2-ADC Result 2 Register High +ADC_RESR2H_RESULT SET 0 + +; RMAP=0 PAGE=2-ADC Result 2 Register Low +ADC_RESR2L_CHNR SET 0 +ADC_RESR2L_DRC SET 0 +ADC_RESR2L_RESULT SET 0 +ADC_RESR2L_VF SET 0 + +; RMAP=0 PAGE=2-ADC Result 3 Register High +ADC_RESR3H_RESULT SET 0 + +; RMAP=0 PAGE=2-ADC Result 3 Register Low +ADC_RESR3L_CHNR SET 0 +ADC_RESR3L_DRC SET 0 +ADC_RESR3L_RESULT SET 0 +ADC_RESR3L_VF SET 0 + +; RMAP=0 PAGE=3-ADC Result 0 View A Register High +ADC_RESRA0H_RESULT SET 0 + +; RMAP=0 PAGE=3-ADC Result 0 View A Register Low +ADC_RESRA0L_CHNR SET 0 +ADC_RESRA0L_DRC SET 0 +ADC_RESRA0L_RESULT SET 0 +ADC_RESRA0L_VF SET 0 + +; RMAP=0 PAGE=3-ADC Result 1 View A Register High +ADC_RESRA1H_RESULT SET 0 + +; RMAP=0 PAGE=3-ADC Result 1 View A Register Low +ADC_RESRA1L_CHNR SET 0 +ADC_RESRA1L_DRC SET 0 +ADC_RESRA1L_RESULT SET 0 +ADC_RESRA1L_VF SET 0 + +; RMAP=0 PAGE=3-ADC Result 2 View A Register High +ADC_RESRA2H_RESULT SET 0 + +; RMAP=0 PAGE=3-ADC Result 2 View A Register Low +ADC_RESRA2L_CHNR SET 0 +ADC_RESRA2L_DRC SET 0 +ADC_RESRA2L_RESULT SET 0 +ADC_RESRA2L_VF SET 0 + +; RMAP=0 PAGE=3-ADC Result 3 View A Register High +ADC_RESRA3H_RESULT SET 0 + +; RMAP=0 PAGE=3-ADC Result 3 View A Register Low +ADC_RESRA3L_CHNR SET 0 +ADC_RESRA3L_DRC SET 0 +ADC_RESRA3L_RESULT SET 0 +ADC_RESRA3L_VF SET 0 + +; RMAP=0 PAGE=4-ADC Valid Flag Clear Register +ADC_VFCR_VFC0 SET 0 +ADC_VFCR_VFC1 SET 0 +ADC_VFCR_VFC2 SET 0 +ADC_VFCR_VFC3 SET 0 + +; RMAP=0 PAGE=0-SCU Baud Rate Control Register +BCON_BGSEL SET 0 +BCON_BRDIS SET 0 +BCON_BRPRE SET 0 +BCON_R SET 0 + +; RMAP=0 PAGE=0-SCU Baud Rate Timer/Reload Register +BG_BR_VALUE SET 1 + +; RMAP=x -CPU B Register +B_B0 SET 0 +B_B1 SET 0 +B_B2 SET 0 +B_B3 SET 0 +B_B4 SET 0 +B_B5 SET 0 +B_B6 SET 0 +B_B7 SET 0 + +; RMAP=0 -MultiCAN Serial Channel Control Register +CAN_ADCON_AUAD SET 0 +CAN_ADCON_BSY SET 0 +CAN_ADCON_RWEN SET 0 +CAN_ADCON_V0 SET 0 +CAN_ADCON_V1 SET 0 +CAN_ADCON_V2 SET 0 +CAN_ADCON_V3 SET 0 + +; RMAP=0 -MultiCAN Baud Rate Control Register +CAN_ADH_CA10 SET 0 +CAN_ADH_CA11 SET 0 +CAN_ADH_CA12 SET 0 +CAN_ADH_CA13 SET 0 + +; RMAP=0 -MultiCAN Serial Data Buffer Register +CAN_ADL_CA2 SET 0 +CAN_ADL_CA3 SET 0 +CAN_ADL_CA4 SET 0 +CAN_ADL_CA5 SET 0 +CAN_ADL_CA6 SET 0 +CAN_ADL_CA7 SET 0 +CAN_ADL_CA8 SET 0 +CAN_ADL_CA9 SET 0 + +; RMAP=0 -MultiCAN CAN Data Register 0 +CAN_DATA0_CD[7:0] SET 0 + +; RMAP=0 -MultiCAN CAN Data Register 1 +CAN_DATA1_CD[15:8] SET 0 + +; RMAP=0 -MultiCAN CAN Data Register 2 +CAN_DATA2_CD SET 0 + +; RMAP=0 -MultiCAN CAN Data Register 3 +CAN_DATA3_CD SET 0 + +; List Register 0 +CAN_LIST0_0 SET 0 +CAN_LIST0_BEGIN SET 0 +CAN_LIST0_EMPTY SET 0 +CAN_LIST0_END SET 0 +CAN_LIST0_SIZE SET 0 + +; List Register 1 +CAN_LIST1_0 SET 0 +CAN_LIST1_BEGIN SET 0 +CAN_LIST1_EMPTY SET 0 +CAN_LIST1_END SET 0 +CAN_LIST1_SIZE SET 0 + +; List Register 2 +CAN_LIST2_0 SET 0 +CAN_LIST2_BEGIN SET 0 +CAN_LIST2_EMPTY SET 0 +CAN_LIST2_END SET 0 +CAN_LIST2_SIZE SET 0 + +; List Register 3 +CAN_LIST3_0 SET 0 +CAN_LIST3_BEGIN SET 0 +CAN_LIST3_EMPTY SET 0 +CAN_LIST3_END SET 0 +CAN_LIST3_SIZE SET 0 + +; List Register 4 +CAN_LIST4_0 SET 0 +CAN_LIST4_BEGIN SET 0 +CAN_LIST4_EMPTY SET 0 +CAN_LIST4_END SET 0 +CAN_LIST4_SIZE SET 0 + +; List Register 5 +CAN_LIST5_0 SET 0 +CAN_LIST5_BEGIN SET 0 +CAN_LIST5_EMPTY SET 0 +CAN_LIST5_END SET 0 +CAN_LIST5_SIZE SET 0 + +; List Register 6 +CAN_LIST6_0 SET 0 +CAN_LIST6_BEGIN SET 0 +CAN_LIST6_EMPTY SET 0 +CAN_LIST6_END SET 0 +CAN_LIST6_SIZE SET 0 + +; List Register 7 +CAN_LIST7_0 SET 0 +CAN_LIST7_BEGIN SET 0 +CAN_LIST7_EMPTY SET 0 +CAN_LIST7_END SET 0 +CAN_LIST7_SIZE SET 0 + +; MultiCAN Module Control Register +CAN_MCR_0 SET 0 +CAN_MCR_0 SET 0 +CAN_MCR_MPSEL SET 0 + +; Module Interrupt Trigger Register +CAN_MITR_IT[31:8] SET 0 +CAN_MITR_IT[7:0] SET 0 + +; CAN Message Object 0 Acceptance Mask Register +CAN_MOAMR0_0 SET 0 +CAN_MOAMR0_AM SET 536870911 +CAN_MOAMR0_MIDE SET 1 + +; CAN Message Object 10 Acceptance Mask Register +CAN_MOAMR10_0 SET 0 +CAN_MOAMR10_AM SET 536870911 +CAN_MOAMR10_MIDE SET 1 + +; CAN Message Object 11 Acceptance Mask Register +CAN_MOAMR11_0 SET 0 +CAN_MOAMR11_AM SET 536870911 +CAN_MOAMR11_MIDE SET 1 + +; CAN Message Object 12 Acceptance Mask Register +CAN_MOAMR12_0 SET 0 +CAN_MOAMR12_AM SET 536870911 +CAN_MOAMR12_MIDE SET 1 + +; CAN Message Object 13 Acceptance Mask Register +CAN_MOAMR13_0 SET 0 +CAN_MOAMR13_AM SET 536870911 +CAN_MOAMR13_MIDE SET 1 + +; CAN Message Object 14 Acceptance Mask Register +CAN_MOAMR14_0 SET 0 +CAN_MOAMR14_AM SET 536870911 +CAN_MOAMR14_MIDE SET 1 + +; CAN Message Object 15 Acceptance Mask Register +CAN_MOAMR15_0 SET 0 +CAN_MOAMR15_AM SET 536870911 +CAN_MOAMR15_MIDE SET 1 + +; CAN Message Object 16 Acceptance Mask Register +CAN_MOAMR16_0 SET 0 +CAN_MOAMR16_AM SET 536870911 +CAN_MOAMR16_MIDE SET 1 + +; CAN Message Object 17 Acceptance Mask Register +CAN_MOAMR17_0 SET 0 +CAN_MOAMR17_AM SET 536870911 +CAN_MOAMR17_MIDE SET 1 + +; CAN Message Object 18 Acceptance Mask Register +CAN_MOAMR18_0 SET 0 +CAN_MOAMR18_AM SET 536870911 +CAN_MOAMR18_MIDE SET 1 + +; CAN Message Object 19 Acceptance Mask Register +CAN_MOAMR19_0 SET 0 +CAN_MOAMR19_AM SET 536870911 +CAN_MOAMR19_MIDE SET 1 + +; CAN Message Object 1 Acceptance Mask Register +CAN_MOAMR1_0 SET 0 +CAN_MOAMR1_AM SET 536870911 +CAN_MOAMR1_MIDE SET 1 + +; CAN Message Object 20 Acceptance Mask Register +CAN_MOAMR20_0 SET 0 +CAN_MOAMR20_AM SET 536870911 +CAN_MOAMR20_MIDE SET 1 + +; CAN Message Object 21 Acceptance Mask Register +CAN_MOAMR21_0 SET 0 +CAN_MOAMR21_AM SET 536870911 +CAN_MOAMR21_MIDE SET 1 + +; CAN Message Object 22 Acceptance Mask Register +CAN_MOAMR22_0 SET 0 +CAN_MOAMR22_AM SET 536870911 +CAN_MOAMR22_MIDE SET 1 + +; CAN Message Object 23 Acceptance Mask Register +CAN_MOAMR23_0 SET 0 +CAN_MOAMR23_AM SET 536870911 +CAN_MOAMR23_MIDE SET 1 + +; CAN Message Object 24 Acceptance Mask Register +CAN_MOAMR24_0 SET 0 +CAN_MOAMR24_AM SET 536870911 +CAN_MOAMR24_MIDE SET 1 + +; CAN Message Object 25 Acceptance Mask Register +CAN_MOAMR25_0 SET 0 +CAN_MOAMR25_AM SET 536870911 +CAN_MOAMR25_MIDE SET 1 + +; CAN Message Object 26 Acceptance Mask Register +CAN_MOAMR26_0 SET 0 +CAN_MOAMR26_AM SET 536870911 +CAN_MOAMR26_MIDE SET 1 + +; CAN Message Object 27 Acceptance Mask Register +CAN_MOAMR27_0 SET 0 +CAN_MOAMR27_AM SET 536870911 +CAN_MOAMR27_MIDE SET 1 + +; CAN Message Object 28 Acceptance Mask Register +CAN_MOAMR28_0 SET 0 +CAN_MOAMR28_AM SET 536870911 +CAN_MOAMR28_MIDE SET 1 + +; CAN Message Object 29 Acceptance Mask Register +CAN_MOAMR29_0 SET 0 +CAN_MOAMR29_AM SET 536870911 +CAN_MOAMR29_MIDE SET 1 + +; CAN Message Object 2 Acceptance Mask Register +CAN_MOAMR2_0 SET 0 +CAN_MOAMR2_AM SET 536870911 +CAN_MOAMR2_MIDE SET 1 + +; CAN Message Object 30 Acceptance Mask Register +CAN_MOAMR30_0 SET 0 +CAN_MOAMR30_AM SET 536870911 +CAN_MOAMR30_MIDE SET 1 + +; CAN Message Object 31 Acceptance Mask Register +CAN_MOAMR31_0 SET 0 +CAN_MOAMR31_AM SET 536870911 +CAN_MOAMR31_MIDE SET 1 + +; CAN Message Object 3 Acceptance Mask Register +CAN_MOAMR3_0 SET 0 +CAN_MOAMR3_AM SET 536870911 +CAN_MOAMR3_MIDE SET 1 + +; CAN Message Object 4 Acceptance Mask Register +CAN_MOAMR4_0 SET 0 +CAN_MOAMR4_AM SET 536870911 +CAN_MOAMR4_MIDE SET 1 + +; CAN Message Object 5 Acceptance Mask Register +CAN_MOAMR5_0 SET 0 +CAN_MOAMR5_AM SET 536870911 +CAN_MOAMR5_MIDE SET 1 + +; CAN Message Object 6 Acceptance Mask Register +CAN_MOAMR6_0 SET 0 +CAN_MOAMR6_AM SET 536870911 +CAN_MOAMR6_MIDE SET 1 + +; CAN Message Object 7 Acceptance Mask Register +CAN_MOAMR7_0 SET 0 +CAN_MOAMR7_AM SET 536870911 +CAN_MOAMR7_MIDE SET 1 + +; CAN Message Object 8 Acceptance Mask Register +CAN_MOAMR8_0 SET 0 +CAN_MOAMR8_AM SET 536870911 +CAN_MOAMR8_MIDE SET 1 + +; CAN Message Object 9 Acceptance Mask Register +CAN_MOAMR9_0 SET 0 +CAN_MOAMR9_AM SET 536870911 +CAN_MOAMR9_MIDE SET 1 + +; CAN Message Object 0 Arbitration Register +CAN_MOAR0_ID SET 268435457 +CAN_MOAR0_IDE SET 1 +CAN_MOAR0_PRI SET 3 + +; CAN Message Object 10 Arbitration Register +CAN_MOAR10_ID SET 0 +CAN_MOAR10_IDE SET 0 +CAN_MOAR10_PRI SET 3 + +; CAN Message Object 11 Arbitration Register +CAN_MOAR11_ID SET 0 +CAN_MOAR11_IDE SET 0 +CAN_MOAR11_PRI SET 3 + +; CAN Message Object 12 Arbitration Register +CAN_MOAR12_ID SET 0 +CAN_MOAR12_IDE SET 0 +CAN_MOAR12_PRI SET 3 + +; CAN Message Object 13 Arbitration Register +CAN_MOAR13_ID SET 0 +CAN_MOAR13_IDE SET 0 +CAN_MOAR13_PRI SET 3 + +; CAN Message Object 14 Arbitration Register +CAN_MOAR14_ID SET 0 +CAN_MOAR14_IDE SET 0 +CAN_MOAR14_PRI SET 3 + +; CAN Message Object 15 Arbitration Register +CAN_MOAR15_ID SET 0 +CAN_MOAR15_IDE SET 0 +CAN_MOAR15_PRI SET 3 + +; CAN Message Object 16 Arbitration Register +CAN_MOAR16_ID SET 0 +CAN_MOAR16_IDE SET 0 +CAN_MOAR16_PRI SET 3 + +; CAN Message Object 17 Arbitration Register +CAN_MOAR17_ID SET 0 +CAN_MOAR17_IDE SET 0 +CAN_MOAR17_PRI SET 3 + +; CAN Message Object 18 Arbitration Register +CAN_MOAR18_ID SET 0 +CAN_MOAR18_IDE SET 0 +CAN_MOAR18_PRI SET 3 + +; CAN Message Object 19 Arbitration Register +CAN_MOAR19_ID SET 0 +CAN_MOAR19_IDE SET 0 +CAN_MOAR19_PRI SET 3 + +; CAN Message Object 1 Arbitration Register +CAN_MOAR1_ID SET 268435458 +CAN_MOAR1_IDE SET 1 +CAN_MOAR1_PRI SET 3 + +; CAN Message Object 20 Arbitration Register +CAN_MOAR20_ID SET 0 +CAN_MOAR20_IDE SET 0 +CAN_MOAR20_PRI SET 3 + +; CAN Message Object 21 Arbitration Register +CAN_MOAR21_ID SET 0 +CAN_MOAR21_IDE SET 0 +CAN_MOAR21_PRI SET 3 + +; CAN Message Object 22 Arbitration Register +CAN_MOAR22_ID SET 0 +CAN_MOAR22_IDE SET 0 +CAN_MOAR22_PRI SET 3 + +; CAN Message Object 23 Arbitration Register +CAN_MOAR23_ID SET 0 +CAN_MOAR23_IDE SET 0 +CAN_MOAR23_PRI SET 3 + +; CAN Message Object 24 Arbitration Register +CAN_MOAR24_ID SET 0 +CAN_MOAR24_IDE SET 0 +CAN_MOAR24_PRI SET 3 + +; CAN Message Object 25 Arbitration Register +CAN_MOAR25_ID SET 0 +CAN_MOAR25_IDE SET 0 +CAN_MOAR25_PRI SET 3 + +; CAN Message Object 26 Arbitration Register +CAN_MOAR26_ID SET 0 +CAN_MOAR26_IDE SET 0 +CAN_MOAR26_PRI SET 3 + +; CAN Message Object 27 Arbitration Register +CAN_MOAR27_ID SET 0 +CAN_MOAR27_IDE SET 0 +CAN_MOAR27_PRI SET 3 + +; CAN Message Object 28 Arbitration Register +CAN_MOAR28_ID SET 0 +CAN_MOAR28_IDE SET 0 +CAN_MOAR28_PRI SET 3 + +; CAN Message Object 29 Arbitration Register +CAN_MOAR29_ID SET 0 +CAN_MOAR29_IDE SET 0 +CAN_MOAR29_PRI SET 3 + +; CAN Message Object 2 Arbitration Register +CAN_MOAR2_ID SET 536870911 +CAN_MOAR2_IDE SET 1 +CAN_MOAR2_PRI SET 3 + +; CAN Message Object 30 Arbitration Register +CAN_MOAR30_ID SET 0 +CAN_MOAR30_IDE SET 0 +CAN_MOAR30_PRI SET 3 + +; CAN Message Object 31 Arbitration Register +CAN_MOAR31_ID SET 0 +CAN_MOAR31_IDE SET 0 +CAN_MOAR31_PRI SET 3 + +; CAN Message Object 3 Arbitration Register +CAN_MOAR3_ID SET 0 +CAN_MOAR3_IDE SET 0 +CAN_MOAR3_PRI SET 3 + +; CAN Message Object 4 Arbitration Register +CAN_MOAR4_ID SET 0 +CAN_MOAR4_IDE SET 0 +CAN_MOAR4_PRI SET 3 + +; CAN Message Object 5 Arbitration Register +CAN_MOAR5_ID SET 3 +CAN_MOAR5_IDE SET 1 +CAN_MOAR5_PRI SET 3 + +; CAN Message Object 6 Arbitration Register +CAN_MOAR6_ID SET 285212673 +CAN_MOAR6_IDE SET 1 +CAN_MOAR6_PRI SET 3 + +; CAN Message Object 7 Arbitration Register +CAN_MOAR7_ID SET 285212674 +CAN_MOAR7_IDE SET 1 +CAN_MOAR7_PRI SET 3 + +; CAN Message Object 8 Arbitration Register +CAN_MOAR8_ID SET 285212675 +CAN_MOAR8_IDE SET 1 +CAN_MOAR8_PRI SET 3 + +; CAN Message Object 9 Arbitration Register +CAN_MOAR9_ID SET 536870896 +CAN_MOAR9_IDE SET 1 +CAN_MOAR9_PRI SET 3 + +; CAN Message Object 0 Control Register +CAN_MOCTR0_CTRL SET 0 +CAN_MOCTR0_DIR SET 1 +CAN_MOCTR0_LIST SET 0 +CAN_MOCTR0_MSGLST SET 0 +CAN_MOCTR0_MSGVAL SET 0 +CAN_MOCTR0_NEWDAT SET 0 +CAN_MOCTR0_RTSEL SET 0 +CAN_MOCTR0_RXEN SET 0 +CAN_MOCTR0_RXPND SET 0 +CAN_MOCTR0_RXUPD SET 0 +CAN_MOCTR0_TXEN0 SET 0 +CAN_MOCTR0_TXEN1 SET 0 +CAN_MOCTR0_TXPND SET 0 +CAN_MOCTR0_TXRQ SET 0 + +; CAN Message Object 10 Control Register +CAN_MOCTR10_CTRL SET 0 +CAN_MOCTR10_DIR SET 0 +CAN_MOCTR10_LIST SET 0 +CAN_MOCTR10_MSGLST SET 0 +CAN_MOCTR10_MSGVAL SET 0 +CAN_MOCTR10_NEWDAT SET 0 +CAN_MOCTR10_RTSEL SET 0 +CAN_MOCTR10_RXEN SET 0 +CAN_MOCTR10_RXPND SET 0 +CAN_MOCTR10_RXUPD SET 0 +CAN_MOCTR10_TXEN0 SET 0 +CAN_MOCTR10_TXEN1 SET 0 +CAN_MOCTR10_TXPND SET 0 +CAN_MOCTR10_TXRQ SET 0 + +; CAN Message Object 11 Control Register +CAN_MOCTR11_CTRL SET 0 +CAN_MOCTR11_DIR SET 0 +CAN_MOCTR11_LIST SET 0 +CAN_MOCTR11_MSGLST SET 0 +CAN_MOCTR11_MSGVAL SET 0 +CAN_MOCTR11_NEWDAT SET 0 +CAN_MOCTR11_RTSEL SET 0 +CAN_MOCTR11_RXEN SET 0 +CAN_MOCTR11_RXPND SET 0 +CAN_MOCTR11_RXUPD SET 0 +CAN_MOCTR11_TXEN0 SET 0 +CAN_MOCTR11_TXEN1 SET 0 +CAN_MOCTR11_TXPND SET 0 +CAN_MOCTR11_TXRQ SET 0 + +; CAN Message Object 12 Control Register +CAN_MOCTR12_CTRL SET 0 +CAN_MOCTR12_DIR SET 0 +CAN_MOCTR12_LIST SET 0 +CAN_MOCTR12_MSGLST SET 0 +CAN_MOCTR12_MSGVAL SET 0 +CAN_MOCTR12_NEWDAT SET 0 +CAN_MOCTR12_RTSEL SET 0 +CAN_MOCTR12_RXEN SET 0 +CAN_MOCTR12_RXPND SET 0 +CAN_MOCTR12_RXUPD SET 0 +CAN_MOCTR12_TXEN0 SET 0 +CAN_MOCTR12_TXEN1 SET 0 +CAN_MOCTR12_TXPND SET 0 +CAN_MOCTR12_TXRQ SET 0 + +; CAN Message Object 13 Control Register +CAN_MOCTR13_CTRL SET 0 +CAN_MOCTR13_DIR SET 0 +CAN_MOCTR13_LIST SET 0 +CAN_MOCTR13_MSGLST SET 0 +CAN_MOCTR13_MSGVAL SET 0 +CAN_MOCTR13_NEWDAT SET 0 +CAN_MOCTR13_RTSEL SET 0 +CAN_MOCTR13_RXEN SET 0 +CAN_MOCTR13_RXPND SET 0 +CAN_MOCTR13_RXUPD SET 0 +CAN_MOCTR13_TXEN0 SET 0 +CAN_MOCTR13_TXEN1 SET 0 +CAN_MOCTR13_TXPND SET 0 +CAN_MOCTR13_TXRQ SET 0 + +; CAN Message Object 14 Control Register +CAN_MOCTR14_CTRL SET 0 +CAN_MOCTR14_DIR SET 0 +CAN_MOCTR14_LIST SET 0 +CAN_MOCTR14_MSGLST SET 0 +CAN_MOCTR14_MSGVAL SET 0 +CAN_MOCTR14_NEWDAT SET 0 +CAN_MOCTR14_RTSEL SET 0 +CAN_MOCTR14_RXEN SET 0 +CAN_MOCTR14_RXPND SET 0 +CAN_MOCTR14_RXUPD SET 0 +CAN_MOCTR14_TXEN0 SET 0 +CAN_MOCTR14_TXEN1 SET 0 +CAN_MOCTR14_TXPND SET 0 +CAN_MOCTR14_TXRQ SET 0 + +; CAN Message Object 15 Control Register +CAN_MOCTR15_CTRL SET 0 +CAN_MOCTR15_DIR SET 0 +CAN_MOCTR15_LIST SET 0 +CAN_MOCTR15_MSGLST SET 0 +CAN_MOCTR15_MSGVAL SET 0 +CAN_MOCTR15_NEWDAT SET 0 +CAN_MOCTR15_RTSEL SET 0 +CAN_MOCTR15_RXEN SET 0 +CAN_MOCTR15_RXPND SET 0 +CAN_MOCTR15_RXUPD SET 0 +CAN_MOCTR15_TXEN0 SET 0 +CAN_MOCTR15_TXEN1 SET 0 +CAN_MOCTR15_TXPND SET 0 +CAN_MOCTR15_TXRQ SET 0 + +; CAN Message Object 16 Control Register +CAN_MOCTR16_CTRL SET 0 +CAN_MOCTR16_DIR SET 0 +CAN_MOCTR16_LIST SET 0 +CAN_MOCTR16_MSGLST SET 0 +CAN_MOCTR16_MSGVAL SET 0 +CAN_MOCTR16_NEWDAT SET 0 +CAN_MOCTR16_RTSEL SET 0 +CAN_MOCTR16_RXEN SET 0 +CAN_MOCTR16_RXPND SET 0 +CAN_MOCTR16_RXUPD SET 0 +CAN_MOCTR16_TXEN0 SET 0 +CAN_MOCTR16_TXEN1 SET 0 +CAN_MOCTR16_TXPND SET 0 +CAN_MOCTR16_TXRQ SET 0 + +; CAN Message Object 17 Control Register +CAN_MOCTR17_CTRL SET 0 +CAN_MOCTR17_DIR SET 0 +CAN_MOCTR17_LIST SET 0 +CAN_MOCTR17_MSGLST SET 0 +CAN_MOCTR17_MSGVAL SET 0 +CAN_MOCTR17_NEWDAT SET 0 +CAN_MOCTR17_RTSEL SET 0 +CAN_MOCTR17_RXEN SET 0 +CAN_MOCTR17_RXPND SET 0 +CAN_MOCTR17_RXUPD SET 0 +CAN_MOCTR17_TXEN0 SET 0 +CAN_MOCTR17_TXEN1 SET 0 +CAN_MOCTR17_TXPND SET 0 +CAN_MOCTR17_TXRQ SET 0 + +; CAN Message Object 18 Control Register +CAN_MOCTR18_CTRL SET 0 +CAN_MOCTR18_DIR SET 0 +CAN_MOCTR18_LIST SET 0 +CAN_MOCTR18_MSGLST SET 0 +CAN_MOCTR18_MSGVAL SET 0 +CAN_MOCTR18_NEWDAT SET 0 +CAN_MOCTR18_RTSEL SET 0 +CAN_MOCTR18_RXEN SET 0 +CAN_MOCTR18_RXPND SET 0 +CAN_MOCTR18_RXUPD SET 0 +CAN_MOCTR18_TXEN0 SET 0 +CAN_MOCTR18_TXEN1 SET 0 +CAN_MOCTR18_TXPND SET 0 +CAN_MOCTR18_TXRQ SET 0 + +; CAN Message Object 19 Control Register +CAN_MOCTR19_CTRL SET 0 +CAN_MOCTR19_DIR SET 0 +CAN_MOCTR19_LIST SET 0 +CAN_MOCTR19_MSGLST SET 0 +CAN_MOCTR19_MSGVAL SET 0 +CAN_MOCTR19_NEWDAT SET 0 +CAN_MOCTR19_RTSEL SET 0 +CAN_MOCTR19_RXEN SET 0 +CAN_MOCTR19_RXPND SET 0 +CAN_MOCTR19_RXUPD SET 0 +CAN_MOCTR19_TXEN0 SET 0 +CAN_MOCTR19_TXEN1 SET 0 +CAN_MOCTR19_TXPND SET 0 +CAN_MOCTR19_TXRQ SET 0 + +; CAN Message Object 1 Control Register +CAN_MOCTR1_CTRL SET 0 +CAN_MOCTR1_DIR SET 0 +CAN_MOCTR1_LIST SET 0 +CAN_MOCTR1_MSGLST SET 0 +CAN_MOCTR1_MSGVAL SET 0 +CAN_MOCTR1_NEWDAT SET 0 +CAN_MOCTR1_RTSEL SET 0 +CAN_MOCTR1_RXEN SET 0 +CAN_MOCTR1_RXPND SET 0 +CAN_MOCTR1_RXUPD SET 0 +CAN_MOCTR1_TXEN0 SET 0 +CAN_MOCTR1_TXEN1 SET 0 +CAN_MOCTR1_TXPND SET 0 +CAN_MOCTR1_TXRQ SET 0 + +; CAN Message Object 20 Control Register +CAN_MOCTR20_CTRL SET 0 +CAN_MOCTR20_DIR SET 0 +CAN_MOCTR20_LIST SET 0 +CAN_MOCTR20_MSGLST SET 0 +CAN_MOCTR20_MSGVAL SET 0 +CAN_MOCTR20_NEWDAT SET 0 +CAN_MOCTR20_RTSEL SET 0 +CAN_MOCTR20_RXEN SET 0 +CAN_MOCTR20_RXPND SET 0 +CAN_MOCTR20_RXUPD SET 0 +CAN_MOCTR20_TXEN0 SET 0 +CAN_MOCTR20_TXEN1 SET 0 +CAN_MOCTR20_TXPND SET 0 +CAN_MOCTR20_TXRQ SET 0 + +; CAN Message Object 21 Control Register +CAN_MOCTR21_CTRL SET 0 +CAN_MOCTR21_DIR SET 0 +CAN_MOCTR21_LIST SET 0 +CAN_MOCTR21_MSGLST SET 0 +CAN_MOCTR21_MSGVAL SET 0 +CAN_MOCTR21_NEWDAT SET 0 +CAN_MOCTR21_RTSEL SET 0 +CAN_MOCTR21_RXEN SET 0 +CAN_MOCTR21_RXPND SET 0 +CAN_MOCTR21_RXUPD SET 0 +CAN_MOCTR21_TXEN0 SET 0 +CAN_MOCTR21_TXEN1 SET 0 +CAN_MOCTR21_TXPND SET 0 +CAN_MOCTR21_TXRQ SET 0 + +; CAN Message Object 22 Control Register +CAN_MOCTR22_CTRL SET 0 +CAN_MOCTR22_DIR SET 0 +CAN_MOCTR22_LIST SET 0 +CAN_MOCTR22_MSGLST SET 0 +CAN_MOCTR22_MSGVAL SET 0 +CAN_MOCTR22_NEWDAT SET 0 +CAN_MOCTR22_RTSEL SET 0 +CAN_MOCTR22_RXEN SET 0 +CAN_MOCTR22_RXPND SET 0 +CAN_MOCTR22_RXUPD SET 0 +CAN_MOCTR22_TXEN0 SET 0 +CAN_MOCTR22_TXEN1 SET 0 +CAN_MOCTR22_TXPND SET 0 +CAN_MOCTR22_TXRQ SET 0 + +; CAN Message Object 23 Control Register +CAN_MOCTR23_CTRL SET 0 +CAN_MOCTR23_DIR SET 0 +CAN_MOCTR23_LIST SET 0 +CAN_MOCTR23_MSGLST SET 0 +CAN_MOCTR23_MSGVAL SET 0 +CAN_MOCTR23_NEWDAT SET 0 +CAN_MOCTR23_RTSEL SET 0 +CAN_MOCTR23_RXEN SET 0 +CAN_MOCTR23_RXPND SET 0 +CAN_MOCTR23_RXUPD SET 0 +CAN_MOCTR23_TXEN0 SET 0 +CAN_MOCTR23_TXEN1 SET 0 +CAN_MOCTR23_TXPND SET 0 +CAN_MOCTR23_TXRQ SET 0 + +; CAN Message Object 24 Control Register +CAN_MOCTR24_CTRL SET 0 +CAN_MOCTR24_DIR SET 0 +CAN_MOCTR24_LIST SET 0 +CAN_MOCTR24_MSGLST SET 0 +CAN_MOCTR24_MSGVAL SET 0 +CAN_MOCTR24_NEWDAT SET 0 +CAN_MOCTR24_RTSEL SET 0 +CAN_MOCTR24_RXEN SET 0 +CAN_MOCTR24_RXPND SET 0 +CAN_MOCTR24_RXUPD SET 0 +CAN_MOCTR24_TXEN0 SET 0 +CAN_MOCTR24_TXEN1 SET 0 +CAN_MOCTR24_TXPND SET 0 +CAN_MOCTR24_TXRQ SET 0 + +; CAN Message Object 25 Control Register +CAN_MOCTR25_CTRL SET 0 +CAN_MOCTR25_DIR SET 0 +CAN_MOCTR25_LIST SET 0 +CAN_MOCTR25_MSGLST SET 0 +CAN_MOCTR25_MSGVAL SET 0 +CAN_MOCTR25_NEWDAT SET 0 +CAN_MOCTR25_RTSEL SET 0 +CAN_MOCTR25_RXEN SET 0 +CAN_MOCTR25_RXPND SET 0 +CAN_MOCTR25_RXUPD SET 0 +CAN_MOCTR25_TXEN0 SET 0 +CAN_MOCTR25_TXEN1 SET 0 +CAN_MOCTR25_TXPND SET 0 +CAN_MOCTR25_TXRQ SET 0 + +; CAN Message Object 26 Control Register +CAN_MOCTR26_CTRL SET 0 +CAN_MOCTR26_DIR SET 0 +CAN_MOCTR26_LIST SET 0 +CAN_MOCTR26_MSGLST SET 0 +CAN_MOCTR26_MSGVAL SET 0 +CAN_MOCTR26_NEWDAT SET 0 +CAN_MOCTR26_RTSEL SET 0 +CAN_MOCTR26_RXEN SET 0 +CAN_MOCTR26_RXPND SET 0 +CAN_MOCTR26_RXUPD SET 0 +CAN_MOCTR26_TXEN0 SET 0 +CAN_MOCTR26_TXEN1 SET 0 +CAN_MOCTR26_TXPND SET 0 +CAN_MOCTR26_TXRQ SET 0 + +; CAN Message Object 27 Control Register +CAN_MOCTR27_CTRL SET 0 +CAN_MOCTR27_DIR SET 0 +CAN_MOCTR27_LIST SET 0 +CAN_MOCTR27_MSGLST SET 0 +CAN_MOCTR27_MSGVAL SET 0 +CAN_MOCTR27_NEWDAT SET 0 +CAN_MOCTR27_RTSEL SET 0 +CAN_MOCTR27_RXEN SET 0 +CAN_MOCTR27_RXPND SET 0 +CAN_MOCTR27_RXUPD SET 0 +CAN_MOCTR27_TXEN0 SET 0 +CAN_MOCTR27_TXEN1 SET 0 +CAN_MOCTR27_TXPND SET 0 +CAN_MOCTR27_TXRQ SET 0 + +; CAN Message Object 28 Control Register +CAN_MOCTR28_CTRL SET 0 +CAN_MOCTR28_DIR SET 0 +CAN_MOCTR28_LIST SET 0 +CAN_MOCTR28_MSGLST SET 0 +CAN_MOCTR28_MSGVAL SET 0 +CAN_MOCTR28_NEWDAT SET 0 +CAN_MOCTR28_RTSEL SET 0 +CAN_MOCTR28_RXEN SET 0 +CAN_MOCTR28_RXPND SET 0 +CAN_MOCTR28_RXUPD SET 0 +CAN_MOCTR28_TXEN0 SET 0 +CAN_MOCTR28_TXEN1 SET 0 +CAN_MOCTR28_TXPND SET 0 +CAN_MOCTR28_TXRQ SET 0 + +; CAN Message Object 29 Control Register +CAN_MOCTR29_CTRL SET 0 +CAN_MOCTR29_DIR SET 0 +CAN_MOCTR29_LIST SET 0 +CAN_MOCTR29_MSGLST SET 0 +CAN_MOCTR29_MSGVAL SET 0 +CAN_MOCTR29_NEWDAT SET 0 +CAN_MOCTR29_RTSEL SET 0 +CAN_MOCTR29_RXEN SET 0 +CAN_MOCTR29_RXPND SET 0 +CAN_MOCTR29_RXUPD SET 0 +CAN_MOCTR29_TXEN0 SET 0 +CAN_MOCTR29_TXEN1 SET 0 +CAN_MOCTR29_TXPND SET 0 +CAN_MOCTR29_TXRQ SET 0 + +; CAN Message Object 2 Control Register +CAN_MOCTR2_CTRL SET 0 +CAN_MOCTR2_DIR SET 1 +CAN_MOCTR2_LIST SET 0 +CAN_MOCTR2_MSGLST SET 0 +CAN_MOCTR2_MSGVAL SET 0 +CAN_MOCTR2_NEWDAT SET 0 +CAN_MOCTR2_RTSEL SET 0 +CAN_MOCTR2_RXEN SET 0 +CAN_MOCTR2_RXPND SET 0 +CAN_MOCTR2_RXUPD SET 0 +CAN_MOCTR2_TXEN0 SET 0 +CAN_MOCTR2_TXEN1 SET 0 +CAN_MOCTR2_TXPND SET 0 +CAN_MOCTR2_TXRQ SET 0 + +; CAN Message Object 30 Control Register +CAN_MOCTR30_CTRL SET 0 +CAN_MOCTR30_DIR SET 0 +CAN_MOCTR30_LIST SET 0 +CAN_MOCTR30_MSGLST SET 0 +CAN_MOCTR30_MSGVAL SET 0 +CAN_MOCTR30_NEWDAT SET 0 +CAN_MOCTR30_RTSEL SET 0 +CAN_MOCTR30_RXEN SET 0 +CAN_MOCTR30_RXPND SET 0 +CAN_MOCTR30_RXUPD SET 0 +CAN_MOCTR30_TXEN0 SET 0 +CAN_MOCTR30_TXEN1 SET 0 +CAN_MOCTR30_TXPND SET 0 +CAN_MOCTR30_TXRQ SET 0 + +; CAN Message Object 31 Control Register +CAN_MOCTR31_CTRL SET 0 +CAN_MOCTR31_DIR SET 0 +CAN_MOCTR31_LIST SET 0 +CAN_MOCTR31_MSGLST SET 0 +CAN_MOCTR31_MSGVAL SET 0 +CAN_MOCTR31_NEWDAT SET 0 +CAN_MOCTR31_RTSEL SET 0 +CAN_MOCTR31_RXEN SET 0 +CAN_MOCTR31_RXPND SET 0 +CAN_MOCTR31_RXUPD SET 0 +CAN_MOCTR31_TXEN0 SET 0 +CAN_MOCTR31_TXEN1 SET 0 +CAN_MOCTR31_TXPND SET 0 +CAN_MOCTR31_TXRQ SET 0 + +; CAN Message Object 3 Control Register +CAN_MOCTR3_CTRL SET 0 +CAN_MOCTR3_DIR SET 0 +CAN_MOCTR3_LIST SET 0 +CAN_MOCTR3_MSGLST SET 0 +CAN_MOCTR3_MSGVAL SET 0 +CAN_MOCTR3_NEWDAT SET 0 +CAN_MOCTR3_RTSEL SET 0 +CAN_MOCTR3_RXEN SET 0 +CAN_MOCTR3_RXPND SET 0 +CAN_MOCTR3_RXUPD SET 0 +CAN_MOCTR3_TXEN0 SET 0 +CAN_MOCTR3_TXEN1 SET 0 +CAN_MOCTR3_TXPND SET 0 +CAN_MOCTR3_TXRQ SET 0 + +; CAN Message Object 4 Control Register +CAN_MOCTR4_CTRL SET 0 +CAN_MOCTR4_DIR SET 0 +CAN_MOCTR4_LIST SET 0 +CAN_MOCTR4_MSGLST SET 0 +CAN_MOCTR4_MSGVAL SET 0 +CAN_MOCTR4_NEWDAT SET 0 +CAN_MOCTR4_RTSEL SET 0 +CAN_MOCTR4_RXEN SET 0 +CAN_MOCTR4_RXPND SET 0 +CAN_MOCTR4_RXUPD SET 0 +CAN_MOCTR4_TXEN0 SET 0 +CAN_MOCTR4_TXEN1 SET 0 +CAN_MOCTR4_TXPND SET 0 +CAN_MOCTR4_TXRQ SET 0 + +; CAN Message Object 5 Control Register +CAN_MOCTR5_CTRL SET 1544 +CAN_MOCTR5_DIR SET 0 +CAN_MOCTR5_LIST SET 1 +CAN_MOCTR5_MSGLST SET 0 +CAN_MOCTR5_MSGVAL SET 1 +CAN_MOCTR5_NEWDAT SET 0 +CAN_MOCTR5_RTSEL SET 0 +CAN_MOCTR5_RXEN SET 0 +CAN_MOCTR5_RXPND SET 0 +CAN_MOCTR5_RXUPD SET 0 +CAN_MOCTR5_TXEN0 SET 0 +CAN_MOCTR5_TXEN1 SET 0 +CAN_MOCTR5_TXPND SET 0 +CAN_MOCTR5_TXRQ SET 0 + +; CAN Message Object 6 Control Register +CAN_MOCTR6_CTRL SET 1797 +CAN_MOCTR6_DIR SET 1 +CAN_MOCTR6_LIST SET 1 +CAN_MOCTR6_MSGLST SET 0 +CAN_MOCTR6_MSGVAL SET 1 +CAN_MOCTR6_NEWDAT SET 0 +CAN_MOCTR6_RTSEL SET 0 +CAN_MOCTR6_RXEN SET 0 +CAN_MOCTR6_RXPND SET 0 +CAN_MOCTR6_RXUPD SET 0 +CAN_MOCTR6_TXEN0 SET 0 +CAN_MOCTR6_TXEN1 SET 0 +CAN_MOCTR6_TXPND SET 0 +CAN_MOCTR6_TXRQ SET 0 + +; CAN Message Object 7 Control Register +CAN_MOCTR7_CTRL SET 2310 +CAN_MOCTR7_DIR SET 0 +CAN_MOCTR7_LIST SET 1 +CAN_MOCTR7_MSGLST SET 0 +CAN_MOCTR7_MSGVAL SET 1 +CAN_MOCTR7_NEWDAT SET 0 +CAN_MOCTR7_RTSEL SET 0 +CAN_MOCTR7_RXEN SET 0 +CAN_MOCTR7_RXPND SET 0 +CAN_MOCTR7_RXUPD SET 0 +CAN_MOCTR7_TXEN0 SET 0 +CAN_MOCTR7_TXEN1 SET 0 +CAN_MOCTR7_TXPND SET 0 +CAN_MOCTR7_TXRQ SET 0 + +; CAN Message Object 8 Control Register +CAN_MOCTR8_CTRL SET 1288 +CAN_MOCTR8_DIR SET 0 +CAN_MOCTR8_LIST SET 1 +CAN_MOCTR8_MSGLST SET 0 +CAN_MOCTR8_MSGVAL SET 1 +CAN_MOCTR8_NEWDAT SET 0 +CAN_MOCTR8_RTSEL SET 0 +CAN_MOCTR8_RXEN SET 0 +CAN_MOCTR8_RXPND SET 0 +CAN_MOCTR8_RXUPD SET 0 +CAN_MOCTR8_TXEN0 SET 0 +CAN_MOCTR8_TXEN1 SET 0 +CAN_MOCTR8_TXPND SET 0 +CAN_MOCTR8_TXRQ SET 0 + +; CAN Message Object 9 Control Register +CAN_MOCTR9_CTRL SET 2311 +CAN_MOCTR9_DIR SET 1 +CAN_MOCTR9_LIST SET 1 +CAN_MOCTR9_MSGLST SET 0 +CAN_MOCTR9_MSGVAL SET 1 +CAN_MOCTR9_NEWDAT SET 0 +CAN_MOCTR9_RTSEL SET 0 +CAN_MOCTR9_RXEN SET 0 +CAN_MOCTR9_RXPND SET 0 +CAN_MOCTR9_RXUPD SET 0 +CAN_MOCTR9_TXEN0 SET 0 +CAN_MOCTR9_TXEN1 SET 0 +CAN_MOCTR9_TXPND SET 0 +CAN_MOCTR9_TXRQ SET 0 + +; CAN Message Object 0 Data Register High +CAN_MODATAH0_DB4 SET 0 +CAN_MODATAH0_DB5 SET 0 +CAN_MODATAH0_DB6 SET 0 +CAN_MODATAH0_DB7 SET 0 + +; CAN Message Object 10 Data Register High +CAN_MODATAH10_DB4 SET 0 +CAN_MODATAH10_DB5 SET 0 +CAN_MODATAH10_DB6 SET 0 +CAN_MODATAH10_DB7 SET 0 + +; CAN Message Object 11 Data Register High +CAN_MODATAH11_DB4 SET 0 +CAN_MODATAH11_DB5 SET 0 +CAN_MODATAH11_DB6 SET 0 +CAN_MODATAH11_DB7 SET 0 + +; CAN Message Object 12 Data Register High +CAN_MODATAH12_DB4 SET 0 +CAN_MODATAH12_DB5 SET 0 +CAN_MODATAH12_DB6 SET 0 +CAN_MODATAH12_DB7 SET 0 + +; CAN Message Object 13 Data Register High +CAN_MODATAH13_DB4 SET 0 +CAN_MODATAH13_DB5 SET 0 +CAN_MODATAH13_DB6 SET 0 +CAN_MODATAH13_DB7 SET 0 + +; CAN Message Object 14 Data Register High +CAN_MODATAH14_DB4 SET 0 +CAN_MODATAH14_DB5 SET 0 +CAN_MODATAH14_DB6 SET 0 +CAN_MODATAH14_DB7 SET 0 + +; CAN Message Object 15 Data Register High +CAN_MODATAH15_DB4 SET 0 +CAN_MODATAH15_DB5 SET 0 +CAN_MODATAH15_DB6 SET 0 +CAN_MODATAH15_DB7 SET 0 + +; CAN Message Object 16 Data Register High +CAN_MODATAH16_DB4 SET 0 +CAN_MODATAH16_DB5 SET 0 +CAN_MODATAH16_DB6 SET 0 +CAN_MODATAH16_DB7 SET 0 + +; CAN Message Object 17 Data Register High +CAN_MODATAH17_DB4 SET 0 +CAN_MODATAH17_DB5 SET 0 +CAN_MODATAH17_DB6 SET 0 +CAN_MODATAH17_DB7 SET 0 + +; CAN Message Object 18 Data Register High +CAN_MODATAH18_DB4 SET 0 +CAN_MODATAH18_DB5 SET 0 +CAN_MODATAH18_DB6 SET 0 +CAN_MODATAH18_DB7 SET 0 + +; CAN Message Object 19 Data Register High +CAN_MODATAH19_DB4 SET 0 +CAN_MODATAH19_DB5 SET 0 +CAN_MODATAH19_DB6 SET 0 +CAN_MODATAH19_DB7 SET 0 + +; CAN Message Object 1 Data Register High +CAN_MODATAH1_DB4 SET 0 +CAN_MODATAH1_DB5 SET 0 +CAN_MODATAH1_DB6 SET 0 +CAN_MODATAH1_DB7 SET 0 + +; CAN Message Object 20 Data Register High +CAN_MODATAH20_DB4 SET 0 +CAN_MODATAH20_DB5 SET 0 +CAN_MODATAH20_DB6 SET 0 +CAN_MODATAH20_DB7 SET 0 + +; CAN Message Object 21 Data Register High +CAN_MODATAH21_DB4 SET 0 +CAN_MODATAH21_DB5 SET 0 +CAN_MODATAH21_DB6 SET 0 +CAN_MODATAH21_DB7 SET 0 + +; CAN Message Object 22 Data Register High +CAN_MODATAH22_DB4 SET 0 +CAN_MODATAH22_DB5 SET 0 +CAN_MODATAH22_DB6 SET 0 +CAN_MODATAH22_DB7 SET 0 + +; CAN Message Object 23 Data Register High +CAN_MODATAH23_DB4 SET 0 +CAN_MODATAH23_DB5 SET 0 +CAN_MODATAH23_DB6 SET 0 +CAN_MODATAH23_DB7 SET 0 + +; CAN Message Object 24 Data Register High +CAN_MODATAH24_DB4 SET 0 +CAN_MODATAH24_DB5 SET 0 +CAN_MODATAH24_DB6 SET 0 +CAN_MODATAH24_DB7 SET 0 + +; CAN Message Object 25 Data Register High +CAN_MODATAH25_DB4 SET 0 +CAN_MODATAH25_DB5 SET 0 +CAN_MODATAH25_DB6 SET 0 +CAN_MODATAH25_DB7 SET 0 + +; CAN Message Object 26 Data Register High +CAN_MODATAH26_DB4 SET 0 +CAN_MODATAH26_DB5 SET 0 +CAN_MODATAH26_DB6 SET 0 +CAN_MODATAH26_DB7 SET 0 + +; CAN Message Object 27 Data Register High +CAN_MODATAH27_DB4 SET 0 +CAN_MODATAH27_DB5 SET 0 +CAN_MODATAH27_DB6 SET 0 +CAN_MODATAH27_DB7 SET 0 + +; CAN Message Object 28 Data Register High +CAN_MODATAH28_DB4 SET 0 +CAN_MODATAH28_DB5 SET 0 +CAN_MODATAH28_DB6 SET 0 +CAN_MODATAH28_DB7 SET 0 + +; CAN Message Object 29 Data Register High +CAN_MODATAH29_DB4 SET 0 +CAN_MODATAH29_DB5 SET 0 +CAN_MODATAH29_DB6 SET 0 +CAN_MODATAH29_DB7 SET 0 + +; CAN Message Object 2 Data Register High +CAN_MODATAH2_DB4 SET 0 +CAN_MODATAH2_DB5 SET 0 +CAN_MODATAH2_DB6 SET 0 +CAN_MODATAH2_DB7 SET 0 + +; CAN Message Object 30 Data Register High +CAN_MODATAH30_DB4 SET 0 +CAN_MODATAH30_DB5 SET 0 +CAN_MODATAH30_DB6 SET 0 +CAN_MODATAH30_DB7 SET 0 + +; CAN Message Object 31 Data Register High +CAN_MODATAH31_DB4 SET 0 +CAN_MODATAH31_DB5 SET 0 +CAN_MODATAH31_DB6 SET 0 +CAN_MODATAH31_DB7 SET 0 + +; CAN Message Object 3 Data Register High +CAN_MODATAH3_DB4 SET 0 +CAN_MODATAH3_DB5 SET 0 +CAN_MODATAH3_DB6 SET 0 +CAN_MODATAH3_DB7 SET 0 + +; CAN Message Object 4 Data Register High +CAN_MODATAH4_DB4 SET 0 +CAN_MODATAH4_DB5 SET 0 +CAN_MODATAH4_DB6 SET 0 +CAN_MODATAH4_DB7 SET 0 + +; CAN Message Object 5 Data Register High +CAN_MODATAH5_DB4 SET 0 +CAN_MODATAH5_DB5 SET 0 +CAN_MODATAH5_DB6 SET 0 +CAN_MODATAH5_DB7 SET 0 + +; CAN Message Object 6 Data Register High +CAN_MODATAH6_DB4 SET 0 +CAN_MODATAH6_DB5 SET 0 +CAN_MODATAH6_DB6 SET 0 +CAN_MODATAH6_DB7 SET 0 + +; CAN Message Object 7 Data Register High +CAN_MODATAH7_DB4 SET 0 +CAN_MODATAH7_DB5 SET 0 +CAN_MODATAH7_DB6 SET 0 +CAN_MODATAH7_DB7 SET 0 + +; CAN Message Object 8 Data Register High +CAN_MODATAH8_DB4 SET 0 +CAN_MODATAH8_DB5 SET 0 +CAN_MODATAH8_DB6 SET 0 +CAN_MODATAH8_DB7 SET 0 + +; CAN Message Object 9 Data Register High +CAN_MODATAH9_DB4 SET 0 +CAN_MODATAH9_DB5 SET 0 +CAN_MODATAH9_DB6 SET 0 +CAN_MODATAH9_DB7 SET 0 + +; CAN Message Object 0 Data Register Low +CAN_MODATAL0_DB0 SET 0 +CAN_MODATAL0_DB1 SET 0 +CAN_MODATAL0_DB2 SET 0 +CAN_MODATAL0_DB3 SET 0 + +; CAN Message Object 10 Data Register Low +CAN_MODATAL10_DB0 SET 0 +CAN_MODATAL10_DB1 SET 0 +CAN_MODATAL10_DB2 SET 0 +CAN_MODATAL10_DB3 SET 0 + +; CAN Message Object 11 Data Register Low +CAN_MODATAL11_DB0 SET 0 +CAN_MODATAL11_DB1 SET 0 +CAN_MODATAL11_DB2 SET 0 +CAN_MODATAL11_DB3 SET 0 + +; CAN Message Object 12 Data Register Low +CAN_MODATAL12_DB0 SET 0 +CAN_MODATAL12_DB1 SET 0 +CAN_MODATAL12_DB2 SET 0 +CAN_MODATAL12_DB3 SET 0 + +; CAN Message Object 13 Data Register Low +CAN_MODATAL13_DB0 SET 0 +CAN_MODATAL13_DB1 SET 0 +CAN_MODATAL13_DB2 SET 0 +CAN_MODATAL13_DB3 SET 0 + +; CAN Message Object 14 Data Register Low +CAN_MODATAL14_DB0 SET 0 +CAN_MODATAL14_DB1 SET 0 +CAN_MODATAL14_DB2 SET 0 +CAN_MODATAL14_DB3 SET 0 + +; CAN Message Object 15 Data Register Low +CAN_MODATAL15_DB0 SET 0 +CAN_MODATAL15_DB1 SET 0 +CAN_MODATAL15_DB2 SET 0 +CAN_MODATAL15_DB3 SET 0 + +; CAN Message Object 16 Data Register Low +CAN_MODATAL16_DB0 SET 0 +CAN_MODATAL16_DB1 SET 0 +CAN_MODATAL16_DB2 SET 0 +CAN_MODATAL16_DB3 SET 0 + +; CAN Message Object 17 Data Register Low +CAN_MODATAL17_DB0 SET 0 +CAN_MODATAL17_DB1 SET 0 +CAN_MODATAL17_DB2 SET 0 +CAN_MODATAL17_DB3 SET 0 + +; CAN Message Object 18 Data Register Low +CAN_MODATAL18_DB0 SET 0 +CAN_MODATAL18_DB1 SET 0 +CAN_MODATAL18_DB2 SET 0 +CAN_MODATAL18_DB3 SET 0 + +; CAN Message Object 19 Data Register Low +CAN_MODATAL19_DB0 SET 0 +CAN_MODATAL19_DB1 SET 0 +CAN_MODATAL19_DB2 SET 0 +CAN_MODATAL19_DB3 SET 0 + +; CAN Message Object 1 Data Register Low +CAN_MODATAL1_DB0 SET 0 +CAN_MODATAL1_DB1 SET 0 +CAN_MODATAL1_DB2 SET 0 +CAN_MODATAL1_DB3 SET 0 + +; CAN Message Object 20 Data Register Low +CAN_MODATAL20_DB0 SET 0 +CAN_MODATAL20_DB1 SET 0 +CAN_MODATAL20_DB2 SET 0 +CAN_MODATAL20_DB3 SET 0 + +; CAN Message Object 21 Data Register Low +CAN_MODATAL21_DB0 SET 0 +CAN_MODATAL21_DB1 SET 0 +CAN_MODATAL21_DB2 SET 0 +CAN_MODATAL21_DB3 SET 0 + +; CAN Message Object 22 Data Register Low +CAN_MODATAL22_DB0 SET 0 +CAN_MODATAL22_DB1 SET 0 +CAN_MODATAL22_DB2 SET 0 +CAN_MODATAL22_DB3 SET 0 + +; CAN Message Object 23 Data Register Low +CAN_MODATAL23_DB0 SET 0 +CAN_MODATAL23_DB1 SET 0 +CAN_MODATAL23_DB2 SET 0 +CAN_MODATAL23_DB3 SET 0 + +; CAN Message Object 24 Data Register Low +CAN_MODATAL24_DB0 SET 0 +CAN_MODATAL24_DB1 SET 0 +CAN_MODATAL24_DB2 SET 0 +CAN_MODATAL24_DB3 SET 0 + +; CAN Message Object 25 Data Register Low +CAN_MODATAL25_DB0 SET 0 +CAN_MODATAL25_DB1 SET 0 +CAN_MODATAL25_DB2 SET 0 +CAN_MODATAL25_DB3 SET 0 + +; CAN Message Object 26 Data Register Low +CAN_MODATAL26_DB0 SET 0 +CAN_MODATAL26_DB1 SET 0 +CAN_MODATAL26_DB2 SET 0 +CAN_MODATAL26_DB3 SET 0 + +; CAN Message Object 27 Data Register Low +CAN_MODATAL27_DB0 SET 0 +CAN_MODATAL27_DB1 SET 0 +CAN_MODATAL27_DB2 SET 0 +CAN_MODATAL27_DB3 SET 0 + +; CAN Message Object 28 Data Register Low +CAN_MODATAL28_DB0 SET 0 +CAN_MODATAL28_DB1 SET 0 +CAN_MODATAL28_DB2 SET 0 +CAN_MODATAL28_DB3 SET 0 + +; CAN Message Object 29 Data Register Low +CAN_MODATAL29_DB0 SET 0 +CAN_MODATAL29_DB1 SET 0 +CAN_MODATAL29_DB2 SET 0 +CAN_MODATAL29_DB3 SET 0 + +; CAN Message Object 2 Data Register Low +CAN_MODATAL2_DB0 SET 0 +CAN_MODATAL2_DB1 SET 0 +CAN_MODATAL2_DB2 SET 0 +CAN_MODATAL2_DB3 SET 0 + +; CAN Message Object 30 Data Register Low +CAN_MODATAL30_DB0 SET 0 +CAN_MODATAL30_DB1 SET 0 +CAN_MODATAL30_DB2 SET 0 +CAN_MODATAL30_DB3 SET 0 + +; CAN Message Object 31 Data Register Low +CAN_MODATAL31_DB0 SET 0 +CAN_MODATAL31_DB1 SET 0 +CAN_MODATAL31_DB2 SET 0 +CAN_MODATAL31_DB3 SET 0 + +; CAN Message Object 3 Data Register Low +CAN_MODATAL3_DB0 SET 0 +CAN_MODATAL3_DB1 SET 0 +CAN_MODATAL3_DB2 SET 0 +CAN_MODATAL3_DB3 SET 0 + +; CAN Message Object 4 Data Register Low +CAN_MODATAL4_DB0 SET 0 +CAN_MODATAL4_DB1 SET 0 +CAN_MODATAL4_DB2 SET 0 +CAN_MODATAL4_DB3 SET 0 + +; CAN Message Object 5 Data Register Low +CAN_MODATAL5_DB0 SET 0 +CAN_MODATAL5_DB1 SET 0 +CAN_MODATAL5_DB2 SET 0 +CAN_MODATAL5_DB3 SET 0 + +; CAN Message Object 6 Data Register Low +CAN_MODATAL6_DB0 SET 0 +CAN_MODATAL6_DB1 SET 0 +CAN_MODATAL6_DB2 SET 0 +CAN_MODATAL6_DB3 SET 0 + +; CAN Message Object 7 Data Register Low +CAN_MODATAL7_DB0 SET 0 +CAN_MODATAL7_DB1 SET 0 +CAN_MODATAL7_DB2 SET 0 +CAN_MODATAL7_DB3 SET 0 + +; CAN Message Object 8 Data Register Low +CAN_MODATAL8_DB0 SET 0 +CAN_MODATAL8_DB1 SET 0 +CAN_MODATAL8_DB2 SET 0 +CAN_MODATAL8_DB3 SET 0 + +; CAN Message Object 9 Data Register Low +CAN_MODATAL9_DB0 SET 0 +CAN_MODATAL9_DB1 SET 0 +CAN_MODATAL9_DB2 SET 0 +CAN_MODATAL9_DB3 SET 0 + +; CAN Message Object 0 Function Control Register +CAN_MOFCR0_0 SET 0 +CAN_MOFCR0_0 SET 0 +CAN_MOFCR0_0 SET 0 +CAN_MOFCR0_0 SET 0 +CAN_MOFCR0_DATC SET 0 +CAN_MOFCR0_DLC SET 8 +CAN_MOFCR0_DLCC SET 0 +CAN_MOFCR0_FRREN SET 0 +CAN_MOFCR0_GDFS SET 0 +CAN_MOFCR0_IDC SET 0 +CAN_MOFCR0_MMC SET 0 +CAN_MOFCR0_OVIE SET 0 +CAN_MOFCR0_RMM SET 0 +CAN_MOFCR0_RXIE SET 0 +CAN_MOFCR0_SDT SET 0 +CAN_MOFCR0_STT SET 0 +CAN_MOFCR0_TXIE SET 0 + +; CAN Message Object 10 Function Control Register +CAN_MOFCR10_0 SET 0 +CAN_MOFCR10_0 SET 0 +CAN_MOFCR10_0 SET 0 +CAN_MOFCR10_0 SET 0 +CAN_MOFCR10_DATC SET 0 +CAN_MOFCR10_DLC SET 0 +CAN_MOFCR10_DLCC SET 0 +CAN_MOFCR10_FRREN SET 0 +CAN_MOFCR10_GDFS SET 0 +CAN_MOFCR10_IDC SET 0 +CAN_MOFCR10_MMC SET 0 +CAN_MOFCR10_OVIE SET 0 +CAN_MOFCR10_RMM SET 0 +CAN_MOFCR10_RXIE SET 0 +CAN_MOFCR10_SDT SET 0 +CAN_MOFCR10_STT SET 0 +CAN_MOFCR10_TXIE SET 0 + +; CAN Message Object 11 Function Control Register +CAN_MOFCR11_0 SET 0 +CAN_MOFCR11_0 SET 0 +CAN_MOFCR11_0 SET 0 +CAN_MOFCR11_0 SET 0 +CAN_MOFCR11_DATC SET 0 +CAN_MOFCR11_DLC SET 0 +CAN_MOFCR11_DLCC SET 0 +CAN_MOFCR11_FRREN SET 0 +CAN_MOFCR11_GDFS SET 0 +CAN_MOFCR11_IDC SET 0 +CAN_MOFCR11_MMC SET 0 +CAN_MOFCR11_OVIE SET 0 +CAN_MOFCR11_RMM SET 0 +CAN_MOFCR11_RXIE SET 0 +CAN_MOFCR11_SDT SET 0 +CAN_MOFCR11_STT SET 0 +CAN_MOFCR11_TXIE SET 0 + +; CAN Message Object 12 Function Control Register +CAN_MOFCR12_0 SET 0 +CAN_MOFCR12_0 SET 0 +CAN_MOFCR12_0 SET 0 +CAN_MOFCR12_0 SET 0 +CAN_MOFCR12_DATC SET 0 +CAN_MOFCR12_DLC SET 0 +CAN_MOFCR12_DLCC SET 0 +CAN_MOFCR12_FRREN SET 0 +CAN_MOFCR12_GDFS SET 0 +CAN_MOFCR12_IDC SET 0 +CAN_MOFCR12_MMC SET 0 +CAN_MOFCR12_OVIE SET 0 +CAN_MOFCR12_RMM SET 0 +CAN_MOFCR12_RXIE SET 0 +CAN_MOFCR12_SDT SET 0 +CAN_MOFCR12_STT SET 0 +CAN_MOFCR12_TXIE SET 0 + +; CAN Message Object 13 Function Control Register +CAN_MOFCR13_0 SET 0 +CAN_MOFCR13_0 SET 0 +CAN_MOFCR13_0 SET 0 +CAN_MOFCR13_0 SET 0 +CAN_MOFCR13_DATC SET 0 +CAN_MOFCR13_DLC SET 0 +CAN_MOFCR13_DLCC SET 0 +CAN_MOFCR13_FRREN SET 0 +CAN_MOFCR13_GDFS SET 0 +CAN_MOFCR13_IDC SET 0 +CAN_MOFCR13_MMC SET 0 +CAN_MOFCR13_OVIE SET 0 +CAN_MOFCR13_RMM SET 0 +CAN_MOFCR13_RXIE SET 0 +CAN_MOFCR13_SDT SET 0 +CAN_MOFCR13_STT SET 0 +CAN_MOFCR13_TXIE SET 0 + +; CAN Message Object 14 Function Control Register +CAN_MOFCR14_0 SET 0 +CAN_MOFCR14_0 SET 0 +CAN_MOFCR14_0 SET 0 +CAN_MOFCR14_0 SET 0 +CAN_MOFCR14_DATC SET 0 +CAN_MOFCR14_DLC SET 0 +CAN_MOFCR14_DLCC SET 0 +CAN_MOFCR14_FRREN SET 0 +CAN_MOFCR14_GDFS SET 0 +CAN_MOFCR14_IDC SET 0 +CAN_MOFCR14_MMC SET 0 +CAN_MOFCR14_OVIE SET 0 +CAN_MOFCR14_RMM SET 0 +CAN_MOFCR14_RXIE SET 0 +CAN_MOFCR14_SDT SET 0 +CAN_MOFCR14_STT SET 0 +CAN_MOFCR14_TXIE SET 0 + +; CAN Message Object 15 Function Control Register +CAN_MOFCR15_0 SET 0 +CAN_MOFCR15_0 SET 0 +CAN_MOFCR15_0 SET 0 +CAN_MOFCR15_0 SET 0 +CAN_MOFCR15_DATC SET 0 +CAN_MOFCR15_DLC SET 0 +CAN_MOFCR15_DLCC SET 0 +CAN_MOFCR15_FRREN SET 0 +CAN_MOFCR15_GDFS SET 0 +CAN_MOFCR15_IDC SET 0 +CAN_MOFCR15_MMC SET 0 +CAN_MOFCR15_OVIE SET 0 +CAN_MOFCR15_RMM SET 0 +CAN_MOFCR15_RXIE SET 0 +CAN_MOFCR15_SDT SET 0 +CAN_MOFCR15_STT SET 0 +CAN_MOFCR15_TXIE SET 0 + +; CAN Message Object 16 Function Control Register +CAN_MOFCR16_0 SET 0 +CAN_MOFCR16_0 SET 0 +CAN_MOFCR16_0 SET 0 +CAN_MOFCR16_0 SET 0 +CAN_MOFCR16_DATC SET 0 +CAN_MOFCR16_DLC SET 0 +CAN_MOFCR16_DLCC SET 0 +CAN_MOFCR16_FRREN SET 0 +CAN_MOFCR16_GDFS SET 0 +CAN_MOFCR16_IDC SET 0 +CAN_MOFCR16_MMC SET 0 +CAN_MOFCR16_OVIE SET 0 +CAN_MOFCR16_RMM SET 0 +CAN_MOFCR16_RXIE SET 0 +CAN_MOFCR16_SDT SET 0 +CAN_MOFCR16_STT SET 0 +CAN_MOFCR16_TXIE SET 0 + +; CAN Message Object 17 Function Control Register +CAN_MOFCR17_0 SET 0 +CAN_MOFCR17_0 SET 0 +CAN_MOFCR17_0 SET 0 +CAN_MOFCR17_0 SET 0 +CAN_MOFCR17_DATC SET 0 +CAN_MOFCR17_DLC SET 0 +CAN_MOFCR17_DLCC SET 0 +CAN_MOFCR17_FRREN SET 0 +CAN_MOFCR17_GDFS SET 0 +CAN_MOFCR17_IDC SET 0 +CAN_MOFCR17_MMC SET 0 +CAN_MOFCR17_OVIE SET 0 +CAN_MOFCR17_RMM SET 0 +CAN_MOFCR17_RXIE SET 0 +CAN_MOFCR17_SDT SET 0 +CAN_MOFCR17_STT SET 0 +CAN_MOFCR17_TXIE SET 0 + +; CAN Message Object 18 Function Control Register +CAN_MOFCR18_0 SET 0 +CAN_MOFCR18_0 SET 0 +CAN_MOFCR18_0 SET 0 +CAN_MOFCR18_0 SET 0 +CAN_MOFCR18_DATC SET 0 +CAN_MOFCR18_DLC SET 0 +CAN_MOFCR18_DLCC SET 0 +CAN_MOFCR18_FRREN SET 0 +CAN_MOFCR18_GDFS SET 0 +CAN_MOFCR18_IDC SET 0 +CAN_MOFCR18_MMC SET 0 +CAN_MOFCR18_OVIE SET 0 +CAN_MOFCR18_RMM SET 0 +CAN_MOFCR18_RXIE SET 0 +CAN_MOFCR18_SDT SET 0 +CAN_MOFCR18_STT SET 0 +CAN_MOFCR18_TXIE SET 0 + +; CAN Message Object 19 Function Control Register +CAN_MOFCR19_0 SET 0 +CAN_MOFCR19_0 SET 0 +CAN_MOFCR19_0 SET 0 +CAN_MOFCR19_0 SET 0 +CAN_MOFCR19_DATC SET 0 +CAN_MOFCR19_DLC SET 0 +CAN_MOFCR19_DLCC SET 0 +CAN_MOFCR19_FRREN SET 0 +CAN_MOFCR19_GDFS SET 0 +CAN_MOFCR19_IDC SET 0 +CAN_MOFCR19_MMC SET 0 +CAN_MOFCR19_OVIE SET 0 +CAN_MOFCR19_RMM SET 0 +CAN_MOFCR19_RXIE SET 0 +CAN_MOFCR19_SDT SET 0 +CAN_MOFCR19_STT SET 0 +CAN_MOFCR19_TXIE SET 0 + +; CAN Message Object 1 Function Control Register +CAN_MOFCR1_0 SET 0 +CAN_MOFCR1_0 SET 0 +CAN_MOFCR1_0 SET 0 +CAN_MOFCR1_0 SET 0 +CAN_MOFCR1_DATC SET 0 +CAN_MOFCR1_DLC SET 8 +CAN_MOFCR1_DLCC SET 0 +CAN_MOFCR1_FRREN SET 0 +CAN_MOFCR1_GDFS SET 0 +CAN_MOFCR1_IDC SET 0 +CAN_MOFCR1_MMC SET 0 +CAN_MOFCR1_OVIE SET 0 +CAN_MOFCR1_RMM SET 0 +CAN_MOFCR1_RXIE SET 0 +CAN_MOFCR1_SDT SET 0 +CAN_MOFCR1_STT SET 0 +CAN_MOFCR1_TXIE SET 0 + +; CAN Message Object 20 Function Control Register +CAN_MOFCR20_0 SET 0 +CAN_MOFCR20_0 SET 0 +CAN_MOFCR20_0 SET 0 +CAN_MOFCR20_0 SET 0 +CAN_MOFCR20_DATC SET 0 +CAN_MOFCR20_DLC SET 0 +CAN_MOFCR20_DLCC SET 0 +CAN_MOFCR20_FRREN SET 0 +CAN_MOFCR20_GDFS SET 0 +CAN_MOFCR20_IDC SET 0 +CAN_MOFCR20_MMC SET 0 +CAN_MOFCR20_OVIE SET 0 +CAN_MOFCR20_RMM SET 0 +CAN_MOFCR20_RXIE SET 0 +CAN_MOFCR20_SDT SET 0 +CAN_MOFCR20_STT SET 0 +CAN_MOFCR20_TXIE SET 0 + +; CAN Message Object 21 Function Control Register +CAN_MOFCR21_0 SET 0 +CAN_MOFCR21_0 SET 0 +CAN_MOFCR21_0 SET 0 +CAN_MOFCR21_0 SET 0 +CAN_MOFCR21_DATC SET 0 +CAN_MOFCR21_DLC SET 0 +CAN_MOFCR21_DLCC SET 0 +CAN_MOFCR21_FRREN SET 0 +CAN_MOFCR21_GDFS SET 0 +CAN_MOFCR21_IDC SET 0 +CAN_MOFCR21_MMC SET 0 +CAN_MOFCR21_OVIE SET 0 +CAN_MOFCR21_RMM SET 0 +CAN_MOFCR21_RXIE SET 0 +CAN_MOFCR21_SDT SET 0 +CAN_MOFCR21_STT SET 0 +CAN_MOFCR21_TXIE SET 0 + +; CAN Message Object 22 Function Control Register +CAN_MOFCR22_0 SET 0 +CAN_MOFCR22_0 SET 0 +CAN_MOFCR22_0 SET 0 +CAN_MOFCR22_0 SET 0 +CAN_MOFCR22_DATC SET 0 +CAN_MOFCR22_DLC SET 0 +CAN_MOFCR22_DLCC SET 0 +CAN_MOFCR22_FRREN SET 0 +CAN_MOFCR22_GDFS SET 0 +CAN_MOFCR22_IDC SET 0 +CAN_MOFCR22_MMC SET 0 +CAN_MOFCR22_OVIE SET 0 +CAN_MOFCR22_RMM SET 0 +CAN_MOFCR22_RXIE SET 0 +CAN_MOFCR22_SDT SET 0 +CAN_MOFCR22_STT SET 0 +CAN_MOFCR22_TXIE SET 0 + +; CAN Message Object 23 Function Control Register +CAN_MOFCR23_0 SET 0 +CAN_MOFCR23_0 SET 0 +CAN_MOFCR23_0 SET 0 +CAN_MOFCR23_0 SET 0 +CAN_MOFCR23_DATC SET 0 +CAN_MOFCR23_DLC SET 0 +CAN_MOFCR23_DLCC SET 0 +CAN_MOFCR23_FRREN SET 0 +CAN_MOFCR23_GDFS SET 0 +CAN_MOFCR23_IDC SET 0 +CAN_MOFCR23_MMC SET 0 +CAN_MOFCR23_OVIE SET 0 +CAN_MOFCR23_RMM SET 0 +CAN_MOFCR23_RXIE SET 0 +CAN_MOFCR23_SDT SET 0 +CAN_MOFCR23_STT SET 0 +CAN_MOFCR23_TXIE SET 0 + +; CAN Message Object 24 Function Control Register +CAN_MOFCR24_0 SET 0 +CAN_MOFCR24_0 SET 0 +CAN_MOFCR24_0 SET 0 +CAN_MOFCR24_0 SET 0 +CAN_MOFCR24_DATC SET 0 +CAN_MOFCR24_DLC SET 0 +CAN_MOFCR24_DLCC SET 0 +CAN_MOFCR24_FRREN SET 0 +CAN_MOFCR24_GDFS SET 0 +CAN_MOFCR24_IDC SET 0 +CAN_MOFCR24_MMC SET 0 +CAN_MOFCR24_OVIE SET 0 +CAN_MOFCR24_RMM SET 0 +CAN_MOFCR24_RXIE SET 0 +CAN_MOFCR24_SDT SET 0 +CAN_MOFCR24_STT SET 0 +CAN_MOFCR24_TXIE SET 0 + +; CAN Message Object 25 Function Control Register +CAN_MOFCR25_0 SET 0 +CAN_MOFCR25_0 SET 0 +CAN_MOFCR25_0 SET 0 +CAN_MOFCR25_0 SET 0 +CAN_MOFCR25_DATC SET 0 +CAN_MOFCR25_DLC SET 0 +CAN_MOFCR25_DLCC SET 0 +CAN_MOFCR25_FRREN SET 0 +CAN_MOFCR25_GDFS SET 0 +CAN_MOFCR25_IDC SET 0 +CAN_MOFCR25_MMC SET 0 +CAN_MOFCR25_OVIE SET 0 +CAN_MOFCR25_RMM SET 0 +CAN_MOFCR25_RXIE SET 0 +CAN_MOFCR25_SDT SET 0 +CAN_MOFCR25_STT SET 0 +CAN_MOFCR25_TXIE SET 0 + +; CAN Message Object 26 Function Control Register +CAN_MOFCR26_0 SET 0 +CAN_MOFCR26_0 SET 0 +CAN_MOFCR26_0 SET 0 +CAN_MOFCR26_0 SET 0 +CAN_MOFCR26_DATC SET 0 +CAN_MOFCR26_DLC SET 0 +CAN_MOFCR26_DLCC SET 0 +CAN_MOFCR26_FRREN SET 0 +CAN_MOFCR26_GDFS SET 0 +CAN_MOFCR26_IDC SET 0 +CAN_MOFCR26_MMC SET 0 +CAN_MOFCR26_OVIE SET 0 +CAN_MOFCR26_RMM SET 0 +CAN_MOFCR26_RXIE SET 0 +CAN_MOFCR26_SDT SET 0 +CAN_MOFCR26_STT SET 0 +CAN_MOFCR26_TXIE SET 0 + +; CAN Message Object 27 Function Control Register +CAN_MOFCR27_0 SET 0 +CAN_MOFCR27_0 SET 0 +CAN_MOFCR27_0 SET 0 +CAN_MOFCR27_0 SET 0 +CAN_MOFCR27_DATC SET 0 +CAN_MOFCR27_DLC SET 0 +CAN_MOFCR27_DLCC SET 0 +CAN_MOFCR27_FRREN SET 0 +CAN_MOFCR27_GDFS SET 0 +CAN_MOFCR27_IDC SET 0 +CAN_MOFCR27_MMC SET 0 +CAN_MOFCR27_OVIE SET 0 +CAN_MOFCR27_RMM SET 0 +CAN_MOFCR27_RXIE SET 0 +CAN_MOFCR27_SDT SET 0 +CAN_MOFCR27_STT SET 0 +CAN_MOFCR27_TXIE SET 0 + +; CAN Message Object 28 Function Control Register +CAN_MOFCR28_0 SET 0 +CAN_MOFCR28_0 SET 0 +CAN_MOFCR28_0 SET 0 +CAN_MOFCR28_0 SET 0 +CAN_MOFCR28_DATC SET 0 +CAN_MOFCR28_DLC SET 0 +CAN_MOFCR28_DLCC SET 0 +CAN_MOFCR28_FRREN SET 0 +CAN_MOFCR28_GDFS SET 0 +CAN_MOFCR28_IDC SET 0 +CAN_MOFCR28_MMC SET 0 +CAN_MOFCR28_OVIE SET 0 +CAN_MOFCR28_RMM SET 0 +CAN_MOFCR28_RXIE SET 0 +CAN_MOFCR28_SDT SET 0 +CAN_MOFCR28_STT SET 0 +CAN_MOFCR28_TXIE SET 0 + +; CAN Message Object 29 Function Control Register +CAN_MOFCR29_0 SET 0 +CAN_MOFCR29_0 SET 0 +CAN_MOFCR29_0 SET 0 +CAN_MOFCR29_0 SET 0 +CAN_MOFCR29_DATC SET 0 +CAN_MOFCR29_DLC SET 0 +CAN_MOFCR29_DLCC SET 0 +CAN_MOFCR29_FRREN SET 0 +CAN_MOFCR29_GDFS SET 0 +CAN_MOFCR29_IDC SET 0 +CAN_MOFCR29_MMC SET 0 +CAN_MOFCR29_OVIE SET 0 +CAN_MOFCR29_RMM SET 0 +CAN_MOFCR29_RXIE SET 0 +CAN_MOFCR29_SDT SET 0 +CAN_MOFCR29_STT SET 0 +CAN_MOFCR29_TXIE SET 0 + +; CAN Message Object 2 Function Control Register +CAN_MOFCR2_0 SET 0 +CAN_MOFCR2_0 SET 0 +CAN_MOFCR2_0 SET 0 +CAN_MOFCR2_0 SET 0 +CAN_MOFCR2_DATC SET 0 +CAN_MOFCR2_DLC SET 8 +CAN_MOFCR2_DLCC SET 0 +CAN_MOFCR2_FRREN SET 0 +CAN_MOFCR2_GDFS SET 0 +CAN_MOFCR2_IDC SET 0 +CAN_MOFCR2_MMC SET 0 +CAN_MOFCR2_OVIE SET 0 +CAN_MOFCR2_RMM SET 0 +CAN_MOFCR2_RXIE SET 0 +CAN_MOFCR2_SDT SET 0 +CAN_MOFCR2_STT SET 0 +CAN_MOFCR2_TXIE SET 0 + +; CAN Message Object 30 Function Control Register +CAN_MOFCR30_0 SET 0 +CAN_MOFCR30_0 SET 0 +CAN_MOFCR30_0 SET 0 +CAN_MOFCR30_0 SET 0 +CAN_MOFCR30_DATC SET 0 +CAN_MOFCR30_DLC SET 0 +CAN_MOFCR30_DLCC SET 0 +CAN_MOFCR30_FRREN SET 0 +CAN_MOFCR30_GDFS SET 0 +CAN_MOFCR30_IDC SET 0 +CAN_MOFCR30_MMC SET 0 +CAN_MOFCR30_OVIE SET 0 +CAN_MOFCR30_RMM SET 0 +CAN_MOFCR30_RXIE SET 0 +CAN_MOFCR30_SDT SET 0 +CAN_MOFCR30_STT SET 0 +CAN_MOFCR30_TXIE SET 0 + +; CAN Message Object 31 Function Control Register +CAN_MOFCR31_0 SET 0 +CAN_MOFCR31_0 SET 0 +CAN_MOFCR31_0 SET 0 +CAN_MOFCR31_0 SET 0 +CAN_MOFCR31_DATC SET 0 +CAN_MOFCR31_DLC SET 0 +CAN_MOFCR31_DLCC SET 0 +CAN_MOFCR31_FRREN SET 0 +CAN_MOFCR31_GDFS SET 0 +CAN_MOFCR31_IDC SET 0 +CAN_MOFCR31_MMC SET 0 +CAN_MOFCR31_OVIE SET 0 +CAN_MOFCR31_RMM SET 0 +CAN_MOFCR31_RXIE SET 0 +CAN_MOFCR31_SDT SET 0 +CAN_MOFCR31_STT SET 0 +CAN_MOFCR31_TXIE SET 0 + +; CAN Message Object 3 Function Control Register +CAN_MOFCR3_0 SET 0 +CAN_MOFCR3_0 SET 0 +CAN_MOFCR3_0 SET 0 +CAN_MOFCR3_0 SET 0 +CAN_MOFCR3_DATC SET 0 +CAN_MOFCR3_DLC SET 0 +CAN_MOFCR3_DLCC SET 0 +CAN_MOFCR3_FRREN SET 0 +CAN_MOFCR3_GDFS SET 0 +CAN_MOFCR3_IDC SET 0 +CAN_MOFCR3_MMC SET 0 +CAN_MOFCR3_OVIE SET 0 +CAN_MOFCR3_RMM SET 0 +CAN_MOFCR3_RXIE SET 0 +CAN_MOFCR3_SDT SET 0 +CAN_MOFCR3_STT SET 0 +CAN_MOFCR3_TXIE SET 0 + +; CAN Message Object 4 Function Control Register +CAN_MOFCR4_0 SET 0 +CAN_MOFCR4_0 SET 0 +CAN_MOFCR4_0 SET 0 +CAN_MOFCR4_0 SET 0 +CAN_MOFCR4_DATC SET 0 +CAN_MOFCR4_DLC SET 0 +CAN_MOFCR4_DLCC SET 0 +CAN_MOFCR4_FRREN SET 0 +CAN_MOFCR4_GDFS SET 0 +CAN_MOFCR4_IDC SET 0 +CAN_MOFCR4_MMC SET 0 +CAN_MOFCR4_OVIE SET 0 +CAN_MOFCR4_RMM SET 0 +CAN_MOFCR4_RXIE SET 0 +CAN_MOFCR4_SDT SET 0 +CAN_MOFCR4_STT SET 0 +CAN_MOFCR4_TXIE SET 0 + +; CAN Message Object 5 Function Control Register +CAN_MOFCR5_0 SET 0 +CAN_MOFCR5_0 SET 0 +CAN_MOFCR5_0 SET 0 +CAN_MOFCR5_0 SET 0 +CAN_MOFCR5_DATC SET 0 +CAN_MOFCR5_DLC SET 8 +CAN_MOFCR5_DLCC SET 0 +CAN_MOFCR5_FRREN SET 0 +CAN_MOFCR5_GDFS SET 0 +CAN_MOFCR5_IDC SET 0 +CAN_MOFCR5_MMC SET 0 +CAN_MOFCR5_OVIE SET 0 +CAN_MOFCR5_RMM SET 0 +CAN_MOFCR5_RXIE SET 0 +CAN_MOFCR5_SDT SET 0 +CAN_MOFCR5_STT SET 0 +CAN_MOFCR5_TXIE SET 0 + +; CAN Message Object 6 Function Control Register +CAN_MOFCR6_0 SET 0 +CAN_MOFCR6_0 SET 0 +CAN_MOFCR6_0 SET 0 +CAN_MOFCR6_0 SET 0 +CAN_MOFCR6_DATC SET 0 +CAN_MOFCR6_DLC SET 8 +CAN_MOFCR6_DLCC SET 0 +CAN_MOFCR6_FRREN SET 0 +CAN_MOFCR6_GDFS SET 0 +CAN_MOFCR6_IDC SET 0 +CAN_MOFCR6_MMC SET 0 +CAN_MOFCR6_OVIE SET 0 +CAN_MOFCR6_RMM SET 0 +CAN_MOFCR6_RXIE SET 0 +CAN_MOFCR6_SDT SET 0 +CAN_MOFCR6_STT SET 0 +CAN_MOFCR6_TXIE SET 0 + +; CAN Message Object 7 Function Control Register +CAN_MOFCR7_0 SET 0 +CAN_MOFCR7_0 SET 0 +CAN_MOFCR7_0 SET 0 +CAN_MOFCR7_0 SET 0 +CAN_MOFCR7_DATC SET 0 +CAN_MOFCR7_DLC SET 8 +CAN_MOFCR7_DLCC SET 0 +CAN_MOFCR7_FRREN SET 0 +CAN_MOFCR7_GDFS SET 0 +CAN_MOFCR7_IDC SET 0 +CAN_MOFCR7_MMC SET 0 +CAN_MOFCR7_OVIE SET 0 +CAN_MOFCR7_RMM SET 0 +CAN_MOFCR7_RXIE SET 0 +CAN_MOFCR7_SDT SET 0 +CAN_MOFCR7_STT SET 0 +CAN_MOFCR7_TXIE SET 0 + +; CAN Message Object 8 Function Control Register +CAN_MOFCR8_0 SET 0 +CAN_MOFCR8_0 SET 0 +CAN_MOFCR8_0 SET 0 +CAN_MOFCR8_0 SET 0 +CAN_MOFCR8_DATC SET 0 +CAN_MOFCR8_DLC SET 8 +CAN_MOFCR8_DLCC SET 0 +CAN_MOFCR8_FRREN SET 0 +CAN_MOFCR8_GDFS SET 0 +CAN_MOFCR8_IDC SET 0 +CAN_MOFCR8_MMC SET 0 +CAN_MOFCR8_OVIE SET 0 +CAN_MOFCR8_RMM SET 0 +CAN_MOFCR8_RXIE SET 0 +CAN_MOFCR8_SDT SET 0 +CAN_MOFCR8_STT SET 0 +CAN_MOFCR8_TXIE SET 0 + +; CAN Message Object 9 Function Control Register +CAN_MOFCR9_0 SET 0 +CAN_MOFCR9_0 SET 0 +CAN_MOFCR9_0 SET 0 +CAN_MOFCR9_0 SET 0 +CAN_MOFCR9_DATC SET 0 +CAN_MOFCR9_DLC SET 8 +CAN_MOFCR9_DLCC SET 0 +CAN_MOFCR9_FRREN SET 0 +CAN_MOFCR9_GDFS SET 0 +CAN_MOFCR9_IDC SET 0 +CAN_MOFCR9_MMC SET 0 +CAN_MOFCR9_OVIE SET 0 +CAN_MOFCR9_RMM SET 0 +CAN_MOFCR9_RXIE SET 0 +CAN_MOFCR9_SDT SET 0 +CAN_MOFCR9_STT SET 0 +CAN_MOFCR9_TXIE SET 0 + +; CAN Message Object 0 FIFO/Gateway Pointer Register +CAN_MOFGPR0_BOT SET 255 +CAN_MOFGPR0_CUR SET 255 +CAN_MOFGPR0_SEL SET 255 +CAN_MOFGPR0_TOP SET 255 + +; CAN Message Object 10 FIFO/Gateway Pointer Register +CAN_MOFGPR10_BOT SET 255 +CAN_MOFGPR10_CUR SET 255 +CAN_MOFGPR10_SEL SET 255 +CAN_MOFGPR10_TOP SET 255 + +; CAN Message Object 11 FIFO/Gateway Pointer Register +CAN_MOFGPR11_BOT SET 255 +CAN_MOFGPR11_CUR SET 255 +CAN_MOFGPR11_SEL SET 255 +CAN_MOFGPR11_TOP SET 255 + +; CAN Message Object 12 FIFO/Gateway Pointer Register +CAN_MOFGPR12_BOT SET 255 +CAN_MOFGPR12_CUR SET 255 +CAN_MOFGPR12_SEL SET 255 +CAN_MOFGPR12_TOP SET 255 + +; CAN Message Object 13 FIFO/Gateway Pointer Register +CAN_MOFGPR13_BOT SET 255 +CAN_MOFGPR13_CUR SET 255 +CAN_MOFGPR13_SEL SET 255 +CAN_MOFGPR13_TOP SET 255 + +; CAN Message Object 14 FIFO/Gateway Pointer Register +CAN_MOFGPR14_BOT SET 255 +CAN_MOFGPR14_CUR SET 255 +CAN_MOFGPR14_SEL SET 255 +CAN_MOFGPR14_TOP SET 255 + +; CAN Message Object 15 FIFO/Gateway Pointer Register +CAN_MOFGPR15_BOT SET 255 +CAN_MOFGPR15_CUR SET 255 +CAN_MOFGPR15_SEL SET 255 +CAN_MOFGPR15_TOP SET 255 + +; CAN Message Object 16 FIFO/Gateway Pointer Register +CAN_MOFGPR16_BOT SET 255 +CAN_MOFGPR16_CUR SET 255 +CAN_MOFGPR16_SEL SET 255 +CAN_MOFGPR16_TOP SET 255 + +; CAN Message Object 17 FIFO/Gateway Pointer Register +CAN_MOFGPR17_BOT SET 255 +CAN_MOFGPR17_CUR SET 255 +CAN_MOFGPR17_SEL SET 255 +CAN_MOFGPR17_TOP SET 255 + +; CAN Message Object 18 FIFO/Gateway Pointer Register +CAN_MOFGPR18_BOT SET 255 +CAN_MOFGPR18_CUR SET 255 +CAN_MOFGPR18_SEL SET 255 +CAN_MOFGPR18_TOP SET 255 + +; CAN Message Object 19 FIFO/Gateway Pointer Register +CAN_MOFGPR19_BOT SET 255 +CAN_MOFGPR19_CUR SET 255 +CAN_MOFGPR19_SEL SET 255 +CAN_MOFGPR19_TOP SET 255 + +; CAN Message Object 1 FIFO/Gateway Pointer Register +CAN_MOFGPR1_BOT SET 255 +CAN_MOFGPR1_CUR SET 255 +CAN_MOFGPR1_SEL SET 255 +CAN_MOFGPR1_TOP SET 255 + +; CAN Message Object 20 FIFO/Gateway Pointer Register +CAN_MOFGPR20_BOT SET 255 +CAN_MOFGPR20_CUR SET 255 +CAN_MOFGPR20_SEL SET 255 +CAN_MOFGPR20_TOP SET 255 + +; CAN Message Object 21 FIFO/Gateway Pointer Register +CAN_MOFGPR21_BOT SET 255 +CAN_MOFGPR21_CUR SET 255 +CAN_MOFGPR21_SEL SET 255 +CAN_MOFGPR21_TOP SET 255 + +; CAN Message Object 22 FIFO/Gateway Pointer Register +CAN_MOFGPR22_BOT SET 255 +CAN_MOFGPR22_CUR SET 255 +CAN_MOFGPR22_SEL SET 255 +CAN_MOFGPR22_TOP SET 255 + +; CAN Message Object 23 FIFO/Gateway Pointer Register +CAN_MOFGPR23_BOT SET 255 +CAN_MOFGPR23_CUR SET 255 +CAN_MOFGPR23_SEL SET 255 +CAN_MOFGPR23_TOP SET 255 + +; CAN Message Object 24 FIFO/Gateway Pointer Register +CAN_MOFGPR24_BOT SET 255 +CAN_MOFGPR24_CUR SET 255 +CAN_MOFGPR24_SEL SET 255 +CAN_MOFGPR24_TOP SET 255 + +; CAN Message Object 25 FIFO/Gateway Pointer Register +CAN_MOFGPR25_BOT SET 255 +CAN_MOFGPR25_CUR SET 255 +CAN_MOFGPR25_SEL SET 255 +CAN_MOFGPR25_TOP SET 255 + +; CAN Message Object 26 FIFO/Gateway Pointer Register +CAN_MOFGPR26_BOT SET 255 +CAN_MOFGPR26_CUR SET 255 +CAN_MOFGPR26_SEL SET 255 +CAN_MOFGPR26_TOP SET 255 + +; CAN Message Object 27 FIFO/Gateway Pointer Register +CAN_MOFGPR27_BOT SET 255 +CAN_MOFGPR27_CUR SET 255 +CAN_MOFGPR27_SEL SET 255 +CAN_MOFGPR27_TOP SET 255 + +; CAN Message Object 28 FIFO/Gateway Pointer Register +CAN_MOFGPR28_BOT SET 255 +CAN_MOFGPR28_CUR SET 255 +CAN_MOFGPR28_SEL SET 255 +CAN_MOFGPR28_TOP SET 255 + +; CAN Message Object 29 FIFO/Gateway Pointer Register +CAN_MOFGPR29_BOT SET 255 +CAN_MOFGPR29_CUR SET 255 +CAN_MOFGPR29_SEL SET 255 +CAN_MOFGPR29_TOP SET 255 + +; CAN Message Object 2 FIFO/Gateway Pointer Register +CAN_MOFGPR2_BOT SET 255 +CAN_MOFGPR2_CUR SET 255 +CAN_MOFGPR2_SEL SET 255 +CAN_MOFGPR2_TOP SET 255 + +; CAN Message Object 30 FIFO/Gateway Pointer Register +CAN_MOFGPR30_BOT SET 255 +CAN_MOFGPR30_CUR SET 255 +CAN_MOFGPR30_SEL SET 255 +CAN_MOFGPR30_TOP SET 255 + +; CAN Message Object 31 FIFO/Gateway Pointer Register +CAN_MOFGPR31_BOT SET 255 +CAN_MOFGPR31_CUR SET 255 +CAN_MOFGPR31_SEL SET 255 +CAN_MOFGPR31_TOP SET 255 + +; CAN Message Object 3 FIFO/Gateway Pointer Register +CAN_MOFGPR3_BOT SET 255 +CAN_MOFGPR3_CUR SET 255 +CAN_MOFGPR3_SEL SET 255 +CAN_MOFGPR3_TOP SET 255 + +; CAN Message Object 4 FIFO/Gateway Pointer Register +CAN_MOFGPR4_BOT SET 255 +CAN_MOFGPR4_CUR SET 255 +CAN_MOFGPR4_SEL SET 255 +CAN_MOFGPR4_TOP SET 255 + +; CAN Message Object 5 FIFO/Gateway Pointer Register +CAN_MOFGPR5_BOT SET 255 +CAN_MOFGPR5_CUR SET 255 +CAN_MOFGPR5_SEL SET 255 +CAN_MOFGPR5_TOP SET 255 + +; CAN Message Object 6 FIFO/Gateway Pointer Register +CAN_MOFGPR6_BOT SET 255 +CAN_MOFGPR6_CUR SET 255 +CAN_MOFGPR6_SEL SET 255 +CAN_MOFGPR6_TOP SET 255 + +; CAN Message Object 7 FIFO/Gateway Pointer Register +CAN_MOFGPR7_BOT SET 255 +CAN_MOFGPR7_CUR SET 255 +CAN_MOFGPR7_SEL SET 255 +CAN_MOFGPR7_TOP SET 255 + +; CAN Message Object 8 FIFO/Gateway Pointer Register +CAN_MOFGPR8_BOT SET 255 +CAN_MOFGPR8_CUR SET 255 +CAN_MOFGPR8_SEL SET 255 +CAN_MOFGPR8_TOP SET 255 + +; CAN Message Object 9 FIFO/Gateway Pointer Register +CAN_MOFGPR9_BOT SET 255 +CAN_MOFGPR9_CUR SET 255 +CAN_MOFGPR9_SEL SET 255 +CAN_MOFGPR9_TOP SET 255 + +; CAN Message Object 0 Interrupt Pointer Register +CAN_MOIPR0_CFCVAL SET 0 +CAN_MOIPR0_MPN SET 0 +CAN_MOIPR0_RXINP SET 0 +CAN_MOIPR0_TXINP SET 0 + +; CAN Message Object 10 Interrupt Pointer Register +CAN_MOIPR10_CFCVAL SET 0 +CAN_MOIPR10_MPN SET 10 +CAN_MOIPR10_RXINP SET 0 +CAN_MOIPR10_TXINP SET 0 + +; CAN Message Object 11 Interrupt Pointer Register +CAN_MOIPR11_CFCVAL SET 0 +CAN_MOIPR11_MPN SET 11 +CAN_MOIPR11_RXINP SET 0 +CAN_MOIPR11_TXINP SET 0 + +; CAN Message Object 12 Interrupt Pointer Register +CAN_MOIPR12_CFCVAL SET 0 +CAN_MOIPR12_MPN SET 12 +CAN_MOIPR12_RXINP SET 0 +CAN_MOIPR12_TXINP SET 0 + +; CAN Message Object 13 Interrupt Pointer Register +CAN_MOIPR13_CFCVAL SET 0 +CAN_MOIPR13_MPN SET 13 +CAN_MOIPR13_RXINP SET 0 +CAN_MOIPR13_TXINP SET 0 + +; CAN Message Object 14 Interrupt Pointer Register +CAN_MOIPR14_CFCVAL SET 0 +CAN_MOIPR14_MPN SET 14 +CAN_MOIPR14_RXINP SET 0 +CAN_MOIPR14_TXINP SET 0 + +; CAN Message Object 15 Interrupt Pointer Register +CAN_MOIPR15_CFCVAL SET 0 +CAN_MOIPR15_MPN SET 15 +CAN_MOIPR15_RXINP SET 0 +CAN_MOIPR15_TXINP SET 0 + +; CAN Message Object 16 Interrupt Pointer Register +CAN_MOIPR16_CFCVAL SET 0 +CAN_MOIPR16_MPN SET 16 +CAN_MOIPR16_RXINP SET 0 +CAN_MOIPR16_TXINP SET 0 + +; CAN Message Object 17 Interrupt Pointer Register +CAN_MOIPR17_CFCVAL SET 0 +CAN_MOIPR17_MPN SET 17 +CAN_MOIPR17_RXINP SET 0 +CAN_MOIPR17_TXINP SET 0 + +; CAN Message Object 18 Interrupt Pointer Register +CAN_MOIPR18_CFCVAL SET 0 +CAN_MOIPR18_MPN SET 18 +CAN_MOIPR18_RXINP SET 0 +CAN_MOIPR18_TXINP SET 0 + +; CAN Message Object 19 Interrupt Pointer Register +CAN_MOIPR19_CFCVAL SET 0 +CAN_MOIPR19_MPN SET 19 +CAN_MOIPR19_RXINP SET 0 +CAN_MOIPR19_TXINP SET 0 + +; CAN Message Object 1 Interrupt Pointer Register +CAN_MOIPR1_CFCVAL SET 0 +CAN_MOIPR1_MPN SET 1 +CAN_MOIPR1_RXINP SET 1 +CAN_MOIPR1_TXINP SET 0 + +; CAN Message Object 20 Interrupt Pointer Register +CAN_MOIPR20_CFCVAL SET 0 +CAN_MOIPR20_MPN SET 20 +CAN_MOIPR20_RXINP SET 0 +CAN_MOIPR20_TXINP SET 0 + +; CAN Message Object 21 Interrupt Pointer Register +CAN_MOIPR21_CFCVAL SET 0 +CAN_MOIPR21_MPN SET 21 +CAN_MOIPR21_RXINP SET 0 +CAN_MOIPR21_TXINP SET 0 + +; CAN Message Object 22 Interrupt Pointer Register +CAN_MOIPR22_CFCVAL SET 0 +CAN_MOIPR22_MPN SET 22 +CAN_MOIPR22_RXINP SET 0 +CAN_MOIPR22_TXINP SET 0 + +; CAN Message Object 23 Interrupt Pointer Register +CAN_MOIPR23_CFCVAL SET 0 +CAN_MOIPR23_MPN SET 23 +CAN_MOIPR23_RXINP SET 0 +CAN_MOIPR23_TXINP SET 0 + +; CAN Message Object 24 Interrupt Pointer Register +CAN_MOIPR24_CFCVAL SET 0 +CAN_MOIPR24_MPN SET 24 +CAN_MOIPR24_RXINP SET 0 +CAN_MOIPR24_TXINP SET 0 + +; CAN Message Object 25 Interrupt Pointer Register +CAN_MOIPR25_CFCVAL SET 0 +CAN_MOIPR25_MPN SET 25 +CAN_MOIPR25_RXINP SET 0 +CAN_MOIPR25_TXINP SET 0 + +; CAN Message Object 26 Interrupt Pointer Register +CAN_MOIPR26_CFCVAL SET 0 +CAN_MOIPR26_MPN SET 26 +CAN_MOIPR26_RXINP SET 0 +CAN_MOIPR26_TXINP SET 0 + +; CAN Message Object 27 Interrupt Pointer Register +CAN_MOIPR27_CFCVAL SET 0 +CAN_MOIPR27_MPN SET 27 +CAN_MOIPR27_RXINP SET 0 +CAN_MOIPR27_TXINP SET 0 + +; CAN Message Object 28 Interrupt Pointer Register +CAN_MOIPR28_CFCVAL SET 0 +CAN_MOIPR28_MPN SET 28 +CAN_MOIPR28_RXINP SET 0 +CAN_MOIPR28_TXINP SET 0 + +; CAN Message Object 29 Interrupt Pointer Register +CAN_MOIPR29_CFCVAL SET 0 +CAN_MOIPR29_MPN SET 29 +CAN_MOIPR29_RXINP SET 0 +CAN_MOIPR29_TXINP SET 0 + +; CAN Message Object 2 Interrupt Pointer Register +CAN_MOIPR2_CFCVAL SET 0 +CAN_MOIPR2_MPN SET 2 +CAN_MOIPR2_RXINP SET 0 +CAN_MOIPR2_TXINP SET 0 + +; CAN Message Object 30 Interrupt Pointer Register +CAN_MOIPR30_CFCVAL SET 0 +CAN_MOIPR30_MPN SET 30 +CAN_MOIPR30_RXINP SET 0 +CAN_MOIPR30_TXINP SET 0 + +; CAN Message Object 31 Interrupt Pointer Register +CAN_MOIPR31_CFCVAL SET 0 +CAN_MOIPR31_MPN SET 31 +CAN_MOIPR31_RXINP SET 0 +CAN_MOIPR31_TXINP SET 0 + +; CAN Message Object 3 Interrupt Pointer Register +CAN_MOIPR3_CFCVAL SET 0 +CAN_MOIPR3_MPN SET 3 +CAN_MOIPR3_RXINP SET 0 +CAN_MOIPR3_TXINP SET 0 + +; CAN Message Object 4 Interrupt Pointer Register +CAN_MOIPR4_CFCVAL SET 0 +CAN_MOIPR4_MPN SET 4 +CAN_MOIPR4_RXINP SET 0 +CAN_MOIPR4_TXINP SET 0 + +; CAN Message Object 5 Interrupt Pointer Register +CAN_MOIPR5_CFCVAL SET 0 +CAN_MOIPR5_MPN SET 5 +CAN_MOIPR5_RXINP SET 0 +CAN_MOIPR5_TXINP SET 0 + +; CAN Message Object 6 Interrupt Pointer Register +CAN_MOIPR6_CFCVAL SET 0 +CAN_MOIPR6_MPN SET 6 +CAN_MOIPR6_RXINP SET 0 +CAN_MOIPR6_TXINP SET 0 + +; CAN Message Object 7 Interrupt Pointer Register +CAN_MOIPR7_CFCVAL SET 0 +CAN_MOIPR7_MPN SET 7 +CAN_MOIPR7_RXINP SET 0 +CAN_MOIPR7_TXINP SET 0 + +; CAN Message Object 8 Interrupt Pointer Register +CAN_MOIPR8_CFCVAL SET 0 +CAN_MOIPR8_MPN SET 8 +CAN_MOIPR8_RXINP SET 0 +CAN_MOIPR8_TXINP SET 0 + +; CAN Message Object 9 Interrupt Pointer Register +CAN_MOIPR9_CFCVAL SET 0 +CAN_MOIPR9_MPN SET 9 +CAN_MOIPR9_RXINP SET 0 +CAN_MOIPR9_TXINP SET 0 + +; Message Index Register 0 +CAN_MSID0_INDEX SET 0 + +; Message Index Register 1 +CAN_MSID1_INDEX SET 0 + +; Message Index Mask Register +CAN_MSIMASK_IM SET 0 + +; Message Pending Register 0 +CAN_MSPND0_PND SET 0 + +; Message Pending Register 1 +CAN_MSPND1_PND SET 0 + +; Node 0 Bit Timing Register +CAN_NBTR0_0 SET 0 +CAN_NBTR0_BRP SET 47 +CAN_NBTR0_DIV8 SET 0 +CAN_NBTR0_SJW SET 1 +CAN_NBTR0_TSEG1 SET 4 +CAN_NBTR0_TSEG2 SET 3 + +; Node 1 Bit Timing Register +CAN_NBTR1_0 SET 0 +CAN_NBTR1_BRP SET 31 +CAN_NBTR1_DIV8 SET 0 +CAN_NBTR1_SJW SET 1 +CAN_NBTR1_TSEG1 SET 8 +CAN_NBTR1_TSEG2 SET 1 + +; Node 0 Control Register +CAN_NCR0_0 SET 0 +CAN_NCR0_ALIE SET 0 +CAN_NCR0_CALM SET 0 +CAN_NCR0_CANDIS SET 0 +CAN_NCR0_CCE SET 0 +CAN_NCR0_INIT SET 0 +CAN_NCR0_LECIE SET 0 +CAN_NCR0_TRIE SET 0 + +; Node 1 Control Register +CAN_NCR1_0 SET 0 +CAN_NCR1_0 SET 0 +CAN_NCR1_ALIE SET 0 +CAN_NCR1_CALM SET 0 +CAN_NCR1_CANDIS SET 0 +CAN_NCR1_CCE SET 0 +CAN_NCR1_INIT SET 1 +CAN_NCR1_LECIE SET 0 +CAN_NCR1_TRIE SET 0 + +; Node 0 Error Counter Register +CAN_NECNT0_0 SET 0 +CAN_NECNT0_EWRNLVL SET 96 +CAN_NECNT0_LEINC SET 0 +CAN_NECNT0_LETD SET 0 +CAN_NECNT0_REC SET 0 +CAN_NECNT0_TEC SET 0 + +; Node 1 Error Counter Register +CAN_NECNT1_0 SET 0 +CAN_NECNT1_EWRNLVL SET 96 +CAN_NECNT1_LEINC SET 0 +CAN_NECNT1_LETD SET 0 +CAN_NECNT1_REC SET 0 +CAN_NECNT1_TEC SET 0 + +; Node 0 Frame Counter Register +CAN_NFCR0_0 SET 0 +CAN_NFCR0_0 SET 0 +CAN_NFCR0_CFC SET 0 +CAN_NFCR0_CFCIE SET 0 +CAN_NFCR0_CFCOV SET 0 +CAN_NFCR0_CFMOD SET 0 +CAN_NFCR0_CFSEL SET 0 + +; Node 1 Frame Counter Register +CAN_NFCR1_0 SET 0 +CAN_NFCR1_0 SET 0 +CAN_NFCR1_CFC SET 0 +CAN_NFCR1_CFCIE SET 0 +CAN_NFCR1_CFCOV SET 0 +CAN_NFCR1_CFMOD SET 0 +CAN_NFCR1_CFSEL SET 0 + +; Node 0 Interrupt Pointer Register +CAN_NIPR0_0 SET 0 +CAN_NIPR0_ALINP SET 0 +CAN_NIPR0_CFCINP SET 0 +CAN_NIPR0_LECINP SET 0 +CAN_NIPR0_TRINP SET 0 + +; Node 1 Interrupt Pointer Register +CAN_NIPR1_0 SET 0 +CAN_NIPR1_ALINP SET 0 +CAN_NIPR1_CFCINP SET 0 +CAN_NIPR1_LECINP SET 0 +CAN_NIPR1_TRINP SET 0 + +; Node 0 Port Control Register +CAN_NPCR0_0 SET 0 +CAN_NPCR0_0 SET 0 +CAN_NPCR0_LBM SET 0 +CAN_NPCR0_RXSEL SET 0 + +; Node 1 Port Control Register +CAN_NPCR1_0 SET 0 +CAN_NPCR1_0 SET 0 +CAN_NPCR1_LBM SET 0 +CAN_NPCR1_RXSEL SET 0 + +; Node 0 Status Register +CAN_NSR0_0 SET 0 +CAN_NSR0_ALERT SET 0 +CAN_NSR0_BOFF SET 0 +CAN_NSR0_EWRN SET 0 +CAN_NSR0_LEC SET 0 +CAN_NSR0_LLE SET 0 +CAN_NSR0_LOE SET 0 +CAN_NSR0_RXOK SET 0 +CAN_NSR0_TXOK SET 0 + +; Node 1 Status Register +CAN_NSR1_0 SET 0 +CAN_NSR1_ALERT SET 0 +CAN_NSR1_BOFF SET 0 +CAN_NSR1_EWRN SET 0 +CAN_NSR1_LEC SET 0 +CAN_NSR1_LLE SET 0 +CAN_NSR1_LOE SET 0 +CAN_NSR1_RXOK SET 0 +CAN_NSR1_TXOK SET 0 + +; Panel Control Register +CAN_PANCTR_0 SET 0 +CAN_PANCTR_BUSY SET 0 +CAN_PANCTR_PANAR1 SET 0 +CAN_PANCTR_PANAR2 SET 0 +CAN_PANCTR_PANCMD SET 0 +CAN_PANCTR_RBUSY SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC60 High +CCU6_CC60RH_CC60VH SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC60 Low +CCU6_CC60RL_CC60VL SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC60 High +CCU6_CC60SRH_CC60SH SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC60 Low +CCU6_CC60SRL_CC60SL SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC61 High +CCU6_CC61RH_CC61VH SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC61 Low +CCU6_CC61RL_CC61VL SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC61 High +CCU6_CC61SRH_CC61SH SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC61 Low +CCU6_CC61SRL_CC61SL SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC62 High +CCU6_CC62RH_CC62VH SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC62 Low +CCU6_CC62RL_CC62VL SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC62 High +CCU6_CC62SRH_CC62SH SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC62 Low +CCU6_CC62SRL_CC62SL SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC63 High +CCU6_CC63RH_CC63VH SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC63 Low +CCU6_CC63RL_CC63VL SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC63 High +CCU6_CC63SRH_CC63SH SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC63 Low +CCU6_CC63SRL_CC63SL SET 0 + +; RMAP=0 PAGE=0-CCU6 Compare State Modification Register High +CCU6_CMPMODIFH_MCC60R SET 0 +CCU6_CMPMODIFH_MCC61R SET 0 +CCU6_CMPMODIFH_MCC62R SET 0 +CCU6_CMPMODIFH_MCC63R SET 0 + +; RMAP=0 PAGE=0-CCU6 Compare State Modification Register Low +CCU6_CMPMODIFL_MCC60S SET 0 +CCU6_CMPMODIFL_MCC61S SET 0 +CCU6_CMPMODIFL_MCC62S SET 0 +CCU6_CMPMODIFL_MCC63S SET 0 + +; RMAP=0 PAGE=3-CCU6 Compare State Register High +CCU6_CMPSTATH_CC60PS SET 0 +CCU6_CMPSTATH_CC61PS SET 0 +CCU6_CMPSTATH_CC62PS SET 0 +CCU6_CMPSTATH_COUT60PS SET 0 +CCU6_CMPSTATH_COUT61PS SET 0 +CCU6_CMPSTATH_COUT62PS SET 0 +CCU6_CMPSTATH_COUT63PS SET 0 +CCU6_CMPSTATH_T13IM SET 0 + +; RMAP=0 PAGE=3-CCU6 Compare State Register Low +CCU6_CMPSTATL_CC60ST SET 0 +CCU6_CMPSTATL_CC61ST SET 0 +CCU6_CMPSTATL_CC62ST SET 0 +CCU6_CMPSTATL_CC63ST SET 0 +CCU6_CMPSTATL_CCPOS0 SET 0 +CCU6_CMPSTATL_CCPOS1 SET 0 +CCU6_CMPSTATL_CCPOS2 SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Enable Register High +CCU6_IENH_ENCHE SET 0 +CCU6_IENH_ENIDLE SET 0 +CCU6_IENH_ENSTR SET 0 +CCU6_IENH_ENT13CM SET 0 +CCU6_IENH_ENT13PM SET 0 +CCU6_IENH_ENTRPF SET 0 +CCU6_IENH_ENWHE SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Enable Register Low +CCU6_IENL_ENCC60F SET 0 +CCU6_IENL_ENCC60R SET 0 +CCU6_IENL_ENCC61F SET 0 +CCU6_IENL_ENCC61R SET 0 +CCU6_IENL_ENCC62F SET 0 +CCU6_IENL_ENCC62R SET 0 +CCU6_IENL_ENT12OM SET 0 +CCU6_IENL_ENT12PM SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Node Pointer Register High +CCU6_INPH_INPERR SET 0 +CCU6_INPH_INPT12 SET 0 +CCU6_INPH_INPT13 SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Node Pointer Register Low +CCU6_INPL_INPCC60 SET 0 +CCU6_INPL_INPCC61 SET 0 +CCU6_INPL_INPCC62 SET 0 +CCU6_INPL_INPCHE SET 0 + +; RMAP=0 PAGE=3-CCU6 Capture/Compare Interrupt Status Register High +CCU6_ISH_CHE SET 0 +CCU6_ISH_IDLE SET 0 +CCU6_ISH_STR SET 0 +CCU6_ISH_T13CM SET 0 +CCU6_ISH_T13PM SET 0 +CCU6_ISH_TRPF SET 0 +CCU6_ISH_TRPS SET 0 +CCU6_ISH_WHE SET 0 + +; RMAP=0 PAGE=3-CCU6 Capture/Compare Interrupt Status Register Low +CCU6_ISL_ICC60F SET 0 +CCU6_ISL_ICC60R SET 0 +CCU6_ISL_ICC61F SET 0 +CCU6_ISL_ICC61R SET 0 +CCU6_ISL_ICC62F SET 0 +CCU6_ISL_ICC62R SET 0 +CCU6_ISL_T12OM SET 0 +CCU6_ISL_T12PM SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Interrupt Status Reset Register High +CCU6_ISRH_RCHE SET 0 +CCU6_ISRH_RIDLE SET 0 +CCU6_ISRH_RSTR SET 0 +CCU6_ISRH_RT13CM SET 0 +CCU6_ISRH_RT13PM SET 0 +CCU6_ISRH_RTRPF SET 0 +CCU6_ISRH_RWHE SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Interrupt Status Reset Register Low +CCU6_ISRL_RCC60F SET 0 +CCU6_ISRL_RCC60R SET 0 +CCU6_ISRL_RCC61F SET 0 +CCU6_ISRL_RCC61R SET 0 +CCU6_ISRL_RCC62F SET 0 +CCU6_ISRL_RCC62R SET 0 +CCU6_ISRL_RT12OM SET 0 +CCU6_ISRL_RT12PM SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Status Set Register High +CCU6_ISSH_SCHE SET 0 +CCU6_ISSH_SIDLE SET 0 +CCU6_ISSH_SSTR SET 0 +CCU6_ISSH_ST13CM SET 0 +CCU6_ISSH_ST13PM SET 0 +CCU6_ISSH_STRPF SET 0 +CCU6_ISSH_SWHC SET 0 +CCU6_ISSH_SWHE SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Status Set Register Low +CCU6_ISSL_SCC60F SET 0 +CCU6_ISSL_SCC60R SET 0 +CCU6_ISSL_SCC61F SET 0 +CCU6_ISSL_SCC61R SET 0 +CCU6_ISSL_SCC62F SET 0 +CCU6_ISSL_SCC62R SET 0 +CCU6_ISSL_ST12OM SET 0 +CCU6_ISSL_ST12PM SET 0 + +; RMAP=0 PAGE=2-CCU6 Multi-Channel Mode Control Register +CCU6_MCMCTR_SWSEL SET 0 +CCU6_MCMCTR_SWSYN SET 0 + +; RMAP=0 PAGE=3-CCU6 Multi-Channel Mode Output Register High +CCU6_MCMOUTH_CURH SET 0 +CCU6_MCMOUTH_EXPH SET 0 + +; RMAP=0 PAGE=3-CCU6 Multi-Channel Mode Output Register Low +CCU6_MCMOUTL_MCMP SET 0 +CCU6_MCMOUTL_R SET 0 + +; RMAP=0 PAGE=0-CCU6 Multi-Channel Mode Output Shadow Register High +CCU6_MCMOUTSH_CURHS SET 0 +CCU6_MCMOUTSH_EXPHS SET 0 +CCU6_MCMOUTSH_STRHP SET 0 + +; RMAP=0 PAGE=0-CCU6 Multi-Channel Mode Output Shadow Register Low +CCU6_MCMOUTSL_MCMPS SET 0 +CCU6_MCMOUTSL_STRMCM SET 0 + +; RMAP=0 PAGE=2-CCU6 Modulation Control Register High +CCU6_MODCTRH_ECT13O SET 0 +CCU6_MODCTRH_T13MODEN SET 0 + +; RMAP=0 PAGE=2-CCU6 Modulation Control Register Low +CCU6_MODCTRL_MCMEN SET 0 +CCU6_MODCTRL_T12MODEN SET 0 + +; RMAP=0 -CCU6 Page Register +CCU6_PAGE_OP SET 0 +CCU6_PAGE_PAGE SET 0 +CCU6_PAGE_STNR SET 0 + +; RMAP=0 PAGE=3-CCU6 Port Input Select 0 Register High +CCU6_PISEL0H_ISPOS0 SET 0 +CCU6_PISEL0H_ISPOS1 SET 0 +CCU6_PISEL0H_ISPOS2 SET 0 +CCU6_PISEL0H_IST12HR SET 0 + +; RMAP=0 PAGE=3-CCU6 Port Input Select 0 Register Low +CCU6_PISEL0L_ISCC60 SET 0 +CCU6_PISEL0L_ISCC61 SET 0 +CCU6_PISEL0L_ISCC62 SET 0 +CCU6_PISEL0L_ISTRP SET 0 + +; RMAP=0 PAGE=3-CCU6 Port Input Select 2 Register +CCU6_PISEL2_IST13HR SET 0 + +; RMAP=0 PAGE=2-CCU6 Passive State Level Register +CCU6_PSLR_PSL SET 0 +CCU6_PSLR_PSL63 SET 0 + +; RMAP=0 PAGE=1-CCU6 Dead-Time Control Register for Timer T12 High +CCU6_T12DTCH_DTE0 SET 0 +CCU6_T12DTCH_DTE1 SET 0 +CCU6_T12DTCH_DTE2 SET 0 +CCU6_T12DTCH_DTR0 SET 0 +CCU6_T12DTCH_DTR1 SET 0 +CCU6_T12DTCH_DTR2 SET 0 + +; RMAP=0 PAGE=1-CCU6 Dead-Time Control Register for Timer T12 Low +CCU6_T12DTCL_DTM SET 1 + +; RMAP=0 PAGE=3-CCU6 Timer T12 Counter Register High +CCU6_T12H_T12CVH SET 0 + +; RMAP=0 PAGE=3-CCU6 Timer T12 Counter Register Low +CCU6_T12L_T12CVL SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Mode Select Register High +CCU6_T12MSELH_DBYP SET 0 +CCU6_T12MSELH_HSYNC SET 0 +CCU6_T12MSELH_MSEL62 SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Mode Select Register Low +CCU6_T12MSELL_MSEL60 SET 0 +CCU6_T12MSELL_MSEL61 SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer T12 Period Register High +CCU6_T12PRH_T12PVH SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer T12 Period Register Low +CCU6_T12PRL_T12PVL SET 1 + +; RMAP=0 PAGE=3-CCU6 Timer T13 Counter Register High +CCU6_T13H_T13CVH SET 0 + +; RMAP=0 PAGE=3-CCU6 Timer T13 Counter Register Low +CCU6_T13L_T13CVL SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer T13 Period Register High +CCU6_T13PRH_T13PVH SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer T13 Period Register Low +CCU6_T13PRL_T13PVL SET 1 + +; RMAP=0 PAGE=1-CCU6 Timer Control 0 Register High +CCU6_TCTR0H_STE13 SET 0 +CCU6_TCTR0H_T13CLK SET 0 +CCU6_TCTR0H_T13PRE SET 0 +CCU6_TCTR0H_T13R SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer Control 0 Register Low +CCU6_TCTR0L_CDIR SET 0 +CCU6_TCTR0L_CTM SET 0 +CCU6_TCTR0L_STE12 SET 0 +CCU6_TCTR0L_T12CLK SET 0 +CCU6_TCTR0L_T12PRE SET 0 +CCU6_TCTR0L_T12R SET 0 + +; RMAP=0 PAGE=2-CCU6 Timer Control 2 Register High +CCU6_TCTR2H_T12RSEL SET 0 +CCU6_TCTR2H_T13RSEL SET 0 + +; RMAP=0 PAGE=2-CCU6 Timer Control 2 Register Low +CCU6_TCTR2L_T12SSC SET 0 +CCU6_TCTR2L_T13SSC SET 0 +CCU6_TCTR2L_T13TEC SET 0 +CCU6_TCTR2L_T13TED SET 0 + +; RMAP=0 PAGE=0-CCU6 Timer Control 4 Register High +CCU6_TCTR4H_T13RES SET 0 +CCU6_TCTR4H_T13RR SET 0 +CCU6_TCTR4H_T13RS SET 0 +CCU6_TCTR4H_T13STD SET 0 +CCU6_TCTR4H_T13STR SET 0 + +; RMAP=0 PAGE=0-CCU6 Timer Control 4 Register Low +CCU6_TCTR4L_DTRES SET 0 +CCU6_TCTR4L_T12RES SET 0 +CCU6_TCTR4L_T12RR SET 0 +CCU6_TCTR4L_T12RS SET 0 +CCU6_TCTR4L_T12STD SET 0 +CCU6_TCTR4L_T12STR SET 0 + +; RMAP=0 PAGE=2-CCU6 Trap Control Register High +CCU6_TRPCTRH_TRPEN SET 0 +CCU6_TRPCTRH_TRPEN13 SET 0 +CCU6_TRPCTRH_TRPPEN SET 0 + +; RMAP=0 PAGE=2-CCU6 Trap Control Register Low +CCU6_TRPCTRL_TRPM0 SET 0 +CCU6_TRPCTRL_TRPM1 SET 0 +CCU6_TRPCTRL_TRPM2 SET 0 + +; RMAP=1 -CORDIC CORDIC Control Register +CD_CON_MODE SET 0 +CD_CON_MPS SET 0 +CD_CON_ROTVEC SET 0 +CD_CON_ST SET 0 +CD_CON_ST_MODE SET 0 +CD_CON_X_USIGN SET 0 + +; RMAP=1 -CORDIC CORDIC X Data High Byte +CD_CORDXH_DATAH SET 0 + +; RMAP=1 -CORDIC CORDIC X Data Low Byte +CD_CORDXL_DATAL SET 0 + +; RMAP=1 -CORDIC CORDIC Y Data High Byte +CD_CORDYH_DATAH SET 0 + +; RMAP=1 -CORDIC CORDIC Y Data Low Byte +CD_CORDYL_DATAL SET 0 + +; RMAP=1 -CORDIC CORDIC Z Data High Byte +CD_CORDZH_DATAH SET 0 + +; RMAP=1 -CORDIC CORDIC Z Data Low Byte +CD_CORDZL_DATAL SET 0 + +; RMAP=1 -CORDIC CORDIC Status and Data Control Register +CD_STATC_CD_BSY SET 0 +CD_STATC_DMAP SET 0 +CD_STATC_EOC SET 0 +CD_STATC_ERROR SET 0 +CD_STATC_INT_EN SET 0 +CD_STATC_KEEPX SET 0 +CD_STATC_KEEPY SET 0 +CD_STATC_KEEPZ SET 0 + +; RMAP=0 PAGE=1-SCU Clock Control Register +CMCON_CLKREL SET 0 +CMCON_FCCFG SET 1 +CMCON_KDIV SET 0 +CMCON_VCOSEL SET 0 + +; RMAP=0 PAGE=1-SCU Clock Output Control Register +COCON_COREL SET 0 +COCON_COUTS SET 0 +COCON_TLEN SET 0 + +; RMAP=x -CPU Data Pointer Register High +DPH_DPH0 SET 0 +DPH_DPH1 SET 0 +DPH_DPH2 SET 0 +DPH_DPH3 SET 0 +DPH_DPH4 SET 0 +DPH_DPH5 SET 0 +DPH_DPH6 SET 0 +DPH_DPH7 SET 0 + +; RMAP=x -CPU Data Pointer Register Low +DPL_DPL0 SET 0 +DPL_DPL1 SET 0 +DPL_DPL2 SET 0 +DPL_DPL3 SET 0 +DPL_DPL4 SET 0 +DPL_DPL5 SET 0 +DPL_DPL6 SET 0 +DPL_DPL7 SET 0 + +; RMAP=x -CPU Extended Operation Register +EO_DPSEL0 SET 0 +EO_TRAP_EN SET 0 + +; RMAP=0 PAGE=0-SCU External Interrupt Control Register 0 +EXICON0_EXINT0 SET 0 +EXICON0_EXINT1 SET 0 +EXICON0_EXINT2 SET 0 +EXICON0_EXINT3 SET 0 + +; RMAP=0 PAGE=0-SCU External Interrupt Control Register 1 +EXICON1_EXINT4 SET 0 +EXICON1_EXINT5 SET 0 +EXICON1_EXINT6 SET 0 + +; RMAP=0 PAGE=0-SCU Fractional Divider Control Register +FDCON_BGS SET 0 +FDCON_BRK SET 0 +FDCON_EOFSYN SET 0 +FDCON_ERRSYN SET 0 +FDCON_FDEN SET 0 +FDCON_FDM SET 0 +FDCON_NDOV SET 0 +FDCON_SYNEN SET 0 + +; RMAP=0 PAGE=0-SCU Fractional Divider Result Register +FDRES_RESULT SET 0 + +; RMAP=0 PAGE=0-SCU Fractional Divider Reload Register +FDSTEP_STEP SET 0 + +; RMAP=0 PAGE=1-SCU Flash Error Address Register High +FEAH_ECCERRADDR SET 0 + +; RMAP=0 PAGE=1-SCU Flash Error Address Register Low +FEAL_ECCERRADDR SET 0 + +; RMAP=1 -OCDS Hardware Breakpoints Data Register +HWBPDR_HWBPXX SET 0 + +; RMAP=1 -OCDS Hardware Breakpoints Select Register +HWBPSR_BPSEL SET 0 +HWBPSR_BPSEL_P SET 0 + +; RMAP=0 PAGE=1-SCU Identity Register +ID_PRODID SET 0 +ID_VERID SET 0 + +; RMAP=x -CPU Interrupt Enable Register 0 +IEN0_EA SET 1 +IEN0_ES SET 0 +IEN0_ET0 SET 0 +IEN0_ET1 SET 0 +IEN0_ET2 SET 1 +IEN0_EX0 SET 0 +IEN0_EX1 SET 0 + +; RMAP=x -CPU Module Interrupt Enable 1 Register +IEN1_EADC SET 0 +IEN1_ECCIP0 SET 0 +IEN1_ECCIP1 SET 0 +IEN1_ECCIP2 SET 0 +IEN1_ECCIP3 SET 0 +IEN1_ESSC SET 0 +IEN1_EX2 SET 0 +IEN1_EXM SET 0 + +; RMAP=x -CPU Interrupt Priority 1 Register +IP1_PADC SET 0 +IP1_PCCIP0 SET 0 +IP1_PCCIP1 SET 0 +IP1_PCCIP2 SET 0 +IP1_PCCIP3 SET 0 +IP1_PSSC SET 0 +IP1_PX2 SET 0 +IP1_PXM SET 0 + +; RMAP=x -CPU Interrupt Priority 1 High Register +IPH1_PADCH SET 0 +IPH1_PCCIP0H SET 0 +IPH1_PCCIP1H SET 0 +IPH1_PCCIP2H SET 0 +IPH1_PCCIP3H SET 0 +IPH1_PSSCH SET 0 +IPH1_PX2H SET 0 +IPH1_PXMH SET 0 + +; RMAP=x -CPU Interrupt Priority High Register +IPH_PSH SET 0 +IPH_PT0H SET 0 +IPH_PT1H SET 0 +IPH_PT2H SET 0 +IPH_PX0H SET 0 +IPH_PX1H SET 0 + +; RMAP=x -CPU Interrupt Priority Register +IP_PS SET 0 +IP_PT0 SET 0 +IP_PT1 SET 0 +IP_PT2 SET 0 +IP_PX0 SET 0 +IP_PX1 SET 0 + +; RMAP=0 PAGE=0-SCU Interrupt Request Register 0 +IRCON0_EXINT0 SET 0 +IRCON0_EXINT1 SET 0 +IRCON0_EXINT2 SET 0 +IRCON0_EXINT3 SET 0 +IRCON0_EXINT4 SET 0 +IRCON0_EXINT5 SET 0 +IRCON0_EXINT6 SET 0 + +; RMAP=0 PAGE=0-SCU Interrupt Request Register 1 +IRCON1_ADCSR0 SET 0 +IRCON1_ADCSR1 SET 0 +IRCON1_CANSRC1 SET 0 +IRCON1_CANSRC2 SET 0 +IRCON1_EIR SET 0 +IRCON1_RIR SET 0 +IRCON1_TIR SET 0 + +; RMAP=0 PAGE=0-SCU Interrupt Request Register 2 +IRCON2_CANSRC0 SET 0 +IRCON2_CANSRC3 SET 0 + +; RMAP=0 PAGE=3-SCU Interrupt Request Register 3 +IRCON3_CANSRC4 SET 0 +IRCON3_CANSRC5 SET 0 +IRCON3_CCU6SR0 SET 0 +IRCON3_CCU6SR1 SET 0 + +; RMAP=0 PAGE=3-SCU Interrupt Request Register 4 +IRCON4_CANSRC6 SET 0 +IRCON4_CANSRC7 SET 0 +IRCON4_CCU6SR2 SET 0 +IRCON4_CCU6SR3 SET 0 + +; RMAP=1 -MDU MDU Operand Register 0 +MDU_MD0_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 1 +MDU_MD1_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 2 +MDU_MD2_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 3 +MDU_MD3_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 4 +MDU_MD4_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 5 +MDU_MD5_DATA SET 0 + +; RMAP=1 -MDU MDU Control Register +MDU_MDUCON_IE SET 0 +MDU_MDUCON_IR SET 0 +MDU_MDUCON_OPCODE SET 0 +MDU_MDUCON_RSEL SET 0 +MDU_MDUCON_START SET 0 + +; RMAP=1 -MDU MDU Status Register +MDU_MDUSTAT_IERR SET 0 +MDU_MDUSTAT_IRDY SET 0 +MDU_MDUSTAT_MDU_BSY SET 0 + +; RMAP=1 -MDU MDU Result Register 0 +MDU_MR0_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 1 +MDU_MR1_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 2 +MDU_MR2_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 3 +MDU_MR3_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 4 +MDU_MR4_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 5 +MDU_MR5_DATA SET 0 + +; RMAP=0 PAGE=1-SCU Miscellaneous Control Register +MISC_CON_DFLASHEN SET 0 + +; RMAP=1 -OCDS BreakPoints Control Register +MMBPCR_HWB0C SET 0 +MMBPCR_HWB1C SET 0 +MMBPCR_HWB2C SET 0 +MMBPCR_HWB3C SET 0 +MMBPCR_SWBC SET 0 + +; RMAP=1 -OCDS Monitor Mode Control 2 Register +MMCR2_ALTDI SET 0 +MMCR2_DSUSP SET 0 +MMCR2_EXBC SET 0 +MMCR2_JENA SET 0 +MMCR2_MBCON SET 0 +MMCR2_MMEP SET 0 +MMCR2_MMODE SET 0 +MMCR2_STMODE SET 0 + +; RMAP=1 -OCDS Monitor Mode Control Register +MMCR_MEXIT SET 0 +MMCR_MEXIT_P SET 0 +MMCR_MRAMS SET 0 +MMCR_MRAMS_P SET 0 +MMCR_MSTEP SET 0 +MMCR_RRF SET 0 +MMCR_TRF SET 0 + +; RMAP=1 -OCDS Monitor Mode Data Transfer Register Receive +MMDR_MMRR SET 0 + +; RMAP=1 -OCDS Monitor Mode Interrupt Control Register +MMICR_COMRST SET 0 +MMICR_DRETR SET 0 +MMICR_DVECT SET 0 +MMICR_MMUIE SET 0 +MMICR_MMUIE_P SET 0 +MMICR_MSTSEL SET 0 +MMICR_RRIE SET 0 +MMICR_RRIE_P SET 0 + +; RMAP=1 -OCDS Monitor Mode Status Register +MMSR_EXBF SET 0 +MMSR_HWB0F SET 0 +MMSR_HWB1F SET 0 +MMSR_HWB2F SET 0 +MMSR_HWB3F SET 0 +MMSR_MBCAM SET 0 +MMSR_MBCIN SET 0 +MMSR_SWBF SET 0 + +; RMAP=1 -OCDS Monitor Work Register 1 +MMWR1_MMWR1 SET 0 + +; RMAP=1 -OCDS Monitor Work Register 2 +MMWR2_MMWR2 SET 0 + +; RMAP=0 PAGE=3-SCU Peripheral Input Select Register 1 +MODPISEL1_EXINT6IS SET 0 +MODPISEL1_JTAGTCKS1 SET 0 +MODPISEL1_JTAGTDIS1 SET 0 +MODPISEL1_T21EXIS SET 0 +MODPISEL1_UR1RIS SET 0 + +; RMAP=0 PAGE=3-SCU Peripheral Input Select Register 2 +MODPISEL2_T0IS SET 0 +MODPISEL2_T1IS SET 0 +MODPISEL2_T21IS SET 0 +MODPISEL2_T2IS SET 0 + +; RMAP=0 PAGE=0-SCU Peripheral Input Select Register +MODPISEL_EXINT0IS SET 0 +MODPISEL_EXINT1IS SET 0 +MODPISEL_EXINT2IS SET 0 +MODPISEL_JTAGTCKS SET 0 +MODPISEL_JTAGTDIS SET 0 +MODPISEL_URRIS SET 0 +MODPISEL_URRISH SET 0 + +; RMAP=0 PAGE=3-SCU Module Suspend Control Register +MODSUSP_T12SUSP SET 0 +MODSUSP_T13SUSP SET 0 +MODSUSP_T21SUSP SET 0 +MODSUSP_T2SUSP SET 0 +MODSUSP_WDTSUSP SET 0 + +; RMAP=0 PAGE=0-SCU NMI Control Register +NMICON_NMIECC SET 0 +NMICON_NMIFLASH SET 0 +NMICON_NMIOCDS SET 0 +NMICON_NMIPLL SET 0 +NMICON_NMIVDD SET 0 +NMICON_NMIVDDP SET 0 +NMICON_NMIWDT SET 0 + +; RMAP=0 PAGE=0-SCU NMI Status Register +NMISR_FNMIECC SET 0 +NMISR_FNMIFLASH SET 0 +NMISR_FNMIOCDS SET 0 +NMISR_FNMIPLL SET 0 +NMISR_FNMIVDD SET 0 +NMISR_FNMIVDDP SET 0 +NMISR_FNMIWDT SET 0 + +; RMAP=0 PAGE=1-SCU OSC Control Register +OSC_CON_ORDRES SET 0 +OSC_CON_OSCPD SET 0 +OSC_CON_OSCR SET 0 +OSC_CON_OSCSS SET 1 +OSC_CON_XPD SET 1 + +; RMAP=0 PAGE=2-P0 P0 Alternate Select 0 Register +P0_ALTSEL0_P0 SET 0 +P0_ALTSEL0_P1 SET 0 +P0_ALTSEL0_P2 SET 0 +P0_ALTSEL0_P3 SET 0 +P0_ALTSEL0_P4 SET 0 +P0_ALTSEL0_P5 SET 0 +P0_ALTSEL0_P6 SET 0 +P0_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P0 P0 Alternate Select 1 Register +P0_ALTSEL1_P0 SET 0 +P0_ALTSEL1_P1 SET 0 +P0_ALTSEL1_P2 SET 0 +P0_ALTSEL1_P3 SET 0 +P0_ALTSEL1_P4 SET 0 +P0_ALTSEL1_P5 SET 0 +P0_ALTSEL1_P6 SET 0 +P0_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P0 P0 Data Register +P0_DATA_P0 SET 0 +P0_DATA_P1 SET 0 +P0_DATA_P2 SET 0 +P0_DATA_P3 SET 0 +P0_DATA_P4 SET 0 +P0_DATA_P5 SET 0 +P0_DATA_P6 SET 0 +P0_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P0 P0 Direction Register +P0_DIR_P0 SET 1 +P0_DIR_P1 SET 1 +P0_DIR_P2 SET 1 +P0_DIR_P3 SET 1 +P0_DIR_P4 SET 0 +P0_DIR_P5 SET 0 +P0_DIR_P6 SET 0 +P0_DIR_P7 SET 1 + +; RMAP=0 PAGE=3-P0 P0 Open Drain Control Register +P0_OD_P0 SET 0 +P0_OD_P1 SET 0 +P0_OD_P2 SET 0 +P0_OD_P3 SET 0 +P0_OD_P4 SET 0 +P0_OD_P5 SET 0 +P0_OD_P6 SET 0 +P0_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P0 P0 Pull-Up/Pull-Down Enable Register +P0_PUDEN_P0 SET 1 +P0_PUDEN_P1 SET 1 +P0_PUDEN_P2 SET 1 +P0_PUDEN_P3 SET 1 +P0_PUDEN_P4 SET 0 +P0_PUDEN_P5 SET 0 +P0_PUDEN_P6 SET 1 +P0_PUDEN_P7 SET 1 + +; RMAP=0 PAGE=1-P0 P0 Pull-Up/Pull-Down Select Register +P0_PUDSEL_P0 SET 0 +P0_PUDSEL_P1 SET 0 +P0_PUDSEL_P2 SET 0 +P0_PUDSEL_P3 SET 0 +P0_PUDSEL_P4 SET 1 +P0_PUDSEL_P5 SET 1 +P0_PUDSEL_P6 SET 1 +P0_PUDSEL_P7 SET 0 + +; RMAP=0 PAGE=2-P1 P1 Alternate Select 0 Register +P1_ALTSEL0_P0 SET 0 +P1_ALTSEL0_P1 SET 1 +P1_ALTSEL0_P2 SET 0 +P1_ALTSEL0_P3 SET 0 +P1_ALTSEL0_P4 SET 0 +P1_ALTSEL0_P5 SET 0 +P1_ALTSEL0_P6 SET 0 +P1_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P1 P1 Alternate Select 1 Register +P1_ALTSEL1_P0 SET 0 +P1_ALTSEL1_P1 SET 1 +P1_ALTSEL1_P2 SET 0 +P1_ALTSEL1_P3 SET 0 +P1_ALTSEL1_P4 SET 0 +P1_ALTSEL1_P5 SET 0 +P1_ALTSEL1_P6 SET 0 +P1_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P1 P1 Data Register +P1_DATA_P0 SET 0 +P1_DATA_P1 SET 0 +P1_DATA_P2 SET 0 +P1_DATA_P3 SET 0 +P1_DATA_P4 SET 0 +P1_DATA_P5 SET 0 +P1_DATA_P6 SET 0 +P1_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P1 P1 Direction Register +P1_DIR_P0 SET 0 +P1_DIR_P1 SET 1 +P1_DIR_P2 SET 0 +P1_DIR_P3 SET 0 +P1_DIR_P4 SET 0 +P1_DIR_P5 SET 0 +P1_DIR_P6 SET 0 +P1_DIR_P7 SET 1 + +; RMAP=0 PAGE=3-P1 P1 Open Drain Control Register +P1_OD_P0 SET 0 +P1_OD_P1 SET 0 +P1_OD_P2 SET 0 +P1_OD_P3 SET 0 +P1_OD_P4 SET 0 +P1_OD_P5 SET 0 +P1_OD_P6 SET 0 +P1_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P1 P1 Pull-Up/Pull-Down Enable Register +P1_PUDEN_P0 SET 1 +P1_PUDEN_P1 SET 1 +P1_PUDEN_P2 SET 0 +P1_PUDEN_P3 SET 0 +P1_PUDEN_P4 SET 0 +P1_PUDEN_P5 SET 0 +P1_PUDEN_P6 SET 1 +P1_PUDEN_P7 SET 1 + +; RMAP=0 PAGE=1-P1 P1 Pull-Up/Pull-Down Select Register +P1_PUDSEL_P0 SET 1 +P1_PUDSEL_P1 SET 1 +P1_PUDSEL_P2 SET 1 +P1_PUDSEL_P3 SET 1 +P1_PUDSEL_P4 SET 1 +P1_PUDSEL_P5 SET 1 +P1_PUDSEL_P6 SET 1 +P1_PUDSEL_P7 SET 0 + +; RMAP=0 PAGE=0-P2 P2 Data Register +P2_DATA_P0 SET 0 +P2_DATA_P1 SET 0 +P2_DATA_P2 SET 0 +P2_DATA_P3 SET 0 +P2_DATA_P4 SET 0 +P2_DATA_P5 SET 0 +P2_DATA_P6 SET 0 +P2_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P2 P2 Direction Register +P2_DIR_P0 SET 0 +P2_DIR_P1 SET 0 +P2_DIR_P2 SET 0 +P2_DIR_P3 SET 0 +P2_DIR_P4 SET 0 +P2_DIR_P5 SET 0 +P2_DIR_P6 SET 0 +P2_DIR_P7 SET 0 + +; RMAP=0 PAGE=1-P2 P2 Pull-Up/Pull-Down Enable Register +P2_PUDEN_P0 SET 0 +P2_PUDEN_P1 SET 0 +P2_PUDEN_P2 SET 0 +P2_PUDEN_P3 SET 0 +P2_PUDEN_P4 SET 1 +P2_PUDEN_P5 SET 1 +P2_PUDEN_P6 SET 1 +P2_PUDEN_P7 SET 1 + +; RMAP=0 PAGE=1-P2 P2 Pull-Up/Pull-Down Select Register +P2_PUDSEL_P0 SET 1 +P2_PUDSEL_P1 SET 1 +P2_PUDSEL_P2 SET 1 +P2_PUDSEL_P3 SET 1 +P2_PUDSEL_P4 SET 1 +P2_PUDSEL_P5 SET 1 +P2_PUDSEL_P6 SET 1 +P2_PUDSEL_P7 SET 1 + +; RMAP=0 PAGE=2-P3 P3 Alternate Select 0 Register +P3_ALTSEL0_P0 SET 0 +P3_ALTSEL0_P1 SET 0 +P3_ALTSEL0_P2 SET 0 +P3_ALTSEL0_P3 SET 0 +P3_ALTSEL0_P4 SET 0 +P3_ALTSEL0_P5 SET 0 +P3_ALTSEL0_P6 SET 0 +P3_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P3 P3 Alternate Select 1 Register +P3_ALTSEL1_P0 SET 0 +P3_ALTSEL1_P1 SET 0 +P3_ALTSEL1_P2 SET 0 +P3_ALTSEL1_P3 SET 0 +P3_ALTSEL1_P4 SET 0 +P3_ALTSEL1_P5 SET 0 +P3_ALTSEL1_P6 SET 0 +P3_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P3 P3 Data Register +P3_DATA_P0 SET 0 +P3_DATA_P1 SET 0 +P3_DATA_P2 SET 0 +P3_DATA_P3 SET 0 +P3_DATA_P4 SET 0 +P3_DATA_P5 SET 0 +P3_DATA_P6 SET 0 +P3_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P3 P3 Direction Register +P3_DIR_P0 SET 0 +P3_DIR_P1 SET 0 +P3_DIR_P2 SET 1 +P3_DIR_P3 SET 1 +P3_DIR_P4 SET 1 +P3_DIR_P5 SET 1 +P3_DIR_P6 SET 0 +P3_DIR_P7 SET 0 + +; RMAP=0 PAGE=3-P3 P3 Open Drain Control Register +P3_OD_P0 SET 0 +P3_OD_P1 SET 0 +P3_OD_P2 SET 1 +P3_OD_P3 SET 1 +P3_OD_P4 SET 1 +P3_OD_P5 SET 1 +P3_OD_P6 SET 0 +P3_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P3 P3 Pull-Up/Pull-Down Enable Register +P3_PUDEN_P0 SET 1 +P3_PUDEN_P1 SET 1 +P3_PUDEN_P2 SET 0 +P3_PUDEN_P3 SET 0 +P3_PUDEN_P4 SET 0 +P3_PUDEN_P5 SET 0 +P3_PUDEN_P6 SET 0 +P3_PUDEN_P7 SET 1 + +; RMAP=0 PAGE=1-P3 P3 Pull-Up/Pull-Down Select Register +P3_PUDSEL_P0 SET 1 +P3_PUDSEL_P1 SET 1 +P3_PUDSEL_P2 SET 1 +P3_PUDSEL_P3 SET 1 +P3_PUDSEL_P4 SET 1 +P3_PUDSEL_P5 SET 1 +P3_PUDSEL_P6 SET 1 +P3_PUDSEL_P7 SET 1 + +; RMAP=0 PAGE=2-P4 P4 Alternate Select 0 Register +P4_ALTSEL0_P0 SET 0 +P4_ALTSEL0_P1 SET 0 +P4_ALTSEL0_P2 SET 0 +P4_ALTSEL0_P3 SET 0 +P4_ALTSEL0_P4 SET 0 +P4_ALTSEL0_P5 SET 0 +P4_ALTSEL0_P6 SET 0 +P4_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P4 P4 Alternate Select 1 Register +P4_ALTSEL1_P0 SET 0 +P4_ALTSEL1_P1 SET 0 +P4_ALTSEL1_P2 SET 0 +P4_ALTSEL1_P3 SET 0 +P4_ALTSEL1_P4 SET 0 +P4_ALTSEL1_P5 SET 0 +P4_ALTSEL1_P6 SET 0 +P4_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P4 P4 Data Register +P4_DATA_P0 SET 0 +P4_DATA_P1 SET 0 +P4_DATA_P2 SET 0 +P4_DATA_P3 SET 0 +P4_DATA_P4 SET 0 +P4_DATA_P5 SET 0 +P4_DATA_P6 SET 0 +P4_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P4 P4 Direction Register +P4_DIR_P0 SET 1 +P4_DIR_P1 SET 1 +P4_DIR_P2 SET 0 +P4_DIR_P3 SET 0 +P4_DIR_P4 SET 0 +P4_DIR_P5 SET 0 +P4_DIR_P6 SET 0 +P4_DIR_P7 SET 0 + +; RMAP=0 PAGE=3-P4 P4 Open Drain Control Register +P4_OD_P0 SET 0 +P4_OD_P1 SET 0 +P4_OD_P2 SET 0 +P4_OD_P3 SET 0 +P4_OD_P4 SET 0 +P4_OD_P5 SET 0 +P4_OD_P6 SET 0 +P4_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P4 P4 Pull-Up/Pull-Down Enable Register +P4_PUDEN_P0 SET 1 +P4_PUDEN_P1 SET 1 +P4_PUDEN_P2 SET 1 +P4_PUDEN_P3 SET 0 +P4_PUDEN_P4 SET 0 +P4_PUDEN_P5 SET 0 +P4_PUDEN_P6 SET 0 +P4_PUDEN_P7 SET 0 + +; RMAP=0 PAGE=1-P4 P4 Pull-Up/Pull-Down Select Register +P4_PUDSEL_P0 SET 0 +P4_PUDSEL_P1 SET 0 +P4_PUDSEL_P2 SET 1 +P4_PUDSEL_P3 SET 1 +P4_PUDSEL_P4 SET 1 +P4_PUDSEL_P5 SET 1 +P4_PUDSEL_P6 SET 1 +P4_PUDSEL_P7 SET 1 + +; RMAP=0 PAGE=2-P5 P5 Alternate Select 0 Register +P5_ALTSEL0_P0 SET 0 +P5_ALTSEL0_P1 SET 0 +P5_ALTSEL0_P2 SET 0 +P5_ALTSEL0_P3 SET 0 +P5_ALTSEL0_P4 SET 0 +P5_ALTSEL0_P5 SET 0 +P5_ALTSEL0_P6 SET 0 +P5_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P5 P5 Alternate Select 1 Register +P5_ALTSEL1_P0 SET 0 +P5_ALTSEL1_P1 SET 0 +P5_ALTSEL1_P2 SET 0 +P5_ALTSEL1_P3 SET 0 +P5_ALTSEL1_P4 SET 0 +P5_ALTSEL1_P5 SET 0 +P5_ALTSEL1_P6 SET 0 +P5_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P5 P5 Data Register +P5_DATA_P0 SET 0 +P5_DATA_P1 SET 0 +P5_DATA_P2 SET 0 +P5_DATA_P3 SET 0 +P5_DATA_P4 SET 0 +P5_DATA_P5 SET 0 +P5_DATA_P6 SET 0 +P5_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P5 P5 Direction Register +P5_DIR_P0 SET 0 +P5_DIR_P1 SET 0 +P5_DIR_P2 SET 0 +P5_DIR_P3 SET 0 +P5_DIR_P4 SET 0 +P5_DIR_P5 SET 0 +P5_DIR_P6 SET 0 +P5_DIR_P7 SET 0 + +; RMAP=0 PAGE=3-P5 P5 Open Drain Control Register +P5_OD_P0 SET 0 +P5_OD_P1 SET 0 +P5_OD_P2 SET 0 +P5_OD_P3 SET 0 +P5_OD_P4 SET 0 +P5_OD_P5 SET 0 +P5_OD_P6 SET 0 +P5_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P5 P5 Pull-Up/Pull-Down Enable Register +P5_PUDEN_P0 SET 0 +P5_PUDEN_P1 SET 0 +P5_PUDEN_P2 SET 0 +P5_PUDEN_P3 SET 0 +P5_PUDEN_P4 SET 0 +P5_PUDEN_P5 SET 0 +P5_PUDEN_P6 SET 0 +P5_PUDEN_P7 SET 0 + +; RMAP=0 PAGE=1-P5 P5 Pull-Up/Pull-Down Select Register +P5_PUDSEL_P0 SET 0 +P5_PUDSEL_P1 SET 0 +P5_PUDSEL_P2 SET 0 +P5_PUDSEL_P3 SET 0 +P5_PUDSEL_P4 SET 0 +P5_PUDSEL_P5 SET 0 +P5_PUDSEL_P6 SET 0 +P5_PUDSEL_P7 SET 0 + +; RMAP=0 PAGE=1-SCU Password Register +PASSWD_MODE SET 0 +PASSWD_PASS SET 0 +PASSWD_PROTECT_S SET 0 + +; RMAP=x -CPU Power Control Register +PCON_GF0 SET 0 +PCON_GF1 SET 0 +PCON_IDLE SET 0 +PCON_SMOD SET 0 + +; RMAP=0 PAGE=1-SCU PLL Control Register +PLL_CON_LOCK SET 0 +PLL_CON_NDIV SET 10 +PLL_CON_OSCDISC SET 0 +PLL_CON_RESLD SET 0 +PLL_CON_VCOBYP SET 0 + +; RMAP=0 PAGE=1-SCU Power Mode Control Register 0 +PMCON0_PD SET 0 +PMCON0_SD SET 0 +PMCON0_WDTRST SET 0 +PMCON0_WKRS SET 0 +PMCON0_WKSEL SET 0 +PMCON0_WS SET 0 + +; RMAP=0 PAGE=1-SCU Power Mode Control Register 1 +PMCON1_ADC_DIS SET 0 +PMCON1_CAN_DIS SET 0 +PMCON1_CCU_DIS SET 0 +PMCON1_CDC_DIS SET 0 +PMCON1_MDU_DIS SET 0 +PMCON1_SSC_DIS SET 1 +PMCON1_T2_DIS SET 0 + +; RMAP=0 PAGE=3-SCU Power Mode Control Register 2 +PMCON2_T21_DIS SET 0 +PMCON2_UART1_DIS SET 0 + +; RMAP=0 -PORT Page Register +PORT_PAGE_OP SET 0 +PORT_PAGE_PAGE SET 0 +PORT_PAGE_STNR SET 0 + +; RMAP=x -CPU Program Status Word Register +PSW_AC SET 0 +PSW_CY SET 0 +PSW_F0 SET 0 +PSW_F1 SET 0 +PSW_OV SET 0 +PSW_P SET 0 +PSW_RS0 SET 0 +PSW_RS1 SET 0 + +; RMAP=x -CPU Serial Data Buffer Register +SBUF_VAL SET 0 + +; RMAP=x -CPU Serial Channel Control Register +SCON_RB8 SET 0 +SCON_REN SET 0 +SCON_RI SET 0 +SCON_SM0 SET 0 +SCON_SM1 SET 0 +SCON_SM2 SET 0 +SCON_TB8 SET 0 +SCON_TI SET 0 + +; RMAP=0 -SCU Page Register +SCU_PAGE_OP SET 0 +SCU_PAGE_PAGE SET 0 +SCU_PAGE_STNR SET 0 + +; RMAP=x -CPU Stack Pointer Register +SP_SP SET 0 + +; RMAP=0 -SSC Baudrate Timer Reload Register High +SSC_BRH_BR_VALUE SET 0 + +; RMAP=0 -SSC Baudrate Timer Reload Register Low +SSC_BRL_BR_VALUE SET 0 + +; RMAP=0 -SSC Control Register High Operating Mode +SSC_CONH_O_BE SET 0 +SSC_CONH_O_BSY SET 0 +SSC_CONH_O_EN SET 0 +SSC_CONH_O_MS SET 0 +SSC_CONH_O_PE SET 0 +SSC_CONH_O_RE SET 0 +SSC_CONH_O_TE SET 0 + +; RMAP=0 -SSC Control Register High Programming Mode +SSC_CONH_P_AREN SET 0 +SSC_CONH_P_BEN SET 0 +SSC_CONH_P_EN SET 0 +SSC_CONH_P_MS SET 1 +SSC_CONH_P_PEN SET 0 +SSC_CONH_P_REN SET 0 +SSC_CONH_P_TEN SET 0 + +; RMAP=0 -SSC Control Register Low Operating Mode +SSC_CONL_O_BC SET 0 + +; RMAP=0 -SSC Control Register Low Programming Mode +SSC_CONL_P_BM SET 1 +SSC_CONL_P_HB SET 0 +SSC_CONL_P_LB SET 0 +SSC_CONL_P_PH SET 0 +SSC_CONL_P_PO SET 0 + +; RMAP=0 -SSC Port Input Select Register +SSC_PISEL_CIS SET 0 +SSC_PISEL_MIS SET 0 +SSC_PISEL_SIS SET 0 + +; RMAP=0 -SSC Receiver Buffer Register Low +SSC_RBL_RB_VALUE SET 0 + +; RMAP=0 -SSC Transmitter Buffer Register Low +SSC_TBL_TB_VALUE SET 0 + +; RMAP=x -SCU System Control Register 0 +SYSCON0_1 SET 0 +SYSCON0_IMODE SET 0 +SYSCON0_RMAP SET 0 + +; RMAP=1 -T21 Timer 2 Reload/Capture Register High +T21_RC2H_RC2 SET 0 + +; RMAP=1 -T21 Timer 2 Reload/Capture Register Low +T21_RC2L_RC2 SET 0 + +; RMAP=1 -T21 Timer 2 Control Register +T21_T2CON_C_T2 SET 0 +T21_T2CON_CP_RL2 SET 0 +T21_T2CON_EXEN2 SET 0 +T21_T2CON_EXF2 SET 0 +T21_T2CON_TF2 SET 0 +T21_T2CON_TR2 SET 0 + +; RMAP=1 -T21 Timer 2 Register High +T21_T2H_THL2 SET 0 + +; RMAP=1 -T21 Timer 2 Register Low +T21_T2L_THL2 SET 0 + +; RMAP=1 -T21 Timer 2 Mode Register +T21_T2MOD_DCEN SET 0 +T21_T2MOD_EDGESEL SET 0 +T21_T2MOD_PREN SET 0 +T21_T2MOD_T2PRE SET 0 +T21_T2MOD_T2REGS SET 0 +T21_T2MOD_T2RHEN SET 0 + +; RMAP=0 -T2 Timer 2 Reload/Capture Register High +T2_RC2H_RC2 SET 248 + +; RMAP=0 -T2 Timer 2 Reload/Capture Register Low +T2_RC2L_RC2 SET 48 + +; RMAP=0 -T2 Timer 2 Control Register +T2_T2CON_C_T2 SET 0 +T2_T2CON_CP_RL2 SET 0 +T2_T2CON_EXEN2 SET 0 +T2_T2CON_EXF2 SET 0 +T2_T2CON_TF2 SET 0 +T2_T2CON_TR2 SET 1 + +; RMAP=0 -T2 Timer 2 Register High +T2_T2H_THL2 SET 248 + +; RMAP=0 -T2 Timer 2 Register Low +T2_T2L_THL2 SET 48 + +; RMAP=0 -T2 Timer 2 Mode Register +T2_T2MOD_DCEN SET 0 +T2_T2MOD_EDGESEL SET 0 +T2_T2MOD_PREN SET 0 +T2_T2MOD_T2PRE SET 0 +T2_T2MOD_T2REGS SET 0 +T2_T2MOD_T2RHEN SET 0 + +; RMAP=x -CPU Timer Control Register +TCON_IE0 SET 0 +TCON_IE1 SET 0 +TCON_IT0 SET 0 +TCON_IT1 SET 0 +TCON_TF0 SET 0 +TCON_TF1 SET 0 +TCON_TR0 SET 0 +TCON_TR1 SET 0 + +; RMAP=x -CPU Timer 0 Register High +TH0_VAL SET 0 + +; RMAP=x -CPU Timer 1 Register High +TH1_VAL SET 0 + +; RMAP=x -CPU Timer 0 Register Low +TL0_VAL SET 0 + +; RMAP=x -CPU Timer 1 Register Low +TL1_VAL SET 0 + +; RMAP=x -CPU Timer Mode Register +TMOD_GATE0 SET 0 +TMOD_GATE1 SET 0 +TMOD_T0M SET 0 +TMOD_T0S SET 0 +TMOD_T1M SET 0 +TMOD_T1S SET 0 + +; RMAP=1 -UART1 Baud Rate Control Register +UART1_BCON_BRPRE SET 0 +UART1_BCON_R SET 0 + +; RMAP=1 -UART1 Baud Rate Timer/Reload Register +UART1_BG_BR_VALUE SET 1 + +; RMAP=1 -UART1 Fractional Divider Control Register +UART1_FDCON_FDEN SET 0 +UART1_FDCON_FDM SET 0 +UART1_FDCON_NDOV SET 0 + +; RMAP=1 -UART1 Fractional Divider Result Register +UART1_FDRES_RESULT SET 0 + +; RMAP=1 -UART1 Fractional Divider Reload Register +UART1_FDSTEP_STEP SET 0 + +; RMAP=1 -UART1 Serial Data Buffer Register +UART1_SBUF_VAL SET 0 + +; RMAP=1 -UART1 Serial Channel Control Register +UART1_SCON_RB8_1 SET 0 +UART1_SCON_REN_1 SET 0 +UART1_SCON_RI_1 SET 0 +UART1_SCON_SM0_1 SET 0 +UART1_SCON_SM1_1 SET 0 +UART1_SCON_SM2_1 SET 0 +UART1_SCON_TB8_1 SET 0 +UART1_SCON_TI_1 SET 0 + +; RMAP=1 -WDT Watchdog Timer Control Register +WDTCON_WDTEN SET 0 +WDTCON_WDTIN SET 1 +WDTCON_WDTPR SET 0 +WDTCON_WDTRS SET 0 +WDTCON_WINBEN SET 0 + +; RMAP=1 -WDT Watchdog Timer Register High +WDTH_WDT SET 0 + +; RMAP=1 -WDT Watchdog Timer Register Low +WDTL_WDT SET 0 + +; RMAP=1 -WDT Watchdog Timer Reload Register +WDTREL_WDTREL SET 219 + +; RMAP=1 -WDT Watchdog Window-Boundary Count Register +WDTWINB_WDTWINB SET 0 + +; RMAP=0 PAGE=3-SCU On-chip XRAM Address Higher Order +XADDRH_ADDRH SET 0 + diff --git a/CL2.0.dav b/CL2.0.dav new file mode 100644 index 0000000..735f3c0 Binary files /dev/null and b/CL2.0.dav differ diff --git a/CL2.0.dpt b/CL2.0.dpt new file mode 100644 index 0000000..734ed69 --- /dev/null +++ b/CL2.0.dpt @@ -0,0 +1,3928 @@ +'**************************************************************************** +' @Filename CL2.0.dpt +' @Project CL2.0.dav +'---------------------------------------------------------------------------- +' @Description The file will be used by your programming environment +' to retrieve information about the generated files or +' the actual project values. +' +' PLEASE DO NOT MODIFY THIS FILE ! +' +'---------------------------------------------------------------------------- +; Date 2025/1/18 20:45:36 +' +'**************************************************************************** + +[General] +Device="XC886CLM" +DeviceType="XC886CLM-8FF" + +[Interface] +Compiler="KEIL" +MemoryModel="COMPACT" + +[Environment] +OscillatorFrequency=0 +DeviceFrequency=96 + +[Files] +File1="MAIN.H" +Type1="H" +File2="MAIN.C" +Type2="C" +File3="SHARED_INT.H" +Type3="H" +File4="SHARED_INT.C" +Type4="C" +File5="IO.H" +Type5="H" +File6="IO.C" +Type6="C" +File7="T2.H" +Type7="H" +File8="T2.C" +Type8="C" +File9="WDT.H" +Type9="H" +File10="WDT.C" +Type10="C" +File11="CAN.H" +Type11="H" +File12="CAN.C" +Type12="C" +File13="CL2.0.asm" +Type13="ASM" +File14="CL2.0.rtf" +Type14="DOC" + + +[Registers] +ACC_ACC0=0 +ACC_ACC1=0 +ACC_ACC2=0 +ACC_ACC3=0 +ACC_ACC4=0 +ACC_ACC5=0 +ACC_ACC6=0 +ACC_ACC7=0 +ADC0_NOTES= +ADC1_NOTES= +ADC2_NOTES= +ADC3_NOTES= +ADC4_NOTES= +ADC5_NOTES= +ADC6_NOTES= +ADC7_NOTES= +ADC_CFILE=ADC.C +ADC_CHCTR0_LCC=0 +ADC_CHCTR0_RESRSEL=0 +ADC_CHCTR1_LCC=0 +ADC_CHCTR1_RESRSEL=0 +ADC_CHCTR2_LCC=0 +ADC_CHCTR2_RESRSEL=0 +ADC_CHCTR3_LCC=0 +ADC_CHCTR3_RESRSEL=0 +ADC_CHCTR4_LCC=0 +ADC_CHCTR4_RESRSEL=0 +ADC_CHCTR5_LCC=0 +ADC_CHCTR5_RESRSEL=0 +ADC_CHCTR6_LCC=0 +ADC_CHCTR6_RESRSEL=0 +ADC_CHCTR7_LCC=0 +ADC_CHCTR7_RESRSEL=0 +ADC_CHINCR_CHINC0=0 +ADC_CHINCR_CHINC1=0 +ADC_CHINCR_CHINC2=0 +ADC_CHINCR_CHINC3=0 +ADC_CHINCR_CHINC4=0 +ADC_CHINCR_CHINC5=0 +ADC_CHINCR_CHINC6=0 +ADC_CHINCR_CHINC7=0 +ADC_CHINFR_CHINF0=0 +ADC_CHINFR_CHINF1=0 +ADC_CHINFR_CHINF2=0 +ADC_CHINFR_CHINF3=0 +ADC_CHINFR_CHINF4=0 +ADC_CHINFR_CHINF5=0 +ADC_CHINFR_CHINF6=0 +ADC_CHINFR_CHINF7=0 +ADC_CHINPR_CHINP0=0 +ADC_CHINPR_CHINP1=0 +ADC_CHINPR_CHINP2=0 +ADC_CHINPR_CHINP3=0 +ADC_CHINPR_CHINP4=0 +ADC_CHINPR_CHINP5=0 +ADC_CHINPR_CHINP6=0 +ADC_CHINPR_CHINP7=0 +ADC_CHINSR_CHINS0=0 +ADC_CHINSR_CHINS1=0 +ADC_CHINSR_CHINS2=0 +ADC_CHINSR_CHINS3=0 +ADC_CHINSR_CHINS4=0 +ADC_CHINSR_CHINS5=0 +ADC_CHINSR_CHINS6=0 +ADC_CHINSR_CHINS7=0 +ADC_CRCR1_CH4=0 +ADC_CRCR1_CH5=0 +ADC_CRCR1_CH6=0 +ADC_CRCR1_CH7=0 +ADC_CRMR1_0=0 +ADC_CRMR1_CLRPND=0 +ADC_CRMR1_ENGT=0 +ADC_CRMR1_ENSI=0 +ADC_CRMR1_ENTR=0 +ADC_CRMR1_LDEV=0 +ADC_CRMR1_RSV=0 +ADC_CRMR1_SCAN=0 +ADC_CRPR1_CHP4=0 +ADC_CRPR1_CHP5=0 +ADC_CRPR1_CHP6=0 +ADC_CRPR1_CHP7=0 +ADC_ETRCR_ETRSEL0=0 +ADC_ETRCR_ETRSEL1=0 +ADC_ETRCR_SYNEN0=0 +ADC_ETRCR_SYNEN1=0 +ADC_EVINCR_EVINC0=0 +ADC_EVINCR_EVINC1=0 +ADC_EVINCR_EVINC4=0 +ADC_EVINCR_EVINC5=0 +ADC_EVINCR_EVINC6=0 +ADC_EVINCR_EVINC7=0 +ADC_EVINFR_EVINF0=0 +ADC_EVINFR_EVINF1=0 +ADC_EVINFR_EVINF4=0 +ADC_EVINFR_EVINF5=0 +ADC_EVINFR_EVINF6=0 +ADC_EVINFR_EVINF7=0 +ADC_EVINPR_EVINP0=0 +ADC_EVINPR_EVINP1=0 +ADC_EVINPR_EVINP4=0 +ADC_EVINPR_EVINP5=0 +ADC_EVINPR_EVINP6=0 +ADC_EVINPR_EVINP7=0 +ADC_EVINSR_EVINS0=0 +ADC_EVINSR_EVINS1=0 +ADC_EVINSR_EVINS4=0 +ADC_EVINSR_EVINS5=0 +ADC_EVINSR_EVINS6=0 +ADC_EVINSR_EVINS7=0 +ADC_GLOBCTR_ANON=0 +ADC_GLOBCTR_CTC=3 +ADC_GLOBCTR_DW=0 +ADC_GLOBSTR_BUSY=0 +ADC_GLOBSTR_CHNR=0 +ADC_GLOBSTR_SAMPLE=0 +ADC_HFILE=ADC.H +ADC_INPCR0_STC=0 +ADC_LCBR_BOUND0=7 +ADC_LCBR_BOUND1=11 +ADC_NAME_BUSY=ADC_ubBusy +ADC_NAME_CLRCHINTR=ADC_vClearChInterruptFlag +ADC_NAME_CLREVENTINTRFLAG=ADC_vClearEventInterruptFlag +ADC_NAME_CLRVALIDFLAG=ADC_vClearValidFlag +ADC_NAME_GETCHINTRFLAG=ADC_ubGetChInterruptFlag +ADC_NAME_GETCONVCHNUM=ADC_ubGetConvChNum +ADC_NAME_GETEVENTINTRFLAG=ADC_ubGetEventInterruptFlag +ADC_NAME_INIT=ADC_vInit +ADC_NAME_ISR=SHINT_viXINTR6Isr +ADC_NAME_PARCLRPND=ADC_vClearPendingBits +ADC_NAME_PARCONVPENDING=ADC_ubGetParConvChNum +ADC_NAME_PARLDEV=ADC_vSetLoadEvent +ADC_NAME_PARREQCH=ADC_vStartParReqChNum +ADC_NAME_READRESULTCHNUM0=ADC_ubGetResultChNum0 +ADC_NAME_READRESULTCHNUM1=ADC_ubGetResultChNum1 +ADC_NAME_READRESULTCHNUM2=ADC_ubGetResultChNum2 +ADC_NAME_READRESULTCHNUM3=ADC_ubGetResultChNum3 +ADC_NAME_READRESULTDATA0=ADC_uwGetResultData0 +ADC_NAME_READRESULTDATA1=ADC_uwGetResultData1 +ADC_NAME_READRESULTDATA2=ADC_uwGetResultData2 +ADC_NAME_READRESULTDATA3=ADC_uwGetResultData3 +ADC_NAME_SAMPLEPHASE=ADC_ubSamplePhase +ADC_NAME_SEQCEV=ADC_vClearEV +ADC_NAME_SEQCLRV=ADC_vClearVBits +ADC_NAME_SEQFLUSH=ADC_vQueFlush +ADC_NAME_SEQREQCHNR=ADC_vStartSeqReqChNum +ADC_NAME_SEQSRCEVENT=ADC_ubGetSeqSrcEvent +ADC_NAME_SEQSRCFILLLEVEL=ADC_ubGetSeqSrcFillLevel +ADC_NAME_SEQSRCQUEEXTTRG=ADC_ubGetQueueExternalTrigger +ADC_NAME_SEQSRCQUEUEEMPTY=ADC_ubGetQueueEmpty +ADC_NAME_SEQSRCREQCHNUM=ADC_ubGetQueueReqChNum +ADC_NAME_SEQSRCREQCHVALID=ADC_ubGetSeqReqChValid +ADC_NAME_SEQTREV=ADC_vSeqSoftTrig +ADC_NAME_SETCHINTR=ADC_vSetChInterruptFlag +ADC_NAME_SETEVENTINTR=ADC_vSetEventInterruptFlag +ADC_NOTES= +ADC_PAGE_OP=0 +ADC_PAGE_PAGE=0 +ADC_PAGE_STNR=0 +ADC_PARA_CHANNEL_0=CHANNEL_0 +ADC_PARA_CHANNEL_1=CHANNEL_1 +ADC_PARA_CHANNEL_2=CHANNEL_2 +ADC_PARA_CHANNEL_3=CHANNEL_3 +ADC_PARA_CHANNEL_4=CHANNEL_4 +ADC_PARA_CHANNEL_5=CHANNEL_5 +ADC_PARA_CHANNEL_6=CHANNEL_6 +ADC_PARA_CHANNEL_7=CHANNEL_7 +ADC_PRAR_ARBM=0 +ADC_PRAR_ASEN0=0 +ADC_PRAR_ASEN1=0 +ADC_PRAR_CSM0=0 +ADC_PRAR_CSM1=0 +ADC_PRAR_PRIO0=0 +ADC_PRAR_PRIO1=0 +ADC_Q0R0_ENSI=0 +ADC_Q0R0_EXTR=0 +ADC_Q0R0_REQCHNR=0 +ADC_Q0R0_RF=0 +ADC_Q0R0_V=0 +ADC_QBUR0_ENSI=0 +ADC_QBUR0_EXTR=0 +ADC_QBUR0_REQCHNR=0 +ADC_QBUR0_RF=0 +ADC_QBUR0_V=0 +ADC_QINR0_ENSI=0 +ADC_QINR0_EXTR=0 +ADC_QINR0_REQCHNR=0 +ADC_QINR0_RF=0 +ADC_QMR0_0=0 +ADC_QMR0_CEV=0 +ADC_QMR0_CLRV=0 +ADC_QMR0_ENGT=0 +ADC_QMR0_ENTR=0 +ADC_QMR0_FLUSH=0 +ADC_QMR0_TREV=0 +ADC_QSR0_EMPTY=0 +ADC_QSR0_EV=0 +ADC_QSR0_FILL=0 +ADC_QSR0_RSV=0 +ADC_RCR0_DRCTR=0 +ADC_RCR0_IEN=0 +ADC_RCR0_VFCTR=0 +ADC_RCR0_WFR=0 +ADC_RCR1_DRCTR=0 +ADC_RCR1_IEN=0 +ADC_RCR1_VFCTR=0 +ADC_RCR1_WFR=0 +ADC_RCR2_DRCTR=0 +ADC_RCR2_IEN=0 +ADC_RCR2_VFCTR=0 +ADC_RCR2_WFR=0 +ADC_RCR3_DRCTR=0 +ADC_RCR3_IEN=0 +ADC_RCR3_VFCTR=0 +ADC_RCR3_WFR=0 +ADC_RESR0H_RESULT=0 +ADC_RESR0L_CHNR=0 +ADC_RESR0L_DRC=0 +ADC_RESR0L_RESULT=0 +ADC_RESR0L_VF=0 +ADC_RESR1H_RESULT=0 +ADC_RESR1L_CHNR=0 +ADC_RESR1L_DRC=0 +ADC_RESR1L_RESULT=0 +ADC_RESR1L_VF=0 +ADC_RESR2H_RESULT=0 +ADC_RESR2L_CHNR=0 +ADC_RESR2L_DRC=0 +ADC_RESR2L_RESULT=0 +ADC_RESR2L_VF=0 +ADC_RESR3H_RESULT=0 +ADC_RESR3L_CHNR=0 +ADC_RESR3L_DRC=0 +ADC_RESR3L_RESULT=0 +ADC_RESR3L_VF=0 +ADC_RESRA0H_RESULT=0 +ADC_RESRA0L_CHNR=0 +ADC_RESRA0L_DRC=0 +ADC_RESRA0L_RESULT=0 +ADC_RESRA0L_VF=0 +ADC_RESRA1H_RESULT=0 +ADC_RESRA1L_CHNR=0 +ADC_RESRA1L_DRC=0 +ADC_RESRA1L_RESULT=0 +ADC_RESRA1L_VF=0 +ADC_RESRA2H_RESULT=0 +ADC_RESRA2L_CHNR=0 +ADC_RESRA2L_DRC=0 +ADC_RESRA2L_RESULT=0 +ADC_RESRA2L_VF=0 +ADC_RESRA3H_RESULT=0 +ADC_RESRA3L_CHNR=0 +ADC_RESRA3L_DRC=0 +ADC_RESRA3L_RESULT=0 +ADC_RESRA3L_VF=0 +ADC_USE_BUSY=0 +ADC_USE_CHANNEL_0=0 +ADC_USE_CHANNEL_1=0 +ADC_USE_CHANNEL_2=0 +ADC_USE_CHANNEL_3=0 +ADC_USE_CHANNEL_4=0 +ADC_USE_CHANNEL_5=0 +ADC_USE_CHANNEL_6=0 +ADC_USE_CHANNEL_7=0 +ADC_USE_CLRCHINTR=0 +ADC_USE_CLREVENTINTRFLAG=0 +ADC_USE_CLRVALIDFLAG=0 +ADC_USE_GETCHINTRFLAG=0 +ADC_USE_GETCONVCHNUM=0 +ADC_USE_GETEVENTINTRFLAG=0 +ADC_USE_INIT=0 +ADC_USE_ISR=0 +ADC_USE_PARCLRPND=0 +ADC_USE_PARCONVPENDING=0 +ADC_USE_PARLDEV=0 +ADC_USE_PARREQCH=0 +ADC_USE_READRESULTCHNUM0=0 +ADC_USE_READRESULTCHNUM1=0 +ADC_USE_READRESULTCHNUM2=0 +ADC_USE_READRESULTCHNUM3=0 +ADC_USE_READRESULTDATA0=0 +ADC_USE_READRESULTDATA1=0 +ADC_USE_READRESULTDATA2=0 +ADC_USE_READRESULTDATA3=0 +ADC_USE_SAMPLEPHASE=0 +ADC_USE_SEQCEV=0 +ADC_USE_SEQCLRV=0 +ADC_USE_SEQFLUSH=0 +ADC_USE_SEQREQCHNR=0 +ADC_USE_SEQSRCEVENT=0 +ADC_USE_SEQSRCFILLLEVEL=0 +ADC_USE_SEQSRCQUEEXTTRG=0 +ADC_USE_SEQSRCQUEUEEMPTY=0 +ADC_USE_SEQSRCREQCHNUM=0 +ADC_USE_SEQSRCREQCHVALID=0 +ADC_USE_SEQTREV=0 +ADC_USE_SETCHINTR=0 +ADC_USE_SETEVENTINTR=0 +ADC_VFCR_VFC0=0 +ADC_VFCR_VFC1=0 +ADC_VFCR_VFC2=0 +ADC_VFCR_VFC3=0 +BCON_BGSEL=0 +BCON_BRDIS=0 +BCON_BRPRE=0 +BCON_R=0 +BG_BR_VALUE=1 +BRG1_INTERRUPT_SELECT=0 +BRG1_NAME_ISR=SHINT_viXINTR8Isr +BRG_INTERRUPT_SELECT=0 +BRG_NAME_ISR=SHINT_viXINTR5Isr +B_B0=0 +B_B1=0 +B_B2=0 +B_B3=0 +B_B4=0 +B_B5=0 +B_B6=0 +B_B7=0 +CAN_ADCON_AUAD=0 +CAN_ADCON_BSY=0 +CAN_ADCON_RWEN=0 +CAN_ADCON_V0=0 +CAN_ADCON_V1=0 +CAN_ADCON_V2=0 +CAN_ADCON_V3=0 +CAN_ADH_CA10=0 +CAN_ADH_CA11=0 +CAN_ADH_CA12=0 +CAN_ADH_CA13=0 +CAN_ADL_CA2=0 +CAN_ADL_CA3=0 +CAN_ADL_CA4=0 +CAN_ADL_CA5=0 +CAN_ADL_CA6=0 +CAN_ADL_CA7=0 +CAN_ADL_CA8=0 +CAN_ADL_CA9=0 +CAN_BAUDRATENODE0=100000 +CAN_BAUDRATENODE1=125000 +CAN_CFILE=CAN.C +CAN_DATA0_CD[7:0]=0 +CAN_DATA1_CD[15:8]=0 +CAN_DATA2_CD=0 +CAN_DATA3_CD=0 +CAN_HFILE=CAN.H +CAN_LIST0_0=0 +CAN_LIST0_BEGIN=0 +CAN_LIST0_EMPTY=0 +CAN_LIST0_END=0 +CAN_LIST0_SIZE=0 +CAN_LIST1_0=0 +CAN_LIST1_BEGIN=0 +CAN_LIST1_EMPTY=0 +CAN_LIST1_END=0 +CAN_LIST1_SIZE=0 +CAN_LIST2_0=0 +CAN_LIST2_BEGIN=0 +CAN_LIST2_EMPTY=0 +CAN_LIST2_END=0 +CAN_LIST2_SIZE=0 +CAN_LIST3_0=0 +CAN_LIST3_BEGIN=0 +CAN_LIST3_EMPTY=0 +CAN_LIST3_END=0 +CAN_LIST3_SIZE=0 +CAN_LIST4_0=0 +CAN_LIST4_BEGIN=0 +CAN_LIST4_EMPTY=0 +CAN_LIST4_END=0 +CAN_LIST4_SIZE=0 +CAN_LIST5_0=0 +CAN_LIST5_BEGIN=0 +CAN_LIST5_EMPTY=0 +CAN_LIST5_END=0 +CAN_LIST5_SIZE=0 +CAN_LIST6_0=0 +CAN_LIST6_BEGIN=0 +CAN_LIST6_EMPTY=0 +CAN_LIST6_END=0 +CAN_LIST6_SIZE=0 +CAN_LIST7_0=0 +CAN_LIST7_BEGIN=0 +CAN_LIST7_EMPTY=0 +CAN_LIST7_END=0 +CAN_LIST7_SIZE=0 +CAN_MCR_0=0 +CAN_MCR_0=0 +CAN_MCR_MPSEL=0 +CAN_MITR_IT[31:8]=0 +CAN_MITR_IT[7:0]=0 +CAN_MO0_LISTPOS=0 +CAN_MO10_LISTPOS=0 +CAN_MO11_LISTPOS=0 +CAN_MO12_LISTPOS=0 +CAN_MO13_LISTPOS=0 +CAN_MO14_LISTPOS=0 +CAN_MO15_LISTPOS=0 +CAN_MO16_LISTPOS=0 +CAN_MO17_LISTPOS=0 +CAN_MO18_LISTPOS=0 +CAN_MO19_LISTPOS=0 +CAN_MO1_LISTPOS=0 +CAN_MO20_LISTPOS=0 +CAN_MO21_LISTPOS=0 +CAN_MO22_LISTPOS=0 +CAN_MO23_LISTPOS=0 +CAN_MO24_LISTPOS=0 +CAN_MO25_LISTPOS=0 +CAN_MO26_LISTPOS=0 +CAN_MO27_LISTPOS=0 +CAN_MO28_LISTPOS=0 +CAN_MO29_LISTPOS=0 +CAN_MO2_LISTPOS=0 +CAN_MO30_LISTPOS=0 +CAN_MO31_LISTPOS=0 +CAN_MO3_LISTPOS=0 +CAN_MO4_LISTPOS=0 +CAN_MO5_LISTPOS=4 +CAN_MO6_LISTPOS=5 +CAN_MO7_LISTPOS=6 +CAN_MO8_LISTPOS=3 +CAN_MO9_LISTPOS=7 +CAN_MOAMR0_0=0 +CAN_MOAMR0_AM=536870911 +CAN_MOAMR0_MIDE=1 +CAN_MOAMR10_0=0 +CAN_MOAMR10_AM=536870911 +CAN_MOAMR10_MIDE=1 +CAN_MOAMR11_0=0 +CAN_MOAMR11_AM=536870911 +CAN_MOAMR11_MIDE=1 +CAN_MOAMR12_0=0 +CAN_MOAMR12_AM=536870911 +CAN_MOAMR12_MIDE=1 +CAN_MOAMR13_0=0 +CAN_MOAMR13_AM=536870911 +CAN_MOAMR13_MIDE=1 +CAN_MOAMR14_0=0 +CAN_MOAMR14_AM=536870911 +CAN_MOAMR14_MIDE=1 +CAN_MOAMR15_0=0 +CAN_MOAMR15_AM=536870911 +CAN_MOAMR15_MIDE=1 +CAN_MOAMR16_0=0 +CAN_MOAMR16_AM=536870911 +CAN_MOAMR16_MIDE=1 +CAN_MOAMR17_0=0 +CAN_MOAMR17_AM=536870911 +CAN_MOAMR17_MIDE=1 +CAN_MOAMR18_0=0 +CAN_MOAMR18_AM=536870911 +CAN_MOAMR18_MIDE=1 +CAN_MOAMR19_0=0 +CAN_MOAMR19_AM=536870911 +CAN_MOAMR19_MIDE=1 +CAN_MOAMR1_0=0 +CAN_MOAMR1_AM=536870911 +CAN_MOAMR1_MIDE=1 +CAN_MOAMR20_0=0 +CAN_MOAMR20_AM=536870911 +CAN_MOAMR20_MIDE=1 +CAN_MOAMR21_0=0 +CAN_MOAMR21_AM=536870911 +CAN_MOAMR21_MIDE=1 +CAN_MOAMR22_0=0 +CAN_MOAMR22_AM=536870911 +CAN_MOAMR22_MIDE=1 +CAN_MOAMR23_0=0 +CAN_MOAMR23_AM=536870911 +CAN_MOAMR23_MIDE=1 +CAN_MOAMR24_0=0 +CAN_MOAMR24_AM=536870911 +CAN_MOAMR24_MIDE=1 +CAN_MOAMR25_0=0 +CAN_MOAMR25_AM=536870911 +CAN_MOAMR25_MIDE=1 +CAN_MOAMR26_0=0 +CAN_MOAMR26_AM=536870911 +CAN_MOAMR26_MIDE=1 +CAN_MOAMR27_0=0 +CAN_MOAMR27_AM=536870911 +CAN_MOAMR27_MIDE=1 +CAN_MOAMR28_0=0 +CAN_MOAMR28_AM=536870911 +CAN_MOAMR28_MIDE=1 +CAN_MOAMR29_0=0 +CAN_MOAMR29_AM=536870911 +CAN_MOAMR29_MIDE=1 +CAN_MOAMR2_0=0 +CAN_MOAMR2_AM=536870911 +CAN_MOAMR2_MIDE=1 +CAN_MOAMR30_0=0 +CAN_MOAMR30_AM=536870911 +CAN_MOAMR30_MIDE=1 +CAN_MOAMR31_0=0 +CAN_MOAMR31_AM=536870911 +CAN_MOAMR31_MIDE=1 +CAN_MOAMR3_0=0 +CAN_MOAMR3_AM=536870911 +CAN_MOAMR3_MIDE=1 +CAN_MOAMR4_0=0 +CAN_MOAMR4_AM=536870911 +CAN_MOAMR4_MIDE=1 +CAN_MOAMR5_0=0 +CAN_MOAMR5_AM=536870911 +CAN_MOAMR5_MIDE=1 +CAN_MOAMR6_0=0 +CAN_MOAMR6_AM=536870911 +CAN_MOAMR6_MIDE=1 +CAN_MOAMR7_0=0 +CAN_MOAMR7_AM=536870911 +CAN_MOAMR7_MIDE=1 +CAN_MOAMR8_0=0 +CAN_MOAMR8_AM=536870911 +CAN_MOAMR8_MIDE=1 +CAN_MOAMR9_0=0 +CAN_MOAMR9_AM=536870911 +CAN_MOAMR9_MIDE=1 +CAN_MOAR0_ID=268435457 +CAN_MOAR0_IDE=1 +CAN_MOAR0_PRI=3 +CAN_MOAR10_ID=0 +CAN_MOAR10_IDE=0 +CAN_MOAR10_PRI=3 +CAN_MOAR11_ID=0 +CAN_MOAR11_IDE=0 +CAN_MOAR11_PRI=3 +CAN_MOAR12_ID=0 +CAN_MOAR12_IDE=0 +CAN_MOAR12_PRI=3 +CAN_MOAR13_ID=0 +CAN_MOAR13_IDE=0 +CAN_MOAR13_PRI=3 +CAN_MOAR14_ID=0 +CAN_MOAR14_IDE=0 +CAN_MOAR14_PRI=3 +CAN_MOAR15_ID=0 +CAN_MOAR15_IDE=0 +CAN_MOAR15_PRI=3 +CAN_MOAR16_ID=0 +CAN_MOAR16_IDE=0 +CAN_MOAR16_PRI=3 +CAN_MOAR17_ID=0 +CAN_MOAR17_IDE=0 +CAN_MOAR17_PRI=3 +CAN_MOAR18_ID=0 +CAN_MOAR18_IDE=0 +CAN_MOAR18_PRI=3 +CAN_MOAR19_ID=0 +CAN_MOAR19_IDE=0 +CAN_MOAR19_PRI=3 +CAN_MOAR1_ID=268435458 +CAN_MOAR1_IDE=1 +CAN_MOAR1_PRI=3 +CAN_MOAR20_ID=0 +CAN_MOAR20_IDE=0 +CAN_MOAR20_PRI=3 +CAN_MOAR21_ID=0 +CAN_MOAR21_IDE=0 +CAN_MOAR21_PRI=3 +CAN_MOAR22_ID=0 +CAN_MOAR22_IDE=0 +CAN_MOAR22_PRI=3 +CAN_MOAR23_ID=0 +CAN_MOAR23_IDE=0 +CAN_MOAR23_PRI=3 +CAN_MOAR24_ID=0 +CAN_MOAR24_IDE=0 +CAN_MOAR24_PRI=3 +CAN_MOAR25_ID=0 +CAN_MOAR25_IDE=0 +CAN_MOAR25_PRI=3 +CAN_MOAR26_ID=0 +CAN_MOAR26_IDE=0 +CAN_MOAR26_PRI=3 +CAN_MOAR27_ID=0 +CAN_MOAR27_IDE=0 +CAN_MOAR27_PRI=3 +CAN_MOAR28_ID=0 +CAN_MOAR28_IDE=0 +CAN_MOAR28_PRI=3 +CAN_MOAR29_ID=0 +CAN_MOAR29_IDE=0 +CAN_MOAR29_PRI=3 +CAN_MOAR2_ID=536870911 +CAN_MOAR2_IDE=1 +CAN_MOAR2_PRI=3 +CAN_MOAR30_ID=0 +CAN_MOAR30_IDE=0 +CAN_MOAR30_PRI=3 +CAN_MOAR31_ID=0 +CAN_MOAR31_IDE=0 +CAN_MOAR31_PRI=3 +CAN_MOAR3_ID=0 +CAN_MOAR3_IDE=0 +CAN_MOAR3_PRI=3 +CAN_MOAR4_ID=0 +CAN_MOAR4_IDE=0 +CAN_MOAR4_PRI=3 +CAN_MOAR5_ID=3 +CAN_MOAR5_IDE=1 +CAN_MOAR5_PRI=3 +CAN_MOAR6_ID=285212673 +CAN_MOAR6_IDE=1 +CAN_MOAR6_PRI=3 +CAN_MOAR7_ID=285212674 +CAN_MOAR7_IDE=1 +CAN_MOAR7_PRI=3 +CAN_MOAR8_ID=285212675 +CAN_MOAR8_IDE=1 +CAN_MOAR8_PRI=3 +CAN_MOAR9_ID=536870896 +CAN_MOAR9_IDE=1 +CAN_MOAR9_PRI=3 +CAN_MOCTR0_CTRL=0 +CAN_MOCTR0_DIR=1 +CAN_MOCTR0_LIST=0 +CAN_MOCTR0_MSGLST=0 +CAN_MOCTR0_MSGVAL=0 +CAN_MOCTR0_NEWDAT=0 +CAN_MOCTR0_RTSEL=0 +CAN_MOCTR0_RXEN=0 +CAN_MOCTR0_RXPND=0 +CAN_MOCTR0_RXUPD=0 +CAN_MOCTR0_TXEN0=0 +CAN_MOCTR0_TXEN1=0 +CAN_MOCTR0_TXPND=0 +CAN_MOCTR0_TXRQ=0 +CAN_MOCTR10_CTRL=0 +CAN_MOCTR10_DIR=0 +CAN_MOCTR10_LIST=0 +CAN_MOCTR10_MSGLST=0 +CAN_MOCTR10_MSGVAL=0 +CAN_MOCTR10_NEWDAT=0 +CAN_MOCTR10_RTSEL=0 +CAN_MOCTR10_RXEN=0 +CAN_MOCTR10_RXPND=0 +CAN_MOCTR10_RXUPD=0 +CAN_MOCTR10_TXEN0=0 +CAN_MOCTR10_TXEN1=0 +CAN_MOCTR10_TXPND=0 +CAN_MOCTR10_TXRQ=0 +CAN_MOCTR11_CTRL=0 +CAN_MOCTR11_DIR=0 +CAN_MOCTR11_LIST=0 +CAN_MOCTR11_MSGLST=0 +CAN_MOCTR11_MSGVAL=0 +CAN_MOCTR11_NEWDAT=0 +CAN_MOCTR11_RTSEL=0 +CAN_MOCTR11_RXEN=0 +CAN_MOCTR11_RXPND=0 +CAN_MOCTR11_RXUPD=0 +CAN_MOCTR11_TXEN0=0 +CAN_MOCTR11_TXEN1=0 +CAN_MOCTR11_TXPND=0 +CAN_MOCTR11_TXRQ=0 +CAN_MOCTR12_CTRL=0 +CAN_MOCTR12_DIR=0 +CAN_MOCTR12_LIST=0 +CAN_MOCTR12_MSGLST=0 +CAN_MOCTR12_MSGVAL=0 +CAN_MOCTR12_NEWDAT=0 +CAN_MOCTR12_RTSEL=0 +CAN_MOCTR12_RXEN=0 +CAN_MOCTR12_RXPND=0 +CAN_MOCTR12_RXUPD=0 +CAN_MOCTR12_TXEN0=0 +CAN_MOCTR12_TXEN1=0 +CAN_MOCTR12_TXPND=0 +CAN_MOCTR12_TXRQ=0 +CAN_MOCTR13_CTRL=0 +CAN_MOCTR13_DIR=0 +CAN_MOCTR13_LIST=0 +CAN_MOCTR13_MSGLST=0 +CAN_MOCTR13_MSGVAL=0 +CAN_MOCTR13_NEWDAT=0 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+CAN_MOFCR4_TXIE=0 +CAN_MOFCR5_0=0 +CAN_MOFCR5_0=0 +CAN_MOFCR5_0=0 +CAN_MOFCR5_0=0 +CAN_MOFCR5_DATC=0 +CAN_MOFCR5_DLC=8 +CAN_MOFCR5_DLCC=0 +CAN_MOFCR5_FRREN=0 +CAN_MOFCR5_GDFS=0 +CAN_MOFCR5_IDC=0 +CAN_MOFCR5_MMC=0 +CAN_MOFCR5_OVIE=0 +CAN_MOFCR5_RMM=0 +CAN_MOFCR5_RXIE=0 +CAN_MOFCR5_SDT=0 +CAN_MOFCR5_STT=0 +CAN_MOFCR5_TXIE=0 +CAN_MOFCR6_0=0 +CAN_MOFCR6_0=0 +CAN_MOFCR6_0=0 +CAN_MOFCR6_0=0 +CAN_MOFCR6_DATC=0 +CAN_MOFCR6_DLC=8 +CAN_MOFCR6_DLCC=0 +CAN_MOFCR6_FRREN=0 +CAN_MOFCR6_GDFS=0 +CAN_MOFCR6_IDC=0 +CAN_MOFCR6_MMC=0 +CAN_MOFCR6_OVIE=0 +CAN_MOFCR6_RMM=0 +CAN_MOFCR6_RXIE=0 +CAN_MOFCR6_SDT=0 +CAN_MOFCR6_STT=0 +CAN_MOFCR6_TXIE=0 +CAN_MOFCR7_0=0 +CAN_MOFCR7_0=0 +CAN_MOFCR7_0=0 +CAN_MOFCR7_0=0 +CAN_MOFCR7_DATC=0 +CAN_MOFCR7_DLC=8 +CAN_MOFCR7_DLCC=0 +CAN_MOFCR7_FRREN=0 +CAN_MOFCR7_GDFS=0 +CAN_MOFCR7_IDC=0 +CAN_MOFCR7_MMC=0 +CAN_MOFCR7_OVIE=0 +CAN_MOFCR7_RMM=0 +CAN_MOFCR7_RXIE=0 +CAN_MOFCR7_SDT=0 +CAN_MOFCR7_STT=0 +CAN_MOFCR7_TXIE=0 +CAN_MOFCR8_0=0 +CAN_MOFCR8_0=0 +CAN_MOFCR8_0=0 +CAN_MOFCR8_0=0 +CAN_MOFCR8_DATC=0 +CAN_MOFCR8_DLC=8 +CAN_MOFCR8_DLCC=0 +CAN_MOFCR8_FRREN=0 +CAN_MOFCR8_GDFS=0 +CAN_MOFCR8_IDC=0 +CAN_MOFCR8_MMC=0 +CAN_MOFCR8_OVIE=0 +CAN_MOFCR8_RMM=0 +CAN_MOFCR8_RXIE=0 +CAN_MOFCR8_SDT=0 +CAN_MOFCR8_STT=0 +CAN_MOFCR8_TXIE=0 +CAN_MOFCR9_0=0 +CAN_MOFCR9_0=0 +CAN_MOFCR9_0=0 +CAN_MOFCR9_0=0 +CAN_MOFCR9_DATC=0 +CAN_MOFCR9_DLC=8 +CAN_MOFCR9_DLCC=0 +CAN_MOFCR9_FRREN=0 +CAN_MOFCR9_GDFS=0 +CAN_MOFCR9_IDC=0 +CAN_MOFCR9_MMC=0 +CAN_MOFCR9_OVIE=0 +CAN_MOFCR9_RMM=0 +CAN_MOFCR9_RXIE=0 +CAN_MOFCR9_SDT=0 +CAN_MOFCR9_STT=0 +CAN_MOFCR9_TXIE=0 +CAN_MOFGPR0_BOT=255 +CAN_MOFGPR0_CUR=255 +CAN_MOFGPR0_SEL=255 +CAN_MOFGPR0_TOP=255 +CAN_MOFGPR10_BOT=255 +CAN_MOFGPR10_CUR=255 +CAN_MOFGPR10_SEL=255 +CAN_MOFGPR10_TOP=255 +CAN_MOFGPR11_BOT=255 +CAN_MOFGPR11_CUR=255 +CAN_MOFGPR11_SEL=255 +CAN_MOFGPR11_TOP=255 +CAN_MOFGPR12_BOT=255 +CAN_MOFGPR12_CUR=255 +CAN_MOFGPR12_SEL=255 +CAN_MOFGPR12_TOP=255 +CAN_MOFGPR13_BOT=255 +CAN_MOFGPR13_CUR=255 +CAN_MOFGPR13_SEL=255 +CAN_MOFGPR13_TOP=255 +CAN_MOFGPR14_BOT=255 +CAN_MOFGPR14_CUR=255 +CAN_MOFGPR14_SEL=255 +CAN_MOFGPR14_TOP=255 +CAN_MOFGPR15_BOT=255 +CAN_MOFGPR15_CUR=255 +CAN_MOFGPR15_SEL=255 +CAN_MOFGPR15_TOP=255 +CAN_MOFGPR16_BOT=255 +CAN_MOFGPR16_CUR=255 +CAN_MOFGPR16_SEL=255 +CAN_MOFGPR16_TOP=255 +CAN_MOFGPR17_BOT=255 +CAN_MOFGPR17_CUR=255 +CAN_MOFGPR17_SEL=255 +CAN_MOFGPR17_TOP=255 +CAN_MOFGPR18_BOT=255 +CAN_MOFGPR18_CUR=255 +CAN_MOFGPR18_SEL=255 +CAN_MOFGPR18_TOP=255 +CAN_MOFGPR19_BOT=255 +CAN_MOFGPR19_CUR=255 +CAN_MOFGPR19_SEL=255 +CAN_MOFGPR19_TOP=255 +CAN_MOFGPR1_BOT=255 +CAN_MOFGPR1_CUR=255 +CAN_MOFGPR1_SEL=255 +CAN_MOFGPR1_TOP=255 +CAN_MOFGPR20_BOT=255 +CAN_MOFGPR20_CUR=255 +CAN_MOFGPR20_SEL=255 +CAN_MOFGPR20_TOP=255 +CAN_MOFGPR21_BOT=255 +CAN_MOFGPR21_CUR=255 +CAN_MOFGPR21_SEL=255 +CAN_MOFGPR21_TOP=255 +CAN_MOFGPR22_BOT=255 +CAN_MOFGPR22_CUR=255 +CAN_MOFGPR22_SEL=255 +CAN_MOFGPR22_TOP=255 +CAN_MOFGPR23_BOT=255 +CAN_MOFGPR23_CUR=255 +CAN_MOFGPR23_SEL=255 +CAN_MOFGPR23_TOP=255 +CAN_MOFGPR24_BOT=255 +CAN_MOFGPR24_CUR=255 +CAN_MOFGPR24_SEL=255 +CAN_MOFGPR24_TOP=255 +CAN_MOFGPR25_BOT=255 +CAN_MOFGPR25_CUR=255 +CAN_MOFGPR25_SEL=255 +CAN_MOFGPR25_TOP=255 +CAN_MOFGPR26_BOT=255 +CAN_MOFGPR26_CUR=255 +CAN_MOFGPR26_SEL=255 +CAN_MOFGPR26_TOP=255 +CAN_MOFGPR27_BOT=255 +CAN_MOFGPR27_CUR=255 +CAN_MOFGPR27_SEL=255 +CAN_MOFGPR27_TOP=255 +CAN_MOFGPR28_BOT=255 +CAN_MOFGPR28_CUR=255 +CAN_MOFGPR28_SEL=255 +CAN_MOFGPR28_TOP=255 +CAN_MOFGPR29_BOT=255 +CAN_MOFGPR29_CUR=255 +CAN_MOFGPR29_SEL=255 +CAN_MOFGPR29_TOP=255 +CAN_MOFGPR2_BOT=255 +CAN_MOFGPR2_CUR=255 +CAN_MOFGPR2_SEL=255 +CAN_MOFGPR2_TOP=255 +CAN_MOFGPR30_BOT=255 +CAN_MOFGPR30_CUR=255 +CAN_MOFGPR30_SEL=255 +CAN_MOFGPR30_TOP=255 +CAN_MOFGPR31_BOT=255 +CAN_MOFGPR31_CUR=255 +CAN_MOFGPR31_SEL=255 +CAN_MOFGPR31_TOP=255 +CAN_MOFGPR3_BOT=255 +CAN_MOFGPR3_CUR=255 +CAN_MOFGPR3_SEL=255 +CAN_MOFGPR3_TOP=255 +CAN_MOFGPR4_BOT=255 +CAN_MOFGPR4_CUR=255 +CAN_MOFGPR4_SEL=255 +CAN_MOFGPR4_TOP=255 +CAN_MOFGPR5_BOT=255 +CAN_MOFGPR5_CUR=255 +CAN_MOFGPR5_SEL=255 +CAN_MOFGPR5_TOP=255 +CAN_MOFGPR6_BOT=255 +CAN_MOFGPR6_CUR=255 +CAN_MOFGPR6_SEL=255 +CAN_MOFGPR6_TOP=255 +CAN_MOFGPR7_BOT=255 +CAN_MOFGPR7_CUR=255 +CAN_MOFGPR7_SEL=255 +CAN_MOFGPR7_TOP=255 +CAN_MOFGPR8_BOT=255 +CAN_MOFGPR8_CUR=255 +CAN_MOFGPR8_SEL=255 +CAN_MOFGPR8_TOP=255 +CAN_MOFGPR9_BOT=255 +CAN_MOFGPR9_CUR=255 +CAN_MOFGPR9_SEL=255 +CAN_MOFGPR9_TOP=255 +CAN_MOIPR0_CFCVAL=0 +CAN_MOIPR0_MPN=0 +CAN_MOIPR0_RXINP=0 +CAN_MOIPR0_TXINP=0 +CAN_MOIPR10_CFCVAL=0 +CAN_MOIPR10_MPN=10 +CAN_MOIPR10_RXINP=0 +CAN_MOIPR10_TXINP=0 +CAN_MOIPR11_CFCVAL=0 +CAN_MOIPR11_MPN=11 +CAN_MOIPR11_RXINP=0 +CAN_MOIPR11_TXINP=0 +CAN_MOIPR12_CFCVAL=0 +CAN_MOIPR12_MPN=12 +CAN_MOIPR12_RXINP=0 +CAN_MOIPR12_TXINP=0 +CAN_MOIPR13_CFCVAL=0 +CAN_MOIPR13_MPN=13 +CAN_MOIPR13_RXINP=0 +CAN_MOIPR13_TXINP=0 +CAN_MOIPR14_CFCVAL=0 +CAN_MOIPR14_MPN=14 +CAN_MOIPR14_RXINP=0 +CAN_MOIPR14_TXINP=0 +CAN_MOIPR15_CFCVAL=0 +CAN_MOIPR15_MPN=15 +CAN_MOIPR15_RXINP=0 +CAN_MOIPR15_TXINP=0 +CAN_MOIPR16_CFCVAL=0 +CAN_MOIPR16_MPN=16 +CAN_MOIPR16_RXINP=0 +CAN_MOIPR16_TXINP=0 +CAN_MOIPR17_CFCVAL=0 +CAN_MOIPR17_MPN=17 +CAN_MOIPR17_RXINP=0 +CAN_MOIPR17_TXINP=0 +CAN_MOIPR18_CFCVAL=0 +CAN_MOIPR18_MPN=18 +CAN_MOIPR18_RXINP=0 +CAN_MOIPR18_TXINP=0 +CAN_MOIPR19_CFCVAL=0 +CAN_MOIPR19_MPN=19 +CAN_MOIPR19_RXINP=0 +CAN_MOIPR19_TXINP=0 +CAN_MOIPR1_CFCVAL=0 +CAN_MOIPR1_MPN=1 +CAN_MOIPR1_RXINP=1 +CAN_MOIPR1_TXINP=0 +CAN_MOIPR20_CFCVAL=0 +CAN_MOIPR20_MPN=20 +CAN_MOIPR20_RXINP=0 +CAN_MOIPR20_TXINP=0 +CAN_MOIPR21_CFCVAL=0 +CAN_MOIPR21_MPN=21 +CAN_MOIPR21_RXINP=0 +CAN_MOIPR21_TXINP=0 +CAN_MOIPR22_CFCVAL=0 +CAN_MOIPR22_MPN=22 +CAN_MOIPR22_RXINP=0 +CAN_MOIPR22_TXINP=0 +CAN_MOIPR23_CFCVAL=0 +CAN_MOIPR23_MPN=23 +CAN_MOIPR23_RXINP=0 +CAN_MOIPR23_TXINP=0 +CAN_MOIPR24_CFCVAL=0 +CAN_MOIPR24_MPN=24 +CAN_MOIPR24_RXINP=0 +CAN_MOIPR24_TXINP=0 +CAN_MOIPR25_CFCVAL=0 +CAN_MOIPR25_MPN=25 +CAN_MOIPR25_RXINP=0 +CAN_MOIPR25_TXINP=0 +CAN_MOIPR26_CFCVAL=0 +CAN_MOIPR26_MPN=26 +CAN_MOIPR26_RXINP=0 +CAN_MOIPR26_TXINP=0 +CAN_MOIPR27_CFCVAL=0 +CAN_MOIPR27_MPN=27 +CAN_MOIPR27_RXINP=0 +CAN_MOIPR27_TXINP=0 +CAN_MOIPR28_CFCVAL=0 +CAN_MOIPR28_MPN=28 +CAN_MOIPR28_RXINP=0 +CAN_MOIPR28_TXINP=0 +CAN_MOIPR29_CFCVAL=0 +CAN_MOIPR29_MPN=29 +CAN_MOIPR29_RXINP=0 +CAN_MOIPR29_TXINP=0 +CAN_MOIPR2_CFCVAL=0 +CAN_MOIPR2_MPN=2 +CAN_MOIPR2_RXINP=0 +CAN_MOIPR2_TXINP=0 +CAN_MOIPR30_CFCVAL=0 +CAN_MOIPR30_MPN=30 +CAN_MOIPR30_RXINP=0 +CAN_MOIPR30_TXINP=0 +CAN_MOIPR31_CFCVAL=0 +CAN_MOIPR31_MPN=31 +CAN_MOIPR31_RXINP=0 +CAN_MOIPR31_TXINP=0 +CAN_MOIPR3_CFCVAL=0 +CAN_MOIPR3_MPN=3 +CAN_MOIPR3_RXINP=0 +CAN_MOIPR3_TXINP=0 +CAN_MOIPR4_CFCVAL=0 +CAN_MOIPR4_MPN=4 +CAN_MOIPR4_RXINP=0 +CAN_MOIPR4_TXINP=0 +CAN_MOIPR5_CFCVAL=0 +CAN_MOIPR5_MPN=5 +CAN_MOIPR5_RXINP=0 +CAN_MOIPR5_TXINP=0 +CAN_MOIPR6_CFCVAL=0 +CAN_MOIPR6_MPN=6 +CAN_MOIPR6_RXINP=0 +CAN_MOIPR6_TXINP=0 +CAN_MOIPR7_CFCVAL=0 +CAN_MOIPR7_MPN=7 +CAN_MOIPR7_RXINP=0 +CAN_MOIPR7_TXINP=0 +CAN_MOIPR8_CFCVAL=0 +CAN_MOIPR8_MPN=8 +CAN_MOIPR8_RXINP=0 +CAN_MOIPR8_TXINP=0 +CAN_MOIPR9_CFCVAL=0 +CAN_MOIPR9_MPN=9 +CAN_MOIPR9_RXINP=0 +CAN_MOIPR9_TXINP=0 +CAN_MSID0_INDEX=0 +CAN_MSID1_INDEX=0 +CAN_MSIMASK_IM=0 +CAN_MSPND0_PND=0 +CAN_MSPND1_PND=0 +CAN_NAME_CONFIGMSGOBJ=CAN_vConfigMsgObj +CAN_NAME_DELMSGOBJ=CAN_ubDelMsgObj +CAN_NAME_FLUSHREADFIFO=CAN_ubFlushReadFIFO +CAN_NAME_GETCANADRVALUE=CAN_ulGetCANAdrValue +CAN_NAME_GETCANDATA=CAN_ulGetCANData +CAN_NAME_GETERRORINCREMENT=CAN_ubGetErrorIncrement +CAN_NAME_GETERRORTRANSFERDIRECTION=CAN_ubGetErrorTransferDirection +CAN_NAME_GETMSGOBJ=CAN_vGetMsgObj +CAN_NAME_GETRXERRORCOUNTER=CAN_ubGetRxErrorCounter +CAN_NAME_GETTXERRORCOUNTER=CAN_ubGetTxErrorCounter +CAN_NAME_INIT=CAN_vInit +CAN_NAME_LOADDATA=CAN_vLoadData +CAN_NAME_MSGLOST=CAN_ubMsgLost +CAN_NAME_NEWDATA=CAN_ubNewData +CAN_NAME_READEN=CAN_vReadEN +CAN_NAME_READFIFO=CAN_ubReadFIFO +CAN_NAME_RELEASEOBJ=CAN_vReleaseObj +CAN_NAME_REQUESTMSGOBJ=CAN_ubRequestMsgObj +CAN_NAME_SETLISTCOMMAND=CAN_vSetListCommand +CAN_NAME_SETMSGVAL=CAN_vSetMSGVAL +CAN_NAME_SRN0=SHINT_viXINTR5Isr +CAN_NAME_SRN1=SHINT_viXINTR6Isr +CAN_NAME_SRN10= +CAN_NAME_SRN11= +CAN_NAME_SRN12= +CAN_NAME_SRN13= +CAN_NAME_SRN14=0 +CAN_NAME_SRN15=CAN_pushAMRegs/_popAMRegs +CAN_NAME_SRN2=SHINT_viXINTR6Isr +CAN_NAME_SRN3=SHINT_viXINTR9Isr +CAN_NAME_SRN4=SHINT_viXINTR10Isr +CAN_NAME_SRN5=SHINT_viXINTR11Isr +CAN_NAME_SRN6=SHINT_viXINTR12Isr +CAN_NAME_SRN7=SHINT_viXINTR13Isr +CAN_NAME_SRN8= +CAN_NAME_SRN9= +CAN_NAME_TRANSMIT=CAN_vTransmit +CAN_NAME_USERDEFINED1=0 +CAN_NAME_USERDEFINED2=0 +CAN_NAME_WRITECANADDRESS=CAN_vWriteCANAddress +CAN_NAME_WRITECANADDRESS_I=CC6_uwGetTmrPeriod +CAN_NAME_WRITECANADRVALUE=CAN_vWriteAMData +CAN_NAME_WRITECANDATA=CAN_vWriteCANData +CAN_NAME_WRITEEN=CAN_vWriteEN +CAN_NAME_WRITEFIFO=CAN_ubWriteFIFO +CAN_NBTR0_0=0 +CAN_NBTR0_BRP=47 +CAN_NBTR0_DIV8=0 +CAN_NBTR0_SJW=1 +CAN_NBTR0_TSEG1=4 +CAN_NBTR0_TSEG2=3 +CAN_NBTR1_0=0 +CAN_NBTR1_BRP=31 +CAN_NBTR1_DIV8=0 +CAN_NBTR1_SJW=1 +CAN_NBTR1_TSEG1=8 +CAN_NBTR1_TSEG2=1 +CAN_NCR0_0=0 +CAN_NCR0_ALIE=0 +CAN_NCR0_CALM=0 +CAN_NCR0_CANDIS=0 +CAN_NCR0_CCE=0 +CAN_NCR0_INIT=0 +CAN_NCR0_LECIE=0 +CAN_NCR0_TRIE=0 +CAN_NCR1_0=0 +CAN_NCR1_0=0 +CAN_NCR1_ALIE=0 +CAN_NCR1_CALM=0 +CAN_NCR1_CANDIS=0 +CAN_NCR1_CCE=0 +CAN_NCR1_INIT=1 +CAN_NCR1_LECIE=0 +CAN_NCR1_TRIE=0 +CAN_NECNT0_0=0 +CAN_NECNT0_EWRNLVL=96 +CAN_NECNT0_LEINC=0 +CAN_NECNT0_LETD=0 +CAN_NECNT0_REC=0 +CAN_NECNT0_TEC=0 +CAN_NECNT1_0=0 +CAN_NECNT1_EWRNLVL=96 +CAN_NECNT1_LEINC=0 +CAN_NECNT1_LETD=0 +CAN_NECNT1_REC=0 +CAN_NECNT1_TEC=0 +CAN_NFCR0_0=0 +CAN_NFCR0_0=0 +CAN_NFCR0_CFC=0 +CAN_NFCR0_CFCIE=0 +CAN_NFCR0_CFCOV=0 +CAN_NFCR0_CFMOD=0 +CAN_NFCR0_CFSEL=0 +CAN_NFCR1_0=0 +CAN_NFCR1_0=0 +CAN_NFCR1_CFC=0 +CAN_NFCR1_CFCIE=0 +CAN_NFCR1_CFCOV=0 +CAN_NFCR1_CFMOD=0 +CAN_NFCR1_CFSEL=0 +CAN_NIPR0_0=0 +CAN_NIPR0_ALINP=0 +CAN_NIPR0_CFCINP=0 +CAN_NIPR0_LECINP=0 +CAN_NIPR0_TRINP=0 +CAN_NIPR1_0=0 +CAN_NIPR1_ALINP=0 +CAN_NIPR1_CFCINP=0 +CAN_NIPR1_LECINP=0 +CAN_NIPR1_TRINP=0 +CAN_NOTES= +CAN_NPCR0_0=0 +CAN_NPCR0_0=0 +CAN_NPCR0_LBM=0 +CAN_NPCR0_RXSEL=0 +CAN_NPCR1_0=0 +CAN_NPCR1_0=0 +CAN_NPCR1_LBM=0 +CAN_NPCR1_RXSEL=0 +CAN_NSR0_0=0 +CAN_NSR0_ALERT=0 +CAN_NSR0_BOFF=0 +CAN_NSR0_EWRN=0 +CAN_NSR0_LEC=0 +CAN_NSR0_LLE=0 +CAN_NSR0_LOE=0 +CAN_NSR0_RXOK=0 +CAN_NSR0_TXOK=0 +CAN_NSR1_0=0 +CAN_NSR1_ALERT=0 +CAN_NSR1_BOFF=0 +CAN_NSR1_EWRN=0 +CAN_NSR1_LEC=0 +CAN_NSR1_LLE=0 +CAN_NSR1_LOE=0 +CAN_NSR1_RXOK=0 +CAN_NSR1_TXOK=0 +CAN_PANCTR_0=0 +CAN_PANCTR_BUSY=0 +CAN_PANCTR_PANAR1=0 +CAN_PANCTR_PANAR2=0 +CAN_PANCTR_PANCMD=0 +CAN_PANCTR_RBUSY=0 +CAN_REQUIREDCLOCK=0 +CAN_USE_CONFIGMSGOBJ=0 +CAN_USE_DELMSGOBJ=0 +CAN_USE_FLUSHREADFIFO=0 +CAN_USE_GETCANADRVALUE=0 +CAN_USE_GETCANDATA=0 +CAN_USE_GETERRORINCREMENT=0 +CAN_USE_GETERRORTRANSFERDIRECTION=0 +CAN_USE_GETMSGOBJ=1 +CAN_USE_GETRXERRORCOUNTER=0 +CAN_USE_GETTXERRORCOUNTER=0 +CAN_USE_INIT=1 +CAN_USE_LOADDATA=1 +CAN_USE_MSGLOST=0 +CAN_USE_NEWDATA=1 +CAN_USE_NODE0_RXD_PIN=1 +CAN_USE_NODE0_TXD_PIN=1 +CAN_USE_NODE1_RXD_PIN=0 +CAN_USE_NODE1_TXD_PIN=0 +CAN_USE_READEN=1 +CAN_USE_READFIFO=0 +CAN_USE_RELEASEOBJ=1 +CAN_USE_REQUESTMSGOBJ=1 +CAN_USE_SETLISTCOMMAND=1 +CAN_USE_SETMSGVAL=0 +CAN_USE_SRN0=0 +CAN_USE_SRN1=0 +CAN_USE_SRN10=0 +CAN_USE_SRN11=0 +CAN_USE_SRN12=0 +CAN_USE_SRN13=0 +CAN_USE_SRN14=0 +CAN_USE_SRN15=1 +CAN_USE_SRN2=0 +CAN_USE_SRN3=0 +CAN_USE_SRN4=0 +CAN_USE_SRN5=0 +CAN_USE_SRN6=0 +CAN_USE_SRN7=0 +CAN_USE_SRN8=0 +CAN_USE_SRN9=0 +CAN_USE_TRANSMIT=1 +CAN_USE_USERDEFINED1=0 +CAN_USE_USERDEFINED2=2 +CAN_USE_WRITECANADDRESS=1 +CAN_USE_WRITECANADDRESS_I=0 +CAN_USE_WRITECANADRVALUE=1 +CAN_USE_WRITECANDATA=1 +CAN_USE_WRITEEN=1 +CAN_USE_WRITEFIFO=0 +CCU6_CC60RH_CC60VH=0 +CCU6_CC60RL_CC60VL=0 +CCU6_CC60SRH_CC60SH=0 +CCU6_CC60SRL_CC60SL=0 +CCU6_CC61RH_CC61VH=0 +CCU6_CC61RL_CC61VL=0 +CCU6_CC61SRH_CC61SH=0 +CCU6_CC61SRL_CC61SL=0 +CCU6_CC62RH_CC62VH=0 +CCU6_CC62RL_CC62VL=0 +CCU6_CC62SRH_CC62SH=0 +CCU6_CC62SRL_CC62SL=0 +CCU6_CC63RH_CC63VH=0 +CCU6_CC63RL_CC63VL=0 +CCU6_CC63SRH_CC63SH=0 +CCU6_CC63SRL_CC63SL=0 +CCU6_CFILE=CC6.C +CCU6_CMPMODIFH_MCC60R=0 +CCU6_CMPMODIFH_MCC61R=0 +CCU6_CMPMODIFH_MCC62R=0 +CCU6_CMPMODIFH_MCC63R=0 +CCU6_CMPMODIFL_MCC60S=0 +CCU6_CMPMODIFL_MCC61S=0 +CCU6_CMPMODIFL_MCC62S=0 +CCU6_CMPMODIFL_MCC63S=0 +CCU6_CMPSTATH_CC60PS=0 +CCU6_CMPSTATH_CC61PS=0 +CCU6_CMPSTATH_CC62PS=0 +CCU6_CMPSTATH_COUT60PS=0 +CCU6_CMPSTATH_COUT61PS=0 +CCU6_CMPSTATH_COUT62PS=0 +CCU6_CMPSTATH_COUT63PS=0 +CCU6_CMPSTATH_T13IM=0 +CCU6_CMPSTATL_CC60ST=0 +CCU6_CMPSTATL_CC61ST=0 +CCU6_CMPSTATL_CC62ST=0 +CCU6_CMPSTATL_CC63ST=0 +CCU6_CMPSTATL_CCPOS0=0 +CCU6_CMPSTATL_CCPOS1=0 +CCU6_CMPSTATL_CCPOS2=0 +CCU6_HFILE=CC6.H +CCU6_IENH_ENCHE=0 +CCU6_IENH_ENIDLE=0 +CCU6_IENH_ENSTR=0 +CCU6_IENH_ENT13CM=0 +CCU6_IENH_ENT13PM=0 +CCU6_IENH_ENTRPF=0 +CCU6_IENH_ENWHE=0 +CCU6_IENL_ENCC60F=0 +CCU6_IENL_ENCC60R=0 +CCU6_IENL_ENCC61F=0 +CCU6_IENL_ENCC61R=0 +CCU6_IENL_ENCC62F=0 +CCU6_IENL_ENCC62R=0 +CCU6_IENL_ENT12OM=0 +CCU6_IENL_ENT12PM=0 +CCU6_INPH_INPERR=0 +CCU6_INPH_INPT12=0 +CCU6_INPH_INPT13=0 +CCU6_INPL_INPCC60=0 +CCU6_INPL_INPCC61=0 +CCU6_INPL_INPCC62=0 +CCU6_INPL_INPCHE=0 +CCU6_ISH_CHE=0 +CCU6_ISH_IDLE=0 +CCU6_ISH_STR=0 +CCU6_ISH_T13CM=0 +CCU6_ISH_T13PM=0 +CCU6_ISH_TRPF=0 +CCU6_ISH_TRPS=0 +CCU6_ISH_WHE=0 +CCU6_ISL_ICC60F=0 +CCU6_ISL_ICC60R=0 +CCU6_ISL_ICC61F=0 +CCU6_ISL_ICC61R=0 +CCU6_ISL_ICC62F=0 +CCU6_ISL_ICC62R=0 +CCU6_ISL_T12OM=0 +CCU6_ISL_T12PM=0 +CCU6_ISRH_RCHE=0 +CCU6_ISRH_RIDLE=0 +CCU6_ISRH_RSTR=0 +CCU6_ISRH_RT13CM=0 +CCU6_ISRH_RT13PM=0 +CCU6_ISRH_RTRPF=0 +CCU6_ISRH_RWHE=0 +CCU6_ISRL_RCC60F=0 +CCU6_ISRL_RCC60R=0 +CCU6_ISRL_RCC61F=0 +CCU6_ISRL_RCC61R=0 +CCU6_ISRL_RCC62F=0 +CCU6_ISRL_RCC62R=0 +CCU6_ISRL_RT12OM=0 +CCU6_ISRL_RT12PM=0 +CCU6_ISSH_SCHE=0 +CCU6_ISSH_SIDLE=0 +CCU6_ISSH_SSTR=0 +CCU6_ISSH_ST13CM=0 +CCU6_ISSH_ST13PM=0 +CCU6_ISSH_STRPF=0 +CCU6_ISSH_SWHC=0 +CCU6_ISSH_SWHE=0 +CCU6_ISSL_SCC60F=0 +CCU6_ISSL_SCC60R=0 +CCU6_ISSL_SCC61F=0 +CCU6_ISSL_SCC61R=0 +CCU6_ISSL_SCC62F=0 +CCU6_ISSL_SCC62R=0 +CCU6_ISSL_ST12OM=0 +CCU6_ISSL_ST12PM=0 +CCU6_MCMCTR_SWSEL=0 +CCU6_MCMCTR_SWSYN=0 +CCU6_MCMOUTH_CURH=0 +CCU6_MCMOUTH_EXPH=0 +CCU6_MCMOUTL_MCMP=0 +CCU6_MCMOUTL_R=0 +CCU6_MCMOUTSH_CURHS=0 +CCU6_MCMOUTSH_EXPHS=0 +CCU6_MCMOUTSH_STRHP=0 +CCU6_MCMOUTSL_MCMPS=0 +CCU6_MCMOUTSL_STRMCM=0 +CCU6_MCMPS_CC60=0 +CCU6_MCMPS_CC61=0 +CCU6_MCMPS_CC62=0 +CCU6_MCMPS_COUT60=0 +CCU6_MCMPS_COUT61=0 +CCU6_MCMPS_COUT62=0 +CCU6_MODCTRH_ECT13O=0 +CCU6_MODCTRH_T13MODEN=0 +CCU6_MODCTRL_MCMEN=0 +CCU6_MODCTRL_T12MODEN=0 +CCU6_NAME_ENABLESHADOWTRANSFER=CC6_vEnableShadowTransfer +CCU6_NAME_GETCHANNELREGISTER=CC6_uwGetChannelRegister +CCU6_NAME_GETCHANNELSHADOWREGISTER=CC6_uwGetChannelShadowRegister +CCU6_NAME_GETTMRCOUNTER=CC6_uwGetTmrCounter +CCU6_NAME_INIT=CC6_vInit +CCU6_NAME_LOADCHANNELSHADOWREGISTER=CC6_vLoadChannelShadowRegister +CCU6_NAME_NODEI0=SHINT_viXINTR10Isr +CCU6_NAME_NODEI1=SHINT_viXINTR11Isr +CCU6_NAME_NODEI2=SHINT_viXINTR12Isr +CCU6_NAME_NODEI3=SHINT_viXINTR13Isr +CCU6_NAME_RESETSTATUSBIT=CC6_vResetStatusBit +CCU6_NAME_RESETTMR=CC6_vResetTmr +CCU6_NAME_SETDEADTIMEPERIOD=CC6_vSetDeadTimePeriod +CCU6_NAME_SETSTATUSBIT=CC6_vSetStatusBit +CCU6_NAME_SETTMRCOUNTER=CC6_uwSetTmrCounter +CCU6_NAME_SETTMRPERIOD=CC6_vSetTmrPeriod +CCU6_NAME_STARTTMR=CC6_vStartTmr +CCU6_NAME_STOPTMR=CC6_vStopTmr +CCU6_NOTES= +CCU6_PAGE_OP=0 +CCU6_PAGE_PAGE=0 +CCU6_PAGE_STNR=0 +CCU6_PARA_CHANNEL_0=CC6_CHANNEL_0 +CCU6_PARA_CHANNEL_1=CC6_CHANNEL_1 +CCU6_PARA_CHANNEL_2=CC6_CHANNEL_2 +CCU6_PARA_CHANNEL_3=CC6_CHANNEL_3 +CCU6_PARA_TIMER_12=CC6_TIMER_12 +CCU6_PARA_TIMER_13=CC6_TIMER_13 +CCU6_PISEL0H_ISPOS0=0 +CCU6_PISEL0H_ISPOS1=0 +CCU6_PISEL0H_ISPOS2=0 +CCU6_PISEL0H_IST12HR=0 +CCU6_PISEL0L_ISCC60=0 +CCU6_PISEL0L_ISCC61=0 +CCU6_PISEL0L_ISCC62=0 +CCU6_PISEL0L_ISTRP=0 +CCU6_PISEL2_IST13HR=0 +CCU6_PSLR_PSL=0 +CCU6_PSLR_PSL63=0 +CCU6_PSL_CC60=0 +CCU6_PSL_CC61=0 +CCU6_PSL_CC62=0 +CCU6_PSL_COUT60=0 +CCU6_PSL_COUT61=0 +CCU6_PSL_COUT62=0 +CCU6_REQUIREDCLOCK= +CCU6_REQ_DUTY_CYCLE_0=100 +CCU6_REQ_DUTY_CYCLE_1=100 +CCU6_REQ_DUTY_CYCLE_2=100 +CCU6_REQ_DUTY_CYCLE_3=100 +CCU6_T12DTCH_DTE0=0 +CCU6_T12DTCH_DTE1=0 +CCU6_T12DTCH_DTE2=0 +CCU6_T12DTCH_DTR0=0 +CCU6_T12DTCH_DTR1=0 +CCU6_T12DTCH_DTR2=0 +CCU6_T12DTCL_DTM=1 +CCU6_T12H_T12CVH=0 +CCU6_T12L_T12CVL=0 +CCU6_T12MODEN_CC60=0 +CCU6_T12MODEN_CC61=0 +CCU6_T12MODEN_CC62=0 +CCU6_T12MODEN_COUT60=0 +CCU6_T12MODEN_COUT61=0 +CCU6_T12MODEN_COUT62=0 +CCU6_T12MSELH_DBYP=0 +CCU6_T12MSELH_HSYNC=0 +CCU6_T12MSELH_MSEL62=0 +CCU6_T12MSELL_MSEL60=0 +CCU6_T12MSELL_MSEL61=0 +CCU6_T12PRH_T12PVH=0 +CCU6_T12PRL_T12PVL=1 +CCU6_T13H_T13CVH=0 +CCU6_T13L_T13CVL=0 +CCU6_T13MODEN_CC60=0 +CCU6_T13MODEN_CC61=0 +CCU6_T13MODEN_CC62=0 +CCU6_T13MODEN_COUT60=0 +CCU6_T13MODEN_COUT61=0 +CCU6_T13MODEN_COUT62=0 +CCU6_T13PRH_T13PVH=0 +CCU6_T13PRL_T13PVL=1 +CCU6_TCTR0H_STE13=0 +CCU6_TCTR0H_T13CLK=0 +CCU6_TCTR0H_T13PRE=0 +CCU6_TCTR0H_T13R=0 +CCU6_TCTR0L_CDIR=0 +CCU6_TCTR0L_CTM=0 +CCU6_TCTR0L_STE12=0 +CCU6_TCTR0L_T12CLK=0 +CCU6_TCTR0L_T12PRE=0 +CCU6_TCTR0L_T12R=0 +CCU6_TCTR2H_T12RSEL=0 +CCU6_TCTR2H_T13RSEL=0 +CCU6_TCTR2L_T12SSC=0 +CCU6_TCTR2L_T13SSC=0 +CCU6_TCTR2L_T13TEC=0 +CCU6_TCTR2L_T13TED=0 +CCU6_TCTR4H_T13RES=0 +CCU6_TCTR4H_T13RR=0 +CCU6_TCTR4H_T13RS=0 +CCU6_TCTR4H_T13STD=0 +CCU6_TCTR4H_T13STR=0 +CCU6_TCTR4L_DTRES=0 +CCU6_TCTR4L_T12RES=0 +CCU6_TCTR4L_T12RR=0 +CCU6_TCTR4L_T12RS=0 +CCU6_TCTR4L_T12STD=0 +CCU6_TCTR4L_T12STR=0 +CCU6_TRPCTRH_TRPEN=0 +CCU6_TRPCTRH_TRPEN13=0 +CCU6_TRPCTRH_TRPPEN=0 +CCU6_TRPCTRL_TRPM0=0 +CCU6_TRPCTRL_TRPM1=0 +CCU6_TRPCTRL_TRPM2=0 +CCU6_TRPEN_CC60=0 +CCU6_TRPEN_CC61=0 +CCU6_TRPEN_CC62=0 +CCU6_TRPEN_COUT60=0 +CCU6_TRPEN_COUT61=0 +CCU6_TRPEN_COUT62=0 +CCU6_USE_#CTRAP_PIN=0 +CCU6_USE_CC60_PIN=0 +CCU6_USE_CC61_PIN=0 +CCU6_USE_CC62_PIN=0 +CCU6_USE_CCPOS0_PIN=0 +CCU6_USE_CCPOS1_PIN=0 +CCU6_USE_CCPOS2_PIN=0 +CCU6_USE_COUT60_PIN=0 +CCU6_USE_COUT61_PIN=0 +CCU6_USE_COUT62_PIN=0 +CCU6_USE_COUT63_PIN=0 +CCU6_USE_ENABLESHADOWTRANSFER=0 +CCU6_USE_GETCHANNELREGISTER=0 +CCU6_USE_GETCHANNELSHADOWREGISTER=0 +CCU6_USE_GETTMRCOUNTER=0 +CCU6_USE_INIT=0 +CCU6_USE_LOADCHANNELSHADOWREGISTER=0 +CCU6_USE_NODEI0=0 +CCU6_USE_NODEI1=0 +CCU6_USE_NODEI2=0 +CCU6_USE_NODEI3=0 +CCU6_USE_RESETSTATUSBIT=0 +CCU6_USE_RESETTMR=0 +CCU6_USE_SETDEADTIMEPERIOD=0 +CCU6_USE_SETSTATUSBIT=0 +CCU6_USE_SETTMRCOUNTER=0 +CCU6_USE_SETTMRPERIOD=0 +CCU6_USE_STARTTMR=0 +CCU6_USE_STOPTMR=0 +CCU6_USE_T12HR_PIN=0 +CCU6_USE_T13HR_PIN=0 +CD_CON_MODE=0 +CD_CON_MPS=0 +CD_CON_ROTVEC=0 +CD_CON_ST=0 +CD_CON_ST_MODE=0 +CD_CON_X_USIGN=0 +CD_CORDXH_DATAH=0 +CD_CORDXL_DATAL=0 +CD_CORDYH_DATAH=0 +CD_CORDYL_DATAL=0 +CD_CORDZH_DATAH=0 +CD_CORDZL_DATAL=0 +CD_STATC_CD_BSY=0 +CD_STATC_DMAP=0 +CD_STATC_EOC=0 +CD_STATC_ERROR=0 +CD_STATC_INT_EN=0 +CD_STATC_KEEPX=0 +CD_STATC_KEEPY=0 +CD_STATC_KEEPZ=0 +CMCON_CLKREL=0 +CMCON_FCCFG=1 +CMCON_KDIV=0 +CMCON_VCOSEL=0 +COCON_COREL=0 +COCON_COUTS=0 +COCON_TLEN=0 +DPH_DPH0=0 +DPH_DPH1=0 +DPH_DPH2=0 +DPH_DPH3=0 +DPH_DPH4=0 +DPH_DPH5=0 +DPH_DPH6=0 +DPH_DPH7=0 +DPL_DPL0=0 +DPL_DPL1=0 +DPL_DPL2=0 +DPL_DPL3=0 +DPL_DPL4=0 +DPL_DPL5=0 +DPL_DPL6=0 +DPL_DPL7=0 +EO_DPSEL0=0 +EO_TRAP_EN=0 +EXICON0_EXINT0=0 +EXICON0_EXINT1=0 +EXICON0_EXINT2=0 +EXICON0_EXINT3=0 +EXICON1_EXINT4=0 +EXICON1_EXINT5=0 +EXICON1_EXINT6=0 +EXINT0_PIN_P0.5_USED=0 +EXINT0_PIN_P1.4_USED=0 +FADC= +FDCON_BGS=0 +FDCON_BRK=0 +FDCON_EOFSYN=0 +FDCON_ERRSYN=0 +FDCON_FDEN=0 +FDCON_FDM=0 +FDCON_NDOV=0 +FDCON_SYNEN=0 +FDRES_RESULT=0 +FDSTEP_STEP=0 +FEAH_ECCERRADDR=0 +FEAL_ECCERRADDR=0 +GEN_USERDEF0=WDT_vDisable +GEN_USERDEF1=0 +GEN_USERDEF2=1 +GEN_USERDEF3=1 +HWBPDR_HWBPXX=0 +HWBPSR_BPSEL=0 +HWBPSR_BPSEL_P=0 +ID_PRODID=0 +ID_VERID=0 +IEN0_EA=1 +IEN0_ES=0 +IEN0_ET0=0 +IEN0_ET1=0 +IEN0_ET2=1 +IEN0_EX0=0 +IEN0_EX1=0 +IEN1_EADC=0 +IEN1_ECCIP0=0 +IEN1_ECCIP1=0 +IEN1_ECCIP2=0 +IEN1_ECCIP3=0 +IEN1_ESSC=0 +IEN1_EX2=0 +IEN1_EXM=0 +INTR_MSGEN=1 +IO_CFILE=IO.C +IO_HFILE=IO.H +IO_NAME_INIT=IO_vInit +IO_NAME_READPIN=IO_ubReadPin +IO_NAME_READPORT=IO_ubReadPort +IO_NAME_RESETPIN=IO_vResetPin +IO_NAME_SETINPUT=IO_vSetInput +IO_NAME_SETOUTPUT=IO_vSetOutput +IO_NAME_SETPIN=IO_vSetPin +IO_NAME_TOGGLEPIN=IO_vTogglePin +IO_NAME_WRITEPORT=IO_vWritePort +IO_NOTES= +IO_USE_INIT=1 +IO_USE_READPIN=1 +IO_USE_READPORT=0 +IO_USE_RESETPIN=1 +IO_USE_SETINPUT=0 +IO_USE_SETOUTPUT=0 +IO_USE_SETPIN=1 +IO_USE_TOGGLEPIN=1 +IO_USE_WRITEPORT=0 +IP1_PADC=0 +IP1_PCCIP0=0 +IP1_PCCIP1=0 +IP1_PCCIP2=0 +IP1_PCCIP3=0 +IP1_PSSC=0 +IP1_PX2=0 +IP1_PXM=0 +IPH1_PADCH=0 +IPH1_PCCIP0H=0 +IPH1_PCCIP1H=0 +IPH1_PCCIP2H=0 +IPH1_PCCIP3H=0 +IPH1_PSSCH=0 +IPH1_PX2H=0 +IPH1_PXMH=0 +IPH_PSH=0 +IPH_PT0H=0 +IPH_PT1H=0 +IPH_PT2H=0 +IPH_PX0H=0 +IPH_PX1H=0 +IP_PS=0 +IP_PT0=0 +IP_PT1=0 +IP_PT2=0 +IP_PX0=0 +IP_PX1=0 +IRCON0_EXINT0=0 +IRCON0_EXINT1=0 +IRCON0_EXINT2=0 +IRCON0_EXINT3=0 +IRCON0_EXINT4=0 +IRCON0_EXINT5=0 +IRCON0_EXINT6=0 +IRCON1_ADCSR0=0 +IRCON1_ADCSR1=0 +IRCON1_CANSRC1=0 +IRCON1_CANSRC2=0 +IRCON1_EIR=0 +IRCON1_RIR=0 +IRCON1_TIR=0 +IRCON2_CANSRC0=0 +IRCON2_CANSRC3=0 +IRCON3_CANSRC4=0 +IRCON3_CANSRC5=0 +IRCON3_CCU6SR0=0 +IRCON3_CCU6SR1=0 +IRCON4_CANSRC6=0 +IRCON4_CANSRC7=0 +IRCON4_CCU6SR2=0 +IRCON4_CCU6SR3=0 +IR_CFILE=INT.C +IR_HFILE=INT.H +IR_NAME_DISABLEALL=INT_vDisableAll +IR_NAME_DISABLEINTERRUPT=INT_vDisableInterrupt +IR_NAME_ENABLEALL=INT_vEnableAll +IR_NAME_ENABLEINTERRUPT=INT_vEnableInterrupt +IR_NAME_INIT=INT_vInit +IR_NAME_ISREXT0=INT_viExt0 +IR_NAME_ISREXT1=INT_viExt1 +IR_NAME_ISREXT2=SHINT_viXINTR8Isr +IR_NAME_ISREXT3=SHINT_viXINTR9Isr +IR_NAME_ISRNMI=INT_viNmiIsr +IR_NOTES= +IR_PARA_ADC_INT= +IR_PARA_CCU6_NODE0_INT= +IR_PARA_CCU6_NODE1_INT= +IR_PARA_CCU6_NODE2_INT= +IR_PARA_CCU6_NODE3_INT= +IR_PARA_EXTERNAL_INT0=EXTERNAL_INT0 +IR_PARA_EXTERNAL_INT1=EXTERNAL_INT1 +IR_PARA_EXTERNAL_INT2= +IR_PARA_EXTERNAL_INT3= +IR_PARA_SSC_INT=SSC_INT +IR_PARA_T0_INT=T0_INT +IR_PARA_T1_INT=T1_INT +IR_PARA_T2_OVERFLOW_INT= +IR_PARA_UART_INT=UART_INT +IR_PARA_XINTR10_INT=XINTR10_INT +IR_PARA_XINTR11_INT=XINTR11_INT +IR_PARA_XINTR12_INT=XINTR12_INT +IR_PARA_XINTR13_INT=XINTR13_INT +IR_PARA_XINTR5_INT=XINTR5_INT +IR_PARA_XINTR6_INT=XINTR6_INT +IR_PARA_XINTR8_INT=XINTR8_INT +IR_PARA_XINTR9_INT=XINTR9_INT +IR_PRIOR= +IR_USE_DISABLEALL=0 +IR_USE_DISABLEINTERRUPT=0 +IR_USE_ENABLEALL=0 +IR_USE_ENABLEINTERRUPT=0 +IR_USE_INIT=0 +IR_USE_ISREXT0=0 +IR_USE_ISREXT1=0 +IR_USE_ISREXT2=0 +IR_USE_ISREXT3=0 +IR_USE_ISRNMI=0 +ISR_CHOICE=2 +MAIN_CCLK=24 +MAIN_CFILE=MAIN.C +MAIN_CLKOUT= +MAIN_CLK_USERDEF0=0 +MAIN_CLK_USERDEF1=0 +MAIN_CLK_USERDEF2=0 +MAIN_COMPILER=Keil +MAIN_CPU_MEM= +MAIN_CPU_TYPE=XC886CLM-8FF +MAIN_EXTOSC=8 +MAIN_EXTOSC_MAX=12 +MAIN_EXTOSC_MIN=3 +MAIN_FCLK= +MAIN_FOSC=8 +MAIN_FSYS=96 +MAIN_FSYS_MAX=96 +MAIN_FSYS_MIN=80 +MAIN_HFILE=MAIN.H +MAIN_KEILSTARTUP=0 +MAIN_MEMORY=COMPACT +MAIN_MEM_SIZE=32 K +MAIN_MEM_TYPE=FLASH +MAIN_NAME_INIT=MAIN_vInit +MAIN_NAME_MAIN=main +MAIN_NOTES= +MAIN_ONCHIPOSC=9.6 +MAIN_PCLK=24 +MAIN_ROM_SIZE= - +MAIN_USERDEF0=0 +MAIN_USERDEF1=0 +MDU_MD0_DATA=0 +MDU_MD1_DATA=0 +MDU_MD2_DATA=0 +MDU_MD3_DATA=0 +MDU_MD4_DATA=0 +MDU_MD5_DATA=0 +MDU_MDUCON_IE=0 +MDU_MDUCON_IR=0 +MDU_MDUCON_OPCODE=0 +MDU_MDUCON_RSEL=0 +MDU_MDUCON_START=0 +MDU_MDUSTAT_IERR=0 +MDU_MDUSTAT_IRDY=0 +MDU_MDUSTAT_MDU_BSY=0 +MDU_MR0_DATA=0 +MDU_MR1_DATA=0 +MDU_MR2_DATA=0 +MDU_MR3_DATA=0 +MDU_MR4_DATA=0 +MDU_MR5_DATA=0 +MISC_CON_DFLASHEN=0 +MMBPCR_HWB0C=0 +MMBPCR_HWB1C=0 +MMBPCR_HWB2C=0 +MMBPCR_HWB3C=0 +MMBPCR_SWBC=0 +MMCR2_ALTDI=0 +MMCR2_DSUSP=0 +MMCR2_EXBC=0 +MMCR2_JENA=0 +MMCR2_MBCON=0 +MMCR2_MMEP=0 +MMCR2_MMODE=0 +MMCR2_STMODE=0 +MMCR_MEXIT=0 +MMCR_MEXIT_P=0 +MMCR_MRAMS=0 +MMCR_MRAMS_P=0 +MMCR_MSTEP=0 +MMCR_RRF=0 +MMCR_TRF=0 +MMDR_MMRR=0 +MMICR_COMRST=0 +MMICR_DRETR=0 +MMICR_DVECT=0 +MMICR_MMUIE=0 +MMICR_MMUIE_P=0 +MMICR_MSTSEL=0 +MMICR_RRIE=0 +MMICR_RRIE_P=0 +MMSR_EXBF=0 +MMSR_HWB0F=0 +MMSR_HWB1F=0 +MMSR_HWB2F=0 +MMSR_HWB3F=0 +MMSR_MBCAM=0 +MMSR_MBCIN=0 +MMSR_SWBF=0 +MMWR1_MMWR1=0 +MMWR2_MMWR2=0 +MODPISEL1_EXINT6IS=0 +MODPISEL1_JTAGTCKS1=0 +MODPISEL1_JTAGTDIS1=0 +MODPISEL1_T21EXIS=0 +MODPISEL1_UR1RIS=0 +MODPISEL2_T0IS=0 +MODPISEL2_T1IS=0 +MODPISEL2_T21IS=0 +MODPISEL2_T2IS=0 +MODPISEL_EXINT0IS=0 +MODPISEL_EXINT1IS=0 +MODPISEL_EXINT2IS=0 +MODPISEL_JTAGTCKS=0 +MODPISEL_JTAGTDIS=0 +MODPISEL_URRIS=0 +MODPISEL_URRISH=0 +MODSUSP_T12SUSP=0 +MODSUSP_T13SUSP=0 +MODSUSP_T21SUSP=0 +MODSUSP_T2SUSP=0 +MODSUSP_WDTSUSP=0 +MUXFOR_#CTRAP_0=0 +MUXFOR_#CTRAP_1=0 +MUXFOR_#CTRAP_2=0 +MUXFOR_AN0=0 +MUXFOR_AN1=0 +MUXFOR_AN2=0 +MUXFOR_AN3=0 +MUXFOR_AN4=0 +MUXFOR_AN5=0 +MUXFOR_AN6=0 +MUXFOR_AN7=0 +MUXFOR_CC60_0(INPUT)=0 +MUXFOR_CC60_0(OUTPUT)=0 +MUXFOR_CC60_1=0 +MUXFOR_CC60_3(INPUT)=0 +MUXFOR_CC60_3(INPUT)=0 +MUXFOR_CC61_0(INPUT)=0 +MUXFOR_CC61_0(OUTPUT)=0 +MUXFOR_CC61_1(INPUT)=0 +MUXFOR_CC61_1(OUTPUT)=0 +MUXFOR_CC61_2(INPUT)=0 +MUXFOR_CC61_2(INPUT)=0 +MUXFOR_CC61_2(OUTPUT)=0 +MUXFOR_CC61_2(OUTPUT)=0 +MUXFOR_CC61_3(INPUT)=0 +MUXFOR_CC61_3(INPUT)=0 +MUXFOR_CC62_0(INPUT)=0 +MUXFOR_CC62_0(OUTPUT)=0 +MUXFOR_CC62_1(INPUT)=0 +MUXFOR_CC62_1(OUTPUT)=0 +MUXFOR_CC62_3(INPUT)=0 +MUXFOR_CC62_3(INPUT)=0 +MUXFOR_CC62_3(INPUT)=0 +MUXFOR_CCPOS0_0=0 +MUXFOR_CCPOS0_1=0 +MUXFOR_CCPOS0_2=0 +MUXFOR_CCPOS1_0=0 +MUXFOR_CCPOS1_1=0 +MUXFOR_CCPOS1_2=0 +MUXFOR_CCPOS2_0=0 +MUXFOR_CCPOS2_1=0 +MUXFOR_CCPOS2_2=0 +MUXFOR_CLKOUT=0 +MUXFOR_CLKOUT_1=0 +MUXFOR_COUT60_0=0 +MUXFOR_COUT60_1=0 +MUXFOR_COUT61_0=0 +MUXFOR_COUT61_1=0 +MUXFOR_COUT62_0=0 +MUXFOR_COUT62_1=0 +MUXFOR_COUT63_0=0 +MUXFOR_COUT63_1=0 +MUXFOR_COUT63_2=0 +MUXFOR_EXF21_0=0 +MUXFOR_EXF21_1=0 +MUXFOR_EXF2_0=0 +MUXFOR_EXF2_1=0 +MUXFOR_EXINT0_0=0 +MUXFOR_EXINT0_0_(GATE)=0 +MUXFOR_EXINT0_0_(WAKE-UP)=0 +MUXFOR_EXINT0_1=0 +MUXFOR_EXINT1=0 +MUXFOR_EXINT1_(GATE)=0 +MUXFOR_EXINT2=0 +MUXFOR_EXINT3=0 +MUXFOR_EXINT4=0 +MUXFOR_EXINT5=0 +MUXFOR_EXINT6=0 +MUXFOR_MRST_0(MASTER_RECEIVE)=0 +MUXFOR_MRST_0(SLAVE_TRANSMIT)=0 +MUXFOR_MRST_1(MASTER_RECEIVE)=0 +MUXFOR_MRST_1(SLAVE_TRANSMIT)=0 +MUXFOR_MTSR_0(MASTER_TRANSMIT)=0 +MUXFOR_MTSR_0(SLAVE_RECEIVE)=0 +MUXFOR_MTSR_1(MASTER_TRANSMIT)=0 +MUXFOR_MTSR_1(SLAVE_RECEIVE)=0 +MUXFOR_P0_0=2 +MUXFOR_P0_1=2 +MUXFOR_P0_2=2 +MUXFOR_P0_3=2 +MUXFOR_P0_4=0 +MUXFOR_P0_5=0 +MUXFOR_P0_6=0 +MUXFOR_P0_7=2 +MUXFOR_P1_0=0 +MUXFOR_P1_1=0 +MUXFOR_P1_2=1 +MUXFOR_P1_3=1 +MUXFOR_P1_4=1 +MUXFOR_P1_5=1 +MUXFOR_P1_6=0 +MUXFOR_P1_7=2 +MUXFOR_P2_0=0 +MUXFOR_P2_1=0 +MUXFOR_P2_2=0 +MUXFOR_P2_3=0 +MUXFOR_P2_4=1 +MUXFOR_P2_5=1 +MUXFOR_P2_6=1 +MUXFOR_P2_7=1 +MUXFOR_P3_0=1 +MUXFOR_P3_1=1 +MUXFOR_P3_2=2 +MUXFOR_P3_3=2 +MUXFOR_P3_4=2 +MUXFOR_P3_5=2 +MUXFOR_P3_6=1 +MUXFOR_P3_7=1 +MUXFOR_P4_0=2 +MUXFOR_P4_1=2 +MUXFOR_P4_2=0 +MUXFOR_P4_3=1 +MUXFOR_RSTIND=0 +MUXFOR_RXD1_0=0 +MUXFOR_RXD1_1=0 +MUXFOR_RXDC0_0=1 +MUXFOR_RXDC0_1=0 +MUXFOR_RXDC0_2=0 +MUXFOR_RXDC0_3=0 +MUXFOR_RXDC1_0=0 +MUXFOR_RXDC1_1=0 +MUXFOR_RXDC1_3=0 +MUXFOR_RXDO1_0=0 +MUXFOR_RXDO1_1=0 +MUXFOR_RXDO_0=0 +MUXFOR_RXDO_1=0 +MUXFOR_RXD_0=0 +MUXFOR_RXD_0_(WAKE-UP)=0 +MUXFOR_RXD_1=0 +MUXFOR_RXD_1_(WAKE-UP)=0 +MUXFOR_SCK_0(INPUT)=0 +MUXFOR_SCK_0(OUTPUT)=0 +MUXFOR_SCK_1(INPUT)=0 +MUXFOR_SCK_1(OUTPUT)=0 +MUXFOR_T0_1=0 +MUXFOR_T12HR_0=0 +MUXFOR_T12HR_1=0 +MUXFOR_T12HR_2=0 +MUXFOR_T13HR_0=0 +MUXFOR_T13HR_1=0 +MUXFOR_T13HR_2=0 +MUXFOR_T1_1=0 +MUXFOR_T21_1=0 +MUXFOR_T2EX=0 +MUXFOR_T2EX1_0=0 +MUXFOR_T2EX1_1=0 +MUXFOR_T2_1=0 +MUXFOR_TCK_0=0 +MUXFOR_TCK_1=0 +MUXFOR_TDI_0=0 +MUXFOR_TDI_1=0 +MUXFOR_TDO_0=0 +MUXFOR_TDO_1=0 +MUXFOR_TXD1_0=0 +MUXFOR_TXD1_1=0 +MUXFOR_TXDC0_0=2 +MUXFOR_TXDC0_1=0 +MUXFOR_TXDC0_2=0 +MUXFOR_TXDC0_3=0 +MUXFOR_TXDC1_0=0 +MUXFOR_TXDC1_1=0 +MUXFOR_TXDC1_3=0 +MUXFOR_TXD_0=0 +MUXFOR_TXD_1=0 +NMICON_NMIECC=0 +NMICON_NMIFLASH=0 +NMICON_NMIOCDS=0 +NMICON_NMIPLL=0 +NMICON_NMIVDD=0 +NMICON_NMIVDDP=0 +NMICON_NMIWDT=0 +NMISR_FNMIECC=0 +NMISR_FNMIFLASH=0 +NMISR_FNMIOCDS=0 +NMISR_FNMIPLL=0 +NMISR_FNMIVDD=0 +NMISR_FNMIVDDP=0 +NMISR_FNMIWDT=0 +OSC_CON_ORDRES=0 +OSC_CON_OSCPD=0 +OSC_CON_OSCR=0 +OSC_CON_OSCSS=1 +OSC_CON_XPD=1 +P0_ALTSEL0_P0=0 +P0_ALTSEL0_P1=0 +P0_ALTSEL0_P2=0 +P0_ALTSEL0_P3=0 +P0_ALTSEL0_P4=0 +P0_ALTSEL0_P5=0 +P0_ALTSEL0_P6=0 +P0_ALTSEL0_P7=0 +P0_ALTSEL1_P0=0 +P0_ALTSEL1_P1=0 +P0_ALTSEL1_P2=0 +P0_ALTSEL1_P3=0 +P0_ALTSEL1_P4=0 +P0_ALTSEL1_P5=0 +P0_ALTSEL1_P6=0 +P0_ALTSEL1_P7=0 +P0_DATA_P0=0 +P0_DATA_P1=0 +P0_DATA_P2=0 +P0_DATA_P3=0 +P0_DATA_P4=0 +P0_DATA_P5=0 +P0_DATA_P6=0 +P0_DATA_P7=0 +P0_DIR_P0=1 +P0_DIR_P1=1 +P0_DIR_P2=1 +P0_DIR_P3=1 +P0_DIR_P4=0 +P0_DIR_P5=0 +P0_DIR_P6=0 +P0_DIR_P7=1 +P0_NAME_P0_0=P0_0 +P0_NAME_P0_1=P0_1 +P0_NAME_P0_2=P0_2 +P0_NAME_P0_3=P0_3 +P0_NAME_P0_4=P0_4 +P0_NAME_P0_5=P0_5 +P0_NAME_P0_6= +P0_NAME_P0_7=P0_7 +P0_NOTES= +P0_OD_P0=0 +P0_OD_P1=0 +P0_OD_P2=0 +P0_OD_P3=0 +P0_OD_P4=0 +P0_OD_P5=0 +P0_OD_P6=0 +P0_OD_P7=0 +P0_PUDEN_P0=1 +P0_PUDEN_P1=1 +P0_PUDEN_P2=1 +P0_PUDEN_P3=1 +P0_PUDEN_P4=0 +P0_PUDEN_P5=0 +P0_PUDEN_P6=1 +P0_PUDEN_P7=1 +P0_PUDSEL_P0=0 +P0_PUDSEL_P1=0 +P0_PUDSEL_P2=0 +P0_PUDSEL_P3=0 +P0_PUDSEL_P4=1 +P0_PUDSEL_P5=1 +P0_PUDSEL_P6=1 +P0_PUDSEL_P7=0 +P1_ALTSEL0_P0=0 +P1_ALTSEL0_P1=1 +P1_ALTSEL0_P2=0 +P1_ALTSEL0_P3=0 +P1_ALTSEL0_P4=0 +P1_ALTSEL0_P5=0 +P1_ALTSEL0_P6=0 +P1_ALTSEL0_P7=0 +P1_ALTSEL1_P0=0 +P1_ALTSEL1_P1=1 +P1_ALTSEL1_P2=0 +P1_ALTSEL1_P3=0 +P1_ALTSEL1_P4=0 +P1_ALTSEL1_P5=0 +P1_ALTSEL1_P6=0 +P1_ALTSEL1_P7=0 +P1_DATA_P0=0 +P1_DATA_P1=0 +P1_DATA_P2=0 +P1_DATA_P3=0 +P1_DATA_P4=0 +P1_DATA_P5=0 +P1_DATA_P6=0 +P1_DATA_P7=0 +P1_DIR_P0=0 +P1_DIR_P1=1 +P1_DIR_P2=0 +P1_DIR_P3=0 +P1_DIR_P4=0 +P1_DIR_P5=0 +P1_DIR_P6=0 +P1_DIR_P7=1 +P1_NAME_P1_0=P1_0 +P1_NAME_P1_1=P1_1 +P1_NAME_P1_2=P1_2 +P1_NAME_P1_3=P1_3 +P1_NAME_P1_4=P1_4 +P1_NAME_P1_5=P1_5 +P1_NAME_P1_6=P1_6 +P1_NAME_P1_7=P1_7 +P1_NOTES= +P1_OD_P0=0 +P1_OD_P1=0 +P1_OD_P2=0 +P1_OD_P3=0 +P1_OD_P4=0 +P1_OD_P5=0 +P1_OD_P6=0 +P1_OD_P7=0 +P1_PUDEN_P0=1 +P1_PUDEN_P1=1 +P1_PUDEN_P2=0 +P1_PUDEN_P3=0 +P1_PUDEN_P4=0 +P1_PUDEN_P5=0 +P1_PUDEN_P6=1 +P1_PUDEN_P7=1 +P1_PUDSEL_P0=1 +P1_PUDSEL_P1=1 +P1_PUDSEL_P2=1 +P1_PUDSEL_P3=1 +P1_PUDSEL_P4=1 +P1_PUDSEL_P5=1 +P1_PUDSEL_P6=1 +P1_PUDSEL_P7=0 +P2_DATA_P0=0 +P2_DATA_P1=0 +P2_DATA_P2=0 +P2_DATA_P3=0 +P2_DATA_P4=0 +P2_DATA_P5=0 +P2_DATA_P6=0 +P2_DATA_P7=0 +P2_DIR_P0=0 +P2_DIR_P1=0 +P2_DIR_P2=0 +P2_DIR_P3=0 +P2_DIR_P4=0 +P2_DIR_P5=0 +P2_DIR_P6=0 +P2_DIR_P7=0 +P2_NAME_P2_0=P2_0 +P2_NAME_P2_1=P2_1 +P2_NAME_P2_2=P2_2 +P2_NAME_P2_3=P2_3 +P2_NAME_P2_4=P2_4 +P2_NAME_P2_5=P2_5 +P2_NAME_P2_6=P2_6 +P2_NAME_P2_7=P2_7 +P2_NOTES= +P2_PUDEN_P0=0 +P2_PUDEN_P1=0 +P2_PUDEN_P2=0 +P2_PUDEN_P3=0 +P2_PUDEN_P4=1 +P2_PUDEN_P5=1 +P2_PUDEN_P6=1 +P2_PUDEN_P7=1 +P2_PUDSEL_P0=1 +P2_PUDSEL_P1=1 +P2_PUDSEL_P2=1 +P2_PUDSEL_P3=1 +P2_PUDSEL_P4=1 +P2_PUDSEL_P5=1 +P2_PUDSEL_P6=1 +P2_PUDSEL_P7=1 +P3_ALTSEL0_P0=0 +P3_ALTSEL0_P1=0 +P3_ALTSEL0_P2=0 +P3_ALTSEL0_P3=0 +P3_ALTSEL0_P4=0 +P3_ALTSEL0_P5=0 +P3_ALTSEL0_P6=0 +P3_ALTSEL0_P7=0 +P3_ALTSEL1_P0=0 +P3_ALTSEL1_P1=0 +P3_ALTSEL1_P2=0 +P3_ALTSEL1_P3=0 +P3_ALTSEL1_P4=0 +P3_ALTSEL1_P5=0 +P3_ALTSEL1_P6=0 +P3_ALTSEL1_P7=0 +P3_DATA_P0=0 +P3_DATA_P1=0 +P3_DATA_P2=0 +P3_DATA_P3=0 +P3_DATA_P4=0 +P3_DATA_P5=0 +P3_DATA_P6=0 +P3_DATA_P7=0 +P3_DIR_P0=0 +P3_DIR_P1=0 +P3_DIR_P2=1 +P3_DIR_P3=1 +P3_DIR_P4=1 +P3_DIR_P5=1 +P3_DIR_P6=0 +P3_DIR_P7=0 +P3_NAME_P3_0=P3_0 +P3_NAME_P3_1=P3_1 +P3_NAME_P3_2=P3_2 +P3_NAME_P3_3=P3_3 +P3_NAME_P3_4=P3_4 +P3_NAME_P3_5=P3_5 +P3_NAME_P3_6=P3_6 +P3_NAME_P3_7=P3_7 +P3_NOTES= +P3_OD_P0=0 +P3_OD_P1=0 +P3_OD_P2=1 +P3_OD_P3=1 +P3_OD_P4=1 +P3_OD_P5=1 +P3_OD_P6=0 +P3_OD_P7=0 +P3_PUDEN_P0=1 +P3_PUDEN_P1=1 +P3_PUDEN_P2=0 +P3_PUDEN_P3=0 +P3_PUDEN_P4=0 +P3_PUDEN_P5=0 +P3_PUDEN_P6=0 +P3_PUDEN_P7=1 +P3_PUDSEL_P0=1 +P3_PUDSEL_P1=1 +P3_PUDSEL_P2=1 +P3_PUDSEL_P3=1 +P3_PUDSEL_P4=1 +P3_PUDSEL_P5=1 +P3_PUDSEL_P6=1 +P3_PUDSEL_P7=1 +P4_ALTSEL0_P0=0 +P4_ALTSEL0_P1=0 +P4_ALTSEL0_P2=0 +P4_ALTSEL0_P3=0 +P4_ALTSEL0_P4=0 +P4_ALTSEL0_P5=0 +P4_ALTSEL0_P6=0 +P4_ALTSEL0_P7=0 +P4_ALTSEL1_P0=0 +P4_ALTSEL1_P1=0 +P4_ALTSEL1_P2=0 +P4_ALTSEL1_P3=0 +P4_ALTSEL1_P4=0 +P4_ALTSEL1_P5=0 +P4_ALTSEL1_P6=0 +P4_ALTSEL1_P7=0 +P4_DATA_P0=0 +P4_DATA_P1=0 +P4_DATA_P2=0 +P4_DATA_P3=0 +P4_DATA_P4=0 +P4_DATA_P5=0 +P4_DATA_P6=0 +P4_DATA_P7=0 +P4_DIR_P0=1 +P4_DIR_P1=1 +P4_DIR_P2=0 +P4_DIR_P3=0 +P4_DIR_P4=0 +P4_DIR_P5=0 +P4_DIR_P6=0 +P4_DIR_P7=0 +P4_NAME_P4_0=P4_0 +P4_NAME_P4_1=P4_1 +P4_NAME_P4_2= +P4_NAME_P4_3=P4_3 +P4_NOTES= +P4_OD_P0=0 +P4_OD_P1=0 +P4_OD_P2=0 +P4_OD_P3=0 +P4_OD_P4=0 +P4_OD_P5=0 +P4_OD_P6=0 +P4_OD_P7=0 +P4_PUDEN_P0=1 +P4_PUDEN_P1=1 +P4_PUDEN_P2=1 +P4_PUDEN_P3=0 +P4_PUDEN_P4=0 +P4_PUDEN_P5=0 +P4_PUDEN_P6=0 +P4_PUDEN_P7=0 +P4_PUDSEL_P0=0 +P4_PUDSEL_P1=0 +P4_PUDSEL_P2=1 +P4_PUDSEL_P3=1 +P4_PUDSEL_P4=1 +P4_PUDSEL_P5=1 +P4_PUDSEL_P6=1 +P4_PUDSEL_P7=1 +P5_ALTSEL0_P0=0 +P5_ALTSEL0_P1=0 +P5_ALTSEL0_P2=0 +P5_ALTSEL0_P3=0 +P5_ALTSEL0_P4=0 +P5_ALTSEL0_P5=0 +P5_ALTSEL0_P6=0 +P5_ALTSEL0_P7=0 +P5_ALTSEL1_P0=0 +P5_ALTSEL1_P1=0 +P5_ALTSEL1_P2=0 +P5_ALTSEL1_P3=0 +P5_ALTSEL1_P4=0 +P5_ALTSEL1_P5=0 +P5_ALTSEL1_P6=0 +P5_ALTSEL1_P7=0 +P5_DATA_P0=0 +P5_DATA_P1=0 +P5_DATA_P2=0 +P5_DATA_P3=0 +P5_DATA_P4=0 +P5_DATA_P5=0 +P5_DATA_P6=0 +P5_DATA_P7=0 +P5_DIR_P0=0 +P5_DIR_P1=0 +P5_DIR_P2=0 +P5_DIR_P3=0 +P5_DIR_P4=0 +P5_DIR_P5=0 +P5_DIR_P6=0 +P5_DIR_P7=0 +P5_OD_P0=0 +P5_OD_P1=0 +P5_OD_P2=0 +P5_OD_P3=0 +P5_OD_P4=0 +P5_OD_P5=0 +P5_OD_P6=0 +P5_OD_P7=0 +P5_PUDEN_P0=0 +P5_PUDEN_P1=0 +P5_PUDEN_P2=0 +P5_PUDEN_P3=0 +P5_PUDEN_P4=0 +P5_PUDEN_P5=0 +P5_PUDEN_P6=0 +P5_PUDEN_P7=0 +P5_PUDSEL_P0=0 +P5_PUDSEL_P1=0 +P5_PUDSEL_P2=0 +P5_PUDSEL_P3=0 +P5_PUDSEL_P4=0 +P5_PUDSEL_P5=0 +P5_PUDSEL_P6=0 +P5_PUDSEL_P7=0 +PASSWD_MODE=0 +PASSWD_PASS=0 +PASSWD_PROTECT_S=0 +PCON_GF0=0 +PCON_GF1=0 +PCON_IDLE=0 +PCON_SMOD=0 +PLL_CON_LOCK=0 +PLL_CON_NDIV=10 +PLL_CON_OSCDISC=0 +PLL_CON_RESLD=0 +PLL_CON_VCOBYP=0 +PLL_CTRL=4 +PMCON0_PD=0 +PMCON0_SD=0 +PMCON0_WDTRST=0 +PMCON0_WKRS=0 +PMCON0_WKSEL=0 +PMCON0_WS=0 +PMCON1_ADC_DIS=0 +PMCON1_CAN_DIS=0 +PMCON1_CCU_DIS=0 +PMCON1_CDC_DIS=0 +PMCON1_MDU_DIS=0 +PMCON1_SSC_DIS=1 +PMCON1_T2_DIS=0 +PMCON2_T21_DIS=0 +PMCON2_UART1_DIS=0 +PORT_PAGE_OP=0 +PORT_PAGE_PAGE=0 +PORT_PAGE_STNR=0 +PSW_AC=0 +PSW_CY=0 +PSW_F0=0 +PSW_F1=0 +PSW_OV=0 +PSW_P=0 +PSW_RS0=0 +PSW_RS1=0 +PS_CFILE=PS.C +PS_HFILE=PS.H +PS_NAME_DISABLEMODULE=PS_vDisableModule +PS_NAME_ENABLEMODULE=PS_vEnableModule +PS_NAME_INIT=PS_vInit +PS_NAME_RESETSLOWDOWN=PS_vResetSlowDown +PS_NAME_SETIDLE=PS_vSetIdle +PS_NAME_SETPOWERDOWN=PS_vSetPowerDown +PS_NAME_SETSLOWDOWN=PS_vSetSlowDown +PS_NAME_WAKEUP= +PS_NOTES= +PS_PARA_MODULE_ADC=ADC +PS_PARA_MODULE_CAN=CAN +PS_PARA_MODULE_CCU=CCU +PS_PARA_MODULE_CDC=CDC +PS_PARA_MODULE_MDU=MDU +PS_PARA_MODULE_SSC=SSC +PS_PARA_MODULE_T2=T2 +PS_PARA_MODULE_T21=T21 +PS_PARA_MODULE_UART1=UART1 +PS_PIN_EX_0_USED=0 +PS_PIN_EX_1_USED=0 +PS_PIN_RXEX0_0_USED=0 +PS_PIN_RXEX0_1_USED= +PS_PIN_RXEX1_0_USED=0 +PS_PIN_RX_0_USED=0 +PS_PIN_RX_1_USED=0 +PS_USE_DISABLEMODULE=0 +PS_USE_ENABLEMODULE=0 +PS_USE_INIT=0 +PS_USE_RESETSLOWDOWN=0 +PS_USE_SETIDLE=0 +PS_USE_SETIDLESLOWDOWN= +PS_USE_SETPOWERDOWN=0 +PS_USE_SETSLOWDOWN=0 +PS_USE_SLOWDOWNACTIVE= +PS_USE_WAKEUP=0 +SBUF_VAL=0 +SCON_RB8=0 +SCON_REN=0 +SCON_RI=0 +SCON_SM0=0 +SCON_SM1=0 +SCON_SM2=0 +SCON_TB8=0 +SCON_TI=0 +SCU_PAGE_OP=0 +SCU_PAGE_PAGE=0 +SCU_PAGE_STNR=0 +SCU_USE_CLOCKOUT=0 +SHINT= +SHINT_NAME_INIT=SHINT_vInit +SP_SP=0 +SSC_BAUDRATE=12000000 +SSC_BR=0 +SSC_BRH_BR_VALUE=0 +SSC_BRL_BR_VALUE=0 +SSC_CFILE=SSC.C +SSC_CONH_O_BE=0 +SSC_CONH_O_BSY=0 +SSC_CONH_O_EN=0 +SSC_CONH_O_MS=0 +SSC_CONH_O_PE=0 +SSC_CONH_O_RE=0 +SSC_CONH_O_TE=0 +SSC_CONH_P_AREN=0 +SSC_CONH_P_BEN=0 +SSC_CONH_P_EN=0 +SSC_CONH_P_MS=1 +SSC_CONH_P_PEN=0 +SSC_CONH_P_REN=0 +SSC_CONH_P_TEN=0 +SSC_CONL_O_BC=0 +SSC_CONL_P_BM=1 +SSC_CONL_P_HB=0 +SSC_CONL_P_LB=0 +SSC_CONL_P_PH=0 +SSC_CONL_P_PO=0 +SSC_HFILE=SSC.H +SSC_MSEL1_CIS=0 +SSC_MSEL1_MIS=0 +SSC_MSEL1_SIS=0 +SSC_MSEL_CIS=0 +SSC_MSEL_MIS=0 +SSC_MSEL_SIS=0 +SSC_NAME_BUSY=SSC_ubBusy +SSC_NAME_ERROR=SSC_ubError +SSC_NAME_GETDATA=SSC_vGetData +SSC_NAME_INIT=SSC_vInit +SSC_NAME_ISR=SSC_vIsr +SSC_NAME_OPERATINGMODE=SSC_ubOperatingMode +SSC_NAME_PROGRAMMINGMODE=SSC_ubProgrammingMode +SSC_NAME_RESETLOOPBACKMODE=SSC_ubResetLoopBackMode +SSC_NAME_SENDDATA=SSC_vSendData +SSC_NAME_SETLOOPBACKMODE=SSC_ubSetLoopBackMode +SSC_NOTES= +SSC_PISEL_CIS=0 +SSC_PISEL_MIS=0 +SSC_PISEL_SIS=0 +SSC_RBL_RB_VALUE=0 +SSC_REQBAUD= +SSC_SSEL1_CIS=0 +SSC_SSEL1_MIS=0 +SSC_SSEL1_SIS=0 +SSC_SSEL_CIS=0 +SSC_SSEL_MIS=0 +SSC_SSEL_SIS=0 +SSC_TBL_TB_VALUE=0 +SSC_USE_BUSY=0 +SSC_USE_ERROR=0 +SSC_USE_GETDATA=0 +SSC_USE_INIT=0 +SSC_USE_ISR=0 +SSC_USE_OPERATINGMODE=0 +SSC_USE_PROGRAMMINGMODE=0 +SSC_USE_RESETLOOPBACKMODE=0 +SSC_USE_SENDDATA=0 +SSC_USE_SETLOOPBACKMODE=0 +SYSCON0_1=0 +SYSCON0_IMODE=0 +SYSCON0_RMAP=0 +T01_CFILE=T01.C +T01_HFILE=T01.H +T01_NAME_CLEARTMR=T01_vClearTmr +T01_NAME_INIT=T01_vInit +T01_NAME_ISRTMR0=T01_viTmr0 +T01_NAME_ISRTMR1=T01_viTmr1 +T01_NAME_LOADTMR=T01_vLoadTmr +T01_NAME_READTMR=T01_ReadTmr +T01_NAME_STARTTMR=T01_vStartTmr +T01_NAME_STARTTMR1=T01_vStartTmr1 +T01_NAME_STOPTMR=T01_vStopTmr +T01_NAME_STOPTMR1=T01_vStopTmr1 +T01_NOTES= +T01_PARA_T01_MODE_0=T01_MODE_0 +T01_PARA_T01_MODE_1=T01_MODE_1 +T01_PARA_T01_MODE_2=T01_MODE_2 +T01_PARA_T01_TIMER_0=T01_TIMER_0 +T01_PARA_T01_TIMER_1=T01_TIMER_1 +T01_USE_CLEARTMR=0 +T01_USE_INIT=0 +T01_USE_ISRTMR0=0 +T01_USE_ISRTMR1=0 +T01_USE_LOADTMR=0 +T01_USE_READTMR=0 +T01_USE_STARTTMR=0 +T01_USE_STARTTMR1=0 +T01_USE_STOPTMR=0 +T01_USE_STOPTMR1=0 +T21_CFILE=T21.C +T21_HFILE=T21.H +T21_INTERRUPT_SELECT=0 +T21_NAME_GETRC2REG=T21_uwGetRC2Reg +T21_NAME_INIT=T21_vInit +T21_NAME_ISRTMR=SHINT_viXINTR8Isr +T21_NAME_READTMR=T21_uwReadTmr +T21_NAME_SETRC2REG=T21_vSetRC2Reg +T21_NAME_STARTTMR=T21_vStartTmr +T21_NAME_STOPTMR=T21_vStopTmr +T21_NOTES= +T21_RC2H_RC2=0 +T21_RC2L_RC2=0 +T21_T2CON_C/T2=0 +T21_T2CON_CP/RL2=0 +T21_T2CON_EXEN2=0 +T21_T2CON_EXF2=0 +T21_T2CON_TF2=0 +T21_T2CON_TR2=0 +T21_T2H_THL2=0 +T21_T2L_THL2=0 +T21_T2MOD_DCEN=0 +T21_T2MOD_EDGESEL=0 +T21_T2MOD_PREN=0 +T21_T2MOD_T2PRE=0 +T21_T2MOD_T2REGS=0 +T21_T2MOD_T2RHEN=0 +T21_USE_GETRC2REG=0 +T21_USE_INIT=0 +T21_USE_ISRTMR=0 +T21_USE_READTMR=0 +T21_USE_SETRC2REG=0 +T21_USE_STARTTMR=0 +T21_USE_STOPTMR=0 +T2_CFILE=T2.C +T2_HFILE=T2.H +T2_INTERRUPT_SELECT= +T2_NAME_GETRC2REG=T2_uwGetRC2Reg +T2_NAME_INIT=T2_vInit +T2_NAME_ISRTMR=SHINT_viXINTR5Isr +T2_NAME_READTMR=T2_uwReadTmr +T2_NAME_SETRC2REG=T2_vSetRC2Reg +T2_NAME_STARTTMR=T2_vStartTmr +T2_NAME_STOPTMR=T2_vStopTmr +T2_NOTES= +T2_RC2H_RC2=248 +T2_RC2L_RC2=48 +T2_T2CON_C/T2=0 +T2_T2CON_CP/RL2=0 +T2_T2CON_EXEN2=0 +T2_T2CON_EXF2=0 +T2_T2CON_TF2=0 +T2_T2CON_TR2=1 +T2_T2H_THL2=248 +T2_T2L_THL2=48 +T2_T2MOD_DCEN=0 +T2_T2MOD_EDGESEL=0 +T2_T2MOD_PREN=0 +T2_T2MOD_T2PRE=0 +T2_T2MOD_T2REGS=0 +T2_T2MOD_T2RHEN=0 +T2_USE_GETRC2REG=0 +T2_USE_INIT=1 +T2_USE_ISRTMR=1 +T2_USE_READTMR=0 +T2_USE_SETRC2REG=0 +T2_USE_STARTTMR=0 +T2_USE_STOPTMR=0 +TCON_IE0=0 +TCON_IE1=0 +TCON_IT0=0 +TCON_IT1=0 +TCON_TF0=0 +TCON_TF1=0 +TCON_TR0=0 +TCON_TR1=0 +TH0_VAL=0 +TH1_VAL=0 +TIMER21_EXF2_PIN_P3.5_USED=0 +TIMER21_EXF2_PIN_P4.3_USED=0 +TIMER21_T2EX_PIN_P0.5_USED=0 +TIMER21_T2EX_PIN_P3.4_USED=0 +TIMER2_EXF2_PIN_P0.1_USED=0 +TIMER2_EXF2_PIN_P1.5_USED=0 +TL0_VAL=0 +TL1_VAL=0 +TMOD_GATE0=0 +TMOD_GATE1=0 +TMOD_T0M=0 +TMOD_T0S=0 +TMOD_T1M=0 +TMOD_T1S=0 +UART1_BAUDRATE=750000 +UART1_BCON_BRPRE=0 +UART1_BCON_R=0 +UART1_BG_BR_VALUE=1 +UART1_CFILE=UART1.C +UART1_FDCON_FDEN=0 +UART1_FDCON_FDM=0 +UART1_FDCON_NDOV=0 +UART1_FDRES_RESULT=0 +UART1_FDSTEP_STEP=0 +UART1_HFILE=UART1.H +UART1_INTERRUPT_SELECT=0 +UART1_NAME_GETDATA8=UART1_ubGetData8 +UART1_NAME_GETDATA9=UART1_uwGetData9 +UART1_NAME_GOTOSLEEP=UART1_vGotoSleep +UART1_NAME_INIT=UART1_vInit +UART1_NAME_ISR=SHINT_viXINTR8Isr +UART1_NAME_OWNADDRESS=UART1_bOwnAddress +UART1_NAME_RXDISABLE=UART1_vRxDisable +UART1_NAME_RXENABLE=UART1_vRxEnable +UART1_NAME_RXREADY=UART1_bRxReady +UART1_NAME_SENDADDR=UART1_vSendAddr +UART1_NAME_SENDDATA8=UART1_vSendData8 +UART1_NAME_SENDDATA9=UART1_vSendData9 +UART1_NAME_SETBAUDRATE= +UART1_NAME_TXREADY=UART1_bTxReady +UART1_NAME_WAKEUP=UART1_vWakeUp +UART1_NOTES= +UART1_RXDO1_0_PIN_P0.3_USED=0 +UART1_RXDO1_1_PIN_P3.0_USED=0 +UART1_RXPIN_P0.5_USED=0 +UART1_RXPIN_P3.2_USED=0 +UART1_SBUF_VAL=0 +UART1_SCON_RB8_1=0 +UART1_SCON_REN_1=0 +UART1_SCON_RI_1=0 +UART1_SCON_SM0_1=0 +UART1_SCON_SM1_1=0 +UART1_SCON_SM2_1=0 +UART1_SCON_TB8_1=0 +UART1_SCON_TI_1=0 +UART1_TXPIN_P0.4_USED=0 +UART1_TXPIN_P3.1_USED=0 +UART1_USE_GETDATA8=0 +UART1_USE_GETDATA9=0 +UART1_USE_GOTOSLEEP=0 +UART1_USE_INIT=0 +UART1_USE_ISR=0 +UART1_USE_OWNADDRESS=0 +UART1_USE_RXDISABLE=0 +UART1_USE_RXENABLE=0 +UART1_USE_RXREADY=0 +UART1_USE_SENDADDR=0 +UART1_USE_SENDDATA8=0 +UART1_USE_SENDDATA9=0 +UART1_USE_SETBAUDRATE=0 +UART1_USE_TXREADY=0 +UART1_USE_WAKEUP=0 +UART_BAUDRATE=750000 +UART_CFILE=UART.C +UART_HFILE=UART.H +UART_NAME_GETDATA8=UART_ubGetData8 +UART_NAME_GETDATA9=UART_uwGetData9 +UART_NAME_GOTOSLEEP=UART_vGotoSleep +UART_NAME_INIT=UART_vInit +UART_NAME_ISR=UART_viIsr +UART_NAME_OWNADDRESS=UART_bOwnAddress +UART_NAME_RXDISABLE=UART_vRxDisable +UART_NAME_RXENABLE=UART_vRxEnable +UART_NAME_RXREADY=UART_bRxReady +UART_NAME_SENDADDR=UART_vSendAddr +UART_NAME_SENDDATA8=UART_vSendData8 +UART_NAME_SENDDATA9=UART_vSendData9 +UART_NAME_SETBAUDRATE= +UART_NAME_TXREADY=UART_bTxReady +UART_NAME_WAKEUP=UART_vWakeUp +UART_NOTES= +UART_RXDO_PIN_P0.0_USED=0 +UART_RXDO_PIN_P1.5_USED=0 +UART_RXPIN_P0.1_USED=0 +UART_RXPIN_P1.0_USED=0 +UART_TXPIN_P0.2_USED=0 +UART_TXPIN_P1.1_USED=0 +UART_USE_GETDATA8=0 +UART_USE_GETDATA9=0 +UART_USE_GOTOSLEEP=0 +UART_USE_INIT=0 +UART_USE_ISR=0 +UART_USE_OWNADDRESS=0 +UART_USE_RXDISABLE=0 +UART_USE_RXENABLE=0 +UART_USE_RXREADY=0 +UART_USE_SENDADDR=0 +UART_USE_SENDDATA8=0 +UART_USE_SENDDATA9=0 +UART_USE_SETBAUDRATE=0 +UART_USE_TXREADY=0 +UART_USE_WAKEUP=0 +WDTCON_WDTEN=0 +WDTCON_WDTIN=1 +WDTCON_WDTPR=0 +WDTCON_WDTRS=0 +WDTCON_WINBEN=0 +WDTH_WDT=0 +WDTL_WDT=0 +WDTREL_WDTREL=219 +WDTWINB_WDTWINB=0 +WDT_CFILE=WDT.C +WDT_HFILE=WDT.H +WDT_NAME_INIT=WDT_vInit +WDT_NAME_REFRESH=WDT_vRefresh +WDT_NAME_RESET=WDT_bWDTReset +WDT_NAME_WINDOWB=WDT_Windowb +WDT_NOTES= +WDT_PARA_CLR_BIT=0 +WDT_PARA_NO_CLR_BIT=1 +WDT_USE_INIT=1 +WDT_USE_REFRESH=1 +WDT_USE_RESET=0 +WDT_USE_WINDOWB=0 +WDT_WDTPERIOD=50 +WDT_WDTUSED=1 +WDT_WINENA=WDT_vEnable +XADDRH_ADDRH=0 + +[Version] +Format=1 +Product=1.3 +Register=2006-01-25 + + diff --git a/CL2.0.plg b/CL2.0.plg new file mode 100644 index 0000000..5ee3c75 --- /dev/null +++ b/CL2.0.plg @@ -0,0 +1,1543 @@ + + +
+
Vision Build Log

+
Project:

+C:\Documents and Settings\Administrator\\cl2\CL2.0.uvproj
+Project File Date:  
+
+
Output:

+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SSC_VSENDDATA?SSC
+Program Size: data=9.0 xdata=0 code=163
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+Config.H(1006): warning C318: can't open file 'user_main.H'
+Config.H(1007): warning C318: can't open file 'FlexrayDriver.h'
+Config.H(1009): warning C318: can't open file 'CanDriver.H'
+compiling SSC.C...
+Config.H(1006): warning C318: can't open file 'user_main.H'
+Config.H(1007): warning C318: can't open file 'FlexrayDriver.h'
+Config.H(1009): warning C318: can't open file 'CanDriver.H'
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SSC_VSENDDATA?SSC
+Program Size: data=9.0 xdata=0 code=163
+"CL2.0" - 0 Error(s), 7 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling SwDriver.C...
+SwDriver.C(240): error C200: left side of '.' requires struct/union
+SwDriver.C(777): error C202: 'P1_2': undefined identifier
+SwDriver.C(778): error C202: 'P1_3': undefined identifier
+SwDriver.C(779): error C202: 'P1_4': undefined identifier
+SwDriver.C(780): error C202: 'P1_4': undefined identifier
+SwDriver.C(781): error C202: 'P1_4': undefined identifier
+SwDriver.C(782): error C202: 'P1_4': undefined identifier
+SwDriver.C(783): error C202: 'P1_4': undefined identifier
+SwDriver.C(784): error C202: 'P1_4': undefined identifier
+SwDriver.C(785): error C202: 'P1_4': undefined identifier
+SwDriver.C(786): error C202: 'P1_4': undefined identifier
+SwDriver.C(787): error C202: 'P1_4': undefined identifier
+SwDriver.C(788): error C202: 'P1_4': undefined identifier
+SwDriver.C(789): error C202: 'P1_4': undefined identifier
+SwDriver.C(790): error C202: 'P1_4': undefined identifier
+SwDriver.C(791): error C202: 'P1_4': undefined identifier
+SwDriver.C(792): error C202: 'P1_4': undefined identifier
+SwDriver.C(793): error C202: 'P1_4': undefined identifier
+SwDriver.C(794): error C202: 'P1_4': undefined identifier
+SwDriver.C(795): error C202: 'P1_4': undefined identifier
+SwDriver.C(796): error C202: 'P1_4': undefined identifier
+SwDriver.C(797): error C202: 'P1_4': undefined identifier
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling SwDriver.C...
+SwDriver.C(240): error C200: left side of '.' requires struct/union
+SwDriver.C(777): error C202: 'P1_2': undefined identifier
+SwDriver.C(778): error C202: 'P1_3': undefined identifier
+SwDriver.C(779): error C202: 'P1_3': undefined identifier
+SwDriver.C(780): error C202: 'P1_3': undefined identifier
+SwDriver.C(781): error C202: 'P1_3': undefined identifier
+SwDriver.C(782): error C202: 'P1_3': undefined identifier
+SwDriver.C(783): error C202: 'P1_3': undefined identifier
+SwDriver.C(784): error C202: 'P1_3': undefined identifier
+SwDriver.C(785): error C202: 'P1_3': undefined identifier
+SwDriver.C(786): error C202: 'P1_3': undefined identifier
+SwDriver.C(787): error C202: 'P1_3': undefined identifier
+SwDriver.C(788): error C202: 'P1_3': undefined identifier
+SwDriver.C(789): error C202: 'P1_3': undefined identifier
+SwDriver.C(790): error C202: 'P1_3': undefined identifier
+SwDriver.C(791): error C202: 'P1_3': undefined identifier
+SwDriver.C(792): error C202: 'P1_3': undefined identifier
+SwDriver.C(793): error C202: 'P1_3': undefined identifier
+SwDriver.C(794): error C202: 'P1_3': undefined identifier
+SwDriver.C(795): error C202: 'P1_3': undefined identifier
+SwDriver.C(796): error C202: 'P1_3': undefined identifier
+SwDriver.C(797): error C202: 'P1_3': undefined identifier
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(863): warning C206: 'Mc33993DataSendRcv': missing function-prototype
+SwDriver.C(863): error C267: 'Mc33993DataSendRcv': requires ANSI-style prototype
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(806): warning C206: 'SSC_vGetData': missing function-prototype
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SWSTASAMPLE?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_LEDLIGHT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_TOGGLEONEBIT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITSW?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993ANALOGCHSEL?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993STARCVONEBIT?SWDRIVER
+*** WARNING L1: UNRESOLVED EXTERNAL SYMBOL
+    SYMBOL:  SSC_VGETDATA
+    MODULE:  SwDriver.obj (SWDRIVER)
+*** WARNING L2: REFERENCE MADE TO UNRESOLVED EXTERNAL
+    SYMBOL:  SSC_VGETDATA
+    MODULE:  SwDriver.obj (SWDRIVER)
+    ADDRESS: 195EH
+Program Size: data=76.4 xdata=0 code=6607
+"CL2.0" - 0 Error(s), 9 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(801): warning C206: 'SSC_vSendData': missing function-prototype
+SwDriver.C(801): error C267: 'SSC_vSendData': requires ANSI-style prototype
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SWSTASAMPLE?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_LEDLIGHT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_TOGGLEONEBIT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITSW?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993ANALOGCHSEL?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993STARCVONEBIT?SWDRIVER
+Program Size: data=76.4 xdata=0 code=6610
+"CL2.0" - 0 Error(s), 6 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SWSTASAMPLE?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993STARCVONEBIT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=63.3 xdata=0 code=4875
+"CL2.0" - 0 Error(s), 3 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993STARCVONEBIT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=53.3 xdata=0 code=4634
+"CL2.0" - 0 Error(s), 3 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=52.2 xdata=0 code=4066
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=52.2 xdata=0 code=4066
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4367
+"CL2.0" - 0 Error(s), 2 Warning(s).
+"XC800_FLOAD.EXE" "C:\Documents and Settings\Administrator\\cl2\CL2.HEX" f"
+--- Error: failed to execute '"XC800_FLOAD.EXE" "C:\Documents and Settings\Administrator\\cl2\CL2.HEX" f"'
+Build target 'Target 1'
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4367
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4370
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4301
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4301
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5591
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+Program Size: data=67.2 xdata=0 code=5594
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5591
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=76.2 xdata=0 code=5615
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+compiling SSC.C...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+compiling IO.C...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+compiling SwDriver.C...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+compiling User.c...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(205): error C231: 'UnSwOut_1': redefinition
+compiling User.c...
+User.c(11): error C231: 'UnSwOut_1': redefinition
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+User.c(11): error C231: 'UnSwOut_1': redefinition
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+User.c(11): error C231: 'UnSwOut_1': redefinition
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=72.2 xdata=0 code=5609
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=72.2 xdata=0 code=5404
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=72.2 xdata=0 code=5404
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(368): error C204: 'ArrData': undefined member
+SwDriver.C(375): error C204: 'ArrData': undefined member
+SwDriver.C(376): error C204: 'ArrData': undefined member
+SwDriver.C(377): error C204: 'ArrData': undefined member
+SwDriver.C(378): error C204: 'ArrData': undefined member
+SwDriver.C(379): error C204: 'ArrData': undefined member
+SwDriver.C(380): error C204: 'ArrData': undefined member
+SwDriver.C(381): error C204: 'ArrData': undefined member
+SwDriver.C(382): error C204: 'ArrData': undefined member
+SwDriver.C(383): error C204: 'ArrData': undefined member
+SwDriver.C(384): error C204: 'ArrData': undefined member
+SwDriver.C(385): error C204: 'ArrData': undefined member
+SwDriver.C(386): error C204: 'ArrData': undefined member
+SwDriver.C(387): error C204: 'ArrData': undefined member
+SwDriver.C(388): error C204: 'ArrData': undefined member
+SwDriver.C(389): error C204: 'ArrData': undefined member
+SwDriver.C(390): error C204: 'ArrData': undefined member
+SwDriver.C(391): error C204: 'ArrData': undefined member
+SwDriver.C(392): error C204: 'ArrData': undefined member
+SwDriver.C(393): error C204: 'ArrData': undefined member
+SwDriver.C(394): error C204: 'ArrData': undefined member
+SwDriver.C(395): error C204: 'ArrData': undefined member
+compiling User.c...
+User.c(11): error C242: 'union': too many initializers
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(368): error C204: 'ArrData': undefined member
+SwDriver.C(375): error C204: 'ArrData': undefined member
+SwDriver.C(376): error C204: 'ArrData': undefined member
+SwDriver.C(377): error C204: 'ArrData': undefined member
+SwDriver.C(378): error C204: 'ArrData': undefined member
+SwDriver.C(379): error C204: 'ArrData': undefined member
+SwDriver.C(380): error C204: 'ArrData': undefined member
+SwDriver.C(381): error C204: 'ArrData': undefined member
+SwDriver.C(382): error C204: 'ArrData': undefined member
+SwDriver.C(383): error C204: 'ArrData': undefined member
+SwDriver.C(384): error C204: 'ArrData': undefined member
+SwDriver.C(385): error C204: 'ArrData': undefined member
+SwDriver.C(386): error C204: 'ArrData': undefined member
+SwDriver.C(387): error C204: 'ArrData': undefined member
+SwDriver.C(388): error C204: 'ArrData': undefined member
+SwDriver.C(389): error C204: 'ArrData': undefined member
+SwDriver.C(390): error C204: 'ArrData': undefined member
+SwDriver.C(391): error C204: 'ArrData': undefined member
+SwDriver.C(392): error C204: 'ArrData': undefined member
+SwDriver.C(393): error C204: 'ArrData': undefined member
+SwDriver.C(394): error C204: 'ArrData': undefined member
+SwDriver.C(395): error C204: 'ArrData': undefined member
+compiling User.c...
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=72.2 xdata=0 code=5404
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+compiling SSC.C...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+compiling IO.C...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+compiling SwDriver.C...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+compiling User.c...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(227): warning C280: 'i': unreferenced local variable
+SwDriver.C(227): warning C280: 'j': unreferenced local variable
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 4 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(227): warning C280: 'i': unreferenced local variable
+SwDriver.C(227): warning C280: 'j': unreferenced local variable
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 4 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(227): warning C280: 'i': unreferenced local variable
+SwDriver.C(227): warning C280: 'j': unreferenced local variable
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 4 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4076
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+Config.H(67): error C238: 'fff': duplicate member
+compiling SSC.C...
+Config.H(67): error C238: 'fff': duplicate member
+compiling IO.C...
+Config.H(67): error C238: 'fff': duplicate member
+compiling SwDriver.C...
+Config.H(67): error C238: 'fff': duplicate member
+compiling User.c...
+Config.H(67): error C238: 'fff': duplicate member
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=58.2 xdata=0 code=4093
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(264): warning C206: 'LedLight': missing function-prototype
+SwDriver.C(264): error C267: 'LedLight': requires ANSI-style prototype
+SwDriver.C(266): error C202: 'j': undefined identifier
+SwDriver.C(266): error C202: 'i': undefined identifier
+SwDriver.C(287): error C204: 'RES43': undefined member
+SwDriver.C(288): error C204: 'RES44': undefined member
+SwDriver.C(292): error C202: 'j': undefined identifier
+SwDriver.C(292): error C202: 'i': undefined identifier
+SwDriver.C(353): error C231: 'LedLight': redefinition
+SwDriver.C(390): error C231: 'LedLight': redefinition
+compiling User.c...
+User.c(11): error C242: 'union': too many initializers
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(264): warning C206: 'LedLight': missing function-prototype
+SwDriver.C(264): error C267: 'LedLight': requires ANSI-style prototype
+SwDriver.C(266): error C202: 'j': undefined identifier
+SwDriver.C(266): error C202: 'i': undefined identifier
+SwDriver.C(287): error C204: 'RES43': undefined member
+SwDriver.C(288): error C204: 'RES44': undefined member
+SwDriver.C(292): error C202: 'j': undefined identifier
+SwDriver.C(292): error C202: 'i': undefined identifier
+SwDriver.C(353): error C231: 'LedLight': redefinition
+SwDriver.C(390): error C231: 'LedLight': redefinition
+compiling User.c...
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(266): warning C206: 'LedLight': missing function-prototype
+SwDriver.C(266): error C267: 'LedLight': requires ANSI-style prototype
+SwDriver.C(355): error C231: 'LedLight': redefinition
+SwDriver.C(392): error C231: 'LedLight': redefinition
+compiling User.c...
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5692
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5695
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5695
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5698
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5698
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5572
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5632
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5560
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5623
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5617
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5614
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5611
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5605
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5602
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5593
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5563
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5560
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5623
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5620
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5617
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5623
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
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+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5620
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+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
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+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5617
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+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
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+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5614
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5611
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+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5608
+"CL2.0" - 0 Error(s), 0 Warning(s).
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+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5605
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5602
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
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+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5599
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5596
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+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5593
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+assembling START_XC.a51...
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+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=7877
+"CL2.0" - 0 Error(s), 0 Warning(s).
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+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0, 1
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=9978
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+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0, 1, 2
+Erasing Bank 1  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
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+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=9977
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+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0, 1, 2
+Erasing Bank 1  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=9977
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0, 1, 2
+Erasing Bank 1  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=9976
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0, 1, 2
+Erasing Bank 1  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=9976
+creating hex file from ".\output\CL2.0"...
+".\output\CL2.0" - 0 Error(s), 0 Warning(s).
diff --git a/CL2.0.rtf b/CL2.0.rtf
new file mode 100644
index 0000000..f34f6a4
--- /dev/null
+++ b/CL2.0.rtf
@@ -0,0 +1,1141 @@
+{\rtf1\ansi\deff0\deftab720{\fonttbl{\f0\fnil MS Sans Serif;}{\f1\fnil\fcharset2 Symbol;}{\f2\fswiss\fprq2 System;}{\f3\fnil Times New Roman;}{\f4\fswiss\fprq2 Arial;}}
+{\colortbl\red0\green0\blue0;\red0\green0\blue128;\red255\green0\blue0;}
+\deflang1031\pard\plain\f4\fs28\cf0 DAvE's Project Documentation
+\par \plain\f4\fs22\cf0
+\par \plain\f4\fs22\cf0 Project: \tab\tab\b CL2.0.dav
+\par 
+\par \plain\f4\fs22\cf0 Controller: \tab\tab\b XC886CLM-8FF
+\par \plain\f4\fs22\cf0 Compiler: \tab\tab\b Keil
+\par \plain\f4\fs22\cf0 Memory Model: \tab\b COMPACT
+\par 
+\par \plain\f4\fs22\cf0 Date: \tab\tab\tab\b 2025/1/18 20:45:36
+\par 
+\par 
+\par \plain\f4\fs22\cf2\b Please read this document carefully and note
+\par \plain\f4\fs22\cf2\b the red-colored hints.
+\par 
+\par \plain\f4\fs22\cf2\b If you miss a file in the generated files list
+\par \plain\f4\fs22\cf2\b maybe you have forgotten to select the
+\par \plain\f4\fs22\cf2\b initialisation function of the related module.
+\par 
+\par \plain\f4\fs22\cf0 Generated Files:
+\plain\f4\fs20\cf0\b
+\par \tab\tab\tab MAIN.H
+\par \tab\tab\tab MAIN.C
+\par \tab\tab\tab SHARED_INT.H
+\par \tab\tab\tab SHARED_INT.C
+\par \tab\tab\tab IO.H
+\par \tab\tab\tab IO.C
+\par \tab\tab\tab T2.H
+\par \tab\tab\tab T2.C
+\par \tab\tab\tab WDT.H
+\par \tab\tab\tab WDT.C
+\par \tab\tab\tab CAN.H
+\par \tab\tab\tab CAN.C
+\par \tab\tab\tab CL2.0.ASM
+\par 
+\par 
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul Project Settings
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void MAIN_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function initializes the microcontroller. It is
+
+\par \tab \tab assumed that the SFRs are in their reset state.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void main(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the main function.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab Configuration of the System Clock:\par 
+\tab - External Osc is selected (configuration is done in the startup file\par 
+\tab 'START_XC.A51')\par 
+\tab - PLL Mode, NDIV =  24\par 
+\tab - input frequency is 8 MHz\par 
+\par 
+\tab *********************************************************************************\par 
+\tab Note : All peripheral related IO configurations are done in the\par 
+\tab respective peripheral modules (alternate functions selection)\par 
+\tab *********************************************************************************\par 
+\par 
+\tab Initialization of module 'GPIO'\par 
+\par 
+\tab Initialization of module 'Timer 2'\par 
+\par 
+\tab Initialization of module 'Watch Dog Timer'\par 
+\par 
+\tab Initialization of module 'MultiCAN Controller '\par 
+\par 
+\tab Initialization of  'Shared interrupts'\par 
+\par 
+\tab \cf2Interrupt structure 2 mode 0 is selected.\cf0\par 
+\par 
+\tab \cf2Interrupt service routine choice 2 is selected.\cf0\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul Shared Interrupt Routines
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void SHINT_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function initializes the shared interrupts.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void SHINT_viXINTR5Isr(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the service routine for the shared interrupt node
+
+\par \tab \tab XINTR5. XINTR5 ISR Node is shared by Timer 2, UART
+
+\par \tab \tab Fractional Divider(BRG Interrupt),MultiCAN Node 0 and LIN.
+
+\par \tab \tab Depending on the selected module interrupt it is called.
+
+\par \tab \tab T2 - Depending on the selected operating mode it is called
+
+\par \tab \tab when TF2 is set by an overflow or underflow of the timer 2
+
+\par \tab \tab register or when EXF2 is set by a negative transition on
+
+\par \tab \tab T2EX.
+
+\par \tab \tab UART - It is called after the BRG timer overflows and sets
+
+\par \tab \tab the NDOV bit.
+
+\par \tab \tab CAN -  It is called for the  Service Request Node 0 of the
+
+\par \tab \tab MultiCAN module.
+
+\par \tab \tab Please note that you have to add application specific code
+
+\par \tab \tab to this function.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b none\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab Configuration of the Shared  Interrupts:\par 
+\tab - Timer 2 Interrupt is Selected\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul GPIO
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab IO_ubReadPin(PinName)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro returns the status of the chosen portpin.
+
+\par \tab \tab Note:
+
+\par \tab \tab 'PinName' identifies the pin of a bit-addressable port. The
+
+\par \tab \tab default names can be changed in the port configuration
+
+\par \tab \tab dialog.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b Status of the chosen portpin\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab PinName:
+
+\par \tab \tab Pin to be read
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab IO_vSetPin(PinName)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab The chosen portpin is set to '1'.
+
+\par \tab \tab Note:
+
+\par \tab \tab 'PinName' identifies the pin of a bit-addressable port. The
+
+\par \tab \tab default names can be changed in the port configuration
+
+\par \tab \tab dialog.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab PinName:
+
+\par \tab \tab Pin to be set to '1'
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab IO_vResetPin(PinName)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab The chosen portpin is set to '0'.
+
+\par \tab \tab Note:
+
+\par \tab \tab 'PinName' identifies the pin of a bit-addressable port. The
+
+\par \tab \tab default names can be changed in the port configuration
+
+\par \tab \tab dialog.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab PinName:
+
+\par \tab \tab Pin to be set to '0'
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab IO_vTogglePin(PinName)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab The chosen portpin will be toggled.
+
+\par \tab \tab Note:
+
+\par \tab \tab 'PinName' identifies the pin of a bit-addressable port. The
+
+\par \tab \tab default names can be changed in the port configuration
+
+\par \tab \tab dialog.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab PinName:
+
+\par \tab \tab Pin to be toggled
+
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void IO_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the initialization function of the IO function
+
+\par \tab \tab library. It is assumed that the SFRs used by this library
+
+\par \tab \tab are in their reset state.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab ***********************************************************************\par 
+\tab Note : All peripheral related IO configurations are done in the\par 
+\tab respective peripheral modules (alternate functions selection)\par 
+\tab \par 
+\tab If no pins are selected DAvE assumes that registers are in default\par 
+\tab settings\par 
+\tab ***********************************************************************\par 
+\par 
+\tab Configuration of Port P0:\par 
+\tab P0.0:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P0.1:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P0.2:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P0.3:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P0.7:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\par 
+\tab Configuration of Port P1:\par 
+\tab P1.0:\par 
+\tab - is used as alternate input for the MCAN Node 0 Receiver Input\par 
+\tab - pull-up device is assigned\par 
+\tab P1.1:\par 
+\tab - is used as alternate output for the MCAN Node 0 Transmitter Output\par 
+\tab - push/pull output is selected\par 
+\tab - pull-up device is assigned\par 
+\tab P1.2:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P1.3:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P1.4:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P1.5:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P1.7:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\par 
+\tab Configuration of Port P2:\par 
+\tab P2.4:\par 
+\tab - is used as general input\par 
+\tab - input driver is enabled\par 
+\tab - pull-up device is assigned\par 
+\tab P2.5:\par 
+\tab - is used as general input\par 
+\tab - input driver is enabled\par 
+\tab - pull-up device is assigned\par 
+\tab P2.6:\par 
+\tab - is used as general input\par 
+\tab - input driver is enabled\par 
+\tab - pull-up device is assigned\par 
+\tab P2.7:\par 
+\tab - is used as general input\par 
+\tab - input driver is enabled\par 
+\tab - pull-up device is assigned\par 
+\par 
+\tab Configuration of Port P3:\par 
+\tab P3.0:\par 
+\tab - is used as general input\par 
+\tab - pull-up device is assigned\par 
+\tab P3.1:\par 
+\tab - is used as general input\par 
+\tab - pull-up device is assigned\par 
+\tab P3.2:\par 
+\tab - is used as general purpose output\par 
+\tab - open drain output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.3:\par 
+\tab - is used as general purpose output\par 
+\tab - open drain output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.4:\par 
+\tab - is used as general purpose output\par 
+\tab - open drain output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.5:\par 
+\tab - is used as general purpose output\par 
+\tab - open drain output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.6:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.7:\par 
+\tab - is used as general input\par 
+\tab - pull-up device is assigned\par 
+\par 
+\tab Configuration of Port P4:\par 
+\tab P4.0:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P4.1:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P4.3:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul Timer 2
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void T2_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the initialization function of the Timer 2 function
+
+\par \tab \tab library. It is assumed that the SFRs used by this library
+
+\par \tab \tab are in their reset state.
+
+\par \tab \tab The following SFRs and SFR fields will be initialized:
+
+\par \tab \tab T2_RC2H/RC2L     - reload/capture timer 2 register
+
+\par \tab \tab T2_T2H/T2L     -  timer 2 register
+
+\par \tab \tab ET2           - timer 2 interrupt enable
+
+\par \tab \tab T2_T2MOD         - timer 2 mode register
+
+\par \tab \tab CP/RL2        - Capture/Reload select
+
+\par \tab \tab EXEN2         - External enable control
+
+\par \tab \tab TR2           - Timer2 run control
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab 16-bit timer function with automatic reload when timer 2 overflows\par 
+\tab the timer 2 resolution is 1 ?s\par 
+\tab the timer 2 overflow is 1000.000 ?s\par 
+\tab timer 2 interrupt: enabled\par 
+\tab timer 2 will be started\par 
+\par 
+\tab timer 2 Interrupt enable bit is set in SHINT_vInit() function\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul Watch Dog Timer
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab WDT_vRefresh()\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro refreshes the watchdog timer to the reload
+
+\par \tab \tab value. The interrupts are disabled during execution of the
+
+\par \tab \tab instructions that set bit WDTRS.
+
+\par \tab \tab Note: The user has to take care that this macro is called
+
+\par \tab \tab before expiry of the watchdog timer.
+
+\par \tab \tab pls refer to the Note on WDT_vInit function Description
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void WDT_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the initialization function of the 'Watch Dog
+
+\par \tab \tab Timer' function library. It is assumed that the SFRs used
+
+\par \tab \tab by this library are in their reset state.
+
+\par \tab \tab The watchdog timer is used.
+
+\par \tab \tab The following SFR fields will be initialized:
+
+\par \tab \tab WDTREL - WDT reload value
+
+\par \tab \tab WDTIN  - WDT input frequency selection
+
+\par \tab \tab Then the watchdog timer will be refreshed.
+
+\par \tab \tab Note: The user has to take care that RMAP bit in SYSCON0 is
+
+\par \tab \tab to be set while using the registers of Watch dog timer.
+
+\par \tab \tab Registers are WDTCON,WDTWINB,WDTREL,WDTH,WDTL
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void WDT_vDisable(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function disables the WDT.
+
+\par \tab \tab pls refer to the Note on WDT_vInit function Description
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab the watchdog timer is used and it is enabled in INIT function,user has\par 
+\tab to take care of WDT refresh\par 
+\tab the RMAP bit of SYSCON0 is set\par 
+\tab the input frequency is fSYS/128\par 
+\tab the watchdog timer reload value is 0xDB\par 
+\tab the watchdog timeout period is 50 ms\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul MultiCAN Controller
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_vReadEN()\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro enables Read mode (CAN Address/Data Control
+
+\par \tab \tab Register).
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_vWriteEN(ubyte ubDCtrl)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro enables Write mode (CAN Address/Data Control
+
+\par \tab \tab Register).
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubDCtrl:
+
+\par \tab \tab Data Control Flags
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_vWriteCANAddress(uword uwAdr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro writes 16-bit CAN address to CAN Address
+
+\par \tab \tab Register Low and High respectively.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab uwAdr:
+
+\par \tab \tab 16-bit Address
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_vWriteCANData(ulong ulValue)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro writes 32-bit Data to CAN Data Register's
+
+\par \tab \tab 0-3respectively.
+
+\par \tab \tab Note:
+
+\par \tab \tab Write Process :
+
+\par \tab \tab ->Write the address of the MultiCAN kernel register to the
+
+\par \tab \tab CAN_ADL and CAN_ADH registers.
+
+\par \tab \tab use macro : CAN_vWriteCANAddress.
+
+\par \tab \tab ->Write the data to the
+
+\par \tab \tab CAN_DATA0/CAN_DATA1/CAN_DATA2/CAN_DATA3 registers.
+
+\par \tab \tab ->Write the register CAN_ADCON, including setting the valid
+
+\par \tab \tab bit of the data registers and setting register bit RWEN to
+
+\par \tab \tab 1.
+
+\par \tab \tab ->The valid data will be written to the MultiCAN kernel
+
+\par \tab \tab only once. Register bit BSY will become 1.
+
+\par \tab \tab ->When Register bit BSY becomes 0, the transmission is
+
+\par \tab \tab finished.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ulValue:
+
+\par \tab \tab 32-bit Data
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_pushAMRegs/_popAMRegs()\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab The macro CAN_pushAMRegs() PUSH the CAN Access Mediator
+
+\par \tab \tab Registers.
+
+\par \tab \tab The macro CAN_popAMRegs() POP the CAN Access Mediator
+
+\par \tab \tab Registers.
+
+\par \tab \tab Note:
+
+\par \tab \tab This macro is used in CAN ISR/Function's to protect Access
+
+\par \tab \tab Mediator Register
+
+\par \tab \tab MultiCAN Access Mediator Registers:
+
+\par \tab \tab ADL, ADH, DATA0, DATA1, DATA2, DATA3.
+
+\par \tab \tab The _push_/_pop_ routine inserts a PUSH/POP instruction
+
+\par \tab \tab into the program saving the contents of the Special
+
+\par \tab \tab Function Register(sfr) on the Stack.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the initialization function of the CAN function
+
+\par \tab \tab library. It is assumed that the SFRs used by this library
+
+\par \tab \tab are in their reset state.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vWriteAMData(ulong ulValue)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function writes 32-bit Data to CAN Data Register's
+
+\par \tab \tab 0-3respectively.
+
+\par \tab \tab Note:
+
+\par \tab \tab Write Process :
+
+\par \tab \tab ->Write the address of the MultiCAN kernel register to the
+
+\par \tab \tab CAN_ADL and CAN_ADH registers.
+
+\par \tab \tab use macro : CAN_vWriteCANAddress.
+
+\par \tab \tab ->Write the data to the
+
+\par \tab \tab CAN_DATA0/CAN_DATA1/CAN_DATA2/CAN_DATA3 registers.
+
+\par \tab \tab ->Write the register CAN_ADCON, including setting the valid
+
+\par \tab \tab bit of the data registers and setting register bit RWEN to
+
+\par \tab \tab 1.
+
+\par \tab \tab ->The valid data will be written to the MultiCAN kernel
+
+\par \tab \tab only once. Register bit BSY will become 1.
+
+\par \tab \tab ->When Register bit BSY becomes 0, the transmission is
+
+\par \tab \tab finished.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ulValue:
+
+\par \tab \tab 32-bit Data
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vSetListCommand(ulong ulVal)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function write's 32-bit Data to CAN_PANCTR Register.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ulVal:
+
+\par \tab \tab 32-bit Data
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vGetMsgObj(ubyte ubObjNr, stCAN_SWObj *pstObj)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function fills the forwarded SW message object with
+
+\par \tab \tab the content of the chosen HW message object.
+
+\par \tab \tab The structure of the SW message object is defined in the
+
+\par \tab \tab header file CAN.H (see stCAN_SWObj).
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object to be read (0-31)
+
+\par \tab \tab *pstObj:
+
+\par \tab \tab Pointer on a message object to be filled by this function
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab ubyte CAN_ubRequestMsgObj(ubyte ubObjNr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab If a TRANSMIT OBJECT is to be reconfigured it must first be
+
+\par \tab \tab accessed. The access to the transmit object is exclusive.
+
+\par \tab \tab This function checks whether the choosen message object is
+
+\par \tab \tab still executing a transmit request, or if the object can be
+
+\par \tab \tab accessed exclusively.
+
+\par \tab \tab After the message object is reserved, it can be
+
+\par \tab \tab reconfigured by using the function CAN_vConfigMsgObj or
+
+\par \tab \tab CAN_vLoadData.
+
+\par \tab \tab Both functions enable access to the object for the CAN
+
+\par \tab \tab controller.
+
+\par \tab \tab By calling the function CAN_vTransmit transfering of data
+
+\par \tab \tab is started.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b 0 message object is busy (a transfer is active), else 1\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object (0-31)
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab ubyte CAN_ubNewData(ubyte ubObjNr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function checks whether the selected RECEIVE OBJECT
+
+\par \tab \tab has received a new message. If so the function returns the
+
+\par \tab \tab value '1'.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b 1 the message object has received a new message, else 0\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object (0-31)
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vTransmit(ubyte ubObjNr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function triggers the CAN controller to send the
+
+\par \tab \tab selected message.
+
+\par \tab \tab If the selected message object is a TRANSMIT OBJECT then
+
+\par \tab \tab this function triggers the sending of a data frame. If
+
+\par \tab \tab however the selected message object is a RECEIVE OBJECT
+
+\par \tab \tab this function triggers the sending of a remote frame.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object (0-31)
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vLoadData(ubyte ubObjNr, ulong *ulpubData)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab If a hardware TRANSMIT OBJECT has to be loaded with data
+
+\par \tab \tab but not with a new identifier, this function may be used
+
+\par \tab \tab instead of the function CAN_vConfigMsgObj. The message
+
+\par \tab \tab object should be accessed by calling the function
+
+\par \tab \tab CAN_ubRequestMsgObj before calling this function. This
+
+\par \tab \tab prevents the CAN controller from working with invalid data.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object to be configured (0-31)
+
+\par \tab \tab *ulpubData:
+
+\par \tab \tab Pointer on a data buffer
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vReleaseObj(ubyte ubObjNr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function resets the NEWDAT flag of the selected
+
+\par \tab \tab RECEIVE OBJECT, so that the CAN controller have access to
+
+\par \tab \tab it. This function must be called if the function
+
+\par \tab \tab CAN_ubNewData detects, that new data are present in the
+
+\par \tab \tab message object and the actual data have been read by
+
+\par \tab \tab calling the function CAN_vGetMsgObj.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object (0-31)
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab Configuration of the Module Clock:\par 
+\tab - the CAN module clock = 48.00 MHz\par 
+\tab - FCLK runs at 2 times the frequency of PCLK.\par 
+\par 
+\tab - CMCON - Clock Control Register is Configured in MAIN_vInit\par 
+\par 
+\tab Configuration of CAN Node 0:\par 
+\par 
+\tab General Configuration of the Node 0:\par 
+\tab - set INIT and CCE\par 
+\par 
+\tab - load NODE 0 interrupt pointer register\par 
+\par 
+\tab Configuration of the used CAN Input Port Pins:\par 
+\tab - Pin P1.0 is used as RXDC0_0 input\par 
+\par 
+\tab - Loop-back mode is disabled\par 
+\par 
+\tab Configuration of the Node 0 Baud Rate:\par 
+\tab - required baud rate = 100.000 kbaud\par 
+\tab - real baud rate     = 100.000 kbaud\par 
+\tab - sample point       = 60.00 %\par 
+\tab - there are 5 time quanta before sample point\par 
+\tab - there are 4 time quanta after sample point\par 
+\tab - the (re)synchronization jump width is 2 time quanta\par 
+\par 
+\tab Configuration of the Node 0 Error Counter:\par 
+\tab - the error warning threshold value (warning level) is 96\par 
+\par 
+\tab Configuration of the Frame Counter:\par 
+\tab - Frame Counter Mode: the counter is incremented upon the reception\par 
+\tab and transmission of frames\par 
+\tab - frame counter: 0x0000\par 
+\par 
+\tab Configuration of CAN Node 1:\par 
+\par 
+\tab General Configuration of the Node 1:\par 
+\tab - set INIT and CCE\par 
+\par 
+\tab Configuration of the used CAN Output Port Pins:\par 
+\tab Pin P1.1 is used as TXDC0_0 Output\par 
+\tab - NODE1 TXD Pin's are not used\par 
+\par 
+\tab Configuration of the CAN Message Object List Structure:\par 
+\par 
+\tab Allocate MOs for list 1:\par 
+\par 
+\tab Configuration of the CAN Message Objects 0 - 31:\par 
+\tab Configuration of Message Object 0:\par 
+\tab - message object 0 is not valid\par 
+\tab Configuration of Message Object 1:\par 
+\tab - message object 1 is not valid\par 
+\tab Configuration of Message Object 2:\par 
+\tab - message object 2 is not valid\par 
+\tab Configuration of Message Object 3:\par 
+\tab - message object 3 is not valid\par 
+\tab Configuration of Message Object 4:\par 
+\tab - message object 4 is not valid\par 
+\tab Configuration of Message Object 5:\par 
+\tab - message object 5 is valid\par 
+\tab - message object is used as receive object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x00000003\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 5\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 6:\par 
+\tab - message object 6 is valid\par 
+\tab - message object is used as transmit object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x11000001\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 6\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 7:\par 
+\tab - message object 7 is valid\par 
+\tab - message object is used as receive object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x11000002\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 7\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 8:\par 
+\tab - message object 8 is valid\par 
+\tab - message object is used as receive object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x11000003\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 8\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 9:\par 
+\tab - message object 9 is valid\par 
+\tab - message object is used as transmit object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x1FFFFFF0\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 9\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 10:\par 
+\tab - message object 10 is not valid\par 
+\tab Configuration of Message Object 11:\par 
+\tab - message object 11 is not valid\par 
+\tab Configuration of Message Object 12:\par 
+\tab - message object 12 is not valid\par 
+\tab Configuration of Message Object 13:\par 
+\tab - message object 13 is not valid\par 
+\tab Configuration of Message Object 14:\par 
+\tab - message object 14 is not valid\par 
+\tab Configuration of Message Object 15:\par 
+\tab - message object 15 is not valid\par 
+\tab Configuration of Message Object 16:\par 
+\tab - message object 16 is not valid\par 
+\tab Configuration of Message Object 17:\par 
+\tab - message object 17 is not valid\par 
+\tab Configuration of Message Object 18:\par 
+\tab - message object 18 is not valid\par 
+\tab Configuration of Message Object 19:\par 
+\tab - message object 19 is not valid\par 
+\tab Configuration of Message Object 20:\par 
+\tab - message object 20 is not valid\par 
+\tab Configuration of Message Object 21:\par 
+\tab - message object 21 is not valid\par 
+\tab Configuration of Message Object 22:\par 
+\tab - message object 22 is not valid\par 
+\tab Configuration of Message Object 23:\par 
+\tab - message object 23 is not valid\par 
+\tab Configuration of Message Object 24:\par 
+\tab - message object 24 is not valid\par 
+\tab Configuration of Message Object 25:\par 
+\tab - message object 25 is not valid\par 
+\tab Configuration of Message Object 26:\par 
+\tab - message object 26 is not valid\par 
+\tab Configuration of Message Object 27:\par 
+\tab - message object 27 is not valid\par 
+\tab Configuration of Message Object 28:\par 
+\tab - message object 28 is not valid\par 
+\tab Configuration of Message Object 29:\par 
+\tab - message object 29 is not valid\par 
+\tab Configuration of Message Object 30:\par 
+\tab - message object 30 is not valid\par 
+\tab Configuration of Message Object 31:\par 
+\tab - message object 31 is not valid\par 
+\par 
+\tab Configuration of the Interrupts:\par 
+\tab - CAN interrupt node 0 is disabled\par 
+\tab - CAN interrupt node 1 is disabled\par 
+\tab - CAN interrupt node 2 is disabled\par 
+\tab - CAN interrupt node 3 is disabled\par 
+\tab - CAN interrupt node 4 is disabled\par 
+\tab - CAN interrupt node 5 is disabled\par 
+\tab - CAN interrupt node 6 is disabled\par 
+\tab - CAN interrupt node 7 is disabled\par 
+\par 
+
+}
diff --git a/CL2.0.uvgui.Administrator b/CL2.0.uvgui.Administrator
new file mode 100644
index 0000000..2ac16cd
--- /dev/null
+++ b/CL2.0.uvgui.Administrator
@@ -0,0 +1,2488 @@
+
+
+
+  -3.1
+
+  
### uVision Project, (C) Keil Software

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diff --git a/CL2.0.uvgui.liuminVir b/CL2.0.uvgui.liuminVir
new file mode 100644
index 0000000..fb83c37
--- /dev/null
+++ b/CL2.0.uvgui.liuminVir
@@ -0,0 +1,1914 @@
+
+
+
+  -6.1
+
+  
### uVision Project, (C) Keil Software

+
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diff --git a/CL2.0.uvgui_Administrator.bak b/CL2.0.uvgui_Administrator.bak
new file mode 100644
index 0000000..f5b622a
--- /dev/null
+++ b/CL2.0.uvgui_Administrator.bak
@@ -0,0 +1,2488 @@
+
+
+
+  -3.1
+
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### uVision Project, (C) Keil Software

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diff --git a/CL2.0.uvopt b/CL2.0.uvopt
new file mode 100644
index 0000000..843e5ec
--- /dev/null
+++ b/CL2.0.uvopt
@@ -0,0 +1,357 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    187610842
+    31157159
+  
+
+  
+    Target 1
+    0x0
+    MCS-51
+    
+      96000000
+      
+        1
+        1
+        1
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+        0
+      
+      
+        0
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+        0
+        0
+      
+      
+        120
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+        8
+        .\output\
+      
+      
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+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+      
+      
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+        1
+        1
+        1
+        1
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+        1
+        1
+        0
+      
+      
+        1
+        0
+        1
+      
+      6
+      
+        
+          0
+          User's Manual
+          DATASHTS\INFINEON\XC886_UM.PDF
+        
+        
+          1
+          XC800 Instruction Set Manual
+          DATASHTS\INFINEON\XC800_IS.PDF
+        
+      
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
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+        1
+        1
+        0
+        1
+        0
+        1
+        1
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+        0
+        1
+        0
+        0
+        7
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        BIN\DAS2XC800.DLL
+      
+      
+        
+          0
+          DLGDC51
+          (5130=-1,-1,-1,-1,0)(5131=-1,-1,-1,-1,0)(5132=-1,-1,-1,-1,0)(5133=-1,-1,-1,-1,0)(5134=-1,-1,-1,-1,0)(1203=-1,-1,-1,-1,0)(5152=-1,-1,-1,-1,0)(94=-1,-1,-1,-1,0)(5150=-1,-1,-1,-1,0)(5140=-1,-1,-1,-1,0)(5141=-1,-1,-1,-1,0)(5142=-1,-1,-1,-1,0)(5143=-1,-1,-1,-1,0)(5144=-1,-1,-1,-1,0)(5145=-1,-1,-1,-1,0)(5019=-1,-1,-1,-1,0)(5020=-1,-1,-1,-1,0)(5018=-1,-1,-1,-1,0)(5021=-1,-1,-1,-1,0)(5022=-1,-1,-1,-1,0)(5151=-1,-1,-1,-1,0)(5155=-1,-1,-1,-1,0)(1219=-1,-1,-1,-1,0)(90=-1,-1,-1,-1,0)(91=-1,-1,-1,-1,0)(1207=-1,-1,-1,-1,0)(5154=-1,-1,-1,-1,0)(5153=-1,-1,-1,-1,0)(1208=-1,-1,-1,-1,0)(5156=-1,-1,-1,-1,0)(5157=-1,-1,-1,-1,0)(5158=-1,-1,-1,-1,0)(5159=-1,-1,-1,-1,0)(3047=-1,-1,-1,-1,0)(3050=-1,-1,-1,-1,0)(3060=-1,-1,-1,-1,0)(3051=-1,-1,-1,-1,0)(3061=-1,-1,-1,-1,0)
+        
+        
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diff --git a/CL2.0.uvproj b/CL2.0.uvproj
new file mode 100644
index 0000000..9724ee2
--- /dev/null
+++ b/CL2.0.uvproj
@@ -0,0 +1,445 @@
+
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+
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### uVision Project, (C) Keil Software

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+          IRAM(0-0xFF) XRAM(0xF000-0xF5FF) IROM(0-0x5FFF) IROM2(0xA000-0xBFFF) CLOCK(24000000) MOD517DP
+          XC800_FLOAD.EXE ("#H" f")
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diff --git a/CL2.0_uvopt.bak b/CL2.0_uvopt.bak
new file mode 100644
index 0000000..1d7f89e
--- /dev/null
+++ b/CL2.0_uvopt.bak
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+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
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+    *.obj
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+  
+
+
diff --git a/CL2.0_uvproj.bak b/CL2.0_uvproj.bak
new file mode 100644
index 0000000..fe007f1
--- /dev/null
+++ b/CL2.0_uvproj.bak
@@ -0,0 +1,410 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x0
+      MCS-51
+      
+        
+          XC886CLM-8FF
+          Infineon
+          IRAM(0-0xFF) XRAM(0xF000-0xF5FF) IROM(0-0x5FFF) IROM2(0xA000-0xBFFF) CLOCK(24000000) MOD517DP
+          XC800_FLOAD.EXE ("#H" f")
+          "LIB\START_XC88x.A51" ("Infineon XC800 Startup Code")
+          
+          4021
+          XC886CLM.H
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          Infineon\
+          Infineon\
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\output\
+          CL2.0
+          1
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+          1
+          1
+          1
+          .\output\
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+          0
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+          0
+          0
+          3
+          
+          
+          65535
+        
+        
+          S8051.DLL
+          -m8051EW
+          DCore51.DLL
+          -pXC886
+          S8051.DLL
+          
+          TCore51.DLL
+          -pXC886
+        
+        
+          
+            0
+            0
+            0
+            0
+            16
+          
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+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            
+            BIN\DAS2XC800.DLL
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            1
+            4100
+          
+          BIN\DAS2XC800.DLL
+          "XC800_FLOAD.EXE" ("#H" f")
+          
+        
+        
+          
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+            2
+            1
+            
+            RESERVE (I:0xC0-I:0xFF)
+            
+            
+            
+            
+            
+            CODE(C:0x2100-C:0x5FFF)
+            
+            ?C_C51STARTUP(C:0x2100), ?PR?main?MAIN
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Dave Files
+          
+            
+              START_XC.a51
+              2
+              .\START_XC.a51
+            
+            
+              MAIN.C
+              1
+              .\MAIN.C
+            
+            
+              IO.C
+              1
+              .\IO.C
+            
+            
+              SHARED_INT.C
+              1
+              .\SHARED_INT.C
+            
+            
+              CAN.C
+              1
+              .\CAN.C
+            
+            
+              T2.C
+              1
+              .\T2.C
+            
+            
+              WDT.C
+              1
+              .\WDT.C
+            
+          
+        
+        
+          User Files
+          
+            
+              User.c
+              1
+              .\User.c
+            
+            
+              boot.c
+              1
+              .\boot.c
+            
+            
+              XC88x_FLHANDLER.ASM
+              2
+              .\XC88x_FLHANDLER.ASM
+            
+          
+        
+      
+    
+  
+
+
diff --git a/Config.H b/Config.H
new file mode 100644
index 0000000..507123b
--- /dev/null
+++ b/Config.H
@@ -0,0 +1,209 @@
+#ifndef _Configfff_H_
+#define _Configfff_H_
+
+
+//-----궨-----------------------------------------------------------------
+//ز--------------------------------------------------------------
+//֧ƽ̨
+//  ___XC164CM___ 		SSCڲѯʽ
+//  ___XC2765X___ 		SSCڲѯʽ
+#define ___XC886CLM___
+
+#define NumChipSw   2//MC33993оƬ
+#define DF_SwInNum  1//ɼоƬ
+#define DF_SwOutNum 1//оƬ
+
+#define Tog       2
+#define On        1
+#define Off       0
+
+//#define  N       6    //NΪż
+
+
+#define   uchar  unsigned char
+#define   ulong  unsigned long
+#define   uint   unsigned int 
+//CANݽգҪ___CANRX___
+//#define ___CANRX___
+
+//Ź
+//#define DF_WDT  P1_OUT_P0
+
+//                    
+#define SwIn01	  P3_1
+#define SwIn02	  P3_7
+#define SwIn03	  P2_4
+#define SwIn04	  P2_7
+#define SwIn05	  P2_6
+#define SwIn06	  P2_5
+#define SwIn07	  P3_0
+#define SwIn08	  P3_6
+
+#define SwOut01	  P3_2
+#define SwOut02	  P3_4
+#define SwOut03	  P4_0
+#define SwOut04	  P0_7
+#define SwOut05	  P0_0
+#define SwOut06	  P0_1
+#define SwOut07	  P1_3
+#define SwOut08	  P1_5
+#define SwOut09	  P0_3
+#define SwOut10	  P4_1
+#define SwOut11	  P3_3
+#define SwOut12	  P3_3
+#define SwOut13	  P1_4
+#define SwOut14	  P1_2
+#define SwOut15	  P0_2
+#define SwOut16	  P1_7
+
+//LEDݽṹ
+typedef union _SwOut
+{
+	struct
+	{
+//		ubyte Arr[DF_SwOutNum][4];	//оƬı޸
+		ubyte Arr[DF_SwOutNum][4];	//оƬı޸		
+	}ArrData;
+	struct
+	{ 
+//-------оƬ1-------------------------------		
+		unsigned int  S21  : 1;//FLGSP0          
+		unsigned int  S22  : 1;//FLGSP1          
+		unsigned int  S23  : 1;//FLGSP2          
+		unsigned int  S24  : 1;//FLGSP3          
+		unsigned int  S34  : 1;//FLGSP4          
+		unsigned int  S33  : 1;//FLGSP5          
+		unsigned int  S32  : 1;//FLGSP6          
+		unsigned int  S31  : 1;//FLGSP7 		
+		unsigned int  S25  : 1;//FLGSG0          
+		unsigned int  S26  : 1;//FLGSG1          
+		unsigned int  S27  : 1;//FLGSG2          
+		unsigned int  S28  : 1;//FLGSG3          
+		unsigned int  S30  : 1;//FLGSG4          
+		unsigned int  S29  : 1;//FLGSG5          
+		unsigned int  S43  : 1;//FLGSG6   
+		unsigned int  S35  : 1;//FLGSG7 
+		unsigned int  S36  : 1;//FLGSG8   
+		unsigned int  S37  : 1;//FLGSG9   
+		unsigned int  S38  : 1;//FLGSG10  
+		unsigned int  S40  : 1;//FLGSG11  
+		unsigned int  S39  : 1;//FLGSG12  
+		unsigned int  S44  : 1;//FLGSG13  
+		unsigned int           : 1;	
+		unsigned int           : 1;	  
+		unsigned int           : 8;
+//-------------------------------------------------			
+	}BitData;
+}UnSwOut,*pUnSwOut;
+
+
+//CAN--------------------------------------------------------------
+#define NumTxCan 1
+#define NumRxCan 1//15
+#define NumTxCanMoS 16 //ϢŵϢʼ
+#define NumRxCanMoS 0 //ϢŵϢʼ
+#define ___CANRX___ 
+
+//CANϢṹ
+typedef union _InfCan
+{
+	struct
+	{
+		ubyte Arr[1][8];
+		ubyte ArrRX[2][8];
+	}ArrData;
+	struct
+	{
+//----------0-0x14000001 -------------------------------------------
+		unsigned int	 Sta09        : 1  ; //FlgSp1 
+		unsigned int	 Sta10        : 1  ; //FlgSp0 
+		unsigned int	 Sta11        : 1  ; //FlgSp7 
+		unsigned int	 Sta12        : 1  ; //FlgSp6 
+		unsigned int	 Sta13        : 1  ; //FlgSp5 
+		unsigned int	 Sta14        : 1  ; //FlgSp4 
+
+		unsigned int	 Sta15        : 1  ; //FlgSg7 
+		unsigned int	 Sta16        : 1  ; //FlgSg8		
+	               
+		unsigned int   Sta01        : 1  ; //FlgSg4 
+		unsigned int	 Sta02        : 1  ; //FlgSg5 
+		unsigned int	 Sta03        : 1  ; //FlgSg3 
+		unsigned int	 Sta04        : 1  ; //FlgSg2 
+    unsigned int	 Sta05        : 1  ; //FlgSg1 
+		unsigned int	 Sta06        : 1  ; //FlgSg0 
+		unsigned int	 Sta07        : 1  ; //FlgSp3 
+		unsigned int	 Sta08        : 1  ; //FlgSp2 		
+
+		unsigned int   CanTx3       : 8  ;  ////
+
+		unsigned int   Dia01        : 1  ; //FlgSg4 
+		unsigned int	 Dia02        : 1  ; //FlgSg5 
+		unsigned int	 Dia03        : 1  ; //FlgSg3 
+		unsigned int	 Dia04        : 1  ; //FlgSg2 
+    unsigned int	 Dia05        : 1  ; //FlgSg1 
+		unsigned int	 Dia06        : 1  ; //FlgSg0 
+		unsigned int	 Dia07        : 1  ; //FlgSp3 
+		unsigned int	 Dia08        : 1  ; //FlgSp2 
+	
+		unsigned int   CanTx5       : 8  ;  ////
+		unsigned int   CanTx4       : 8  ;  ////	
+		unsigned int   CanTx7       : 8  ;  ////
+		unsigned int   CanTx6       : 8  ;  ////		
+																						
+//----------0x14000002 -------------------------------------------- 
+		unsigned int	 D29        : 1  ; //FlgSp1 
+		unsigned int	 D30        : 1  ; //FlgSp0 
+		unsigned int	 D31        : 1  ; //FlgSp7 
+		unsigned int	 D32        : 1  ; //FlgSp6 
+		unsigned int	 D33        : 1  ; //FlgSp5 
+		unsigned int	 D34        : 1  ; //FlgSp4 
+		unsigned int	 D35        : 1  ; //FlgSg7 
+		unsigned int	 D36        : 1  ; //FlgSg8		
+	               
+		unsigned int   D21        : 1  ; //FlgSg4 
+		unsigned int	 D22        : 1  ; //FlgSg5 
+		unsigned int	 D23        : 1  ; //FlgSg3 
+		unsigned int	 D24        : 1  ; //FlgSg2 
+    unsigned int	 D25        : 1  ; //FlgSg1 
+		unsigned int	 D26        : 1  ; //FlgSg0 
+		unsigned int	 D27        : 1  ; //FlgSp3 
+		unsigned int	 D28        : 1  ; //FlgSp2 		
+
+		unsigned int   CanRx3     : 8  ;  ////
+		unsigned int   CanRx2     : 8  ;  ////	
+		unsigned int   CanRx5     : 8  ;  ////
+		unsigned int   CanRx4     : 8  ;  ////	
+		unsigned int   CanRx7     : 8  ;  ////
+		unsigned int   CanRx6     : 8  ;  ////
+
+//----------0x14000003 -------------------------------------------- 
+		unsigned int	 Pwm_01        : 4  ; //FlgSp1 
+		unsigned int	 Pwm_02        : 4  ; //FlgSp0 
+		unsigned int	 Pwm_03        : 4  ; //FlgSp7 
+		unsigned int	 Pwm_04        : 4  ; //FlgSp6 
+		unsigned int	 Pwm_05        : 4  ; //FlgSp5 
+		unsigned int	 Pwm_06        : 4  ; //FlgSp4 
+		unsigned int	 Pwm_07        : 4  ; //FlgSg7 
+		unsigned int	 Pwm_08        : 4  ; //FlgSg8			               
+		unsigned int   Pwm_09        : 4  ; //FlgSg4 
+		unsigned int	 Pwm_10        : 4  ; //FlgSg5 
+		unsigned int	 Pwm_11        : 4  ; //FlgSg3 
+		unsigned int	 Pwm_12        : 4  ; //FlgSg2 
+    unsigned int	 Pwm_13        : 4  ; //FlgSg1 
+		unsigned int	 Pwm_14        : 4  ; //FlgSg0 
+		unsigned int	 Pwm_15        : 4  ; //FlgSp3 
+		unsigned int	 Pwm_16        : 4  ; //FlgSp2 		
+
+	}BitData;       
+}UnInfCan,*pInfCan;
+
+
+
+
+
+
+//-----ļ----------------------------------------------
+#include  "user.H"
+#include  "boot.H"
+#include  "temperature.H"
+#endif
\ No newline at end of file
diff --git a/Config.H.bak b/Config.H.bak
new file mode 100644
index 0000000..8f29e50
--- /dev/null
+++ b/Config.H.bak
@@ -0,0 +1,247 @@
+#ifndef _Configfff_H_
+#define _Configfff_H_
+
+
+//-----궨-----------------------------------------------------------------
+//ز--------------------------------------------------------------
+//֧ƽ̨
+//  ___XC164CM___ 		SSCڲѯʽ
+//  ___XC2765X___ 		SSCڲѯʽ
+#define ___XC886CLM___
+
+#define NumChipSw   2//MC33993оƬ
+#define DF_SwInNum  1//ɼоƬ
+#define DF_SwOutNum 1//оƬ
+
+#define Tog       2
+#define On        1
+#define Off       0
+
+//#define  N       6    //NΪż
+
+
+#define   uchar  unsigned char
+#define   ulong  unsigned long
+#define   uint   unsigned int 
+//CANݽգҪ___CANRX___
+//#define ___CANRX___
+
+//Ź
+//#define DF_WDT  P1_OUT_P0
+
+//
+#define SwIn01	  P3_0
+#define SwIn02	  P3_7
+#define SwIn03	  P2_4
+#define SwIn04	  P2_5
+#define SwIn05	  P3_1
+#define SwIn06	  P3_6
+#define SwIn07	  P2_6
+#define SwIn08	  P2_7
+#define SwOut01	  P3_2
+#define SwOut02	  P3_4
+#define SwOut03	  P4_0
+#define SwOut04	  P0_7
+#define SwOut05	  P0_0
+#define SwOut06	  P0_1
+#define SwOut07	  P1_3
+#define SwOut08	  P1_5
+#define SwOut09	  P0_3
+#define SwOut10	  P4_1
+#define SwOut11	  P3_5
+#define SwOut12	  P3_3
+#define SwOut13	  P1_4
+#define SwOut14	  P1_2
+#define SwOut15	  P0_2
+#define SwOut16	  P1_7
+
+
+//زɼݽṹӲأӲ޸ҪӦ޸
+typedef union _SwSample
+{
+	struct
+	{
+		ubyte Arr[DF_SwInNum][4];
+	}ArrData;
+	struct
+	{ 
+//-------ɼоƬ1-------------------------------		
+		unsigned int  S6        : 1;//FlgSg0          
+		unsigned int  S5        : 1;//FlgSg1    
+		unsigned int  S4        : 1;//FlgSg2    
+		unsigned int  S3        : 1;//FlgSg3    
+		unsigned int  S1        : 1;//FlgSg4    
+		unsigned int  S2        : 1;//FlgSg5    
+		unsigned int  S41       : 1;//FlgSg6    
+		unsigned int  S15       : 1;//FlgSg7    
+		unsigned int  S16       : 1;//FlgSg8    
+		unsigned int  S17       : 1;//FlgSg9    
+		unsigned int  S18       : 1;//FlgSg10   
+		unsigned int  S20       : 1;//FlgSg11   
+		unsigned int  S19       : 1;//FlgSg12   
+		unsigned int  S42       : 1;//FlgSg13   
+		unsigned int  S10       : 1;//FlgSp0    
+		unsigned int  S9        : 1;//FlgSp1    
+		unsigned int  S8        : 1;//FlgSp2    
+		unsigned int  S7        : 1;//FlgSp3    
+		unsigned int  S14       : 1;//FlgSp4    
+		unsigned int  S13       : 1;//FlgSp5    
+		unsigned int  S12       : 1;//FlgSp6    
+		unsigned int  S11       : 1;//FlgSp7    
+		unsigned int            : 1;//FlgInt    
+		unsigned int            : 1;//FlgThem	
+		unsigned int            : 8;//	
+			
+	}BitData;
+}UnSwSample,*pUnSwSample;
+
+//LEDݽṹ
+typedef union _SwOut
+{
+	struct
+	{
+		ubyte Arr[DF_SwOutNum][4];	//оƬı޸
+	}ArrData;
+	struct
+	{ 
+//-------оƬ1-------------------------------		
+		unsigned int  S21  : 1;//FLGSP0          
+		unsigned int  S22  : 1;//FLGSP1          
+		unsigned int  S23  : 1;//FLGSP2          
+		unsigned int  S24  : 1;//FLGSP3          
+		unsigned int  S34  : 1;//FLGSP4          
+		unsigned int  S33  : 1;//FLGSP5          
+		unsigned int  S32  : 1;//FLGSP6          
+		unsigned int  S31  : 1;//FLGSP7 		
+		unsigned int  S25  : 1;//FLGSG0          
+		unsigned int  S26  : 1;//FLGSG1          
+		unsigned int  S27  : 1;//FLGSG2          
+		unsigned int  S28  : 1;//FLGSG3          
+		unsigned int  S30  : 1;//FLGSG4          
+		unsigned int  S29  : 1;//FLGSG5          
+		unsigned int  S43  : 1;//FLGSG6   
+		unsigned int  S35  : 1;//FLGSG7 
+		unsigned int  S36  : 1;//FLGSG8   
+		unsigned int  S37  : 1;//FLGSG9   
+		unsigned int  S38  : 1;//FLGSG10  
+		unsigned int  S40  : 1;//FLGSG11  
+		unsigned int  S39  : 1;//FLGSG12  
+		unsigned int  S44  : 1;//FLGSG13  
+		unsigned int           : 1;	
+		unsigned int           : 1;	  
+		unsigned int           : 8;
+//-------------------------------------------------			
+	}BitData;
+}UnSwOut,*pUnSwOut;
+
+
+//CAN--------------------------------------------------------------
+#define NumTxCan 1
+#define NumRxCan 1//15
+#define NumTxCanMoS 16 //ϢŵϢʼ
+#define NumRxCanMoS 0 //ϢŵϢʼ
+#define ___CANRX___ 
+
+//CANϢṹ
+typedef union _InfCan
+{
+	struct
+	{
+		ubyte Arr[1][8];
+		ubyte ArrRX[2][8];
+	}ArrData;
+	struct
+	{
+//----------0-0x10000001 -------------------------------------------
+		unsigned int	 Sta09        : 1  ; //FlgSp1 
+		unsigned int	 Sta10        : 1  ; //FlgSp0 
+		unsigned int	 Sta11        : 1  ; //FlgSp7 
+		unsigned int	 Sta12        : 1  ; //FlgSp6 
+		unsigned int	 Sta13        : 1  ; //FlgSp5 
+		unsigned int	 Sta14        : 1  ; //FlgSp4 
+		unsigned int	 Sta15        : 1  ; //FlgSg7 
+		unsigned int	 Sta16        : 1  ; //FlgSg8		
+	               
+		unsigned int   Sta01        : 1  ; //FlgSg4 
+		unsigned int	 Sta02        : 1  ; //FlgSg5 
+		unsigned int	 Sta03        : 1  ; //FlgSg3 
+		unsigned int	 Sta04        : 1  ; //FlgSg2 
+    unsigned int	 Sta05        : 1  ; //FlgSg1 
+		unsigned int	 Sta06        : 1  ; //FlgSg0 
+		unsigned int	 Sta07        : 1  ; //FlgSp3 
+		unsigned int	 Sta08        : 1  ; //FlgSp2 		
+
+		unsigned int   CanTx3       : 8  ;  ////
+
+		unsigned int   Dia01        : 1  ; //FlgSg4 
+		unsigned int	 Dia02        : 1  ; //FlgSg5 
+		unsigned int	 Dia03        : 1  ; //FlgSg3 
+		unsigned int	 Dia04        : 1  ; //FlgSg2 
+    unsigned int	 Dia05        : 1  ; //FlgSg1 
+		unsigned int	 Dia06        : 1  ; //FlgSg0 
+		unsigned int	 Dia07        : 1  ; //FlgSp3 
+		unsigned int	 Dia08        : 1  ; //FlgSp2 
+	
+		unsigned int   CanTx5       : 8  ;  ////
+		unsigned int   CanTx4       : 8  ;  ////	
+		unsigned int   CanTx7       : 8  ;  ////
+		unsigned int   CanTx6       : 8  ;  ////		
+																						
+//----------0x10000002 -------------------------------------------- 
+		unsigned int	 D29        : 1  ; //FlgSp1 
+		unsigned int	 D30        : 1  ; //FlgSp0 
+		unsigned int	 D31        : 1  ; //FlgSp7 
+		unsigned int	 D32        : 1  ; //FlgSp6 
+		unsigned int	 D33        : 1  ; //FlgSp5 
+		unsigned int	 D34        : 1  ; //FlgSp4 
+		unsigned int	 D35        : 1  ; //FlgSg7 
+		unsigned int	 D36        : 1  ; //FlgSg8		
+	               
+		unsigned int   D21        : 1  ; //FlgSg4 
+		unsigned int	 D22        : 1  ; //FlgSg5 
+		unsigned int	 D23        : 1  ; //FlgSg3 
+		unsigned int	 D24        : 1  ; //FlgSg2 
+    unsigned int	 D25        : 1  ; //FlgSg1 
+		unsigned int	 D26        : 1  ; //FlgSg0 
+		unsigned int	 D27        : 1  ; //FlgSp3 
+		unsigned int	 D28        : 1  ; //FlgSp2 		
+
+		unsigned int   CanRx3     : 8  ;  ////
+		unsigned int   CanRx2     : 8  ;  ////	
+		unsigned int   CanRx5     : 8  ;  ////
+		unsigned int   CanRx4     : 8  ;  ////	
+		unsigned int   CanRx7     : 8  ;  ////
+		unsigned int   CanRx6     : 8  ;  ////
+
+//----------0x14000003 -------------------------------------------- 
+		unsigned int	 Pwm01        : 4  ; //FlgSp1 
+		unsigned int	 Pwm02        : 4  ; //FlgSp0 
+		unsigned int	 Pwm03        : 4  ; //FlgSp7 
+		unsigned int	 Pwm04        : 4  ; //FlgSp6 
+		unsigned int	 Pwm05        : 4  ; //FlgSp5 
+		unsigned int	 Pwm06        : 4  ; //FlgSp4 
+		unsigned int	 Pwm07        : 4  ; //FlgSg7 
+		unsigned int	 Pwm08        : 4  ; //FlgSg8			               
+		unsigned int   Pwm09        : 4  ; //FlgSg4 
+		unsigned int	 Pwm10        : 4  ; //FlgSg5 
+		unsigned int	 Pwm11        : 4  ; //FlgSg3 
+		unsigned int	 Pwm12        : 4  ; //FlgSg2 
+    unsigned int	 Pwm13        : 4  ; //FlgSg1 
+		unsigned int	 Pwm14        : 4  ; //FlgSg0 
+		unsigned int	 Pwm15        : 4  ; //FlgSp3 
+		unsigned int	 Pwm16        : 4  ; //FlgSp2 		
+
+	}BitData;       
+}UnInfCan,*pInfCan;
+
+
+
+
+
+
+
+
+//-----ļ----------------------------------------------
+#include  "user.H"
+#include  "boot.H"
+#endif
\ No newline at end of file
diff --git a/ExtDll.iex b/ExtDll.iex
new file mode 100644
index 0000000..b661f48
--- /dev/null
+++ b/ExtDll.iex
@@ -0,0 +1,2 @@
+[EXTDLL]
+Count=0
diff --git a/IO.C b/IO.C
new file mode 100644
index 0000000..0465a69
--- /dev/null
+++ b/IO.C
@@ -0,0 +1,375 @@
+//****************************************************************************
+// @Module        GPIO
+// @Filename      IO.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the IO module.
+//
+//----------------------------------------------------------------------------
+// @Date          2021/9/7 09:54:12
+//
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (IO_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void IO_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the IO function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2021/9/7
+//
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Init,1)
+
+// USER CODE END
+
+void IO_vInit(void)
+{
+  // USER CODE BEGIN (IO_Init,2)
+  ubyte i = 0;
+//  ubyte j = 0;
+  // USER CODE END
+
+
+  ///  ***********************************************************************
+  ///  Note : All peripheral related IO configurations are done in the 
+  ///  respective peripheral modules (alternate functions selection)
+  ///  
+  ///  If no pins are selected DAvE assumes that registers are in default 
+  ///  settings
+  ///  ***********************************************************************
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P0:
+  ///  -----------------------------------------------------------------------
+  ///  P0.0:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P0.1:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P0.2:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P0.3:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P0.7:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P0_PUDSEL     =  0x70;         // load pullup/pulldown select register
+  P0_PUDEN      =  0xCF;         // load pullup/pulldown enable register
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P0_DIR        =  0x8F;         // load direction register
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P1:
+  ///  -----------------------------------------------------------------------
+  ///  P1.0:
+  ///  - is used as alternate input for the MCAN Node 0 Receiver Input
+  ///  - pull-up device is assigned
+  ///  P1.1:
+  ///  - is used as alternate output for the MCAN Node 0 Transmitter Output
+  ///  - push/pull output is selected
+  ///  - pull-up device is assigned
+  ///  P1.2:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P1.3:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P1.4:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P1.5:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P1.7:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P1_PUDSEL     =  0x43;         // load pullup/pulldown select register
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P1_DIR        =  0xBC;         // load direction register
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P2:
+  ///  -----------------------------------------------------------------------
+  ///  P2.4:
+  ///  - is used as general input
+  ///  - input driver is enabled
+  ///  - pull-up device is assigned
+  ///  P2.5:
+  ///  - is used as general input
+  ///  - input driver is enabled
+  ///  - pull-up device is assigned
+  ///  P2.6:
+  ///  - is used as general input
+  ///  - input driver is enabled
+  ///  - pull-up device is assigned
+  ///  P2.7:
+  ///  - is used as general input
+  ///  - input driver is enabled
+  ///  - pull-up device is assigned
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P2_PUDEN      =  0xF0;         // load pullup/pulldown enable register
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P3:
+  ///  -----------------------------------------------------------------------
+  ///  P3.0:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+  ///  P3.1:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+  ///  P3.2:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P3.3:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P3.4:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P3.5:
+  ///  - is used as general purpose output
+  ///  - open drain output is selected
+  ///  - the pin status is high level
+  ///  - pull-up device is assigned
+  ///  P3.6:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+  ///  P3.7:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+
+  SFR_PAGE(_pp3, noSST);         // switch to page 3
+  P3_OD         =  0x20;         // load open-drain register
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P3_PUDSEL     =  0xE3;         // load pullup/pulldown select register
+  P3_PUDEN      =  0xFF;         // load pullup/pulldown enable register
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  0x3C;         // load direction register
+  P3_DATA       =  0x20;         // load data output register
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P4:
+  ///  -----------------------------------------------------------------------
+  ///  P4.0:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P4.1:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P4.3:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P4_PUDSEL     =  0x00;         // load pullup/pulldown select register
+  P4_PUDEN      =  0x0B;         // load pullup/pulldown enable register
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P4_DIR        =  0x0B;         // load direction register
+
+
+  // USER CODE BEGIN (IO_Init,3)
+	if((0x55 != RestartDataFlg1) || (0x55 != RestartDataFlg2))//ֻҪһֵͬ˵Ϊϵ
+	{
+		for(i=0;i<8;i++)//0xF5E8~0xF5FF
+		{
+			UnInfCan_1.ArrData.Arr[0][i] = 0;
+			UnInfCan_1.ArrData.ArrRX[0][i] = 0;
+			UnInfCan_1.ArrData.ArrRX[1][i] = 0;
+		}
+	  RestartDataFlg1 = 0x55;//״̬ҪֵΪ0x55 0xF5E7
+    RestartDataFlg2 = 0x55;//ַ0xF600
+		
+		dfOut_01 = 0;//ϵ磬ʼ
+		dfOut_02 = 0;
+		dfOut_03 = 0;
+		dfOut_04 = 0;
+		dfOut_05 = 0;
+		dfOut_06 = 0;
+		dfOut_07 = 0;
+		dfOut_08 = 0;
+		dfOut_09 = 0;
+		dfOut_10 = 0;
+		dfOut_11 = 0;
+		dfOut_12 = 0;
+		dfOut_13 = 0;
+		dfOut_14 = 0;
+		dfOut_15 = 0;
+		dfOut_16 = 0;
+		RestartDataKGF = 0;
+	}	
+	else//,IOھͻָ
+	{
+		dfOut_01 = (bit)(RestartDataKGF&0x0001);      //20210906ָIO״̬ KGFָʾ˸		עubyteתΪbitֱͣȡΪǸݸֵΪ0ȡ0Ϊ1ȡ1
+		dfOut_02 = (bit)((RestartDataKGF >> 1)&0x0001);
+		dfOut_03 = (bit)((RestartDataKGF >> 2)&0x0001);
+		dfOut_04 = (bit)((RestartDataKGF >> 3)&0x0001);
+		dfOut_05 = (bit)((RestartDataKGF >> 4)&0x0001);
+		dfOut_06 = (bit)((RestartDataKGF >> 5)&0x0001);
+		dfOut_07 = (bit)((RestartDataKGF >> 6)&0x0001);
+		dfOut_08 = (bit)((RestartDataKGF >> 7)&0x0001);
+		dfOut_09 = (bit)((RestartDataKGF >> 8)&0x0001);
+		dfOut_10 = (bit)((RestartDataKGF >> 9)&0x0001);
+		dfOut_11 = (bit)((RestartDataKGF >> 10)&0x0001);
+		dfOut_12 = (bit)((RestartDataKGF >> 11)&0x0001);
+		dfOut_13 = (bit)((RestartDataKGF >> 12)&0x0001);
+		dfOut_14 = (bit)((RestartDataKGF >> 13)&0x0001);
+		dfOut_15 = (bit)((RestartDataKGF >> 14)&0x0001);
+		dfOut_16 = (bit)((RestartDataKGF >> 15)&0x0001);			
+	}
+	
+  // USER CODE END
+
+} //  End of function IO_vInit
+
+
+
+
+// USER CODE BEGIN (IO_General,10)
+
+// USER CODE END
+
diff --git a/IO.H b/IO.H
new file mode 100644
index 0000000..3605c35
--- /dev/null
+++ b/IO.H
@@ -0,0 +1,248 @@
+//****************************************************************************
+// @Module        GPIO
+// @Filename      IO.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the IO module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:29
+//
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _IO_H_
+#define _IO_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,4)
+
+// USER CODE END
+
+//   Port 0
+
+sbit P0_0       = 0x80;    
+sbit P0_1       = 0x81;    
+sbit P0_2       = 0x82;    
+sbit P0_3       = 0x83;    
+sbit P0_4       = 0x84;    
+sbit P0_5       = 0x85;    
+sbit P0_7       = 0x87;    
+
+//   Port 1
+
+sbit P1_0       = 0x90;    
+sbit P1_1       = 0x91;    
+sbit P1_2       = 0x92;    
+sbit P1_3       = 0x93;    
+sbit P1_4       = 0x94;    
+sbit P1_5       = 0x95;    
+sbit P1_6       = 0x96;    
+sbit P1_7       = 0x97;    
+
+//   Port 2
+
+sbit P2_0       = 0xA0;    
+sbit P2_1       = 0xA1;    
+sbit P2_2       = 0xA2;    
+sbit P2_3       = 0xA3;    
+sbit P2_4       = 0xA4;    
+sbit P2_5       = 0xA5;    
+sbit P2_6       = 0xA6;    
+sbit P2_7       = 0xA7;    
+
+//   Port 3
+
+sbit P3_0       = 0xB0;    
+sbit P3_1       = 0xB1;    
+sbit P3_2       = 0xB2;    
+sbit P3_3       = 0xB3;    
+sbit P3_4       = 0xB4;    
+sbit P3_5       = 0xB5;    
+sbit P3_6       = 0xB6;    
+sbit P3_7       = 0xB7;    
+
+//   Port 4
+
+sbit P4_0       = 0xC8;    
+sbit P4_1       = 0xC9;    
+sbit P4_3       = 0xCB;    
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void IO_vInit(void);
+
+
+// USER CODE BEGIN (IO_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         IO_ubReadPin(PinName) 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro returns the status of the chosen portpin.
+//                Note:
+//                'PinName' identifies the pin of a bit-addressable port. The 
+//                default names can be changed in the port configuration 
+//                dialog. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   Status of the chosen portpin
+//
+//----------------------------------------------------------------------------
+// @Parameters    PinName: 
+//                Pin to be read
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define IO_ubReadPin(PinName) PinName
+
+//****************************************************************************
+// @Macro         IO_vSetPin(PinName) 
+//
+//----------------------------------------------------------------------------
+// @Description   The chosen portpin is set to '1'.
+//                Note:
+//                'PinName' identifies the pin of a bit-addressable port. The 
+//                default names can be changed in the port configuration 
+//                dialog. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    PinName: 
+//                Pin to be set to '1'
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define IO_vSetPin(PinName) PinName = 1
+
+//****************************************************************************
+// @Macro         IO_vResetPin(PinName) 
+//
+//----------------------------------------------------------------------------
+// @Description   The chosen portpin is set to '0'. 
+//                Note: 
+//                'PinName' identifies the pin of a bit-addressable port. The 
+//                default names can be changed in the port configuration 
+//                dialog. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    PinName: 
+//                Pin to be set to '0'
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define IO_vResetPin(PinName) PinName = 0
+
+//****************************************************************************
+// @Macro         IO_vTogglePin(PinName) 
+//
+//----------------------------------------------------------------------------
+// @Description   The chosen portpin will be toggled. 
+//                Note:
+//                'PinName' identifies the pin of a bit-addressable port. The 
+//                default names can be changed in the port configuration 
+//                dialog. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    PinName: 
+//                Pin to be toggled
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define IO_vTogglePin(PinName) PinName ^= 1
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,9)
+
+// USER CODE END
+
+
+#endif  // ifndef _IO_H_
diff --git a/MAIN.C b/MAIN.C
new file mode 100644
index 0000000..08a19a6
--- /dev/null
+++ b/MAIN.C
@@ -0,0 +1,271 @@
+//****************************************************************************
+// @Module        Project Settings
+// @Filename      MAIN.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description   This file contains the Project initialization function.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:29
+//
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (MAIN_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+
+// USER CODE BEGIN (MAIN_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void MAIN_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function initializes the microcontroller. It is 
+//                assumed that the SFRs are in their reset state.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Init,1)
+
+// USER CODE END
+
+void MAIN_vInit(void)
+{
+  // USER CODE BEGIN (MAIN_Init,2)
+
+  // USER CODE END
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the System Clock:
+  ///  -----------------------------------------------------------------------
+  ///  - External Osc is selected (configuration is done in the startup file 
+  ///    'START_XC.A51')
+  ///  - PLL Mode, NDIV =  24
+  ///  - input frequency is 8 MHz
+
+
+  //   FCLK runs at 2 times the frequency of PCLK.
+  SFR_PAGE(_su1, noSST);         // switch to page1
+
+  CMCON         =  0x10;         // load Clock Control Register
+
+  SFR_PAGE(_su0, noSST);         // switch to page0
+
+
+  ///  *********************************************************************************
+  ///  Note : All peripheral related IO configurations are done in the 
+  ///  respective peripheral modules (alternate functions selection)
+  ///  *********************************************************************************
+
+  ///  Initialization of module 'GPIO'
+  IO_vInit();
+
+  ///  Initialization of module 'Timer 2'
+  T2_vInit();
+
+  ///  Initialization of module 'Watch Dog Timer'
+  WDT_vInit();
+
+  ///  Initialization of module 'MultiCAN Controller '
+  CAN_vInit();
+
+  ///  Initialization of  'Shared interrupts'
+  SHINT_vInit();
+
+  //   Interrupt Priority
+
+  IP            =  0x00;         // load Interrupt Priority Register
+  IPH           =  0x00;         // load Interrupt Priority High Register
+  IP1           =  0x00;         // load Interrupt Priority 1 Register
+  IPH1          =  0x00;         // load Interrupt Priority 1 High Register
+
+
+  // USER CODE BEGIN (MAIN_Init,3)
+
+  // USER CODE END
+
+  //// Interrupt structure 2 mode 0 is selected.
+
+  //// Interrupt service routine choice 2 is selected.
+
+  //   globally enable interrupts
+  EA            =  1;           
+
+} //  End of function MAIN_vInit
+
+
+//****************************************************************************
+// @Function      void main(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the main function.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Main,1)
+
+// USER CODE END
+
+void main(void)
+{
+  // USER CODE BEGIN (MAIN_Main,2)
+//  ulong i,j;
+// 	static ubyte tmp[8] = {0};
+//	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+
+  // USER CODE END
+
+  MAIN_vInit();
+
+  // USER CODE BEGIN (MAIN_Main,3)
+	SCU_PAGE        = 0;
+	SP              = 0xC0;    // Initialize Stack Pointer to 0xC0;	
+//	CanTransmit();
+
+//	 BM8563_InitTime();	
+//	 BM8563_Set4HourAlarm();//
+//	KGF_PIN = 1;//KGF
+	
+	SetConfig(CFG_MPS_Single,CFG_Repeatbility_High);
+//	FlgCan_1 = 1;//λʱһʱٵCAN
+  // USER CODE END
+	
+//	SetConfig(1,CFG_MPS_Single,CFG_Repeatbility_High);	
+	
+//  RomNum = Search_ROM(romid);//ǰϵоƬROM IDromidоƬ
+	
+	
+  while(1)
+  {
+
+  // USER CODE BEGIN (MAIN_Main,4)
+//  		for(j=0;j<200;j++){for(i=0;i<133;i++)WDT_vRefresh();}
+//  		tmp[3] = (ubyte)CntCan_1;
+//  		tmp[2] = (ubyte)(CntCan_1>>8);
+
+//		SwSample();
+    RestartDataFlg1 = 0x55;//״̬ҪֵΪ0x55
+    RestartDataFlg2 = 0x55;
+		
+		CanRXTX();
+		CanErrorProcess();			
+		WDT_vRefresh();
+		LedDr();
+		BootMain();
+		
+		
+// 		tmp[1] = (ubyte)CntCan_1;
+//  		tmp[0] = (ubyte)(CntCan_1>>8);
+//  		CAN_vLoadData(0x2, (ulong *)(tmp)); // Add this Line			
+//  		CAN_vTransmit(2);	
+//  		for(j=0;j<200;j++){for(i=0;i<133;i++)WDT_vRefresh();}
+  // USER CODE END
+
+  }
+
+} //  End of function main
+
+
+// USER CODE BEGIN (MAIN_General,10)
+
+// USER CODE END
+
diff --git a/MAIN.H b/MAIN.H
new file mode 100644
index 0000000..df8056c
--- /dev/null
+++ b/MAIN.H
@@ -0,0 +1,625 @@
+//****************************************************************************
+// @Module        Project Settings
+// @Filename      MAIN.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description   This is the include header file for all other modules.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:27
+//
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _MAIN_H_
+#define _MAIN_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// Please ensure that SCU_PAGE is switched to Page 1 before using these macros
+#define MAIN_vUnlockProtecReg() PASSWD = 0x9B 
+#define MAIN_vlockProtecReg()   PASSWD = 0xAB
+
+
+// USER CODE BEGIN (MAIN_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,4)
+
+// USER CODE END
+
+#define bool  bit
+#define ulong unsigned long
+#define uword unsigned int
+#define ubyte unsigned char
+
+
+#define KEIL
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+
+// USER CODE BEGIN (MAIN_Header,5)
+
+// USER CODE END
+
+
+//   -------------------------------------------------------------------------
+//   Declaration of SFRs
+//   -------------------------------------------------------------------------
+
+//   Notes: You can avoid the problem that your compiler does not yet support 
+//          the latest derivatives if you use the SFR definitions generated 
+//          by DAvE instead of those that come along with your compiler (in 
+//          the "Register File").
+
+//          PORT SFRs are defined in file 'IO.H'.
+
+//   SFR byte definitions
+sfr ACC        = 0xE0;    
+sfr ADC_CHCTR0 = 0xCA;    
+sfr ADC_CHCTR1 = 0xCB;    
+sfr ADC_CHCTR2 = 0xCC;    
+sfr ADC_CHCTR3 = 0xCD;    
+sfr ADC_CHCTR4 = 0xCE;    
+sfr ADC_CHCTR5 = 0xCF;    
+sfr ADC_CHCTR6 = 0xD2;    
+sfr ADC_CHCTR7 = 0xD3;    
+sfr ADC_CHINCR = 0xCB;    
+sfr ADC_CHINFR = 0xCA;    
+sfr ADC_CHINPR = 0xCD;    
+sfr ADC_CHINSR = 0xCC;    
+sfr ADC_CRCR1  = 0xCA;    
+sfr ADC_CRMR1  = 0xCC;    
+sfr ADC_CRPR1  = 0xCB;    
+sfr ADC_ETRCR  = 0xCF;    
+sfr ADC_EVINCR = 0xCF;    
+sfr ADC_EVINFR = 0xCE;    
+sfr ADC_EVINPR = 0xD3;    
+sfr ADC_EVINSR = 0xD2;    
+sfr ADC_GLOBCTR = 0xCA;    
+sfr ADC_GLOBSTR = 0xCB;    
+sfr ADC_INPCR0 = 0xCE;    
+sfr ADC_LCBR   = 0xCD;    
+sfr ADC_PAGE   = 0xD1;    
+sfr ADC_PRAR   = 0xCC;    
+sfr ADC_Q0R0   = 0xCF;    
+sfr ADC_QBUR0  = 0xD2;    
+sfr ADC_QINR0  = 0xD2;    
+sfr ADC_QMR0   = 0xCD;    
+sfr ADC_QSR0   = 0xCE;    
+sfr ADC_RCR0   = 0xCA;    
+sfr ADC_RCR1   = 0xCB;    
+sfr ADC_RCR2   = 0xCC;    
+sfr ADC_RCR3   = 0xCD;    
+sfr ADC_RESR0H = 0xCB;    
+sfr ADC_RESR0L = 0xCA;    
+sfr ADC_RESR1H = 0xCD;    
+sfr ADC_RESR1L = 0xCC;    
+sfr ADC_RESR2H = 0xCF;    
+sfr ADC_RESR2L = 0xCE;    
+sfr ADC_RESR3H = 0xD3;    
+sfr ADC_RESR3L = 0xD2;    
+sfr ADC_RESRA0H = 0xCB;    
+sfr ADC_RESRA0L = 0xCA;    
+sfr ADC_RESRA1H = 0xCD;    
+sfr ADC_RESRA1L = 0xCC;    
+sfr ADC_RESRA2H = 0xCF;    
+sfr ADC_RESRA2L = 0xCE;    
+sfr ADC_RESRA3H = 0xD3;    
+sfr ADC_RESRA3L = 0xD2;    
+sfr ADC_VFCR   = 0xCE;    
+sfr B          = 0xF0;    
+sfr BCON       = 0xBD;    
+sfr BG         = 0xBE;    
+sfr CAN_ADCON  = 0xD8;    
+sfr CAN_ADH    = 0xDA;    
+sfr CAN_ADL    = 0xD9;    
+sfr CAN_DATA0  = 0xDB;    
+sfr CAN_DATA1  = 0xDC;    
+sfr CAN_DATA2  = 0xDD;    
+sfr CAN_DATA3  = 0xDE;    
+sfr CCU6_CC60RH = 0xFB;    
+sfr CCU6_CC60RL = 0xFA;    
+sfr CCU6_CC60SRH = 0xFB;    
+sfr CCU6_CC60SRL = 0xFA;    
+sfr CCU6_CC61RH = 0xFD;    
+sfr CCU6_CC61RL = 0xFC;    
+sfr CCU6_CC61SRH = 0xFD;    
+sfr CCU6_CC61SRL = 0xFC;    
+sfr CCU6_CC62RH = 0xFF;    
+sfr CCU6_CC62RL = 0xFE;    
+sfr CCU6_CC62SRH = 0xFF;    
+sfr CCU6_CC62SRL = 0xFE;    
+sfr CCU6_CC63RH = 0x9B;    
+sfr CCU6_CC63RL = 0x9A;    
+sfr CCU6_CC63SRH = 0x9B;    
+sfr CCU6_CC63SRL = 0x9A;    
+sfr CCU6_CMPMODIFH = 0xA7;    
+sfr CCU6_CMPMODIFL = 0xA6;    
+sfr CCU6_CMPSTATH = 0xFF;    
+sfr CCU6_CMPSTATL = 0xFE;    
+sfr CCU6_IENH  = 0x9D;    
+sfr CCU6_IENL  = 0x9C;    
+sfr CCU6_INPH  = 0x9F;    
+sfr CCU6_INPL  = 0x9E;    
+sfr CCU6_ISH   = 0x9D;    
+sfr CCU6_ISL   = 0x9C;    
+sfr CCU6_ISRH  = 0xA5;    
+sfr CCU6_ISRL  = 0xA4;    
+sfr CCU6_ISSH  = 0xA5;    
+sfr CCU6_ISSL  = 0xA4;    
+sfr CCU6_MCMCTR = 0xA7;    
+sfr CCU6_MCMOUTH = 0x9B;    
+sfr CCU6_MCMOUTL = 0x9A;    
+sfr CCU6_MCMOUTSH = 0x9F;    
+sfr CCU6_MCMOUTSL = 0x9E;    
+sfr CCU6_MODCTRH = 0xFD;    
+sfr CCU6_MODCTRL = 0xFC;    
+sfr CCU6_PAGE  = 0xA3;    
+sfr CCU6_PISEL0H = 0x9F;    
+sfr CCU6_PISEL0L = 0x9E;    
+sfr CCU6_PISEL2 = 0xA4;    
+sfr CCU6_PSLR  = 0xA6;    
+sfr CCU6_T12DTCH = 0xA5;    
+sfr CCU6_T12DTCL = 0xA4;    
+sfr CCU6_T12H  = 0xFB;    
+sfr CCU6_T12L  = 0xFA;    
+sfr CCU6_T12MSELH = 0x9B;    
+sfr CCU6_T12MSELL = 0x9A;    
+sfr CCU6_T12PRH = 0x9D;    
+sfr CCU6_T12PRL = 0x9C;    
+sfr CCU6_T13H  = 0xFD;    
+sfr CCU6_T13L  = 0xFC;    
+sfr CCU6_T13PRH = 0x9F;    
+sfr CCU6_T13PRL = 0x9E;    
+sfr CCU6_TCTR0H = 0xA7;    
+sfr CCU6_TCTR0L = 0xA6;    
+sfr CCU6_TCTR2H = 0xFB;    
+sfr CCU6_TCTR2L = 0xFA;    
+sfr CCU6_TCTR4H = 0x9D;    
+sfr CCU6_TCTR4L = 0x9C;    
+sfr CCU6_TRPCTRH = 0xFF;    
+sfr CCU6_TRPCTRL = 0xFE;    
+sfr CD_CON     = 0xA1;    
+sfr CD_CORDXH  = 0x9B;    
+sfr CD_CORDXL  = 0x9A;    
+sfr CD_CORDYH  = 0x9D;    
+sfr CD_CORDYL  = 0x9C;    
+sfr CD_CORDZH  = 0x9F;    
+sfr CD_CORDZL  = 0x9E;    
+sfr CD_STATC   = 0xA0;    
+sfr CMCON      = 0xBA;    
+sfr COCON      = 0xBE;    
+sfr DPH        = 0x83;    
+sfr DPL        = 0x82;    
+sfr EO         = 0xA2;    
+sfr EXICON0    = 0xB7;    
+sfr EXICON1    = 0xBA;    
+sfr FDCON      = 0xE9;    
+sfr FDRES      = 0xEB;    
+sfr FDSTEP     = 0xEA;    
+sfr FEAH       = 0xBD;    
+sfr FEAL       = 0xBC;    
+sfr HWBPDR     = 0xF7;    
+sfr HWBPSR     = 0xF6;    
+sfr ID         = 0xB3;    
+sfr IEN0       = 0xA8;    
+sfr IEN1       = 0xE8;    
+sfr IP         = 0xB8;    
+sfr IP1        = 0xF8;    
+sfr IPH        = 0xB9;    
+sfr IPH1       = 0xF9;    
+sfr IRCON0     = 0xB4;    
+sfr IRCON1     = 0xB5;    
+sfr IRCON2     = 0xB6;    
+sfr IRCON3     = 0xB4;    
+sfr IRCON4     = 0xB5;    
+sfr MDU_MD0    = 0xB2;    
+sfr MDU_MD1    = 0xB3;    
+sfr MDU_MD2    = 0xB4;    
+sfr MDU_MD3    = 0xB5;    
+sfr MDU_MD4    = 0xB6;    
+sfr MDU_MD5    = 0xB7;    
+sfr MDU_MDUCON = 0xB1;    
+sfr MDU_MDUSTAT = 0xB0;    
+sfr MDU_MR0    = 0xB2;    
+sfr MDU_MR1    = 0xB3;    
+sfr MDU_MR2    = 0xB4;    
+sfr MDU_MR3    = 0xB5;    
+sfr MDU_MR4    = 0xB6;    
+sfr MDU_MR5    = 0xB7;    
+sfr MISC_CON   = 0xE9;    
+sfr MMBPCR     = 0xF3;    
+sfr MMCR       = 0xF1;    
+sfr MMCR2      = 0xE9;    
+sfr MMDR       = 0xF5;    
+sfr MMICR      = 0xF4;    
+sfr MMSR       = 0xF2;    
+sfr MMWR1      = 0xEB;    
+sfr MMWR2      = 0xEC;    
+sfr MODPISEL   = 0xB3;    
+sfr MODPISEL1  = 0xB7;    
+sfr MODPISEL2  = 0xBA;    
+sfr MODSUSP    = 0xBD;    
+sfr NMICON     = 0xBB;    
+sfr NMISR      = 0xBC;    
+sfr OSC_CON    = 0xB6;    
+sfr P0_ALTSEL0 = 0x80;    
+sfr P0_ALTSEL1 = 0x86;    
+sfr P0_DATA    = 0x80;    
+sfr P0_DIR     = 0x86;    
+sfr P0_OD      = 0x80;    
+sfr P0_PUDEN   = 0x86;    
+sfr P0_PUDSEL  = 0x80;    
+sfr P1_ALTSEL0 = 0x90;    
+sfr P1_ALTSEL1 = 0x91;    
+sfr P1_DATA    = 0x90;    
+sfr P1_DIR     = 0x91;    
+sfr P1_OD      = 0x90;    
+sfr P1_PUDEN   = 0x91;    
+sfr P1_PUDSEL  = 0x90;    
+sfr P2_DATA    = 0xA0;    
+sfr P2_DIR     = 0xA1;    
+sfr P2_PUDEN   = 0xA1;    
+sfr P2_PUDSEL  = 0xA0;    
+sfr P3_ALTSEL0 = 0xB0;    
+sfr P3_ALTSEL1 = 0xB1;    
+sfr P3_DATA    = 0xB0;    
+sfr P3_DIR     = 0xB1;    
+sfr P3_OD      = 0xB0;    
+sfr P3_PUDEN   = 0xB1;    
+sfr P3_PUDSEL  = 0xB0;    
+sfr P4_ALTSEL0 = 0xC8;    
+sfr P4_ALTSEL1 = 0xC9;    
+sfr P4_DATA    = 0xC8;    
+sfr P4_DIR     = 0xC9;    
+sfr P4_OD      = 0xC8;    
+sfr P4_PUDEN   = 0xC9;    
+sfr P4_PUDSEL  = 0xC8;    
+sfr P5_ALTSEL0 = 0x92;    
+sfr P5_ALTSEL1 = 0x93;    
+sfr P5_DATA    = 0x92;    
+sfr P5_DIR     = 0x93;    
+sfr P5_OD      = 0x92;    
+sfr P5_PUDEN   = 0x93;    
+sfr P5_PUDSEL  = 0x92;    
+sfr PASSWD     = 0xBB;    
+sfr PCON       = 0x87;    
+sfr PLL_CON    = 0xB7;    
+sfr PMCON0     = 0xB4;    
+sfr PMCON1     = 0xB5;    
+sfr PMCON2     = 0xBB;    
+sfr PORT_PAGE  = 0xB2;    
+sfr PSW        = 0xD0;    
+sfr SBUF       = 0x99;    
+sfr SCON       = 0x98;    
+sfr SCU_PAGE   = 0xBF;    
+sfr SP         = 0x81;    
+sfr SSC_BRH    = 0xAF;    
+sfr SSC_BRL    = 0xAE;    
+sfr SSC_CONH_O = 0xAB;    
+sfr SSC_CONH_P = 0xAB;    
+sfr SSC_CONL_O = 0xAA;    
+sfr SSC_CONL_P = 0xAA;    
+sfr SSC_PISEL  = 0xA9;    
+sfr SSC_RBL    = 0xAD;    
+sfr SSC_TBL    = 0xAC;    
+sfr SYSCON0    = 0x8F;    
+sfr T21_RC2H   = 0xC3;    
+sfr T21_RC2L   = 0xC2;    
+sfr T21_T2CON  = 0xC0;    
+sfr T21_T2H    = 0xC5;    
+sfr T21_T2L    = 0xC4;    
+sfr T21_T2MOD  = 0xC1;    
+sfr T2_RC2H    = 0xC3;    
+sfr T2_RC2L    = 0xC2;    
+sfr T2_T2CON   = 0xC0;    
+sfr T2_T2H     = 0xC5;    
+sfr T2_T2L     = 0xC4;    
+sfr T2_T2MOD   = 0xC1;    
+sfr TCON       = 0x88;    
+sfr TH0        = 0x8C;    
+sfr TH1        = 0x8D;    
+sfr TL0        = 0x8A;    
+sfr TL1        = 0x8B;    
+sfr TMOD       = 0x89;    
+sfr UART1_BCON = 0xCA;    
+sfr UART1_BG   = 0xCB;    
+sfr UART1_FDCON = 0xCC;    
+sfr UART1_FDRES = 0xCE;    
+sfr UART1_FDSTEP = 0xCD;    
+sfr UART1_SBUF = 0xC9;    
+sfr UART1_SCON = 0xC8;    
+sfr WDTCON     = 0xBB;    //   located in the mapped SFR area
+sfr WDTH       = 0xBF;    //   located in the mapped SFR area
+sfr WDTL       = 0xBE;    //   located in the mapped SFR area
+sfr WDTREL     = 0xBC;    //   located in the mapped SFR area
+sfr WDTWINB    = 0xBD;    //   located in the mapped SFR area
+sfr XADDRH     = 0xB3;    
+
+//   SFR bit definitions
+
+//   CD_STATC
+sbit CD_BSY     = 0xA0;    
+sbit DMAP       = 0xA4;    
+sbit EOC        = 0xA2;    
+sbit ERROR      = 0xA1;    
+sbit INT_EN     = 0xA3;    
+sbit KEEPX      = 0xA5;    
+sbit KEEPY      = 0xA6;    
+sbit KEEPZ      = 0xA7;    
+
+//   IEN0
+sbit EA         = 0xAF;    
+sbit ES         = 0xAC;    
+sbit ET0        = 0xA9;    
+sbit ET1        = 0xAB;    
+sbit ET2        = 0xAD;    
+sbit EX0        = 0xA8;    
+sbit EX1        = 0xAA;    
+
+//   IEN1
+sbit EADC       = 0xE8;    
+sbit ECCIP0     = 0xEC;    
+sbit ECCIP1     = 0xED;    
+sbit ECCIP2     = 0xEE;    
+sbit ECCIP3     = 0xEF;    
+sbit ESSC       = 0xE9;    
+sbit EX2        = 0xEA;    
+sbit EXM        = 0xEB;    
+
+//   IP1
+sbit PADC       = 0xF8;    
+sbit PCCIP0     = 0xFC;    
+sbit PCCIP1     = 0xFD;    
+sbit PCCIP2     = 0xFE;    
+sbit PCCIP3     = 0xFF;    
+sbit PSSC       = 0xF9;    
+sbit PX2        = 0xFA;    
+sbit PXM        = 0xFB;    
+
+//   IP
+sbit PS         = 0xBC;    
+sbit PT0        = 0xB9;    
+sbit PT1        = 0xBB;    
+sbit PT2        = 0xBD;    
+sbit PX0        = 0xB8;    
+sbit PX1        = 0xBA;    
+
+//   MDU_MDUSTAT
+sbit IERR       = 0xB1;    
+sbit IRDY       = 0xB0;    
+sbit MDU_BSY    = 0xB2;    
+
+//   PSW
+sbit AC         = 0xD6;    
+sbit CY         = 0xD7;    
+sbit F0         = 0xD5;    
+sbit F1         = 0xD1;    
+sbit OV         = 0xD2;    
+sbit P          = 0xD0;    
+sbit RS0        = 0xD3;    
+sbit RS1        = 0xD4;    
+
+//   SCON
+sbit RB8        = 0x9A;    
+sbit REN        = 0x9C;    
+sbit RI         = 0x98;    
+sbit SM0        = 0x9F;    
+sbit SM1        = 0x9E;    
+sbit SM2        = 0x9D;    
+sbit TB8        = 0x9B;    
+sbit TI         = 0x99;    
+
+//   T2_T2CON and T21_T2CON
+sbit C_T2       = 0xC1;    
+sbit CP_RL2     = 0xC0;    
+sbit EXEN2      = 0xC3;    
+sbit EXF2       = 0xC6;    
+sbit TF2        = 0xC7;    
+sbit TR2        = 0xC2;    
+
+//   TCON
+sbit IE0        = 0x89;    
+sbit IE1        = 0x8B;    
+sbit IT0        = 0x88;    
+sbit IT1        = 0x8A;    
+sbit TF0        = 0x8D;    
+sbit TF1        = 0x8F;    
+sbit TR0        = 0x8C;    
+sbit TR1        = 0x8E;    
+
+//   UART1_SCON
+sbit RB8_1      = 0xCA;    
+sbit REN_1      = 0xCC;    
+sbit RI_1       = 0xC8;    
+sbit SM0_1      = 0xCF;    
+sbit SM1_1      = 0xCE;    
+sbit SM2_1      = 0xCD;    
+sbit TB8_1      = 0xCB;    
+sbit TI_1       = 0xC9;    
+
+
+//   Definition of the 16-bit SFR
+//   sfr16 data type to access two 8-bit SFRs as a single 16-bit SFR.
+
+sfr16 CAN_ADLH = 0xD9;           // 16-bit Address
+sfr16 CAN_DATA01 = 0xDB;         // 16-bit Address
+sfr16 CAN_DATA23 = 0xDD;         // 16-bit Address
+sfr16 CCU6_CC60RLH = 0xFA;       // 16-bit Address
+sfr16 CCU6_CC60SRLH = 0xFA;      // 16-bit Address
+sfr16 CCU6_CC61RLH = 0xFC;       // 16-bit Address
+sfr16 CCU6_CC61SRLH = 0xFC;      // 16-bit Address
+sfr16 CCU6_CC62RLH = 0xFE;       // 16-bit Address
+sfr16 CCU6_CC62SRLH = 0xFE;      // 16-bit Address
+sfr16 CCU6_CC63RLH = 0x9A;       // 16-bit Address
+sfr16 CCU6_CC63SRLH = 0x9A;      // 16-bit Address
+sfr16 CCU6_T12LH = 0xFA;         // 16-bit Address
+sfr16 CCU6_T12PRLH = 0x9C;       // 16-bit Address
+sfr16 CCU6_T13LH = 0xFC;         // 16-bit Address
+sfr16 CCU6_T13PRLH = 0x9E;       // 16-bit Address
+sfr16 T21_RC2LH = 0xC2;          // 16-bit Address
+sfr16 T21_T2LH = 0xC4;           // 16-bit Address
+sfr16 T2_RC2LH = 0xC2;           // 16-bit Address
+sfr16 T2_T2LH = 0xC4;            // 16-bit Address
+
+//   Definition of the PAGE SFR
+
+//   PORT_PAGE
+#define _pp0 PORT_PAGE=0 // PORT_PAGE postfix
+#define _pp1 PORT_PAGE=1 // PORT_PAGE postfix
+#define _pp2 PORT_PAGE=2 // PORT_PAGE postfix
+#define _pp3 PORT_PAGE=3 // PORT_PAGE postfix
+
+//   ADC_PAGE
+#define _ad0 ADC_PAGE=0 // ADC_PAGE postfix
+#define _ad1 ADC_PAGE=1 // ADC_PAGE postfix
+#define _ad2 ADC_PAGE=2 // ADC_PAGE postfix
+#define _ad3 ADC_PAGE=3 // ADC_PAGE postfix
+#define _ad4 ADC_PAGE=4 // ADC_PAGE postfix
+#define _ad5 ADC_PAGE=5 // ADC_PAGE postfix
+#define _ad6 ADC_PAGE=6 // ADC_PAGE postfix
+
+//   SCU_PAGE
+#define _su0 SCU_PAGE=0 // SCU_PAGE postfix
+#define _su1 SCU_PAGE=1 // SCU_PAGE postfix
+#define _su2 SCU_PAGE=2 // SCU_PAGE postfix
+#define _su3 SCU_PAGE=3 // SCU_PAGE postfix
+
+//   CCU6_PAGE
+#define _cc0 CCU6_PAGE=0 // CCU6_PAGE postfix
+#define _cc1 CCU6_PAGE=1 // CCU6_PAGE postfix
+#define _cc2 CCU6_PAGE=2 // CCU6_PAGE postfix
+#define _cc3 CCU6_PAGE=3 // CCU6_PAGE postfix
+
+#define SST0  0x80        // Save SFR page to ST0
+#define RST0  0xC0        // Restore SFR page from ST0
+#define SST1  0x90        // Save SFR page to ST1
+#define RST1  0xD0        // Restore SFR page from ST1
+#define SST2  0xA0        // Save SFR page to ST2
+#define RST2  0xE0        // Restore SFR page from ST2
+#define SST3  0xB0        // Save SFR page to ST3
+#define RST3  0xF0        // Restore SFR page from ST3
+#define noSST 0x00        // Switch page without saving
+
+#define SFR_PAGE(pg,op) pg+op
+
+//   SYSCON0_RMAP
+//   The access to the mapped SFR area is enabled.
+#define SET_RMAP() SYSCON0 |= 0x01
+
+//   The access to the standard SFR area is enabled.
+#define RESET_RMAP() SYSCON0 &= ~0x01
+
+
+#define _su  SCU_PAGE // SCU_PAGE
+
+#define STR_PAGE(pg,op)  { _push_(op); \
+   pg ; }
+
+#define RST_PAGE(op)  _pop_(op)
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,10)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+
+
+#include 
+
+#include "IO.H"
+#include "T2.H"
+#include "WDT.H"
+#include "PS.H"
+#include "CAN.H"
+#include "SHARED_INT.H"
+
+
+
+
+
+
+
+// USER CODE BEGIN (MAIN_Header,11)
+#include  "Config.H"
+// USER CODE END
+
+
+#endif  // ifndef _MAIN_H_
diff --git a/PS.C b/PS.C
new file mode 100644
index 0000000..b581d11
--- /dev/null
+++ b/PS.C
@@ -0,0 +1,295 @@
+//****************************************************************************
+// @Module        Power Saving Modes
+// @Filename      PS.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the PS module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21 08:53:36
+//
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (PS_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void PS_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the Power Saving 
+//                function library. It is assumed that the SFRs used by this 
+//                library are in their reset state. 
+//                
+//                This function does not contain any generated C-code, but it 
+//                is possible to insert application specific source lines. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Init,1)
+
+// USER CODE END
+
+void PS_vInit(void)
+{
+  // USER CODE BEGIN (PS_Init,2)
+
+  // USER CODE END
+
+  ///  Slow Down Clock is 48.00 MHz
+  ///  which is 1/4 of the System Clock fSYS
+
+  ///  wake up with reset is selected
+
+
+  SFR_PAGE(_su1, noSST);         // switch to page1 with out saving
+
+  ///  Pin P0.1 (input)
+  ///  - used as wake up pin via RXD_1 from powerdown 
+
+  ///  Pin P0.5 (input)
+  ///  - used as wake up pin via EXINT0 from powerdown 
+
+  PMCON0        =  0x13;         //  wakeup control register
+
+  //   ---------- Modules configuration status for PMCON1 reg.----------
+
+  ///   ADC enabled
+  ///   SSC disabled
+  ///   CCU enabled
+  ///   T2 enabled
+  ///   MDU enabled
+  ///   CAN enabled
+  ///   CDC enabled
+  PMCON1        =  0x02;         //  Power mode control register 1
+
+  SFR_PAGE(_su3, noSST);         // switch to page3 with out saving
+
+  //   ---------- Modules configuration status for PMCON2 reg.----------
+
+  ///   T21 enabled
+  ///   UART1 enabled
+  PMCON2        =  0x00;         //  Power mode control register 2
+
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+
+  IEN0         |= 0x01;          // interrupt enable  register 0
+  TCON          =  0x01;         // Set TCON.IT0 
+
+  MODPISEL      =  0x01;         // load peripheral input select reg
+
+} //  End of function PS_vInit
+
+
+//****************************************************************************
+// @Function      void PS_vSetPowerDown(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function invokes the software power down mode by 
+//                execution of following steps:
+//                - the external wake-up from software power down remains 
+//                disabled
+//                - bit PD in SFR PMCON0 will be set
+//                  (this will stop all controller functions)
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+void PS_vSetPowerDown(void)
+{
+  //   enter software power down mode
+  STR_PAGE(_su1, _su);           // push current SCU page and switch to page1
+
+  ///  External wake-up enabled
+
+  ///  Wake-up via pin RxD_1 and EXINT0 is selected
+  PMCON0|=0x03;
+
+  MAIN_vUnlockProtecReg();       // open access to protected register
+ 
+  PMCON0 |= 0x04;     //   set   PD
+ 
+  MAIN_vlockProtecReg();         // close access to protected register
+
+  RST_PAGE(_su);                 // restore the old SCU page
+
+} //  End of function PS_vSetPowerDown
+
+
+//****************************************************************************
+// @Function      void PS_vSetSlowDown(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function activates the slow down mode by setting bit 
+//                SD in SFR PMCON0.
+//                Note: DAvE's project settings for the on-chip peripheral 
+//                components are only valid for normal clock operation. 
+//                During slow down mode the behavior of the peripherals can 
+//                differ from these settings due to the reduced clock rate!
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+//void PS_vSetSlowDown(void)
+//{
+
+//  STR_PAGE(_su1, _su);           // push current SCU page and switch to page1
+
+
+//  MAIN_vUnlockProtecReg();       // open access to protected register
+
+//  PMCON0 |= 0x08;     //   set   SD
+
+//  MAIN_vlockProtecReg();         // close access to protected register
+
+//  RST_PAGE(_su);                 // restore the old SCU page
+
+//} //  End of function PS_vSetSlowDown
+
+
+//****************************************************************************
+// @Function      void PS_vResetSlowDown(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function terminates the slow down mode by clearing bit 
+//                SD in SFR PMCON0.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+//void PS_vResetSlowDown(void)
+//{
+
+//  STR_PAGE(_su1, _su);           // push current SCU page and switch to page1
+
+//  MAIN_vUnlockProtecReg();       // open access to protected register
+
+//  PMCON0 &= ~(ubyte)0x08; //   clear SD
+
+//  MAIN_vlockProtecReg();         // close access to protected register
+
+//  RST_PAGE(_su);                 // restore the old SCU page
+
+//} //  End of function PS_vResetSlowDown
+
+
+// USER CODE BEGIN (PS_General,10)
+
+// USER CODE END
+
diff --git a/PS.H b/PS.H
new file mode 100644
index 0000000..fc8ce79
--- /dev/null
+++ b/PS.H
@@ -0,0 +1,202 @@
+//****************************************************************************
+// @Module        Power Saving Modes
+// @Filename      PS.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the PS module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21 08:53:36
+//
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _PS_H_
+#define _PS_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void PS_vInit(void);
+void PS_vSetPowerDown(void);
+void PS_vSetSlowDown(void);
+void PS_vResetSlowDown(void);
+
+// USER CODE BEGIN (PS_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         void PS_vSetIdle() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro enters the idle mode by setting bit IDLE in SFR 
+//                PCON. The instruction will stop the CPU immediately. Thus 
+//                any following code will not be executed before the 
+//                controller has been restarted by an interrupt.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+#define PS_vSetIdle() PCON |= 0x01
+
+
+//****************************************************************************
+// @Macro         PS_vDisableModule(ModuleName) 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro disables a specific peripheral module which is 
+//                passed in a parameter.Switch the page to 1 using the 
+//                statementSFR_PAGE(_su1, SST1);    before calling this 
+//                Disable macro.After that again switch back the page to 0 
+//                with the macro SFR_PAGE(_su1, RST1);.The following 
+//                constants are available for 'ModuleName':
+//                ADC, T2, CCU, SSC, MDU, CAN, CDC, T21, UART1
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ModuleName: 
+//                Name of the Module
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+#define PS_vDisableModule(Module) PS_vDisableModule_(Module)
+
+#define PS_vDisableModule_(Module) PS_vDisableModule_##Module
+
+#define PS_vDisableModule_ADC                  PMCON1 |= 0x01
+#define PS_vDisableModule_T2                   PMCON1 |= 0x08
+#define PS_vDisableModule_CCU                  PMCON1 |= 0x04
+#define PS_vDisableModule_SSC                  PMCON1 |= 0x02
+#define PS_vDisableModule_MDU                  PMCON1 |= 0x10
+#define PS_vDisableModule_CAN                  PMCON1 |= 0x20
+#define PS_vDisableModule_CDC                  PMCON1 |= 0x40
+#define PS_vDisableModule_T21                  PMCON2 |= 0x01
+#define PS_vDisableModule_UART1                PMCON2 |= 0x02
+
+
+//****************************************************************************
+// @Macro         PS_vEnableModule(ModuleName) 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro enables a specific peripheral module which is 
+//                passed in a parameter. Switch the page to 1 using the 
+//                statement SFR_PAGE(_su1, SST1);    before calling this 
+//                Enable macro.After that again switch back the page to 0 
+//                with the macro SFR_PAGE(_su1, RST1);.The following 
+//                constants are available for 'ModuleName':
+//                ADC, T2, CCU, SSC, MDU, CAN, CDC, T21, UART1
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ModuleName: 
+//                Name of the Module
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+#define PS_vEnableModule(Module) PS_vEnableModule_(Module)
+
+#define PS_vEnableModule_(Module) PS_vEnableModule_##Module
+
+#define PS_vEnableModule_ADC                  PMCON1 &= ~(ubyte)0x01
+#define PS_vEnableModule_T2                   PMCON1 &= ~(ubyte)0x08
+#define PS_vEnableModule_CCU                  PMCON1 &= ~(ubyte)0x04
+#define PS_vEnableModule_SSC                  PMCON1 &= ~(ubyte)0x02
+#define PS_vEnableModule_MDU                  PMCON1 &= ~(ubyte)0x10
+#define PS_vEnableModule_CAN                  PMCON1 &= ~(ubyte)0x20
+#define PS_vEnableModule_CDC                  PMCON1 &= ~(ubyte)0x40
+#define PS_vEnableModule_T21                  PMCON2 &= ~(ubyte)0x01
+#define PS_vEnableModule_UART1                PMCON2 &= ~(ubyte)0x02
+
+
+// USER CODE BEGIN (PS_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _PS_H_
diff --git a/RTC.c b/RTC.c
new file mode 100644
index 0000000..380954c
--- /dev/null
+++ b/RTC.c
@@ -0,0 +1,415 @@
+#include "MAIN.H"
+#include 
+#include "RTC.H"
+
+unsigned char bySta = 0;
+
+// ̬·ƽ꣬1~12Ӧ1~12£
+ubyte days_in_month[12] = {
+    31, // 1
+    28, // 2£ƽ꣩
+    31, // 3
+    30, // 4
+    31, // 5
+    30, // 6
+    31, // 7
+    31, // 8
+    30, // 9
+    31, // 10
+    30, // 11
+    31  // 12
+};
+
+
+void SDAOut(bit c)
+{
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P0_DIR        =  P0_DIR | 0x08;//޸P0.3Ϊ
+	P0_3 = c;
+
+}
+
+void SCLOut(bit c)
+{
+	P0_2 = c;
+}
+
+void iic_start(void)
+{
+  SDAOut(1);
+  _nop_();
+  SCLOut(1);
+  somenop;
+  SDAOut(0);
+  somenop;
+  SCLOut(0);
+}
+
+void iic_stop(void)
+{
+  SDAOut(0);
+  _nop_();
+  SCLOut(1);
+  somenop;
+  SDAOut(1);
+}
+
+void iic_ack(bit ackbit)
+{
+  if(ackbit) 
+	SDAOut(0);
+  else 
+	SDAOut(1); 
+  somenop;
+  SCLOut(1);
+  somenop;
+  SCLOut(0);
+  SDAOut(1); 
+  somenop;
+}
+
+bit iic_waitack(void)
+{
+  SDAOut(1);
+  somenop;
+  SCLOut(1);
+	
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P0_DIR        =  P0_DIR & 0xF7;//޸P4.3Ϊ
+	
+  somenop;
+  if(P0_3)    
+  {   
+		SCLOut(0);
+		iic_stop();
+		return 0;
+  }
+  else  
+  { 
+		SCLOut(0);
+		return 1;
+  }
+}
+
+void iic_sendbyte(unsigned char byt)
+{
+  unsigned char i;
+  for(i=0;i<8;i++)
+  {   
+	  if(byt&0x80) 
+	    SDAOut(1);
+		else 
+		  SDAOut(0);
+		somenop;
+		SCLOut(1);
+		byt <<= 1;
+		somenop;
+	  SCLOut(0);
+  }
+}
+
+
+unsigned char iic_recbyte(void)
+{
+  unsigned char da;
+  unsigned char i;
+	
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P0_DIR        =  P0_DIR & 0xF7;//޸P4.3Ϊ
+	
+  for(i=0;i<8;i++)
+  {   
+     SCLOut(1);
+     somenop;
+     da <<= 1;
+
+//	P1_IOCR01      =  0x0020;      // load port control register 1
+	  if(P0_3)
+		  da |= 0x01;
+		SCLOut(0);
+		somenop;
+  }
+  return da;
+}
+
+// ʮת BCD 
+unsigned char DecToBcd(unsigned char dec) 
+{
+    return ((dec / 10) << 4) | (dec % 10);
+}
+
+// BCD תʮ
+unsigned char BcdToDec(unsigned char bcd) 
+{
+    return ((bcd >> 4) * 10) + (bcd & 0x0F);
+}
+
+
+
+// BM8563 дĴ
+void BM8563_WriteReg(unsigned char reg, unsigned char rdata)
+{
+	iic_start();
+	iic_sendbyte(BM8563_ADDR);  //  BM8563  I2C ַд
+	iic_waitack();
+	iic_sendbyte(reg);  // ͼĴַ
+	iic_waitack();	
+	iic_sendbyte(rdata);  // 
+	iic_waitack();
+	iic_stop();
+}
+
+
+// BM8563 Ĵ
+unsigned char BM8563_ReadReg(unsigned char reg)
+{
+	unsigned char rdata;
+	iic_start();
+	iic_sendbyte(BM8563_ADDR);  //  BM8563  I2C ַд
+	iic_waitack();	
+	iic_sendbyte(reg);  // ͼĴַ
+	iic_waitack();	
+	iic_start();
+	iic_sendbyte(BM8563_ADDR | 0x01);  //  BM8563  I2C ַ
+	iic_waitack();
+	rdata = iic_recbyte();
+  iic_ack(0); 
+	iic_stop();
+	return rdata;
+}
+
+// ж
+ubyte leapYear(uword year) {
+    return (year % 4 == 0 && year % 100 != 0) || year % 400 == 0;
+}
+
+
+/**
+  * @brief  ȡָݺ·ݵԶ꣩
+  * @param  year: ݣλ2024
+  * @param  month: ·ݣ1-12
+  * @retval Ƿ0
+  */
+ubyte getMonthDays(uword year, ubyte month) {
+    // ̬·ƽ꣬1~12Ӧ1~12£
+     ubyte days_in_month[13] = {
+        0, 31, 28, 31, 30, 31, 30, 
+        31, 31, 30, 31, 30, 31
+    };
+
+    // У
+    if (month < 1 || month > 12) return 0;
+
+    // 2
+    if (month == 2 && leapYear(year)) {
+        return 29;
+    }
+
+    // س
+    return days_in_month[month];
+}
+
+
+/**
+  * @brief  鱨־AFǷλBit3
+  * @retval true-Ѵfalse-ޱ
+  */
+bool bm8563CheckAlarmFlag(void) {
+    ubyte reg_val = BM8563_ReadReg(BM8563_CSR2);
+    return (reg_val & BM8563_AF_BIT) != 0;  // Bit3
+}
+
+/**
+  * @brief  ־AFBit3
+  * @note   λBit1 AIE־״̬
+  */
+void bm8563ClearAlarmFlag(void) {
+    ubyte reg_val = BM8563_ReadReg(BM8563_CSR2);
+    reg_val &= ~BM8563_AF_BIT;  // Bit3
+    BM8563_WriteReg(BM8563_CSR2, reg_val);
+}
+
+
+
+/**
+  * @brief  BM8563ǰʱ䣨λ·ݼĴ
+  * @param  pTime: ʱṹָ루Ϊλ19842024
+  * @retval 
+  */
+void bm8563SetTime(UnTimeOutput *pTime) {
+	
+    ubyte century_bit = 0;  // λ
+  	ubyte reg_sec = 0;
+  	ubyte month_bcd = 0;	
+    if (pTime == NULL) return;
+
+    // --- λ ---
+    // ͱ־0:20ͼ֮1:19ͣ
+//    uint8_t century_bit = (pTime->bit_data.year >= 2000) ? 0 : 1;  // λ
+
+    // --- Ĵд루룩---
+    // 루ַ0x02Bit7CHʱֹͣλ
+    reg_sec = BM8563_ReadReg(BM8563_SEC) & 0x80;  
+    BM8563_WriteReg(BM8563_SEC, reg_sec | (DecToBcd(pTime->bit_data.second) & 0x7F));
+    
+    // ַ֣0x03
+    BM8563_WriteReg(BM8563_MIN, DecToBcd(pTime->bit_data.minute) & 0x7F);  
+    
+    // Сʱַ0x0424Сʱ
+    BM8563_WriteReg(BM8563_HOUR, DecToBcd(pTime->bit_data.hour) & 0x3F);   
+    
+    // գַ0x05ʹλ
+    BM8563_WriteReg(BM8563_DAY, DecToBcd(pTime->bit_data.day) & 0x3F);     
+    
+    // ܣַ0x06ֵΧ1-7
+    BM8563_WriteReg(BM8563_WEEK, pTime->bit_data.week & 0x07);             
+    
+    // £ַ0x07λдBit7·ռ5λ
+    month_bcd = DecToBcd(pTime->bit_data.month);
+    BM8563_WriteReg(BM8563_MONTH, (century_bit << 7) | (month_bcd & 0x1F)); 
+    
+    // ַ꣨0x08洢λ20240x24
+    BM8563_WriteReg(BM8563_YEAR, DecToBcd(pTime->bit_data.year));    
+}
+
+
+/**
+  * @brief  ȡBM8563ǰʱ䵽
+  * @param  pTime: UnTimeOutputָ루ڴ洢ȡʱݣ
+  * @retval 
+  */
+void bm8563GetTime(UnTimeOutput *pTime) {
+    if (pTime == NULL) {
+        return;  // չ
+    }
+
+    // ȡ루ַ0x02
+    pTime->bit_data.second = BcdToDec(BM8563_ReadReg(BM8563_SEC) & 0x7F);  // Чλ
+    
+    // ȡӣַ0x03
+    pTime->bit_data.minute = BcdToDec(BM8563_ReadReg(BM8563_MIN) & 0x7F);
+    
+    // ȡСʱַ0x04
+    pTime->bit_data.hour = BcdToDec(BM8563_ReadReg(BM8563_HOUR) & 0x3F);   // 24СʱBit6-7
+    
+    // ȡգַ0x05
+    pTime->bit_data.day = BcdToDec(BM8563_ReadReg(BM8563_DAY) & 0x3F);     // ολ
+    
+    // ȡܣַ0x06BM8563ֵΪ0x01-0x07BCDת
+    pTime->bit_data.week = BM8563_ReadReg(BM8563_WEEK) & 0x07;             // 3λ
+    
+    // ȡ£ַ0x07
+    pTime->bit_data.month = BcdToDec(BM8563_ReadReg(BM8563_MONTH) & 0x1F);  // Bit5-7
+    
+    // ȡַ꣨0x08Ϊ2000+꣩
+    pTime->bit_data.year = BcdToDec(BM8563_ReadReg(BM8563_YEAR));
+}
+
+
+
+
+/**
+  * @brief  BM8563ӣֶΪ0ʱöӦ
+  * @param  pTime: UnTimeOutputָ룬ʱ
+  * @retval 
+  */
+ubyte bm8563SetAlarm(UnTimeOutput *pTime) {
+	
+  	UnTimeOutput un_temp_output = {0};//趨ʱ	
+	  ubyte carry_hour = 0;
+	  ubyte carry_day = 0;
+    ubyte month_days = 0;		
+//-------------------------------------------------		
+    // ָЧ
+    if( (pTime == NULL) || ( (0 == pTime->bit_data.minute) && (0 == pTime->bit_data.hour) && (0 == pTime->bit_data.day) ) )//ݶΪ0ָ붼Ϊ0
+		{
+        // ѡӴ־
+        return 1;
+    }
+	
+		bm8563GetTime(¤ttime);
+	
+		// 0-59
+		un_temp_output.bit_data.minute = currenttime.bit_data.minute + pTime->bit_data.minute;
+		if (un_temp_output.bit_data.minute >= 60) {
+				un_temp_output.bit_data.minute -= 60;
+				carry_hour = 1; // Сʱλ
+		}
+
+		// Сʱ0-23
+		un_temp_output.bit_data.hour = currenttime.bit_data.hour + pTime->bit_data.hour + carry_hour;
+		if (un_temp_output.bit_data.hour >= 24) {
+				un_temp_output.bit_data.hour -= 24;
+				carry_day = 1; // λ
+		}
+
+		// 迼·
+		un_temp_output.bit_data.day = currenttime.bit_data.day + pTime->bit_data.day + carry_day;
+		//2¿ƽ
+		month_days = getMonthDays( (currenttime.bit_data.year+2000),currenttime.bit_data.month);
+
+		// 迼·
+		if (un_temp_output.bit_data.day > month_days) 
+		{
+				un_temp_output.bit_data.day -= month_days;
+				//ƣ1£һ죬BM8563ֻ֧ô
+				if(un_temp_output.bit_data.day == currenttime.bit_data.day)
+				{
+					 un_temp_output.bit_data.day = (currenttime.bit_data.day - 1);
+				}							
+		}
+						
+		un_temp_output.bit_data.week = 0;//Ҫܱ		
+
+// ãַ0x09
+		BM8563_WriteReg(BM8563_ALARM_MIN, DecToBcd(un_temp_output.bit_data.minute) & 0x7F); // AE_M=0ã
+// Сʱãַ0x0A
+		BM8563_WriteReg(BM8563_ALARM_HOUR, DecToBcd(un_temp_output.bit_data.hour) & 0x7F);  // AE_H=0ã
+// ձ/ܱ
+		BM8563_WriteReg(BM8563_ALARM_DAY, DecToBcd(un_temp_output.bit_data.day) & 0x7F);    // AE_D=0գ
+		BM8563_WriteReg(BM8563_ALARM_WEEK, 0x80);                                   // AE_W=1ܣ
+// ʹжϣַ0x01AIE=1AF=0
+    BM8563_WriteReg(BM8563_CSR2, 0x02);
+		
+    return 0;		
+}
+
+
+
+
+
+
+
+
+
+
+
+
+////  BM8563 ӣʵּ 4 СʱĻ
+//void BM8563_Set4HourAlarm() 
+//{
+//    unsigned char alarmMin =  BcdToDec( BM8563_ReadReg(BM8563_MIN) );
+//    unsigned char alarmMinBcd = 0;	
+////------------------------------------------------------------	
+//    alarmMin = (alarmMin + 2) % 60;// 4 СʱСʱ
+//    alarmMinBcd  = DecToBcd(alarmMin);
+
+//    BM8563_WriteReg(BM8563_ALARM_MIN,alarmMinBcd&0x7F);// ӷ
+//    BM8563_WriteReg(BM8563_ALARM_HOUR, 0x80);       // Ч
+//    BM8563_WriteReg(BM8563_ALARM_DAY , 0x80);       // Ч
+//    BM8563_WriteReg(BM8563_ALARM_WEEK, 0x80);       // Ч
+//    
+//    // ӿƼĴʹж
+//    BM8563_WriteReg(BM8563_CSR2, 0x02); 
+//}
+
+
+
+
+
+
+
+
+
+
+
diff --git a/RTC.h b/RTC.h
new file mode 100644
index 0000000..a3d5eba
--- /dev/null
+++ b/RTC.h
@@ -0,0 +1,101 @@
+#ifndef _RTC_H_
+#define _RTC_H_
+
+//#define _nop_()   udelay(1);
+#define somenop   {_nop_();_nop_();_nop_();_nop_();_nop_();}
+
+
+typedef enum {
+    STATE_INIT = 0,  // ʼ״̬״У
+    STATE_ON,        // ON״̬ѹģʽ
+    STATE_OFF,       // OFF״̬׼ߣ
+    STATE_OFF2,       // OFF2״̬߼أ
+    STATE_ON2       // ON2״̬ģʽ		
+} SystemState;
+
+
+
+
+typedef struct {
+    ubyte   year;    // ꣨洢λ202525
+    ubyte   month;   // £1-12
+    ubyte   day;     // գ1-31
+    ubyte   hour;    // Сʱ0-23
+    ubyte   week;    //   0-6	
+    ubyte   minute;  // ӣ0-59
+    ubyte   second;  //   0-59	
+	  ubyte   resver;
+} DateTimeInfo;      // ʹôշ巨˹
+
+typedef union _UnTimeOutput
+{
+    DateTimeInfo bit_data;             // ʹöĽṹ
+    ubyte arr[sizeof(DateTimeInfo)]; // ͨṹȷС
+} UnTimeOutput;
+
+
+
+extern unsigned char bySta;
+extern UnTimeOutput  currenttime;
+extern UnTimeOutput  un_time_output1;//趨ʱ
+
+
+
+//  BM8563  I2C ַ
+#define BM8563_ADDR 0xA2  
+
+//  BM8563 Ĵַ
+#define BM8563_CSR2 0x01
+#define BM8563_SEC 0x02
+#define BM8563_MIN 0x03
+#define BM8563_HOUR 0x04
+#define BM8563_DAY 0x05
+#define BM8563_WEEK 0x06
+#define BM8563_MONTH 0x07
+#define BM8563_YEAR 0x08
+#define BM8563_ALARM_MIN 0x09
+#define BM8563_ALARM_HOUR 0x0A
+#define BM8563_ALARM_DAY 0x0B
+#define BM8563_ALARM_WEEK 0x0C
+#define BM8563_CONTROL 0x0E  // ʱƼĴ
+#define BM8563_STATUS 0x01
+#define BM8563_TIMER_VALUE 0x0F  // ʱĴ
+
+#define BM8563_AF_BIT    0x08  // AF־λBit3
+
+
+ubyte leapYear(uword year);
+void BM8563_InitTime();
+void BM8563_Set4HourCountdown();
+unsigned char BM8563_ReadReg(unsigned char reg);
+void BM8563_WriteReg(unsigned char reg, unsigned char rdata);
+void BM8563_Set4HourAlarm(); 
+void bm8563GetTime(UnTimeOutput *pTime);
+ubyte bm8563SetAlarm(UnTimeOutput *pTime);
+void bm8563SetTime(UnTimeOutput *pTime);
+bool bm8563CheckAlarmFlag(void);
+void bm8563ClearAlarmFlag(void);
+
+void iic_start(void);
+void iic_stop(void);
+void iic_ack(bit ackbit);
+void iic_sendbyte(unsigned char byt);
+void wrbyte_24c02(unsigned int add,unsigned char dat);
+
+bit iic_waitack(void);
+unsigned char i2c_recbyte(void);
+unsigned char rdbyte_24c02(unsigned int add);
+unsigned char wrEE_CRC_Bak(unsigned char add,unsigned char *eeData,unsigned char len,unsigned char addbak);
+unsigned char rdEE_CRC_Bak(unsigned char add,unsigned char *eeData,unsigned char len,unsigned char addbak);
+
+
+
+
+
+
+
+
+
+
+
+#endif
\ No newline at end of file
diff --git a/SHARED_INT.C b/SHARED_INT.C
new file mode 100644
index 0000000..bd52036
--- /dev/null
+++ b/SHARED_INT.C
@@ -0,0 +1,223 @@
+//****************************************************************************
+// @Module        Shared Interrupt Routines
+// @Filename      SHARED_INT.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description   This file contains the Shared interrupt routines.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:29
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "SHARED_INT.H"
+
+// USER CODE BEGIN (SHARED_INT_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+
+// USER CODE BEGIN (SHARED_INT_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void SHINT_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function initializes the shared interrupts. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SHINT_Init,1)
+
+// USER CODE END
+
+void SHINT_vInit(void)
+{
+  // USER CODE BEGIN (SHINT_Init,2)
+
+  // USER CODE END
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the Shared  Interrupts:
+  ///  -----------------------------------------------------------------------
+  ///  - Timer 2 Interrupt is Selected
+
+
+  IEN0         |=  0x20;         // load interrupt enable register 0
+
+
+
+  IEN1         |=  0x00;         // load interrupt enable register 1
+
+
+  // USER CODE BEGIN (SHINT_Init,3)
+
+  // USER CODE END
+
+
+} //  End of function SHINT_vInit
+
+
+//****************************************************************************
+// @Function      void SHINT_viXINTR5Isr(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the service routine for the shared interrupt node 
+//                XINTR5. XINTR5 ISR Node is shared by Timer 2, UART 
+//                Fractional Divider(BRG Interrupt),MultiCAN Node 0 and LIN. 
+//                Depending on the selected module interrupt it is called.
+//                T2 - Depending on the selected operating mode it is called 
+//                when TF2 is set by an overflow or underflow of the timer 2 
+//                register or when EXF2 is set by a negative transition on 
+//                T2EX.
+//                UART - It is called after the BRG timer overflows and sets 
+//                the NDOV bit.
+//                CAN -  It is called for the  Service Request Node 0 of the 
+//                MultiCAN module.
+//                Please note that you have to add application specific code 
+//                to this function.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   none
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+//   You have two choices for interrupt type select in Project Settings Page 
+//   under Global Settings Section.
+//   If you select CHOICE 1 then ISR will be generated with push and pop.
+//   If you select CHOICE 2 then ISR will be generated without push and pop.
+//   Default choice is CHOICE 2.
+//   Current selection is CHOICE 2 
+
+// USER CODE BEGIN (SHINT_XINTR5Isr,1)
+
+// USER CODE END
+
+void SHINT_viXINTR5Isr(void) interrupt XINTR5INT
+{
+  // USER CODE BEGIN (SHINT_XINTR5Isr,2)
+
+  // USER CODE END
+
+  SFR_PAGE(_su0, SST0);          // switch to page 0
+
+  //   Timer 2 interrupt handling section...
+
+  if (TF2)
+  {
+    //   a timer 2 overflow has occured
+
+    TF2 = 0;
+
+    // USER CODE BEGIN (SHINT_XINTR5Isr,3)
+RTCProcess();
+    // USER CODE END
+
+  }
+
+  // USER CODE BEGIN (SHINT_XINTR5Isr,7)
+
+  // USER CODE END
+
+  SFR_PAGE(_su0, RST0);          // restore the old SCU page
+} //  End of function SHINT_viXINTR5Isr
+
+
+// USER CODE BEGIN (SHARED_INT_General,10)
+
+// USER CODE END
+
+
diff --git a/SHARED_INT.H b/SHARED_INT.H
new file mode 100644
index 0000000..5daa27a
--- /dev/null
+++ b/SHARED_INT.H
@@ -0,0 +1,121 @@
+//****************************************************************************
+// @Module        Shared Interrupt Routines
+// @Filename      SHARED_INT.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description   This is the include header file for shared interrupts.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:29
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _SHARED_INT_H_
+#define _SHARED_INT_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,4)
+
+// USER CODE END
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void SHINT_vInit(void);
+
+
+// USER CODE BEGIN (SHARED_INT_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+#define  XINTR5INT   5
+
+// USER CODE BEGIN (SHARED_INT_Header,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+
+
+
+
+
+#include "MAIN.H"
+
+
+// USER CODE BEGIN (SHARED_INT_Header,10)
+
+// USER CODE END
+
+
+#endif  // ifndef _SHARED_INT_H_
diff --git a/SSC.C b/SSC.C
new file mode 100644
index 0000000..d73aaef
--- /dev/null
+++ b/SSC.C
@@ -0,0 +1,264 @@
+//****************************************************************************
+// @Module        High Speed Synchronous Serial Interface(SSC)
+// @Filename      SSC.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.9
+//
+// @Description:  This file contains functions that use the SSC module.
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11 12:29:47
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (SSC_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void SSC_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the SSC function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11
+//
+//****************************************************************************
+
+// USER CODE BEGIN (Init,1)
+
+// USER CODE END
+
+void SSC_vInit(void)
+{
+  // USER CODE BEGIN (Init,2)
+
+  // USER CODE END
+
+  ///  - Port Selection
+  SSC_PISEL     =  0x01;         // load SSC Port Input Select Register to 
+                                 // Port A
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the used SSC Port Pins:
+  ///  -----------------------------------------------------------------------
+  ///  Pin SCLK (P0.3) is selected for SCLK ouput 
+  ///  Pin MTSR_1 (P0.4) is selected for Master Transmit Output 
+  ///  Pin MRST_1 (P0.5) is selected for Master Receive Input 
+
+  SFR_PAGE(_pp2, noSST);         // switch to page 2 without saving
+  P0_ALTSEL0      |= 0x18;              //  set AltSel0 
+  P0_ALTSEL1      &= ~(ubyte)0x18;      //  set AltSel1
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0 without saving
+  P0_DIR          |= 0x18;      //  set OutPut Direction
+
+
+  ///  Pin SCLK (P1.2) is Not selected for SCLK ouput 
+  ///  Pin MTSR_0 (P1.3) is Not selected for Master Transmit Output 
+  ///  Pin MRST_0 (P1.4) Not is selected for Master Receive Input 
+
+  SSC_CONH_P &= ~(ubyte)0x80;           //  enable access to control bits
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the SSC Baud Rate Generator:
+  ///  -----------------------------------------------------------------------
+  ///  - required baud rate = 2000.000 kbaud
+  ///  - real baud rate     = 2000.000 kbaud
+  ///  - deviation          = 0.000 %
+
+  SSC_BRH       =  0x00;         // load SSC baud rate time reload register 
+                                 // high
+  SSC_BRL       =  0x05;         // load SSC baud rate time reload register 
+                                 // low
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the SSC Operation Mode:
+  ///  -----------------------------------------------------------------------
+  ///  - this device is configured as SSC master
+  ///  - transfer data width is 8 bit
+  ///  - transfer/receive MSB first
+  ///  - shift transmit data on the leading clock edge, latch on trailing edge
+  ///  - idle clock line is low, leading clock edge is low-to-high transition
+  ///  - ignore receive error
+  ///  - ignore phase error
+
+
+  SSC_CONH_P    =  0x40;         // load SSC control register
+
+  SSC_CONL_P    =  0x17;         // load SSC control register
+
+  SSC_CONH_P |= 0x80;           //  disable access to control bits
+
+  ///  - SSC interrupt is disabled
+
+  // USER CODE BEGIN (Init,3)
+
+  // USER CODE END
+
+} //  End of function SSC_vInit
+
+
+//****************************************************************************
+// @Function      void SSC_vSendData(ubyte Data) 
+//
+//----------------------------------------------------------------------------
+// @Description   The master device can initiate the first data transfer by 
+//                writing the transmit data into transmit buffer. This value 
+//                is copied into the shift register (which is assumed to be 
+//                empty at this time), and the selected first bit of the 
+//                transmit data is placed onto the MTSR line on the next 
+//                clock from the baud rate generator. 
+//                A slave device immediately outputs the selected first bit 
+//                (MSB or LSB of the transfer data) at pin MRST, when the 
+//                contents of the transmit buffer are copied into the slave's 
+//                shift register. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    Data: 
+//                Data to be send
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SendData,1)
+
+// USER CODE END
+
+void SSC_vSendData(ubyte Data)
+{
+  SSC_TBL  = Data;   //  load transmit buffer register
+
+} //  End of function SSC_vSendData
+
+
+//****************************************************************************
+// @Function      ubyte SSC_vGetData(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function returns the contents of the receive buffer. 
+//                When the receive interrupt request flag is set this implies 
+//                that data is available for reading in the receive buffer. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   Received data
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11
+//
+//****************************************************************************
+
+// USER CODE BEGIN (GetData,1)
+
+// USER CODE END
+
+ubyte SSC_vGetData(void)
+{
+  return(SSC_RBL);     // return receive buffer register
+
+} //  End of function SSC_vGetData
+
+
+
+// USER CODE BEGIN (SSC_General,10)
+
+// USER CODE END
+
diff --git a/SSC.H b/SSC.H
new file mode 100644
index 0000000..6d112f6
--- /dev/null
+++ b/SSC.H
@@ -0,0 +1,107 @@
+//****************************************************************************
+// @Module        High Speed Synchronous Serial Interface(SSC)
+// @Filename      SSC.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.9
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the SSC module.
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11 12:29:47
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _SSC_H_
+#define _SSC_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void SSC_vInit(void);
+void SSC_vSendData(ubyte Data);
+ubyte SSC_vGetData(void);
+
+
+// USER CODE BEGIN (SSC_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+
+// USER CODE BEGIN (SSC_Header,9)
+
+// USER CODE END
+
+
+#endif  // ifndef _SSC_H_
diff --git a/START_XC.a51 b/START_XC.a51
new file mode 100644
index 0000000..d34a0dd
--- /dev/null
+++ b/START_XC.a51
@@ -0,0 +1,521 @@
+$NOMOD51
+;------------------------------------------------------------------------------
+;  This file is part of the C51 Compiler package
+;  Startup Code for the Infineon XC8xx devices 
+;  Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc.
+;  Version 20100601
+;  -------- Revision ---------
+;  - Previous version 20100405
+;  - Added XC864 with option for LIN_BSL parameters
+;  - Renamed NDIV_XC866 to NDIV_XC86x
+;
+;  *** <<< Use Configuration Wizard in Context Menu >>> ***
+;------------------------------------------------------------------------------
+;  STARTUP.A51:  This code is executed after processor reset.
+;
+;  To translate this file use A51 with the following invocation:
+;
+;     A51 STARTUP.A51
+;
+;  To link the modified STARTUP.OBJ file to your application use the following
+;  Lx51 invocation:
+;
+;     Lx51 your object file list, STARTUP.OBJ  controls
+;
+;------------------------------------------------------------------------------
+;
+; Use off-chip XTAL
+; XC8xx series runs by default from on-chip osciallator.
+; optionally you may use a off-chip XTAL
+;
+XTAL          EQU     1   ; set to 0 On-chip oscillator/ not used for XC82x devices
+;
+; Device = " XC82x "
+XC82x_CHIP    EQU   0     ;applicable to XC83x
+;---------------------------------------------------------------------
+;resulting in fsys = 80MHz for XC866/XC864 and fsys = 96MHz for XC88x unless otherwise mentioned
+;
+; Device = " XC866 "
+XC866_CHIP    EQU   0
+; Device = " XC864 "
+XC864_CHIP    EQU   0
+;
+;  PLL N-Divider
+;  PLL N-Divider must result in fsys = 80MHz
+; <0=>  N=14
+; <1=>  N=15
+; <2=>  N=16 (10 MHz XTAL)
+; <3=>  N=17
+; <4=>  N=18
+; <5=>  N=19
+; <6=>  N=20 (8 MHz XTAL)
+; <7=>  N=21
+; <8=>  N=24
+; <9=>  N=28
+; <10=> N=30
+; <11=> N=32 (5 MHz XTAL)
+; <12=> N=40
+; <13=> N=42
+; <14=> N=45
+; <15=> N=50
+;
+NDIV_XC86x    EQU      2   ; default 2
+;    
+
+;---------------------------------------------------------------------
+; Device = " XC88x "
+XC88x_CHIP    EQU   1
+;
+;  PLL N-Divider for *NON-SAL* device fsys = 96 MHz
+; <0=>  N=10
+; <1=>  N=12 
+; <2=>  N=13
+; <3=>  N=14
+; <4=>  N=15
+; <5=>  N=16 (12 MHz XTAL)
+; <6=>  N=17
+; <7=>  N=18
+; <8=>  N=19
+; <9=>  N=20 (9.6 MHz On-Chip XTAL)
+; <10=> N=24 (8 MHz XTAL)
+; <11=> N=30
+; <12=> N=32 (6 MHz XTAL)
+; <13=> N=36
+; <14=> N=40
+; <15=> N=48 (4 MHz XTAL)
+;
+;  PLL N-Divider for *SAL* device -> fsys = 80 MHz
+; <0=>  N=10 
+; <1=>  N=12
+; <2=>  N=13
+; <3=>  N=14
+; <4=>  N=15
+; <5=>  N=16 (10 MHz On-Chip XTAL)
+; <6=>  N=17
+; <7=>  N=18
+; <8=>  N=19
+; <9=>  N=20 (8 MHz XTAL)
+; <10=> N=24 
+; <11=> N=30
+; <12=> N=32 (5 MHz XTAL)
+; <13=> N=36
+; <14=> N=40 (4 MHz XTAL)
+; <15=> N=48
+;
+
+NDIV_XC88x    EQU       10   ; default 10
+;
+
+;---------------------------------------------------------------------
+; Device = " XC87x "
+XC878_CHIP_16FF    EQU       0
+XC878_CHIP_13FF    EQU       0
+XC874_CHIP_16FF    EQU       0
+XC874_CHIP_13FF    EQU       0
+
+;4 MHz 
+NDIV_XC87x_PLL_CON    EQU       0x18
+NDIV_XC87x_PLL_CON1   EQU       0x20
+NR_XC87x              EQU       0x00
+OD_XC87x              EQU       0x00
+
+;6 MHz 
+;NDIV_XC87x_PLL_CON    EQU       0x18
+;NDIV_XC87x_PLL_CON1   EQU       0x20
+;NR_XC87x              EQU       0x01
+;OD_XC87x              EQU       0x00
+
+;8 MHz default
+;NDIV_XC87x_PLL_CON    EQU       0x18
+;NDIV_XC87x_PLL_CON1   EQU       0x20
+;NR_XC87x              EQU       0x02
+;OD_XC87x              EQU       0x00
+
+;
+
+;
+;------------------------------------------------------------------------------
+;
+;  User-defined  Power-On Initialization of Memory
+;
+;  With the following EQU statements the initialization of memory
+;  at processor reset can be defined:
+;
+; IDATA memory length <0x0-0x100>
+; Note: The absolute start-address of IDATA memory is always 0
+;       The IDATA space overlaps physically the DATA and BIT areas.
+IDATALEN        EQU     0x100
+;
+;  XDATA memory start address <0x0-0xFFFF> 
+;  absolute start-address of XDATA memory
+XDATASTART      EQU     0xF000     
+;
+;  XDATA memory length <0x0-0xFFFF> 
+;  length of XDATA memory in bytes.
+IF (XC82x_CHIP)
+  XDATALEN      EQU     0x100 
+ELSEIF (XC866_CHIP || XC864_CHIP)
+  XDATALEN      EQU     0x200
+ELSEIF (XC88x_CHIP)
+  XDATALEN      EQU     0x600
+ELSEIF (XC878_CHIP_16FF || XC878_CHIP_13FF)
+  XDATALEN      EQU     0xC00
+ELSEIF (XC874_CHIP_16FF || XC874_CHIP_13FF) 
+  XDATALEN      EQU     0xC00
+
+ENDIF
+  
+;
+;  PDATA memory start address <0x0-0xFFFF> 
+;  absolute start-address of PDATA memory
+PDATASTART      EQU     0xF000
+;
+;  PDATA memory length <0x0-0xFF> 
+;  length of PDATA memory in bytes.
+PDATALEN        EQU     0
+;
+; 
+;------------------------------------------------------------------------------
+;
+;  Reentrant Stack Initilization
+;
+;  The following EQU statements define the stack pointer for reentrant
+;  functions and initialized it:
+;
+; Stack Space for reentrant functions in the SMALL model.
+;  Activate reentrant Stack (SMALL model)
+IBPSTACK        EQU     0       ; set to 1 if small reentrant is used.
+;  top of stack <0x0-0xFF> 
+;  set top of stack to highest location+1 
+IBPSTACKTOP     EQU     0xFF +1     ; default 0FFH+1  
+; 
+;
+;  Stack Space for reentrant functions in the LARGE model.      
+;  Activate reentrant Stack (LARGE model)
+XBPSTACK        EQU     0       ; set to 1 if large reentrant is used.
+;  top of stack <0x0-0xFFFF> 
+;  set top of stack to highest location+1.
+XBPSTACKTOP     EQU     0xFFFF +1   ; default 0FFFFH+1 
+; 
+;
+;  Stack Space for reentrant functions in the COMPACT model.    
+;  Activate reentrant Stack (COMPACT model)
+PBPSTACK        EQU     0       ; set to 1 if compact reentrant is used.
+;
+;  top of stack <0x0-0xFF> 
+;  set top of stack to highest location+1.
+PBPSTACKTOP     EQU     0xFF +1     ; default 0FFH+1  
+; 
+; 
+;------------------------------------------------------------------------------
+;
+;  Set Memory Page for Using the Compact Model with 64 KByte xdata RAM
+;
+;  Define the xdata page used for pdata variables. 
+;  PPAGE must conform with the PPAGE set in the linker invocation.
+;
+; Enable pdata memory page initalization
+PPAGEENABLE     EQU     0       ; set to 1 if pdata object are used.
+;
+;  PPAGE number <0x0-0xFF> 
+;  uppermost 256-byte address of the page used for pdata variables.
+PPAGE           EQU     0xF0
+;
+; 
+;------------------------------------------------------------------------------
+;
+;  Parameters for LIN Boostrap Loader (XC864 only)
+;  When these values are not defined, an XC864 device stays in 
+;  LIN-BSL mode and does not start the user application 
+;
+; Enable LIN BSL parameter initialization
+LIN_BSL         EQU     1           ; set to 1 if LIN BSL parameters should be generated in flash table
+;
+;  NAC: No. Activity Count <0x00-0xFF> 
+;  specifies the delay (n * 5ms) before jumping to user mode.
+;  0x01:  0 ms delay. Jump to User Mode immediately
+;  0x02:  5 ms delay before jumping to User Mode
+;  0x03: 10 ms delay before jumping to User Mode
+;  0x04 - 0x0C: 15 - 55 ms delay before jumping to User Mode
+;  0x0D - 0xFF, 0x00: Enter LIN BSL Mode (Invalid NAC)
+LIN_NAC         EQU     0x01
+;
+;  NAD: Node Address for Diagnostic <0x00-0xFF> 
+;  specifies the address of the active slave node.
+LIN_NAD         EQU     0x01
+;
+; 
+;------------------------------------------------------------------------------
+
+;Check the chip selection
+IF ((XC82x_CHIP + XC866_CHIP + XC864_CHIP + XC88x_CHIP + XC878_CHIP_16FF + XC878_CHIP_13FF + XC874_CHIP_16FF + XC874_CHIP_13FF) > 1)
+      __ERROR__  "Please select only one chip!"
+ELSEIF ((XC82x_CHIP + XC866_CHIP + XC864_CHIP + XC88x_CHIP + XC878_CHIP_16FF + XC878_CHIP_13FF + XC874_CHIP_16FF + XC874_CHIP_13FF) == 0)
+      __ERROR__  "Please select a chip!"
+ENDIF
+
+IF (XTAL <> 0)
+    IF (XC866_CHIP <> 0 || XC864_CHIP <> 0)
+       NDIV EQU NDIV_XC86x
+    ELSEIF (XC88x_CHIP <> 0)
+       NDIV EQU NDIV_XC88x
+    ELSEIF (XC878_CHIP_16FF <> 0 || XC878_CHIP_13FF <> 0)
+       ;nothing   
+    ELSEIF (XC874_CHIP_16FF <> 0 || XC874_CHIP_13FF <> 0)
+       ;nothing
+    ELSEIF (XC82x_CHIP <> 0)
+       ;nothing
+    ELSE
+      __WARNING__  "Default NDIV selection is XC866"
+      NDIV EQU NDIV_XC86x  ;Default
+    ENDIF
+ ENDIF                   ;End of XTAL selection
+
+; Standard SFR Symbols 
+ACC     DATA    0E0H
+B       DATA    0F0H
+SP      DATA    81H
+DPL     DATA    82H
+DPH     DATA    83H
+
+; XC8xx specific SFR Symbols used in STARTUP code
+IF (XC82x_CHIP == 0)
+; Take note of different SFR addresses for XC82x. Currently not used.
+        sfr  SCU_PAGE = 0xBF
+        sfr  PLL_CON  = 0xB7
+        sfr  PLL_CON1 = 0xEA;//SCU,RMAP=0,Page=1
+        sfr  CMCON    = 0xBA
+        sfr  OSC_CON  = 0xB6
+        sfr  PASSWD   = 0xBB
+        sfr  XADDRH   = 0xB3
+        sfr  MEX3     = 0x96
+ENDIF
+
+IF(XC874_CHIP_13FF == 1 || XC874_CHIP_16FF == 1)
+        sfr  PORT_PAGE = 0xB2
+        sfr  P3_PUDEN  = 0xB1
+        sfr  P4_PUDEN  = 0xC9
+ENDIF
+
+                NAME    ?C_STARTUP
+
+?C_C51STARTUP   SEGMENT   CODE
+?STACK          SEGMENT   IDATA
+
+                RSEG    ?STACK
+                DS      1
+
+                EXTRN CODE (?C_START)
+                PUBLIC  ?C_STARTUP
+
+                CSEG    AT      0x2000
+?C_STARTUP:     LJMP    STARTUP1
+
+                RSEG    ?C_C51STARTUP
+//жΪϵ绹 20210907ʱָʾ˸
+STARTUP1:
+                MOV     DPTR,#0xF5E7
+                MOVX    A,@DPTR 
+                CJNE    A,#0x55,ClOCKINIT  ;жǷȣȾͳʼʱӱʾΪϵ
+				        AJMP    Restart1
+				
+Restart1:       MOV     DPTR,#0xF600
+                MOVX    A,@DPTR
+                CJNE    A,#0x55,ClOCKINIT  ;жǷȣȾͳʼʱӱʾΪϵ
+			        	AJMP    STARECMAIN         ;жȾֱתmain
+
+
+STARECMAIN:     MOV     SP,#?STACK-1
+                LJMP    ?C_START 
+								
+									
+ClOCKINIT:
+
+IF (XTAL <> 0)       
+                    ; switch to external XTAL
+        IF(XC878_CHIP_16FF <> 0 || XC878_CHIP_13FF <> 0 || XC874_CHIP_16FF <> 0 || XC874_CHIP_13FF <> 0)
+                MOV     SCU_PAGE,#1;
+                MOV     PASSWD, #11000000B     ;Disable Bit-Protection
+                ANL     OSC_CON, #~(0x01 << 2) ;OSCSS = 0
+                ORL     OSC_CON, #(0x01 << 6)  ;Bypass PLL Output ( PLLBYP = 1 )
+                ORL     OSC_CON, #(0x01 << 5)  ;Set PLL Power Down Mode ( PLLPD = 1)
+                ANL     OSC_CON, #~(0x01 << 3) ;XPD = 0, XTAL not powered down
+                          
+                          
+        WAIT_XTAL_STABLE:          ; delay necssary for external clock to stablise
+                MOV     R2,#0x1E   ; wait about 1.5 ms ( varies with oscillator freq )
+        LOOP:
+                MOV     R3,#0x64   
+                DJNZ    R3, $
+                DJNZ    R2, LOOP
+     OSC_WDT:
+                ORL     OSC_CON, #(0x01 << 1)  ;Restart external oscillator watchdog
+                MOV     R0,#0x41               ;Wait for 65 cycles
+                DJNZ    R0, $
+             ;user may want to add an error counter for oscillator detection
+        CHECK_EXTOSCR:
+                MOV     A, OSC_CON
+                JNB     ACC.0, OSC_WDT        
+                ORL     OSC_CON, #(0x01 << 2)  ;Select external oscillator 
+                MOV     PLL_CON,  #NDIV_XC87x_PLL_CON      ; NDIV value 
+                MOV     PLL_CON1, #NDIV_XC87x_PLL_CON1     ; NDIV Value 
+                MOV     A, #NR_XC87x                       ; PDIV Value 
+                ORL     PLL_CON1, A                                     
+                MOV     A, #OD_XC87x                       ; KDIV Value 
+                ORL     CMCON,    A                                     
+                ANL     OSC_CON, #~(0x01 << 5)  ;Change to PLL Normal Mode ( PLLPD = 0) 
+                ORL     OSC_CON, #(0x01 << 7)   ;Restart the PLL watchdog ( PLLRDRES = 1) 
+
+             ;user may want to add an error counter for PLL lock detection
+        PLLNOTRUN:
+                MOV     A, PLL_CON
+                JNB     ACC.1, PLLNOTRUN           ;PLL_Run Status
+
+        PLLNOTLOCKED:
+                MOV     A, PLL_CON
+                JNB     ACC.0, PLLNOTLOCKED        ;PLL_Lock Status
+
+                ANL     OSC_CON, #~(0x01 << 6)     ;Disable bypass PLL output 
+                MOV     PASSWD, #11000011B         ;Enable Bit-Protection
+                MOV     SCU_PAGE,#0
+
+ELSEIF(XC866_CHIP <> 0 || XC864_CHIP <> 0 || XC88x_CHIP <> 0)
+                MOV     SCU_PAGE,#1
+                ORL     PLL_CON, #0x08  ; VCOBYP = 1
+                ORL     PLL_CON, #0x04  ; OSCDISC = 1   _ _ _ NDIV, VCOBYP, OSCDISC, RESLD, LOCK
+                ANL     OSC_CON, #0xF7  ; XPD = 0       power xtal
+                ORL     OSC_CON, #0x04  ; OSCSS = 1     0, 0, 0, OSCPD, XPD, OSCSS, ORDRES, OSCR
+                ;all calculations are based on no wait state
+                MOV     R1,#0
+DelayXTAL0:
+                MOV     R0,#10         ; delay necssary for external clock to stablise (amplitude >= 0.4 * VDDC - refer to product data sheet)
+DelayXTAL:            ; delay time should be adjusted according to different external osciallators
+                DJNZ    R1,$
+                DJNZ    R0,DelayXTAL
+                
+                ; redetection of osc
+OSCR_NOTSET:
+                MOV     R0, #86
+                ORL     OSC_CON, #0x02  ; ORDRES = 1    ;restart oscillator run detection
+                ;assume no wait state, K = 2, 
+                ;Apollo requires to wait for 256 clock cycles -> 2048 vco cycles
+                ;Elektra requires to wait for 342 clock cycles -> 2048 vco cycles
+                ;djnz = 4 cc
+                DJNZ    R0, $
+                MOV     A,OSC_CON
+                JNB     ACC.0, OSCR_NOTSET
+                
+                ;reprogram the NDIV factor to required value
+                ;ORL     PLL_CON, #0x08      ; VCOBYP = 1 to change N-Divider
+                MOV     PASSWD,  #0x98      ; open access to writing protected bit
+                ANL     PLL_CON, #0x0F
+                ORL     PLL_CON, #NDIV*16
+                ANL     PLL_CON, #0xFB      ; OSCDISC = 0, reconnect oscillator to the PLL
+                
+                ;PLL lock detection
+                ORL     PLL_CON, #0x02     ; detect PLL lock
+                MOV     R0, #100           ; LOCK flag should be set within 200us, user need to adapt accordingly
+                                           ; assume a 10MHz XTAL for XC866/XC864 device
+                                           ; device is in prescaler mode, k = 2 therefore fsys = 5MHz
+                                           ; ## 1cclk = 1/(5MHz/3) = 600 ns
+                                           ; DJNZ requires 4 x 600ns = 2.4 us therefore 100 DJNZ -> 240us
+                                           ; for XC88x, the factor 3 (##) is changed to 4 then the calculated value is 
+                                           ; 320 us based on a 10MHz XTAL
+WAIT_LOCK:
+                DJNZ    R0, $
+                MOV     A, PLL_CON
+                JNB     ACC.0, OSCR_NOTSET
+                ; reconnect to PLL
+                ANL     PLL_CON, #0xF7   ; VCOBYP = 0
+                MOV     SCU_PAGE,#0     
+        ENDIF
+ENDIF
+
+IF IDATALEN <> 0
+                MOV     R0,#IDATALEN - 1
+                CLR     A
+IDATALOOP:      MOV     @R0,A
+                DJNZ    R0,IDATALOOP
+ENDIF
+
+IF (XC878_CHIP_16FF <> 0 || XC874_CHIP_16FF <> 0)
+                MOV     MEX3, #0x1F
+ENDIF
+
+IF (XC874_CHIP_13FF <> 0 || XC874_CHIP_16FF <> 0)
+                MOV     PORT_PAGE, #0x01
+                ORL     P3_PUDEN, #0x80
+                ORL     P4_PUDEN, #0xF0
+                MOV     PORT_PAGE, #0x00
+ENDIF
+
+
+
+IF XDATALEN <> 0
+                MOV     DPTR,#XDATASTART
+                MOV     R7,#LOW (XDATALEN)
+  IF (LOW (XDATALEN)) <> 0
+                MOV     R6,#(HIGH (XDATALEN)) +1
+  ELSE
+                MOV     R6,#HIGH (XDATALEN)
+  ENDIF
+                CLR     A
+XDATALOOP:      MOVX    @DPTR,A
+                INC     DPTR
+                DJNZ    R7,XDATALOOP
+                DJNZ    R6,XDATALOOP
+ENDIF
+
+IF PPAGEENABLE <> 0
+                MOV     SCU_PAGE,#3 
+                MOV     XADDRH,#PPAGE
+                MOV     SCU_PAGE,#0 
+ENDIF
+
+IF PDATALEN <> 0
+                MOV     R0,#LOW (PDATASTART)
+                MOV     R7,#LOW (PDATALEN)
+                CLR     A
+PDATALOOP:      MOVX    @R0,A
+                INC     R0
+                DJNZ    R7,PDATALOOP
+ENDIF
+
+IF IBPSTACK <> 0
+EXTRN DATA (?C_IBP)
+
+                MOV     ?C_IBP,#LOW IBPSTACKTOP
+ENDIF
+
+IF XBPSTACK <> 0
+EXTRN DATA (?C_XBP)
+
+                MOV     ?C_XBP,#HIGH XBPSTACKTOP
+                MOV     ?C_XBP+1,#LOW XBPSTACKTOP
+ENDIF
+
+IF PBPSTACK <> 0
+EXTRN DATA (?C_PBP)
+                MOV     ?C_PBP,#LOW PBPSTACKTOP
+ENDIF
+
+                MOV     SP,#?STACK-1
+
+                LJMP    ?C_START
+
+; Overwrite ?C?DPSEL address for XC866 Device
+PUBLIC ?C?DPSEL
+?C?DPSEL DATA 0A2H   ; DPSEL address for Mentor M8051EW
+
+IF XC864_CHIP <> 0
+  ; Optional ROM-table for XC864 LIN-BSL
+  IF LIN_BSL <> 0
+                  CSEG    AT      0FFCH
+                  DB      LIN_NAC
+                  DB      NOT(LIN_NAC)
+                  DB      LIN_NAD
+                  DB      NOT(LIN_NAD)
+  ENDIF
+ENDIF
+
+                END
diff --git a/SwDriver.C b/SwDriver.C
new file mode 100644
index 0000000..2fda42b
--- /dev/null
+++ b/SwDriver.C
@@ -0,0 +1,496 @@
+#include "MAIN.h"
+
+
+
+//*****************************************************************************
+//ݽṹ
+//*****************************************************************************
+//ÿ33993Ŀ״̬ڵ߸ŵ33993ڲλʱø״ָ̬
+struct StaMc33993CmdSet
+{
+	unsigned char CmdSetting        ;
+	unsigned char CmdInt_Sp         ;
+	unsigned int  CmdInt_Sg         ;
+	unsigned char CmdMetallic_Sp    ;
+	unsigned int  CmdMetallic_Sg    ;
+	unsigned char CmdWetCurr_Sp  	  ;
+	unsigned int  CmdWetCurr_Sg     ;
+	unsigned char CmdTriState_Sp    ;
+	unsigned int  CmdTriState_Sg    ;
+	unsigned char CmdAnalog			    ;
+};
+//33993Ŀ״̬ԲֽڷʣҲ԰λ//XC886һ޸
+union ByteBitAccess
+{
+	struct
+	{
+		ubyte SoMc33993Byte1;
+		ubyte SoMc33993Byte0;
+		ubyte SoMc33993Byte3;
+		ubyte SoMc33993Byte2;
+	}ByteData;
+	struct
+	{
+		unsigned int  FlgSg0    : 1;
+		unsigned int  FlgSg1    : 1;
+		unsigned int  FlgSg2    : 1;
+		unsigned int  FlgSg3    : 1;
+		unsigned int  FlgSg4    : 1;
+		unsigned int  FlgSg5    : 1;
+		unsigned int  FlgSg6    : 1;
+		unsigned int  FlgSg7    : 1;
+		unsigned int  FlgSg8    : 1;
+		unsigned int  FlgSg9    : 1;
+		unsigned int  FlgSg10   : 1;
+		unsigned int  FlgSg11   : 1;
+		unsigned int  FlgSg12   : 1;
+		unsigned int  FlgSg13   : 1;
+		unsigned int  FlgSp0    : 1;
+		unsigned int  FlgSp1    : 1;
+		unsigned int  FlgSp2    : 1;
+		unsigned int  FlgSp3    : 1;
+		unsigned int  FlgSp4    : 1;
+		unsigned int  FlgSp5    : 1;
+		unsigned int  FlgSp6    : 1;
+		unsigned int  FlgSp7    : 1;
+		unsigned int  FlgInt    : 1;
+		unsigned int  FlgThem   : 1;
+		unsigned int            : 8;
+	}BitData;
+};
+//33993Ŀ״̬ԲֽڷʣҲ԰λ
+union WordByteBitAccess
+{
+	uword StaSg;
+	struct
+	{
+		ubyte StaSgH;
+		ubyte StaSgL;
+	}ByteData;
+	struct
+	{
+		unsigned int 	FlgSg0_FlgSp0         : 1;
+		unsigned int  FlgSg1_FlgSp1         : 1;
+		unsigned int  FlgSg2_FlgSp2         : 1;
+		unsigned int  FlgSg3_FlgSp3         : 1;
+		unsigned int  FlgSg4_FlgSp4         : 1;
+		unsigned int  FlgSg5_FlgSp5         : 1;
+		unsigned int  FlgSg6_FlgSp6         : 1;
+		unsigned int  FlgSg7_FlgSp7         : 1;
+		unsigned int  FlgSg8		            : 1;
+		unsigned int  FlgSg9                : 1;
+		unsigned int  FlgSg10               : 1;
+		unsigned int  FlgSg11               : 1;
+		unsigned int  FlgSg12               : 1;
+		unsigned int  FlgSg13               : 1;
+		unsigned int                        : 1;
+		unsigned int                        : 1;
+	}BitData;
+};
+//*****************************************************************************
+//ȫֱ
+//*****************************************************************************
+static struct StaMc33993CmdSet PntSta[2] = {0};
+//*****************************************************************************
+//ļȫֺ
+//*****************************************************************************
+bit Mc33993StaRcvOneBit(ubyte NumMc,ubyte Sp0ToSg13);
+ubyte Mc33993CmdSendOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13,bit Status);
+void InitMc33993Sec(void);
+void ToggleOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13);
+
+union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL);
+
+
+
+////****************************************************************************
+//// @Function     ubyte Mc33993AnalogChSel(struct StaMc33993CmdSet *PntSta,ubyte NumMc,ubyte Mode,ubyte Channal)
+////
+////----------------------------------------------------------------------------
+//// @Description   ģͨѡģʽѡ
+////
+////----------------------------------------------------------------------------
+//// @Returnvalue   ͨлɹ1
+////								Mode,裬2mA16mA
+////----------------------------------------------------------------------------
+//// @Parameters    None
+////
+////----------------------------------------------------------------------------
+//// @Date          2008-12-2
+////
+////****************************************************************************
+//ubyte Mc33993AnalogChSel(ubyte NumMc,ubyte Mode,ubyte Channal)
+//{
+//	union WordByteBitAccess  RcvSoMc33993;
+////----------------------------------------------------------------------------
+//	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1); //NumChipSwƬ
+//	RcvSoMc33993.ByteData.StaSgL = 0;
+//	RcvSoMc33993.ByteData.StaSgL = (RcvSoMc33993.ByteData.StaSgL | Channal);
+//	switch(Mode)
+//	{
+//    case DF_AN_HIMP:
+//				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;//λѡģʽ
+//				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+//				 break;
+//    case DF_AN_2MA:
+//				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;
+//				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 1;
+//				 break;
+//    case DF_AN_16MA:
+//				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 1;
+//				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+//				 break;
+//    default:
+//				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;
+//				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+//	}
+//	Mc33993CmdSend(NumMc,DF_CMDANALOG,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+//
+//	(*(PntSta+NumMc)).CmdAnalog = RcvSoMc33993.ByteData.StaSgL;//״̬
+//
+//	return 1;
+//}
+
+
+//---------------------------------------------------
+
+//*****************************************************************************
+//
+//*****************************************************************************
+
+////****************************************************************************
+//// @Function      void SwStaSample(UnSwSample *ptmp,ubyte NumSampleChip)
+////
+////----------------------------------------------------------------------------
+//// @Description   ɼ33993Ŀźš
+////
+////----------------------------------------------------------------------------
+//// @Returnvalue   None
+////
+////----------------------------------------------------------------------------
+//// @Parameters    ptmpݽṹָ룬NumSampleChip33993оƬ
+////
+////----------------------------------------------------------------------------
+//// @Date          2008-12-2
+////
+////****************************************************************************
+void SwStaSample(UnSwSample *ptmp)
+{
+  union ByteBitAccess  *pStaSwIn;
+	uword i,k;
+//----ʼ------------------------------------------------------------------------
+  InitMc33993Sec();//һѭһΣ12V33993λϿԻָ
+//ʼɼIO
+	for(i=0;i>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP0 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP0 ,Gnd);break;
+				case 1 :if(((((*tmpUn).ArrData.Arr[i][1])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP1 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP1 ,Gnd);break;
+				case 2 :if(((((*tmpUn).ArrData.Arr[i][1])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP2 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP2 ,Gnd);break;
+				case 3 :if(((((*tmpUn).ArrData.Arr[i][1])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP3 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP3 ,Gnd);break;
+				case 4 :if(((((*tmpUn).ArrData.Arr[i][1])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP4 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP4 ,Gnd);break;
+				case 5 :if(((((*tmpUn).ArrData.Arr[i][1])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP5 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP5 ,Gnd);break;
+				case 6 :if(((((*tmpUn).ArrData.Arr[i][1])>>6 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP6 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP6 ,Gnd);break;
+				case 7 :if(((((*tmpUn).ArrData.Arr[i][1])>>7 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP7 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP7 ,Gnd);break;
+				case 8 :if(((((*tmpUn).ArrData.Arr[i][0])>>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG0 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG0 ,Gnd);break;
+				case 9 :if(((((*tmpUn).ArrData.Arr[i][0])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG1 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG1 ,Gnd);break;
+				case 10:if(((((*tmpUn).ArrData.Arr[i][0])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG2 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG2 ,Gnd);break;
+				case 11:if(((((*tmpUn).ArrData.Arr[i][0])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG3 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG3 ,Gnd);break;
+				case 12:if(((((*tmpUn).ArrData.Arr[i][0])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG4 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG4 ,Gnd);break;
+				case 13:if(((((*tmpUn).ArrData.Arr[i][0])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG5 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG5 ,Gnd);break;
+				case 14:if(((((*tmpUn).ArrData.Arr[i][0])>>6 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG6 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG6 ,Gnd);break;
+				case 15:if(((((*tmpUn).ArrData.Arr[i][0])>>7 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG7 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG7 ,Gnd);break;
+				case 16:if(((((*tmpUn).ArrData.Arr[i][3])>>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG8 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG8 ,Gnd);break;
+				case 17:if(((((*tmpUn).ArrData.Arr[i][3])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG9 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG9 ,Gnd);break;
+				case 18:if(((((*tmpUn).ArrData.Arr[i][3])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG10,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG10,Gnd);break;
+				case 19:if(((((*tmpUn).ArrData.Arr[i][3])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG11,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG11,Gnd);break;
+				case 20:if(((((*tmpUn).ArrData.Arr[i][3])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG12,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG12,Gnd);break;
+				case 21:if(((((*tmpUn).ArrData.Arr[i][3])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG13,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG13,Gnd);break;
+				default:;
+			}
+		}
+	}
+}
+
+
+
+//****************************************************************************
+// @Function      void InitMc33993Sec(struct StaMc33993CmdSet *PntSta)
+//
+//----------------------------------------------------------------------------
+// @Description   MC33993γʼҲÿβ33993ʱ֮ǰ״̬ʼ
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    MC33993״̬洢ṹָPntSta
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void InitMc33993Sec(void)
+{
+  ubyte i;
+  for(i=DF_SwInNum;i>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdInt_Sg)&0x00ff));   //1رж
+		Mc33993CmdSend(i,DF_CMDMETALLIC_SP,  0,                                                  (*(PntSta+i)).CmdMetallic_Sp);    //02mA
+		Mc33993CmdSend(i,DF_CMDMETALLIC_SG,  (ubyte)((((*(PntSta+i)).CmdMetallic_Sg)>>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdMetallic_Sg)&0x00ff));    //02mA
+		Mc33993CmdSend(i,DF_CMDANALOG,       0,                                                  (*(PntSta+i)).CmdAnalog);         //0ѡκͨ
+		Mc33993CmdSend(i,DF_CMDWETCURR_SP,   0,                                                  (*(PntSta+i)).CmdWetCurr_Sp);     //0ʪʱر
+		Mc33993CmdSend(i,DF_CMDWETCURR_SG,   (ubyte)((((*(PntSta+i)).CmdWetCurr_Sg) >>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdWetCurr_Sg)&0x00ff));     //0ʪʱر
+		Mc33993CmdSend(i,DF_CMDTRISTATE_SP,  0,                                                  (*(PntSta+i)).CmdTriState_Sp);    //0ֹ̬
+		Mc33993CmdSend(i,DF_CMDTRISTATE_SG,  (ubyte)((((*(PntSta+i)).CmdTriState_Sg)>>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdTriState_Sg)&0x00ff));    //0ʹ̬
+  }
+}
+
+//****************************************************************************
+// @Function      void InitMc33993(struct StaMc33993CmdSet *PntSta)
+//
+//----------------------------------------------------------------------------
+// @Description   MC33993ڵƬϵʱʼ
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void InitSW(void)
+{
+  ubyte i;
+  for(i=0;i (NumChipSw-1))NumMc = (NumChipSw-1);
+	switch(CmdBit)
+	{
+//DF_CMDTRISTATE_SP
+		case DF_CMDTRISTATE_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdTriState_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdTriState_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDTRISTATE_SG
+		case DF_CMDTRISTATE_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdTriState_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdTriState_Sg = RcvSoMc33993.StaSg;
+			break;
+		default:;
+	}
+	return 1;
+}
+
+//Ƭѡ
+//20ƬҪ
+void ChangeCsMc33993(ubyte NumMc,bit HorL)
+{
+  switch(NumMc)
+  {
+    case Mc33993_0 :  CS_SwChip_0  = HorL;break;
+    case Mc33993_1 :  CS_SwChip_1  = HorL;break;
+    default:;
+  }
+}
+//****************************************************************************
+// @Function     ubyte Mc33993DataSendRcv(ubyte Data)
+//
+//----------------------------------------------------------------------------
+// @Description   ,ؽ
+//                ˺CPUƽ̨,ͬCPUҪ޸ġ
+//                ˺XC2765SSCòѯʽ
+//----------------------------------------------------------------------------
+// @Returnvalue   ؽյ
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2011-3-4 10:28:27
+//
+//****************************************************************************
+ubyte Mc33993DataSendRcv(ubyte Data)
+{
+	uword i;
+	SSC_vSendData(Data);	
+	for(i=0;(i<6000)&&(!(IRCON1&0x02));i++);
+  IRCON1 &= 0xFD;
+	for(i=0;(i<6000)&&(!(IRCON1&0x04));i++);
+  IRCON1 &= 0xFB;
+  return((ubyte)(SSC_vGetData()));
+}
+
+//****************************************************************************
+// @Function     union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL)
+//
+//----------------------------------------------------------------------------
+// @Description   33993IJ,ؿ״̬
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   ؽյ3ֽڵĿ״̬
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2011-3-4 10:36:27
+//
+//****************************************************************************
+union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL)
+{
+  union ByteBitAccess  RcvSoMc,*Pnt;
+	union WordByteBitAccess  RcvSoMc33993W;
+//	uword i;
+//----------------------------------------------------------------------------
+	RcvSoMc33993W.ByteData.StaSgH = SetBitH;
+	RcvSoMc33993W.ByteData.StaSgL = SetBitL;
+	switch(CmdBit)//״̬
+	{
+		case DF_CMDSETTING    :(*(PntSta+NumMc)).CmdSetting     = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDINT_SP     :(*(PntSta+NumMc)).CmdInt_Sp      = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDINT_SG     :(*(PntSta+NumMc)).CmdInt_Sg      = RcvSoMc33993W.StaSg;break;
+		case DF_CMDMETALLIC_SP:(*(PntSta+NumMc)).CmdMetallic_Sp = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDMETALLIC_SG:(*(PntSta+NumMc)).CmdMetallic_Sg = RcvSoMc33993W.StaSg;break;
+		case DF_CMDANALOG     :(*(PntSta+NumMc)).CmdAnalog      = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDWETCURR_SP :(*(PntSta+NumMc)).CmdWetCurr_Sp  = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDWETCURR_SG :(*(PntSta+NumMc)).CmdWetCurr_Sg  = RcvSoMc33993W.StaSg;break;
+		case DF_CMDTRISTATE_SP:(*(PntSta+NumMc)).CmdTriState_Sp = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDTRISTATE_SG:(*(PntSta+NumMc)).CmdTriState_Sg = RcvSoMc33993W.StaSg;break;
+		default:;
+	}
+	
+	
+	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1);
+  ChangeCsMc33993(NumMc,0);
+//----------------------------
+  _nop_();
+	_nop_();
+	_nop_();
+	_nop_();
+	
+//-------------------------------
+
+  RcvSoMc.ByteData.SoMc33993Byte2 = Mc33993DataSendRcv(CmdBit);
+
+  RcvSoMc.ByteData.SoMc33993Byte1 = Mc33993DataSendRcv(SetBitH);
+
+  RcvSoMc.ByteData.SoMc33993Byte0 = Mc33993DataSendRcv(SetBitL);
+
+  ChangeCsMc33993(NumMc,1);
+//----------------------------
+  _nop_();
+	_nop_();
+	_nop_();
+	_nop_();
+//-------------------------------
+  Pnt = &RcvSoMc;
+  return (Pnt);
+}
diff --git a/SwDriver.C.bak b/SwDriver.C.bak
new file mode 100644
index 0000000..d6ac035
--- /dev/null
+++ b/SwDriver.C.bak
@@ -0,0 +1,893 @@
+#include "MAIN.h"
+
+//*****************************************************************************
+//궨
+//*****************************************************************************
+//20ƬҪ
+#define Mc33993_0 			0
+#define Mc33993_1		 		1
+#define Mc33993_2		 		2
+#define Mc33993_3		 		3
+#define Mc33993_4		 		4
+#define Mc33993_5		 		5
+#define Mc33993_6		 		6
+#define Mc33993_7 			7
+#define Mc33993_8 			8
+#define Mc33993_9 			9
+#define Mc33993_10			10
+#define Mc33993_11			11
+#define Mc33993_12			12
+#define Mc33993_13			13
+#define Mc33993_14			14
+#define Mc33993_15			15
+#define Mc33993_16			16
+#define Mc33993_17			17
+#define Mc33993_18			18
+#define Mc33993_19			19
+#define Mc33993_20			20
+
+
+#define D24V		 		0
+#define Gnd		 	   	1
+
+#define TriOff		 	0
+#define TriOn		 	  1
+
+#define WetCur2mA		0
+#define WetCur16mA	1
+
+#define SwToGnd		 	0
+#define SwToPwr		 	1
+
+#define ALLTRI		 	0xff
+#define ALLD24V		 	0x0
+
+#define DF_CMDSWSTATUS 			0x00
+#define DF_CMDSETTING 			0x01
+#define DF_CMDINT_SP 				0x02
+#define DF_CMDINT_SG 				0x03
+#define DF_CMDMETALLIC_SP 	0x04
+#define DF_CMDMETALLIC_SG 	0x05
+#define DF_CMDANALOG 				0x06
+#define DF_CMDWETCURR_SP 		0x07
+#define DF_CMDWETCURR_SG 		0x08
+#define DF_CMDTRISTATE_SP 	0x09
+#define DF_CMDTRISTATE_SG 	0x0A
+#define DF_CMDCALIBRATION 	0x0B
+#define DF_CMDSLEEP				 	0x0C
+#define DF_CMDRESET				 	0x7F
+
+
+#define  DF_FLGTHEM					10
+#define  DF_FLGINT          11
+#define  DF_FLGSP7          12
+#define  DF_FLGSP6          13
+#define  DF_FLGSP5          14
+#define  DF_FLGSP4          15
+#define  DF_FLGSP3          16
+#define  DF_FLGSP2          17
+#define  DF_FLGSP1          18
+#define  DF_FLGSP0          19
+#define  DF_FLGSG13         20
+#define  DF_FLGSG12         21
+#define  DF_FLGSG11         22
+#define  DF_FLGSG10         23
+#define  DF_FLGSG9          24
+#define  DF_FLGSG8          25
+#define  DF_FLGSG7          26
+#define  DF_FLGSG6          27
+#define  DF_FLGSG5          28
+#define  DF_FLGSG4          29
+#define  DF_FLGSG3          30
+#define  DF_FLGSG2          31
+#define  DF_FLGSG1          32
+#define  DF_FLGSG0          33
+
+//Analog
+#define  DF_AN_HIMP          1
+#define  DF_AN_2MA           2
+#define  DF_AN_16MA          3
+
+#define  DF_CH_SG0           1
+#define  DF_CH_SG1           2
+#define  DF_CH_SG2           3
+#define  DF_CH_SG3           4
+#define  DF_CH_SG4           5
+#define  DF_CH_SG5           6
+#define  DF_CH_SG6           7
+#define  DF_CH_SG7           8
+#define  DF_CH_SG8           9
+#define  DF_CH_SG9           10
+#define  DF_CH_SG10          11
+#define  DF_CH_SG11          12
+#define  DF_CH_SG12          13
+#define  DF_CH_SG13          14
+#define  DF_CH_SP0           15
+#define  DF_CH_SP1           16
+#define  DF_CH_SP2           17
+#define  DF_CH_SP3           18
+#define  DF_CH_SP4           19
+#define  DF_CH_SP5           20
+#define  DF_CH_SP6           21
+#define  DF_CH_SP7           22
+
+//*****************************************************************************
+//ݽṹ
+//*****************************************************************************
+//ÿ33993Ŀ״̬ڵ߸ŵ33993ڲλʱø״ָ̬
+struct StaMc33993CmdSet
+{
+	unsigned char CmdSetting        ;
+	unsigned char CmdInt_Sp         ;
+	unsigned int  CmdInt_Sg         ;
+	unsigned char CmdMetallic_Sp    ;
+	unsigned int  CmdMetallic_Sg    ;
+	unsigned char CmdWetCurr_Sp  	  ;
+	unsigned int  CmdWetCurr_Sg     ;
+	unsigned char CmdTriState_Sp    ;
+	unsigned int  CmdTriState_Sg    ;
+	unsigned char CmdAnalog			    ;
+};
+//33993Ŀ״̬ԲֽڷʣҲ԰λ//XC886һ޸
+union ByteBitAccess
+{
+	struct
+	{
+		ubyte SoMc33993Byte1;
+		ubyte SoMc33993Byte0;
+		ubyte SoMc33993Byte3;
+		ubyte SoMc33993Byte2;
+	}ByteData;
+	struct
+	{
+		unsigned int  FlgSg0    : 1;
+		unsigned int  FlgSg1    : 1;
+		unsigned int  FlgSg2    : 1;
+		unsigned int  FlgSg3    : 1;
+		unsigned int  FlgSg4    : 1;
+		unsigned int  FlgSg5    : 1;
+		unsigned int  FlgSg6    : 1;
+		unsigned int  FlgSg7    : 1;
+		unsigned int  FlgSg8    : 1;
+		unsigned int  FlgSg9    : 1;
+		unsigned int  FlgSg10   : 1;
+		unsigned int  FlgSg11   : 1;
+		unsigned int  FlgSg12   : 1;
+		unsigned int  FlgSg13   : 1;
+		unsigned int  FlgSp0    : 1;
+		unsigned int  FlgSp1    : 1;
+		unsigned int  FlgSp2    : 1;
+		unsigned int  FlgSp3    : 1;
+		unsigned int  FlgSp4    : 1;
+		unsigned int  FlgSp5    : 1;
+		unsigned int  FlgSp6    : 1;
+		unsigned int  FlgSp7    : 1;
+		unsigned int  FlgInt    : 1;
+		unsigned int  FlgThem   : 1;
+		unsigned int            : 8;
+	}BitData;
+};
+//33993Ŀ״̬ԲֽڷʣҲ԰λ
+union WordByteBitAccess
+{
+	uword StaSg;
+	struct
+	{
+		ubyte StaSgH;
+		ubyte StaSgL;
+	}ByteData;
+	struct
+	{
+		unsigned int 	FlgSg0_FlgSp0         : 1;
+		unsigned int  FlgSg1_FlgSp1         : 1;
+		unsigned int  FlgSg2_FlgSp2         : 1;
+		unsigned int  FlgSg3_FlgSp3         : 1;
+		unsigned int  FlgSg4_FlgSp4         : 1;
+		unsigned int  FlgSg5_FlgSp5         : 1;
+		unsigned int  FlgSg6_FlgSp6         : 1;
+		unsigned int  FlgSg7_FlgSp7         : 1;
+		unsigned int  FlgSg8		            : 1;
+		unsigned int  FlgSg9                : 1;
+		unsigned int  FlgSg10               : 1;
+		unsigned int  FlgSg11               : 1;
+		unsigned int  FlgSg12               : 1;
+		unsigned int  FlgSg13               : 1;
+		unsigned int                        : 1;
+		unsigned int                        : 1;
+	}BitData;
+};
+//*****************************************************************************
+//ȫֱ
+//*****************************************************************************
+static struct StaMc33993CmdSet PntSta[2] = {0};
+//*****************************************************************************
+//ļȫֺ
+//*****************************************************************************
+bit Mc33993StaRcvOneBit(ubyte NumMc,ubyte Sp0ToSg13);
+ubyte Mc33993CmdSendOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13,bit Status);
+void InitMc33993Sec(void);
+void ToggleOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13);
+ubyte Mc33993AnalogChSel(ubyte NumMc,ubyte Mode,ubyte Channal);
+union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL);
+
+
+
+
+
+
+//---------------------------------------------------
+
+//*****************************************************************************
+//
+//*****************************************************************************
+void Swtest2(void)
+{
+ 		ulong  i,j;
+	
+	UnSwOut_1.BitData.S21 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S22 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S23 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S24 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S25 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S26 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S27 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S28 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S29 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S30 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S31 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S32 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S33 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S34 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S35 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S36 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S37 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S38 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S39 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S40 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+
+	UnSwOut_1.BitData.S21 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S22 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S23 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S24 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S25 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S26 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S27 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S28 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S29 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S30 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S31 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S32 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S33 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S34 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S35 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S36 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S37 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S38 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S39 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S40 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}
+
+
+}
+
+//****************************************************************************
+// @Function      void SwStaSample(UnSwSample *ptmp,ubyte NumSampleChip)
+//
+//----------------------------------------------------------------------------
+// @Description   ɼ33993Ŀźš
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ptmpݽṹָ룬NumSampleChip33993оƬ
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void SwStaSample(UnSwSample *ptmp)
+{
+  union ByteBitAccess  *pStaSwIn;
+	uword i,k;
+//----ʼ------------------------------------------------------------------------
+  InitMc33993Sec();//һѭһΣ12V33993λϿԻָ
+//ʼɼIO
+	for(i=0;i>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP0 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP0 ,Gnd);break;
+				case 1 :if(((((*tmpUn).ArrData.Arr[i][1])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP1 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP1 ,Gnd);break;
+				case 2 :if(((((*tmpUn).ArrData.Arr[i][1])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP2 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP2 ,Gnd);break;
+				case 3 :if(((((*tmpUn).ArrData.Arr[i][1])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP3 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP3 ,Gnd);break;
+				case 4 :if(((((*tmpUn).ArrData.Arr[i][1])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP4 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP4 ,Gnd);break;
+				case 5 :if(((((*tmpUn).ArrData.Arr[i][1])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP5 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP5 ,Gnd);break;
+				case 6 :if(((((*tmpUn).ArrData.Arr[i][1])>>6 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP6 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP6 ,Gnd);break;
+				case 7 :if(((((*tmpUn).ArrData.Arr[i][1])>>7 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP7 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP7 ,Gnd);break;
+				case 8 :if(((((*tmpUn).ArrData.Arr[i][0])>>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG0 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG0 ,Gnd);break;
+				case 9 :if(((((*tmpUn).ArrData.Arr[i][0])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG1 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG1 ,Gnd);break;
+				case 10:if(((((*tmpUn).ArrData.Arr[i][0])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG2 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG2 ,Gnd);break;
+				case 11:if(((((*tmpUn).ArrData.Arr[i][0])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG3 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG3 ,Gnd);break;
+				case 12:if(((((*tmpUn).ArrData.Arr[i][0])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG4 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG4 ,Gnd);break;
+				case 13:if(((((*tmpUn).ArrData.Arr[i][0])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG5 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG5 ,Gnd);break;
+				case 14:if(((((*tmpUn).ArrData.Arr[i][0])>>6 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG6 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG6 ,Gnd);break;
+				case 15:if(((((*tmpUn).ArrData.Arr[i][0])>>7 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG7 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG7 ,Gnd);break;
+				case 16:if(((((*tmpUn).ArrData.Arr[i][3])>>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG8 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG8 ,Gnd);break;
+				case 17:if(((((*tmpUn).ArrData.Arr[i][3])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG9 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG9 ,Gnd);break;
+				case 18:if(((((*tmpUn).ArrData.Arr[i][3])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG10,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG10,Gnd);break;
+				case 19:if(((((*tmpUn).ArrData.Arr[i][3])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG11,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG11,Gnd);break;
+				case 20:if(((((*tmpUn).ArrData.Arr[i][3])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG12,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG12,Gnd);break;
+				case 21:if(((((*tmpUn).ArrData.Arr[i][3])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG13,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG13,Gnd);break;
+				default:;
+			}
+		}
+	}
+}
+
+
+//****************************************************************************
+// @Function      void ToggleOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13)
+//
+//----------------------------------------------------------------------------
+// @Description   ȡоƬĸλҪṩλ
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    MC33993״̬洢ṹָPntSta
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+// void ToggleOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13)
+// {
+//   union WordByteBitAccess  RcvSoMc33993;
+// 	bit status;
+
+// 	if(CmdBit == DF_CMDTRISTATE_SG)
+// 	{
+// 		RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdTriState_Sg;
+
+// 		switch(Sp0ToSg13)
+// 		{
+// 			case 	DF_FLGSG13:	status = RcvSoMc33993.BitData.FlgSg13      ;break;
+// 			case 	DF_FLGSG12:	status = RcvSoMc33993.BitData.FlgSg12      ;break;
+// 			case 	DF_FLGSG11:	status = RcvSoMc33993.BitData.FlgSg11      ;break;
+// 			case 	DF_FLGSG10:	status = RcvSoMc33993.BitData.FlgSg10      ;break;
+// 			case 	DF_FLGSG9 :	status = RcvSoMc33993.BitData.FlgSg9       ;break;
+// 			case 	DF_FLGSG8 :	status = RcvSoMc33993.BitData.FlgSg8       ;break;
+// 			case 	DF_FLGSG7 :	status = RcvSoMc33993.BitData.FlgSg7_FlgSp7;break;
+// 			case 	DF_FLGSG6 :	status = RcvSoMc33993.BitData.FlgSg6_FlgSp6;break;
+// 			case 	DF_FLGSG5 :	status = RcvSoMc33993.BitData.FlgSg5_FlgSp5;break;
+// 			case 	DF_FLGSG4 :	status = RcvSoMc33993.BitData.FlgSg4_FlgSp4;break;
+// 			case 	DF_FLGSG3 :	status = RcvSoMc33993.BitData.FlgSg3_FlgSp3;break;
+// 			case 	DF_FLGSG2 :	status = RcvSoMc33993.BitData.FlgSg2_FlgSp2;break;
+// 			case 	DF_FLGSG1 :	status = RcvSoMc33993.BitData.FlgSg1_FlgSp1;break;
+// 			case 	DF_FLGSG0 :	status = RcvSoMc33993.BitData.FlgSg0_FlgSp0;break;
+// 			default:;
+// 		}
+// 		if(status)Mc33993CmdSendOneBit(Mc33993_1,DF_CMDTRISTATE_SG,Sp0ToSg13,D24V);
+// 		else			Mc33993CmdSendOneBit(Mc33993_1,DF_CMDTRISTATE_SG,Sp0ToSg13,Gnd);
+// 	}
+// 	else if(CmdBit == DF_CMDTRISTATE_SP)
+// 	{
+// 		RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdTriState_Sp;
+
+// 		switch(Sp0ToSg13)
+// 		{
+// 			case 	DF_FLGSG7 :	status = RcvSoMc33993.BitData.FlgSg7_FlgSp7;break;
+// 			case 	DF_FLGSG6 :	status = RcvSoMc33993.BitData.FlgSg6_FlgSp6;break;
+// 			case 	DF_FLGSG5 :	status = RcvSoMc33993.BitData.FlgSg5_FlgSp5;break;
+// 			case 	DF_FLGSG4 :	status = RcvSoMc33993.BitData.FlgSg4_FlgSp4;break;
+// 			case 	DF_FLGSG3 :	status = RcvSoMc33993.BitData.FlgSg3_FlgSp3;break;
+// 			case 	DF_FLGSG2 :	status = RcvSoMc33993.BitData.FlgSg2_FlgSp2;break;
+// 			case 	DF_FLGSG1 :	status = RcvSoMc33993.BitData.FlgSg1_FlgSp1;break;
+// 			case 	DF_FLGSG0 :	status = RcvSoMc33993.BitData.FlgSg0_FlgSp0;break;
+// 			default:;
+// 		}
+// 		if(status)Mc33993CmdSendOneBit(Mc33993_1,DF_CMDTRISTATE_SP,Sp0ToSg13,D24V);
+// 		else			Mc33993CmdSendOneBit(Mc33993_1,DF_CMDTRISTATE_SP,Sp0ToSg13,Gnd);
+// 	}
+// }
+
+//****************************************************************************
+// @Function      void InitMc33993Sec(struct StaMc33993CmdSet *PntSta)
+//
+//----------------------------------------------------------------------------
+// @Description   MC33993γʼҲÿβ33993ʱ֮ǰ״̬ʼ
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    MC33993״̬洢ṹָPntSta
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void InitMc33993Sec(void)
+{
+  ubyte i;
+  for(i=0;i>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdInt_Sg)&0x00ff));   //1رж
+		Mc33993CmdSend(i,DF_CMDMETALLIC_SP,  0,                                                  (*(PntSta+i)).CmdMetallic_Sp);    //02mA
+		Mc33993CmdSend(i,DF_CMDMETALLIC_SG,  (ubyte)((((*(PntSta+i)).CmdMetallic_Sg)>>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdMetallic_Sg)&0x00ff));    //02mA
+		Mc33993CmdSend(i,DF_CMDANALOG,       0,                                                  (*(PntSta+i)).CmdAnalog);         //0ѡκͨ
+		Mc33993CmdSend(i,DF_CMDWETCURR_SP,   0,                                                  (*(PntSta+i)).CmdWetCurr_Sp);     //0ʪʱر
+		Mc33993CmdSend(i,DF_CMDWETCURR_SG,   (ubyte)((((*(PntSta+i)).CmdWetCurr_Sg) >>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdWetCurr_Sg)&0x00ff));     //0ʪʱر
+		Mc33993CmdSend(i,DF_CMDTRISTATE_SP,  0,                                                  (*(PntSta+i)).CmdTriState_Sp);    //0ֹ̬
+		Mc33993CmdSend(i,DF_CMDTRISTATE_SG,  (ubyte)((((*(PntSta+i)).CmdTriState_Sg)>>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdTriState_Sg)&0x00ff));    //0ʹ̬
+  }
+}
+
+//****************************************************************************
+// @Function      void InitMc33993(struct StaMc33993CmdSet *PntSta)
+//
+//----------------------------------------------------------------------------
+// @Description   MC33993ڵƬϵʱʼ
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void InitSW(void)
+{
+  ubyte i;
+  for(i=0;i (NumChipSw-1))NumMc = (NumChipSw-1); //NumChipSwƬ
+// 	RcvSoMc33993.ByteData.StaSgL = 0;
+// 	RcvSoMc33993.ByteData.StaSgL = (RcvSoMc33993.ByteData.StaSgL | Channal);
+// 	switch(Mode)
+// 	{
+//     case DF_AN_HIMP:
+// 				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;//λѡģʽ
+// 				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+// 				 break;
+//     case DF_AN_2MA:
+// 				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;
+// 				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 1;
+// 				 break;
+//     case DF_AN_16MA:
+// 				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 1;
+// 				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+// 				 break;
+//     default:
+// 				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;
+// 				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+// 	}
+// 	Mc33993CmdSend(NumMc,DF_CMDANALOG,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+
+// 	(*(PntSta+NumMc)).CmdAnalog = RcvSoMc33993.ByteData.StaSgL;//״̬
+
+// 	return 1;
+// }
+
+//****************************************************************************
+// @Function     bit Mc33993StaRcvOneBit(ubyte NumMc,ubyte Sp0ToSg13)
+//
+//----------------------------------------------------------------------------
+// @Description   ȡһλĿ״̬
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   λ״̬
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+// bit Mc33993StaRcvOneBit(ubyte NumMc,ubyte Sp0ToSg13)
+// {
+// 	union ByteBitAccess  *Pnt;
+// 	bit  BitRcvOneBit;
+// //-----------------------------------------------------------------------------
+// 	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1);
+// 	Pnt = Mc33993CmdSend(NumMc,DF_CMDSWSTATUS,0xff,0xff);
+
+// 			 if(Sp0ToSg13 == DF_FLGTHEM)BitRcvOneBit = (*Pnt).BitData.FlgThem;
+// 	else if(Sp0ToSg13 == DF_FLGINT )BitRcvOneBit = (*Pnt).BitData.FlgInt;
+// 	else if(Sp0ToSg13 == DF_FLGSP7 )BitRcvOneBit = (*Pnt).BitData.FlgSp7;
+// 	else if(Sp0ToSg13 == DF_FLGSP6 )BitRcvOneBit = (*Pnt).BitData.FlgSp6;
+// 	else if(Sp0ToSg13 == DF_FLGSP5 )BitRcvOneBit = (*Pnt).BitData.FlgSp5;
+// 	else if(Sp0ToSg13 == DF_FLGSP4 )BitRcvOneBit = (*Pnt).BitData.FlgSp4;
+// 	else if(Sp0ToSg13 == DF_FLGSP3 )BitRcvOneBit = (*Pnt).BitData.FlgSp3;
+// 	else if(Sp0ToSg13 == DF_FLGSP2 )BitRcvOneBit = (*Pnt).BitData.FlgSp2;
+// 	else if(Sp0ToSg13 == DF_FLGSP1 )BitRcvOneBit = (*Pnt).BitData.FlgSp1;
+// 	else if(Sp0ToSg13 == DF_FLGSP0 )BitRcvOneBit = (*Pnt).BitData.FlgSp0;
+// 	else if(Sp0ToSg13 == DF_FLGSG13)BitRcvOneBit = (*Pnt).BitData.FlgSg13;
+// 	else if(Sp0ToSg13 == DF_FLGSG12)BitRcvOneBit = (*Pnt).BitData.FlgSg12;
+// 	else if(Sp0ToSg13 == DF_FLGSG11)BitRcvOneBit = (*Pnt).BitData.FlgSg11;
+// 	else if(Sp0ToSg13 == DF_FLGSG10)BitRcvOneBit = (*Pnt).BitData.FlgSg10;
+// 	else if(Sp0ToSg13 == DF_FLGSG9 )BitRcvOneBit = (*Pnt).BitData.FlgSg9;
+// 	else if(Sp0ToSg13 == DF_FLGSG8 )BitRcvOneBit = (*Pnt).BitData.FlgSg8;
+// 	else if(Sp0ToSg13 == DF_FLGSG7 )BitRcvOneBit = (*Pnt).BitData.FlgSg7;
+// 	else if(Sp0ToSg13 == DF_FLGSG6 )BitRcvOneBit = (*Pnt).BitData.FlgSg6;
+// 	else if(Sp0ToSg13 == DF_FLGSG5 )BitRcvOneBit = (*Pnt).BitData.FlgSg5;
+// 	else if(Sp0ToSg13 == DF_FLGSG4 )BitRcvOneBit = (*Pnt).BitData.FlgSg4;
+// 	else if(Sp0ToSg13 == DF_FLGSG3 )BitRcvOneBit = (*Pnt).BitData.FlgSg3;
+// 	else if(Sp0ToSg13 == DF_FLGSG2 )BitRcvOneBit = (*Pnt).BitData.FlgSg2;
+// 	else if(Sp0ToSg13 == DF_FLGSG1 )BitRcvOneBit = (*Pnt).BitData.FlgSg1;
+// 	else if(Sp0ToSg13 == DF_FLGSG0 )BitRcvOneBit = (*Pnt).BitData.FlgSg0;
+// 	else ;
+// 	return 	BitRcvOneBit;
+// }
+
+//****************************************************************************
+// @Function     ubyte Mc33993CmdSendOneBit(struct StaMc33993CmdSet *PntSta,ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13,bit Status)
+//
+//----------------------------------------------------------------------------
+// @Description   дMC33993λMc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   ɹ1
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+ubyte Mc33993CmdSendOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13,bit Status)
+{
+	union WordByteBitAccess  RcvSoMc33993;
+//----------------------------------------------------------------------------
+	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1);
+	switch(CmdBit)
+	{
+//DF_CMDSETTING
+		case DF_CMDSETTING:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdSetting; //֮ǰ״̬RcvSoMc33993ֽ,ҲDzıλ״̬
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;//Ҫıλ
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+			//(*(PntSta+NumMc)).CmdSetting = RcvSoMc33993.ByteData.StaSgL;//º״̬
+		  break;
+//DF_CMDINT_SP
+		case DF_CMDINT_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdInt_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+			//(*(PntSta+NumMc)).CmdInt_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDMETALLIC_SP
+		case DF_CMDMETALLIC_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdMetallic_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+			//(*(PntSta+NumMc)).CmdMetallic_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDWETCURR_SP
+		case DF_CMDWETCURR_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdWetCurr_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+			//(*(PntSta+NumMc)).CmdWetCurr_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDTRISTATE_SP
+		case DF_CMDTRISTATE_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdTriState_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdTriState_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDINT_SG
+		case DF_CMDINT_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdInt_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdInt_Sg = RcvSoMc33993.StaSg;
+			break;
+//DF_CMDMETALLIC_SG
+		case DF_CMDMETALLIC_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdMetallic_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdMetallic_Sg = RcvSoMc33993.StaSg;
+			break;
+//DF_CMDWETCURR_SG
+		case DF_CMDWETCURR_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdWetCurr_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdWetCurr_Sg = RcvSoMc33993.StaSg;
+			break;
+//DF_CMDTRISTATE_SG
+		case DF_CMDTRISTATE_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdTriState_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdTriState_Sg = RcvSoMc33993.StaSg;
+			break;
+		default:;
+	}
+	return 1;
+}
+
+//Ƭѡ
+//20ƬҪ
+void ChangeCsMc33993(ubyte NumMc,bit HorL)
+{
+  switch(NumMc)
+  {
+    case Mc33993_0 :  CS_SwChip_0  = HorL;break;
+    case Mc33993_1 :  CS_SwChip_1  = HorL;break;
+    default:;
+  }
+}
+//****************************************************************************
+// @Function     ubyte Mc33993DataSendRcv(ubyte Data)
+//
+//----------------------------------------------------------------------------
+// @Description   ,ؽ
+//                ˺CPUƽ̨,ͬCPUҪ޸ġ
+//                ˺XC2765SSCòѯʽ
+//----------------------------------------------------------------------------
+// @Returnvalue   ؽյ
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2011-3-4 10:28:27
+//
+//****************************************************************************
+ubyte Mc33993DataSendRcv(ubyte Data)
+{
+	uword i;
+	SSC_vSendData(Data);	
+	for(i=0;(i<6000)&&(!(IRCON1&0x02));i++);
+  IRCON1 &= 0xFD;
+	for(i=0;(i<6000)&&(!(IRCON1&0x04));i++);
+  IRCON1 &= 0xFB;
+  return((ubyte)(SSC_vGetData()));
+}
+
+//****************************************************************************
+// @Function     union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL)
+//
+//----------------------------------------------------------------------------
+// @Description   33993IJ,ؿ״̬
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   ؽյ3ֽڵĿ״̬
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2011-3-4 10:36:27
+//
+//****************************************************************************
+union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL)
+{
+  union ByteBitAccess  RcvSoMc33993,*Pnt;
+	union WordByteBitAccess  RcvSoMc33993W;
+//	uword i;
+//----------------------------------------------------------------------------
+	RcvSoMc33993W.ByteData.StaSgH = SetBitH;
+	RcvSoMc33993W.ByteData.StaSgL = SetBitL;
+	switch(CmdBit)//״̬
+	{
+		case DF_CMDSETTING    :(*(PntSta+NumMc)).CmdSetting     = RcvSoMc33993W.StaSg;break;
+		case DF_CMDINT_SP     :(*(PntSta+NumMc)).CmdInt_Sp      = RcvSoMc33993W.StaSg;break;
+		case DF_CMDINT_SG     :(*(PntSta+NumMc)).CmdInt_Sg      = RcvSoMc33993W.StaSg;break;
+		case DF_CMDMETALLIC_SP:(*(PntSta+NumMc)).CmdMetallic_Sp = RcvSoMc33993W.StaSg;break;
+		case DF_CMDMETALLIC_SG:(*(PntSta+NumMc)).CmdMetallic_Sg = RcvSoMc33993W.StaSg;break;
+		case DF_CMDANALOG     :(*(PntSta+NumMc)).CmdAnalog      = RcvSoMc33993W.StaSg;break;
+		case DF_CMDWETCURR_SP :(*(PntSta+NumMc)).CmdWetCurr_Sp  = RcvSoMc33993W.StaSg;break;
+		case DF_CMDWETCURR_SG :(*(PntSta+NumMc)).CmdWetCurr_Sg  = RcvSoMc33993W.StaSg;break;
+		case DF_CMDTRISTATE_SP:(*(PntSta+NumMc)).CmdTriState_Sp = RcvSoMc33993W.StaSg;break;
+		case DF_CMDTRISTATE_SG:(*(PntSta+NumMc)).CmdTriState_Sg = RcvSoMc33993W.StaSg;break;
+		default:;
+	}
+	
+	
+	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1);
+  ChangeCsMc33993(NumMc,0);
+//----------------------------
+  _nop_();
+	_nop_();
+	_nop_();
+	_nop_();
+	
+//-------------------------------
+
+  RcvSoMc33993.ByteData.SoMc33993Byte2 = Mc33993DataSendRcv(CmdBit);
+
+  RcvSoMc33993.ByteData.SoMc33993Byte1 = Mc33993DataSendRcv(SetBitH);
+
+  RcvSoMc33993.ByteData.SoMc33993Byte0 = Mc33993DataSendRcv(SetBitL);
+
+  ChangeCsMc33993(NumMc,1);
+//----------------------------
+  _nop_();
+	_nop_();
+	_nop_();
+	_nop_();
+//-------------------------------
+  Pnt = &RcvSoMc33993;
+  return (Pnt);
+}
diff --git a/SwDriver.H b/SwDriver.H
new file mode 100644
index 0000000..91e78e1
--- /dev/null
+++ b/SwDriver.H
@@ -0,0 +1,122 @@
+#ifndef _MC33993_H_
+#define _MC33993_H_
+
+//*****************************************************************************
+//궨
+//*****************************************************************************
+//20ƬҪ
+#define Mc33993_0 			0
+#define Mc33993_1		 		1
+#define Mc33993_2		 		2
+#define Mc33993_3		 		3
+#define Mc33993_4		 		4
+#define Mc33993_5		 		5
+#define Mc33993_6		 		6
+#define Mc33993_7 			7
+#define Mc33993_8 			8
+#define Mc33993_9 			9
+#define Mc33993_10			10
+#define Mc33993_11			11
+#define Mc33993_12			12
+#define Mc33993_13			13
+#define Mc33993_14			14
+#define Mc33993_15			15
+#define Mc33993_16			16
+#define Mc33993_17			17
+#define Mc33993_18			18
+#define Mc33993_19			19
+#define Mc33993_20			20
+
+
+#define D24V		 		0
+#define Gnd		 	   	1
+
+#define TriOff		 	0
+#define TriOn		 	  1
+
+#define WetCur2mA		0
+#define WetCur16mA	1
+
+#define SwToGnd		 	0
+#define SwToPwr		 	1
+
+#define ALLTRI		 	0xff
+#define ALLD24V		 	0x0
+
+#define DF_CMDSWSTATUS 			0x00
+#define DF_CMDSETTING 			0x01
+#define DF_CMDINT_SP 				0x02
+#define DF_CMDINT_SG 				0x03
+#define DF_CMDMETALLIC_SP 	0x04
+#define DF_CMDMETALLIC_SG 	0x05
+#define DF_CMDANALOG 				0x06
+#define DF_CMDWETCURR_SP 		0x07
+#define DF_CMDWETCURR_SG 		0x08
+#define DF_CMDTRISTATE_SP 	0x09
+#define DF_CMDTRISTATE_SG 	0x0A
+#define DF_CMDCALIBRATION 	0x0B
+#define DF_CMDSLEEP				 	0x0C
+#define DF_CMDRESET				 	0x7F
+
+
+#define  DF_FLGTHEM					10
+#define  DF_FLGINT          11
+#define  DF_FLGSP7          12
+#define  DF_FLGSP6          13
+#define  DF_FLGSP5          14
+#define  DF_FLGSP4          15
+#define  DF_FLGSP3          16
+#define  DF_FLGSP2          17
+#define  DF_FLGSP1          18
+#define  DF_FLGSP0          19
+#define  DF_FLGSG13         20
+#define  DF_FLGSG12         21
+#define  DF_FLGSG11         22
+#define  DF_FLGSG10         23
+#define  DF_FLGSG9          24
+#define  DF_FLGSG8          25
+#define  DF_FLGSG7          26
+#define  DF_FLGSG6          27
+#define  DF_FLGSG5          28
+#define  DF_FLGSG4          29
+#define  DF_FLGSG3          30
+#define  DF_FLGSG2          31
+#define  DF_FLGSG1          32
+#define  DF_FLGSG0          33
+
+//Analog
+#define  DF_AN_HIMP          1
+#define  DF_AN_2MA           2
+#define  DF_AN_16MA          3
+
+#define  DF_CH_SG0           1
+#define  DF_CH_SG1           2
+#define  DF_CH_SG2           3
+#define  DF_CH_SG3           4
+#define  DF_CH_SG4           5
+#define  DF_CH_SG5           6
+#define  DF_CH_SG6           7
+#define  DF_CH_SG7           8
+#define  DF_CH_SG8           9
+#define  DF_CH_SG9           10
+#define  DF_CH_SG10          11
+#define  DF_CH_SG11          12
+#define  DF_CH_SG12          13
+#define  DF_CH_SG13          14
+#define  DF_CH_SP0           15
+#define  DF_CH_SP1           16
+#define  DF_CH_SP2           17
+#define  DF_CH_SP3           18
+#define  DF_CH_SP4           19
+#define  DF_CH_SP5           20
+#define  DF_CH_SP6           21
+#define  DF_CH_SP7           22 
+//*****************************************************************************
+//ⲿȫֺ
+//*****************************************************************************
+void SwStaSample(UnSwSample *ptmp);
+void InitSW(void);
+void LedLight(UnSwOut *tmpUn);
+//void Swtest2(void);
+//ubyte Mc33993AnalogChSel(ubyte NumMc,ubyte Mode,ubyte Channal);
+#endif
\ No newline at end of file
diff --git a/T2.C b/T2.C
new file mode 100644
index 0000000..c9fc744
--- /dev/null
+++ b/T2.C
@@ -0,0 +1,175 @@
+//****************************************************************************
+// @Module        Timer 2
+// @Filename      T2.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the T2 module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:31
+//
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (T2_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void T2_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the Timer 2 function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//                
+//                The following SFRs and SFR fields will be initialized:
+//                T2_RC2H/RC2L     - reload/capture timer 2 register
+//                T2_T2H/T2L     -  timer 2 register
+//                ET2           - timer 2 interrupt enable
+//                T2_T2MOD         - timer 2 mode register
+//                CP/RL2        - Capture/Reload select
+//                EXEN2         - External enable control
+//                TR2           - Timer2 run control
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Init,1)
+
+// USER CODE END
+
+void T2_vInit(void)
+{
+  // USER CODE BEGIN (T2_Init,2)
+
+  // USER CODE END
+
+  //   -----------------------------------------------------------------------
+  //   Operating Mode
+  //   -----------------------------------------------------------------------
+
+  ///  16-bit timer function with automatic reload when timer 2 overflows
+  ///  the timer 2 resolution is 1 ?s
+  ///  the timer 2 overflow is 1000.000 ?s
+  ///  timer 2 interrupt: enabled
+  ///  timer 2 will be started
+
+  //   -----------------------------------------------------------------------
+  //   Register Initialization
+  //   -----------------------------------------------------------------------
+
+  T2_T2L        =  0x30;         // load timer 2  register,   low byte
+
+  T2_T2H        =  0xF8;         // load timer 2  register,   high byte
+
+  T2_RC2L       =  0x30;         // load timer 2 reload/capture register,   
+                                 // low byte
+  T2_RC2H       =  0xF8;         // load timer 2 reload/capture register,   
+                                 // high byte
+  T2_T2MOD      =  0x00;         // load timer 2 mode register
+
+  ///  timer 2 Interrupt enable bit is set in SHINT_vInit() function
+
+  // USER CODE BEGIN (T2_Init,3)
+
+  // USER CODE END
+
+  TR2 = 1; //   start timer
+
+} //  End of function T2_vInit
+
+
+// USER CODE BEGIN (T2_General,10)
+
+// USER CODE END
+
diff --git a/T2.H b/T2.H
new file mode 100644
index 0000000..a55512d
--- /dev/null
+++ b/T2.H
@@ -0,0 +1,104 @@
+//****************************************************************************
+// @Module        Timer 2
+// @Filename      T2.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the T2 module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:31
+//
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _T2_H_
+#define _T2_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,4)
+
+// USER CODE END
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void T2_vInit(void);
+
+// USER CODE BEGIN (T2_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+
+//   Shared interrupt vector definitions are defined in SHARED_INT.H
+
+// USER CODE BEGIN (T2_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _T2_H_
diff --git a/UART.C b/UART.C
new file mode 100644
index 0000000..9d28748
--- /dev/null
+++ b/UART.C
@@ -0,0 +1,350 @@
+//****************************************************************************
+// @Module        UART (Serial Interface)
+// @Filename      UART.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the UART module.
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12 19:56:03
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (UART_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void UART_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the UART function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//                
+//                The following SFR fields will be initialized:
+//                - register SCON
+//                - bits SMOD and ES
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Init,1)
+
+// USER CODE END
+
+void UART_vInit(void)
+{
+  // USER CODE BEGIN (UART_Init,2)
+
+  // USER CODE END
+
+  ///  -----------------------------------------------------------------------
+  ///  UART settings
+  ///  -----------------------------------------------------------------------
+  ///  Pin TXD_1 (P0.2) is selected for transmission
+  ///  Pin RXD_1 (P0.1) is selected for reception
+  ///  Receiver enabled
+  ///  Mode 1: 8-bit data, 1 start bit, 1 stop bit, variable baud rate
+  ///  BRG is selected for baudrate generation
+
+  SFR_PAGE(_pp2, noSST);         // switch to page 2 without saving
+  P0_ALTSEL0   &= ~(ubyte)0x04;  // configure alternate function register 0
+  P0_ALTSEL1   |=  (ubyte)0x04;  // configure alternate function register 1
+  SFR_PAGE(_pp0, noSST);         // switch to page 0 without saving
+  P0_DIR       |=  (ubyte)0x04;  // set output direction
+
+
+  MODPISEL     |=  (ubyte)0x01;  // configure peripheral input select register
+  BCON          =  0x00;         // reset baudrate timer/reload register
+  SCON          =  0x50;         // load serial channel control register
+
+  ///  -----------------------------------------------------------------------
+  ///  Baudrate generator settings
+  ///  -----------------------------------------------------------------------
+  ///  input clock = fPCLK
+  ///  Fractional divider is disabled
+  ///  baudrate = 100.0000 kbaud
+
+  BG            =  0x0E;         // load baudrate timer/reload register
+  BCON         |=  0x01;         // load baud rate control register
+
+
+  // USER CODE BEGIN (UART_Init,3)
+
+  // USER CODE END
+
+  ///  UART interrupt enabled
+  ES = 1;
+
+} //  End of function UART_vInit
+
+
+//****************************************************************************
+// @Function      void UART_viIsr(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the service routine for the UART interrupt. It is 
+//                called after each transmission (flag TI set) or reception 
+//                (flag RI set) of a data unit.
+//                Please note that you have to add application specific code 
+//                to this function.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+//   You have two choices for interrupt type select in Project Settings Page 
+//   under Global Settings Section.
+//   If you select CHOICE 1 then ISR will be generated with push and pop.
+//   If you select CHOICE 2 then ISR will be generated without push and pop.
+//   Default choice is CHOICE 2.
+//   Current selection is CHOICE 2 
+
+// USER CODE BEGIN (UART_Isr,1)
+uint16_t char_data[25] = {0};
+// USER CODE END
+
+void UART_viIsr(void) interrupt UARTINT
+{
+
+    // USER CODE BEGIN (UART_Isr,2)
+//	static uint8_t i = 0;
+	static uint8_t cnt_sbus = 0;
+	static uint8_t state = 0;
+	static uint8_t receive = 0;
+	static uint8_t sbus_buff[25];
+	SBusData *tmp_sbus_data;
+    // USER CODE END
+  SFR_PAGE(_su0, SST0);          // switch to page 0
+  if (TI)
+  {
+    // USER CODE BEGIN (UART_Isr,3)
+
+       TI = 0;
+
+    // USER CODE END
+  }
+  if (RI)
+  {
+    // USER CODE BEGIN (UART_Isr,4)
+       RI = 0;
+		
+      char_data[0] = (ubyte)SBUF;		
+//		UART_vSendData8(char_data[0]);
+		
+			switch(state)
+			{				
+				case 0:
+					if(0x0f == char_data[0])
+					{
+						receive = 0;
+						cnt_sbus = 0;
+						sbus_buff[cnt_sbus] = char_data[0];
+						cnt_sbus++;
+						state = 1;
+					}
+					else
+					{
+						state = 0;
+					}
+					break;
+				case 1:
+					if(cnt_sbus >= 24)
+					{
+						if(0x0 == char_data[0])
+						{
+							cnt_sbus = 0;
+							receive = 0;
+							sbus_buff[cnt_sbus] = char_data[0];
+							state = 0;
+							tmp_sbus_data = parseSBusData(sbus_buff);
+						}
+					}
+					else if( (0x0f == char_data[0]) && (10 != cnt_sbus) )//Ϊ10ֽΪ0x0FģԲ0
+					{
+						receive = 0;
+						cnt_sbus = 0;
+						sbus_buff[cnt_sbus] = char_data[0];
+						cnt_sbus++;
+						state = 1;
+					}
+					else
+					{
+						sbus_buff[cnt_sbus] = char_data[0];
+						cnt_sbus ++;
+						state = 1;
+					}
+					break;
+				default:break;
+			}
+		
+    // USER CODE END
+  }
+
+    // USER CODE BEGIN (UART_Isr,5)
+
+    // USER CODE END
+  SFR_PAGE(_su0, RST0);          // restore the old page
+} //  End of function UART_viIsr
+
+
+//****************************************************************************
+// @Function      ubyte UART_ubGetData8(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function returns the last received 8-bit data unit. 
+//                Interrupt flag RI will be cleared.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   received data unit
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+//ubyte UART_ubGetData8(void)
+//{
+//  //   Clear the receiver interrupt flag
+//  RI = 0;
+
+//  //   Return the received data byte
+//  return(SBUF);
+
+//} //  End of function UART_ubGetData8
+
+
+//****************************************************************************
+// @Function      void UART_vSendData8(ubyte ubData) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function transmits an 8-bit data unit. At first 
+//                interrupt flag TI is cleared, then buffer SBUF is written.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ubData: 
+//                data to be transmitted
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+//void UART_vSendData8(ubyte ubData)
+//{
+//  //   Clear the transmitter interrupt flag
+//  TI = 0;
+
+//  //   Write the transmit data byte, this initiates the transmission.
+//  SBUF = ubData;
+//} //  End of function UART_vSendData8
+
+
+// USER CODE BEGIN (UART_General,10)
+
+// USER CODE END
+
diff --git a/UART.H b/UART.H
new file mode 100644
index 0000000..22efa1c
--- /dev/null
+++ b/UART.H
@@ -0,0 +1,127 @@
+//****************************************************************************
+// @Module        UART (Serial Interface)
+// @Filename      UART.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the UART module.
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12 19:56:03
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _UART_H_
+#define _UART_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void UART_vInit(void);
+ubyte UART_ubGetData8(void);
+void UART_vSendData8(ubyte ubData);
+
+// USER CODE BEGIN (UART_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         UART_vRxEnable() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro releases the receive function of the UART by 
+//                setting bit REN.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+#define UART_vRxEnable() REN = 1
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+#define UARTINT  4
+
+// USER CODE BEGIN (UART_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _UART_H_
diff --git a/UART1.C b/UART1.C
new file mode 100644
index 0000000..416fc49
--- /dev/null
+++ b/UART1.C
@@ -0,0 +1,261 @@
+//****************************************************************************
+// @Module        UART1 (Serial Interface)
+// @Filename      UART1.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the UART1 module.
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31 19:17:02
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (UART1_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void UART1_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the UART1 function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//                
+//                The following SFR fields will be initialized:
+//                - register SCON
+//                - bits SMOD and EX2
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Init,1)
+
+// USER CODE END
+
+void UART1_vInit(void)
+{
+  // USER CODE BEGIN (UART1_Init,2)
+
+  // USER CODE END
+
+  ///  -----------------------------------------------------------------------
+  ///  UART1 settings
+  ///  -----------------------------------------------------------------------
+  ///  Pin TXD1_1 (P3.1) is selected for transmission
+  ///  Pin RXD1_1 (P3.2) is selected for reception
+  ///  Receiver enabled
+  ///  UART1 interrupt is enabled
+  ///  Ignore Normal divider overflow interrupt
+  ///  Mode 1: 8-bit data, 1 start bit, 1 stop bit, variable baud rate
+  ///  Receiver interrupt flag RI_1 will only be activated if a valid stop 
+  ///  bit was received
+  ///  BRG is selected for baudrate generation
+
+  SFR_PAGE(_pp2, noSST);         // switch to page 2 without saving
+  P3_ALTSEL0   |=  (ubyte)0x02;  // configure alternate function register 0
+  P3_ALTSEL1   |=  (ubyte)0x02;  // configure alternate function register 1
+  SFR_PAGE(_pp0, noSST);         // switch to page 0 without saving
+  P3_DIR       |=  (ubyte)0x02;  // set output direction
+
+
+  SFR_PAGE(_su3, noSST);         // switch to page 3 without saving
+  MODPISEL1    |=  (ubyte)0x08;  // configure peripheral input select register
+  SFR_PAGE(_su0, noSST);         // switch to page 0 without saving
+
+  SET_RMAP();                   
+
+  UART1_BCON    =  0x00;         // reset baudrate timer/reload register
+  UART1_SCON    =  0x50;         // load serial channel control register
+
+  ///  -----------------------------------------------------------------------
+  ///  Baudrate generator settings
+  ///  -----------------------------------------------------------------------
+  ///  input clock = fPCLK
+  ///  Fractional divider is disabled
+  ///  baudrate = 9.6154 kbaud
+
+  UART1_BG      =  0x9B;         // load baudrate timer/reload register
+  UART1_BCON   |=  0x01;         // load baud rate control register
+
+
+  RESET_RMAP();                 
+
+
+  // USER CODE BEGIN (UART1_Init,3)
+
+  // USER CODE END
+
+} //  End of function UART1_vInit
+
+
+//****************************************************************************
+// @Function      ubyte UART1_ubGetData8(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function returns the last received 8-bit data unit. 
+//                Interrupt flag RI_1 will be cleared.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   received data unit
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+ubyte UART1_ubGetData8(void)
+{
+
+  ubyte ubData;
+
+  _push_(SYSCON0);               // push the current RMAP
+  SET_RMAP();                   
+
+  //   Clear the receiver interrupt flag
+  UART1_SCON   &= ~(ubyte)0x01; 
+
+
+  //   Read the received data bits 0..7
+  ubData = (ubyte)UART1_SBUF;
+
+
+  _pop_(SYSCON0);                // restore the old RMAP
+
+  //   Return the received data byte
+  return(ubData);
+
+} //  End of function UART1_ubGetData8
+//****************************************************************************
+// @Function      void UART1_vSendData8(ubyte ubData) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function transmits an 8-bit data unit. At first 
+//                interrupt flag TI_1 is cleared, then buffer SBUF is written.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ubData: 
+//                data to be transmitted
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+void UART1_vSendData8(ubyte ubData)
+{
+
+  _push_(SYSCON0);               // push the current RMAP
+  SET_RMAP();                   
+
+  //   Clear the transmitter interrupt flag
+  UART1_SCON   &= ~(ubyte)0x02; 
+
+  //   Write the transmit data byte, this initiates the transmission.
+  UART1_SBUF = ubData;
+
+  _pop_(SYSCON0);                // restore the old RMAP
+
+} //  End of function UART1_vSendData8
+
+
+// USER CODE BEGIN (UART1_General,10)
+
+// USER CODE END
+
diff --git a/UART1.H b/UART1.H
new file mode 100644
index 0000000..7fa5c4f
--- /dev/null
+++ b/UART1.H
@@ -0,0 +1,153 @@
+//****************************************************************************
+// @Module        UART1 (Serial Interface)
+// @Filename      UART1.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the UART1 module.
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31 19:17:02
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _UART1_H_
+#define _UART1_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void UART1_vInit(void);
+ubyte UART1_ubGetData8(void);
+void UART1_vSendData8(ubyte ubData);
+
+// USER CODE BEGIN (UART1_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         UART1_vRxEnable() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro releases the receive function of the UART1 by 
+//                setting bit REN_1.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+//   RMAP should be set before calling this macro.
+
+#define UART1_vRxEnable() REN_1 = 1
+
+
+//****************************************************************************
+// @Macro         UART1_vRxDisable() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro disables the receive function of the UART1 by 
+//                clearing bit REN_1.
+//                Note: Any data that is currently being received is received 
+//                to completion, including the setting of interrupt flag RI_1.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+//   RMAP should be set before calling this macro.
+
+#define UART1_vRxDisable() REN_1 = 0
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+
+// USER CODE BEGIN (UART1_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _UART1_H_
diff --git a/User.c b/User.c
new file mode 100644
index 0000000..befaf01
--- /dev/null
+++ b/User.c
@@ -0,0 +1,465 @@
+#include "MAIN.H"
+#include "temperature.H"
+#include 
+
+
+//RAM־
+ubyte RestartDataFlg1    _at_ 0xF5E7;
+ubyte RestartDataFlg2    _at_ 0xF600;
+//KGF
+uword RestartDataKGF     _at_ 0xF5E5;
+
+//canϢ
+UnInfCan    UnInfCan_1   _at_ 0xF5E8;
+UnSwOut	    UnSwOut_1    = {0};
+
+//CAN
+uword             CntCan_1    = 0;
+bit               FlgCan_1    = 0;
+//һβɼЧָʾ
+bit FlgOneTime = 0;
+
+uword RgCanPerid = 1000;
+
+//UnTimeOutput                 sleeptime = {0};
+//UnTimeOutput                 waketime = {0};
+//UnTimeOutput                 currenttime = {0};
+//UnTimeOutput                 un_time_output1 = {0};//趨ʱ
+//UnInfCanKGFOutput            un_inf_can_kgf_output2 = {0};//kgf
+//UnTimeOutput                 waketimelast = {0};
+//UnTimeOutput                 wake_time_10min = {0};
+//SystemState                  sleepstate = STATE_INIT;
+//PWM 20181227
+ubyte PwmH[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+
+ubyte powerstate = 0;//Դ״̬
+
+ubyte vcu_can_cnt = 0;  // ֡ۼ
+ubyte vcu_can_last = 0; // ֡ۼȥֵ
+bool flg_wake_ecu = 0;   //ѱ־
+//-----------------------------------------------------------------------
+//RTCʱ
+//-----------------------------------------------------------------------
+void RTCProcess(void)
+{
+//************************************************************************
+//////CAN
+	if(FlgCan_1){CntCan_1++;if(CntCan_1 >= RgCanPerid){FlgCan_1=0; CntCan_1=0;}}else{CntCan_1=0;}
+
+//************************************************************************
+}
+
+
+//can
+void CanErrorProcess(void)
+{
+	ubyte ubNSRL;
+	ubyte ubNSRH;
+	ubyte ubResetLEC = 0x3F;
+//-------------------------------------------
+	EA            =  0;
+
+	CAN_pushAMRegs();              // push the CAN Access Mediator Registers
+	SFR_PAGE(_su0, SST0);          // switch to page 0
+
+	CAN_vWriteCANAddress(CAN_NSR0);
+	CAN_vReadEN();
+	ubNSRL = CAN_DATA0;
+	ubNSRH = CAN_DATA1;
+	if (ubNSRL & 0x20)      // if ALERT
+	{
+		CAN_vInit();
+	}
+	if (ubNSRL & 0x07)  // if LEC
+	{
+		ubResetLEC = 0x38;
+	}
+	//// Reset LEC, TXOK, RXOK, ALERT, EWRN, BOFF, LLE, LOE (if set)
+	CAN_vWriteCANAddress(CAN_NSR0); // Addressing CAN_NSR0
+	CAN_DATA0   =  ~(ubNSRL & ubResetLEC);       // load CAN_NSR0 status register[7-0]
+	CAN_DATA1   =  ~(ubNSRH);       // load CAN_NSR0 status register[15-8]
+	CAN_vWriteEN(D0_VALID+D1_VALID);  // Data0 and Data1 are Valid for
+
+	SFR_PAGE(_su0, RST0);          // restore the old SCU page
+	CAN_popAMRegs();               // restore the CAN Access Mediator Registers
+
+	EA            =  1;
+}
+
+//PWM	20181227
+/*
+ubyte *pStt,	״̬
+bit Cmd,			״̬룬1PwmHֵ00
+bit Out,			״̬
+ubyte *pCnt,	ʱ
+ubyte *pPwmH	״̬PWMĸߵƽʱ
+*/ 
+bit funcPwmOut(ubyte *pStt,bit Cmd,ubyte *pCnt,ubyte *pPwmH)
+{
+ubyte PwmL = 0; 
+bit Out = 0;
+//------------------------------------------------------------------------------------------------
+	if((*pPwmH) > dfPwmH)(*pPwmH) = dfPwmH;	 //ֵ
+	PwmL = dfPwmH - (*pPwmH);//PWM͵ƽ
+
+	if((1 == Cmd) )
+	{
+		if(0 == (*pPwmH))	 //ߵƽΪ0ʾPWMЧCmdƣCmdΪ11CmdΪ00
+		{
+			Out = 1;
+			(*pStt) = 0;	
+		}
+		else
+		{
+			switch((*pStt))
+			{
+				case 0:
+					(*pCnt) = 0;
+					(*pStt) = 1;
+					Out = 1;
+				break;
+				case 1:
+					if((*pCnt) >= (*pPwmH))
+					{
+						(*pCnt) = 0;
+						(*pStt) = 2;
+						Out = 0;
+					}
+					else
+					{
+					 	(*pCnt)++;
+						(*pStt) = 1;
+						Out = 1;
+					}
+				break;
+				case 2:
+					if((*pCnt) >= PwmL)
+					{
+						(*pCnt) = 0;
+						(*pStt) = 1;
+						Out = 1;
+					}
+					else
+					{
+					 	(*pCnt)++;
+						(*pStt) = 2;
+						Out = 0;
+					}
+				break;
+		//-----------------------------------------------------
+				default:;
+			}//switch
+		}//else
+	}//if
+	else 
+	{
+		Out = 0;		
+		(*pStt) = 0;
+	}
+	return Out;
+}
+
+//ݽյCANӦ̣ţָʾơ
+void LedDr(void)
+{
+static ubyte RgSTT[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+static ubyte CntTime[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  ubyte i = 0;
+//------------------------------------------------------------------------------------------------
+
+//	dfOut_01 = funcPwmOut(&RgSTT[0 ],dfCmd_01,&CntTime[0 ],&PwmH[0 ]);	
+//	dfOut_02 = funcPwmOut(&RgSTT[1 ],dfCmd_02,&CntTime[1 ],&PwmH[1 ]);	
+//	dfOut_03 = funcPwmOut(&RgSTT[2 ],dfCmd_03,&CntTime[2 ],&PwmH[2 ]);	
+//	dfOut_04 = funcPwmOut(&RgSTT[3 ],dfCmd_04,&CntTime[3 ],&PwmH[3 ]);	
+//	dfOut_05 = funcPwmOut(&RgSTT[4 ],dfCmd_05,&CntTime[4 ],&PwmH[4 ]);	
+//	dfOut_06 = funcPwmOut(&RgSTT[5 ],dfCmd_06,&CntTime[5 ],&PwmH[5 ]);	
+//	dfOut_07 = funcPwmOut(&RgSTT[6 ],dfCmd_07,&CntTime[6 ],&PwmH[6 ]);	
+//	dfOut_08 = funcPwmOut(&RgSTT[7 ],dfCmd_08,&CntTime[7 ],&PwmH[7 ]);	
+//	dfOut_09 = funcPwmOut(&RgSTT[8 ],dfCmd_09,&CntTime[8 ],&PwmH[8 ]);	
+//	dfOut_10 = funcPwmOut(&RgSTT[9 ],dfCmd_10,&CntTime[9 ],&PwmH[9 ]);	
+//	dfOut_11 = funcPwmOut(&RgSTT[10],dfCmd_11,&CntTime[10],&PwmH[10]);	
+//	dfOut_12 = funcPwmOut(&RgSTT[11],dfCmd_12,&CntTime[11],&PwmH[11]);	
+//	dfOut_13 = funcPwmOut(&RgSTT[12],dfCmd_13,&CntTime[12],&PwmH[12]);	
+//	dfOut_14 = funcPwmOut(&RgSTT[13],dfCmd_14,&CntTime[13],&PwmH[13]);	
+//	dfOut_15 = funcPwmOut(&RgSTT[14],dfCmd_15,&CntTime[14],&PwmH[14]);	
+//	dfOut_16 = funcPwmOut(&RgSTT[15],dfCmd_16,&CntTime[15],&PwmH[15]);	
+
+	i = dfOut_02;										  //20210906IO״̬ KGFָʾ˸
+  RestartDataKGF = dfOut_01;
+	RestartDataKGF = RestartDataKGF + (i<<1);  
+	i = dfOut_03;
+	RestartDataKGF = RestartDataKGF + (i<<2); 
+	i = dfOut_04;
+	RestartDataKGF = RestartDataKGF + (i<<3);
+	i = dfOut_05;
+	RestartDataKGF = RestartDataKGF + (i<<4); 
+	i = dfOut_06;
+	RestartDataKGF = RestartDataKGF + (i<<5);
+	i = dfOut_07;
+	RestartDataKGF = RestartDataKGF + (i<<6); 
+	i = dfOut_08;
+	RestartDataKGF = RestartDataKGF + (i<<7);
+	i = dfOut_09;
+	RestartDataKGF = RestartDataKGF + (i<<8); 
+	i = dfOut_10;
+	RestartDataKGF = RestartDataKGF + (i<<9);
+	i = dfOut_11;
+	RestartDataKGF = RestartDataKGF + (i<<10); 
+	i = dfOut_12;
+	RestartDataKGF = RestartDataKGF + (i<<11);
+	i = dfOut_13;
+	RestartDataKGF = RestartDataKGF + (i<<12); 
+	i = dfOut_14;
+	RestartDataKGF = RestartDataKGF + (i<<13);
+	i = dfOut_15;
+	RestartDataKGF = RestartDataKGF + (i<<14); 
+	i = dfOut_16;
+	RestartDataKGF = RestartDataKGF + (i<<15);
+}
+void CanTransmit(void)
+{
+//	ulong i;
+//-----------------	--------
+	CAN_waitTransmit(DF_SwTx);//ǰȴһ֡ϣᶪ֡
+//	Password();
+
+	CAN_vLoadData(DF_SwTx, (ulong *)(&UnInfCan_1.ArrData.Arr[0][0])); // װ
+	CAN_vTransmit(DF_SwTx);
+}
+
+
+void canSendTo(ubyte index,ubyte *buf)
+{
+  ubyte CanTransmitbuf[8] = {0,0,0,0,0,0,0,0};
+//-----------------	--------
+	CanTransmitbuf[2] = buf[0];
+	CanTransmitbuf[3] = buf[1];	
+	CanTransmitbuf[0] = buf[2];	
+	CanTransmitbuf[1] = buf[3];	
+	CanTransmitbuf[6] = buf[4];	
+	CanTransmitbuf[7] = buf[5];	
+	CanTransmitbuf[4] = buf[6];	
+	CanTransmitbuf[5] = buf[7];		
+
+	CAN_waitTransmit(index);//ǰȴһ֡ϣᶪ֡
+	CAN_vLoadData(index, (ulong *)CanTransmitbuf);// װ
+	CAN_vTransmit(index);
+}
+
+//CANһ֡
+void CanTX(void)
+{
+//-----------------------------------
+	if(1 == SwOut09)UnInfCan_1.ArrData.Arr[0][3] |= 0x01;else UnInfCan_1.ArrData.Arr[0][3]  &= (~0x01);		//KGF1		//20200303޸Ϊյһ£յʱΪһ
+	if(1 == SwOut10)UnInfCan_1.ArrData.Arr[0][3] |= 0x02;else UnInfCan_1.ArrData.Arr[0][3]  &= (~0x02);		//KGF2		
+	if(1 == SwOut04)UnInfCan_1.ArrData.Arr[0][3] |= 0x04;else UnInfCan_1.ArrData.Arr[0][3]  &= (~0x04);		//KGF3
+	if(1 == SwOut03)UnInfCan_1.ArrData.Arr[0][3] |= 0x08;else UnInfCan_1.ArrData.Arr[0][3]  &= (~0x08);		//KGF4
+	if(1 == SwOut06)UnInfCan_1.ArrData.Arr[0][3] |= 0x10;else UnInfCan_1.ArrData.Arr[0][3]  &= (~0x10);		//KGF5
+	if(1 == SwOut05)UnInfCan_1.ArrData.Arr[0][3] |= 0x20;else UnInfCan_1.ArrData.Arr[0][3]  &= (~0x20);		//KGF6
+	if(1 == SwOut15)UnInfCan_1.ArrData.Arr[0][3] |= 0x40;else UnInfCan_1.ArrData.Arr[0][3]  &= (~0x40);		//KGF7
+	if(1 == SwOut16)UnInfCan_1.ArrData.Arr[0][3] |= 0x80;else UnInfCan_1.ArrData.Arr[0][3]  &= (~0x80);		//KGF8
+	if(1 == SwOut13)UnInfCan_1.ArrData.Arr[0][2] |= 0x01;else UnInfCan_1.ArrData.Arr[0][2]  &= (~0x01);		//KGF9
+	if(1 == SwOut14)UnInfCan_1.ArrData.Arr[0][2] |= 0x02;else UnInfCan_1.ArrData.Arr[0][2]  &= (~0x02);		//KGF10
+	if(1 == SwOut08)UnInfCan_1.ArrData.Arr[0][2] |= 0x04;else UnInfCan_1.ArrData.Arr[0][2]  &= (~0x04);		//KGF11
+	if(1 == SwOut07)UnInfCan_1.ArrData.Arr[0][2] |= 0x08;else UnInfCan_1.ArrData.Arr[0][2]  &= (~0x08);		//KGF12
+	if(1 == SwOut02)UnInfCan_1.ArrData.Arr[0][2] |= 0x10;else UnInfCan_1.ArrData.Arr[0][2]  &= (~0x10);		//KGF13
+	if(1 == SwOut01)UnInfCan_1.ArrData.Arr[0][2] |= 0x20;else UnInfCan_1.ArrData.Arr[0][2]  &= (~0x20);		//KGF14
+	if(1 == SwOut11)UnInfCan_1.ArrData.Arr[0][2] |= 0x40;else UnInfCan_1.ArrData.Arr[0][2]  &= (~0x40);		//KGF15
+	if(1 == SwOut12)UnInfCan_1.ArrData.Arr[0][2] |= 0x80;else UnInfCan_1.ArrData.Arr[0][2]  &= (~0x80);		//KGF16
+
+	if(1 == SwIn01 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x01);else UnInfCan_1.ArrData.Arr[0][1] |= 0x01;		//Dia01  20200225޸Ϊ0ݱΪ1,1ݱΪ0CPU㴦
+	if(1 == SwIn02 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x02);else UnInfCan_1.ArrData.Arr[0][1] |= 0x02;		//Dia02
+	if(1 == SwIn03 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x04);else UnInfCan_1.ArrData.Arr[0][1] |= 0x04;		//Dia03
+	if(1 == SwIn04 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x08);else UnInfCan_1.ArrData.Arr[0][1] |= 0x08;		//Dia04
+	if(1 == SwIn05 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x10);else UnInfCan_1.ArrData.Arr[0][1] |= 0x10;		//Dia05
+	if(1 == SwIn06 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x20);else UnInfCan_1.ArrData.Arr[0][1] |= 0x20;		//Dia06
+	if(1 == SwIn07 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x40);else UnInfCan_1.ArrData.Arr[0][1] |= 0x40;		//Dia07	  
+	if(1 == SwIn08 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x80);else UnInfCan_1.ArrData.Arr[0][1] |= 0x80;		//Dia08			
+                               
+	UnInfCan_1.ArrData.Arr[0][0] = 0;
+	UnInfCan_1.ArrData.Arr[0][7] = 0;
+	UnInfCan_1.ArrData.Arr[0][6] = RomNum;
+	UnInfCan_1.ArrData.Arr[0][5] = (ubyte)(UnSwSample_1.bit_data.temperature[0]);
+	UnInfCan_1.ArrData.Arr[0][4] = (ubyte)(UnSwSample_1.bit_data.temperature[0]>>8);
+
+	CanTransmit();
+}
+
+//------------------------------------------------------------------
+// ״̬¶ȿ״̬
+// ˵
+// current_state - ǰ״ָ̬루豣ڣ
+// current_temp  - ǰ¶ֵͨжϸ[6](@ref)
+//------------------------------------------------------------------
+void tempStateMachine(SystemState *current_state, float current_temp) 
+{
+    switch (*current_state) 
+    {
+        // ʼ״̬ҳ5ʼ߼ǿ
+        case STATE_INIT_CHECK:
+            if(current_temp < INIT_THRESHOLD) 
+            {
+                *current_state = STATE_INIT_HEATING;
+						   	HERTER_CMD(1);
+							  PC_CMD(0); 
+            }
+            else 
+            {
+                // ǵ»ֱӽȴ״̬
+                *current_state = STATE_COOLING;  
+						   	HERTER_CMD(0);
+							  PC_CMD(1); 
+            }
+            break;
+
+        case STATE_INIT_HEATING://20250330ʼ״ֻ̬е¶ȴ趨Żᣬ״̬δȵ趨¶Ȼرռ״̬ᡣ
+            if(current_temp > (HEATING_STOP  + TEMP_HYSTERESIS)) 
+            {
+                 *current_state = STATE_COOLING;
+						   	HERTER_CMD(0);
+							  PC_CMD(1); 
+            }
+            else 
+            {
+                // ǵ»ֱӽȴ״̬
+                *current_state = STATE_INIT_HEATING;  
+						   	HERTER_CMD(1);
+							  PC_CMD(0); 
+            }
+            break;						
+						
+						
+        // ״̬ҳ3Ƚ׶Ż
+        case STATE_HEATING:
+            if(current_temp > (HEATING_STOP  + TEMP_HYSTERESIS)) 
+            {
+                *current_state = STATE_COOLING;
+						   	HERTER_CMD(0);
+							  PC_CMD(1); 
+            }
+            else 
+            {
+						   	HERTER_CMD(1);
+							  PC_CMD(1); 
+            }
+            break;
+
+        // ȴ״̬ҳ6״̬лĽ
+        case STATE_COOLING:
+            if(current_temp < (COOLING_RESTART - TEMP_HYSTERESIS)) 
+            {
+                *current_state = STATE_HEATING;
+						   	HERTER_CMD(1);
+							  PC_CMD(1); 
+            }
+            else 
+            {
+						   	HERTER_CMD(0);
+							  PC_CMD(1); 
+            }
+            break;
+
+        default:
+            // 쳣ҳ1ȫ淶
+            *current_state = STATE_INIT_CHECK;
+            break;
+    }
+}
+
+//CANͽ
+void CanRXTX(void)
+{
+	stCAN_SWObj StrCanRx = {0};
+	uword tmp = 0;
+	ubyte i = 0,j = 0;
+	static SystemState temp_state = STATE_INIT_CHECK;
+	float current_temp = 0.0f;
+//------------------------------------
+	if(CAN_ubNewData(DF_SwRx))
+	{
+		CAN_vGetMsgObj(DF_SwRx, &StrCanRx);
+
+		UnInfCan_1.ArrData.ArrRX[0][3] = StrCanRx.ulDATAL.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[0][2] = StrCanRx.ulDATAL.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[0][1] = StrCanRx.ulDATAL.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[0][0] = StrCanRx.ulDATAL.ubDB[3];
+		UnInfCan_1.ArrData.ArrRX[0][7] = StrCanRx.ulDATAH.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[0][6] = StrCanRx.ulDATAH.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[0][5] = StrCanRx.ulDATAH.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[0][4] = StrCanRx.ulDATAH.ubDB[3];
+
+		CAN_vReleaseObj(DF_SwRx);
+
+		//CAN	50-5000ms
+		tmp = (uword)UnInfCan_1.ArrData.ArrRX[0][6];
+		tmp = (tmp << 8);
+		tmp |= ((uword)UnInfCan_1.ArrData.ArrRX[0][7]);
+		if(tmp >= 50)RgCanPerid = tmp;
+		if(tmp >= 5000)RgCanPerid = 5000;
+
+//		UnInfCan_1.ArrData.Arr[0][3] = UnInfCan_1.ArrData.ArrRX[0][0];
+//		UnInfCan_1.ArrData.Arr[0][2] = UnInfCan_1.ArrData.ArrRX[0][1];
+//		UnInfCan_1.ArrData.Arr[0][1] = UnInfCan_1.ArrData.ArrRX[0][2]; 20200225עͲ
+//		UnInfCan_1.ArrData.Arr[0][0] = UnInfCan_1.ArrData.ArrRX[0][3];
+//		UnInfCan_1.ArrData.Arr[0][7] = UnInfCan_1.ArrData.ArrRX[0][4];
+//		UnInfCan_1.ArrData.Arr[0][6] = UnInfCan_1.ArrData.ArrRX[0][5];
+//		UnInfCan_1.ArrData.Arr[0][5] = (ubyte)(RgCanPerid>>8);
+//		UnInfCan_1.ArrData.Arr[0][4] = (ubyte)(RgCanPerid);
+//		CanTransmit();	 20200730͸
+	}
+
+	if(CAN_ubNewData(DF_SwRxPwm))
+	{
+		CAN_vGetMsgObj(DF_SwRxPwm, &StrCanRx);
+
+		UnInfCan_1.ArrData.ArrRX[1][2] = StrCanRx.ulDATAL.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[1][3] = StrCanRx.ulDATAL.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[1][0] = StrCanRx.ulDATAL.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[1][1] = StrCanRx.ulDATAL.ubDB[3];
+		UnInfCan_1.ArrData.ArrRX[1][6] = StrCanRx.ulDATAH.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[1][7] = StrCanRx.ulDATAH.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[1][4] = StrCanRx.ulDATAH.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[1][5] = StrCanRx.ulDATAH.ubDB[3];
+
+		CAN_vReleaseObj(DF_SwRxPwm);
+		//յݱ浽PWMݽṹ20181227
+		PwmH[0 ] = (ubyte)UnInfCan_1.BitData.Pwm_01;
+		PwmH[1 ] = (ubyte)UnInfCan_1.BitData.Pwm_02;
+		PwmH[2 ] = (ubyte)UnInfCan_1.BitData.Pwm_03;
+		PwmH[3 ] = (ubyte)UnInfCan_1.BitData.Pwm_04;
+		PwmH[4 ] = (ubyte)UnInfCan_1.BitData.Pwm_05;
+		PwmH[5 ] = (ubyte)UnInfCan_1.BitData.Pwm_06;
+		PwmH[6 ] = (ubyte)UnInfCan_1.BitData.Pwm_07;
+		PwmH[7 ] = (ubyte)UnInfCan_1.BitData.Pwm_08;
+		PwmH[8 ] = (ubyte)UnInfCan_1.BitData.Pwm_09;
+		PwmH[9 ] = (ubyte)UnInfCan_1.BitData.Pwm_10;
+		PwmH[10] = (ubyte)UnInfCan_1.BitData.Pwm_11;
+		PwmH[11] = (ubyte)UnInfCan_1.BitData.Pwm_12;
+		PwmH[12] = (ubyte)UnInfCan_1.BitData.Pwm_13;
+		PwmH[13] = (ubyte)UnInfCan_1.BitData.Pwm_14;
+		PwmH[14] = (ubyte)UnInfCan_1.BitData.Pwm_15;
+		PwmH[15] = (ubyte)UnInfCan_1.BitData.Pwm_16;
+
+	}
+	
+		//һ֡һεƳ
+	LedDr();
+	
+	
+
+//100msһ֡
+	if(!FlgCan_1)
+	{
+		FlgCan_1 = 1;
+		GetTemp();//1sɼһ¶
+		current_temp = (float)((int)UnSwSample_1.bit_data.temperature[0]);
+		current_temp = current_temp/10.0f;//
+		tempStateMachine(&temp_state, current_temp); 		
+		CanTX();
+	}
+}
+
+
+
+
+
diff --git a/User.c.bak b/User.c.bak
new file mode 100644
index 0000000..22b39dd
--- /dev/null
+++ b/User.c.bak
@@ -0,0 +1,330 @@
+#include "MAIN.H"
+//canϢ
+UnInfCan    UnInfCan_1   = {0};
+UnSwSample  UnSwSample_1 = {0};
+UnSwOut	    UnSwOut_1    = {0};
+
+//CAN
+uword             CntCan_1    = 0;
+bit               FlgCan_1    = 0;
+//һβɼЧָʾ
+bit FlgOneTime = 0;
+
+uword RgCanPerid = 1000;
+
+//PWM 20181227
+ubyte PwmH[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+//-----------------------------------------------------------------------
+//RTCʱ
+//-----------------------------------------------------------------------
+void RTCProcess(void)
+{
+//************************************************************************
+//////CAN
+	if(FlgCan_1){CntCan_1++;if(CntCan_1 >= RgCanPerid){FlgCan_1=0; CntCan_1=0;}}else{CntCan_1=0;}
+
+//************************************************************************
+}
+
+//PWM	20181227
+/*
+ubyte *pStt,	״̬
+bit Cmd,			״̬룬1PwmHֵ00
+bit Out,			״̬
+ubyte *pCnt,	ʱ
+ubyte *pPwmH	״̬PWMĸߵƽʱ
+*/ 
+bit funcPwmOut(ubyte *pStt,bit Cmd,ubyte *pCnt,ubyte *pPwmH)
+{
+ubyte PwmL = 0; 
+bit Out = 0;
+//------------------------------------------------------------------------------------------------
+	if((*pPwmH) > dfPwmH)(*pPwmH) = dfPwmH;	 //ֵ
+	PwmL = dfPwmH - (*pPwmH);//PWM͵ƽ
+
+	if((1 == Cmd) )
+	{
+		if(0 == (*pPwmH))	 //ߵƽΪ0ʾPWMЧCmdƣCmdΪ11CmdΪ00
+		{
+			Out = 1;
+			(*pStt) = 0;	
+		}
+		else
+		{
+			switch((*pStt))
+			{
+				case 0:
+					(*pCnt) = 0;
+					(*pStt) = 1;
+					Out = 1;
+				break;
+				case 1:
+					if((*pCnt) >= (*pPwmH))
+					{
+						(*pCnt) = 0;
+						(*pStt) = 2;
+						Out = 0;
+					}
+					else
+					{
+					 	(*pCnt)++;
+						(*pStt) = 1;
+						Out = 1;
+					}
+				break;
+				case 2:
+					if((*pCnt) >= PwmL)
+					{
+						(*pCnt) = 0;
+						(*pStt) = 1;
+						Out = 1;
+					}
+					else
+					{
+					 	(*pCnt)++;
+						(*pStt) = 2;
+						Out = 0;
+					}
+				break;
+		//-----------------------------------------------------
+				default:;
+			}//switch
+		}//else
+	}//if
+	else 
+	{
+		Out = 0;		
+		(*pStt) = 0;
+	}
+	return Out;
+}
+
+
+//ݽյCANӦ̣ţָʾơ
+void LedDr(void)
+{
+static ubyte RgSTT[16] = {0};
+static ubyte CntTime[16] = {0};
+//------------------------------------------------------------------------------------------------
+
+	dfOut_01 = funcPwmOut(&RgSTT[0 ],dfCmd_01,&CntTime[0 ],&PwmH[0 ]);	
+	dfOut_02 = funcPwmOut(&RgSTT[1 ],dfCmd_02,&CntTime[1 ],&PwmH[1 ]);	
+	dfOut_03 = funcPwmOut(&RgSTT[2 ],dfCmd_03,&CntTime[2 ],&PwmH[2 ]);	
+	dfOut_04 = funcPwmOut(&RgSTT[3 ],dfCmd_04,&CntTime[3 ],&PwmH[3 ]);	
+	dfOut_05 = funcPwmOut(&RgSTT[4 ],dfCmd_05,&CntTime[4 ],&PwmH[4 ]);	
+	dfOut_06 = funcPwmOut(&RgSTT[5 ],dfCmd_06,&CntTime[5 ],&PwmH[5 ]);	
+	dfOut_07 = funcPwmOut(&RgSTT[6 ],dfCmd_07,&CntTime[6 ],&PwmH[6 ]);	
+	dfOut_08 = funcPwmOut(&RgSTT[7 ],dfCmd_08,&CntTime[7 ],&PwmH[7 ]);	
+	dfOut_09 = funcPwmOut(&RgSTT[8 ],dfCmd_09,&CntTime[8 ],&PwmH[8 ]);	
+	dfOut_10 = funcPwmOut(&RgSTT[9 ],dfCmd_10,&CntTime[9 ],&PwmH[9 ]);	
+	dfOut_11 = funcPwmOut(&RgSTT[10],dfCmd_11,&CntTime[10],&PwmH[10]);	
+	dfOut_12 = funcPwmOut(&RgSTT[11],dfCmd_12,&CntTime[11],&PwmH[11]);	
+	dfOut_13 = funcPwmOut(&RgSTT[12],dfCmd_13,&CntTime[12],&PwmH[12]);	
+	dfOut_14 = funcPwmOut(&RgSTT[13],dfCmd_14,&CntTime[13],&PwmH[13]);	
+	dfOut_15 = funcPwmOut(&RgSTT[14],dfCmd_15,&CntTime[14],&PwmH[14]);	
+	dfOut_16 = funcPwmOut(&RgSTT[15],dfCmd_16,&CntTime[15],&PwmH[15]);	
+
+}
+
+
+//can
+void CanErrorProcess(void)
+{
+	ubyte ubNSRL;
+	ubyte ubNSRH;
+	ubyte ubResetLEC = 0x3F;
+//-------------------------------------------
+	EA            =  0;
+
+	CAN_pushAMRegs();              // push the CAN Access Mediator Registers
+	SFR_PAGE(_su0, SST0);          // switch to page 0
+
+	CAN_vWriteCANAddress(CAN_NSR0);
+	CAN_vReadEN();
+	ubNSRL = CAN_DATA0;
+	ubNSRH = CAN_DATA1;
+	if (ubNSRL & 0x20)      // if ALERT
+	{
+		CAN_vInit();
+	}
+	if (ubNSRL & 0x07)  // if LEC
+	{
+		ubResetLEC = 0x38;
+	}
+	//// Reset LEC, TXOK, RXOK, ALERT, EWRN, BOFF, LLE, LOE (if set)
+	CAN_vWriteCANAddress(CAN_NSR0); // Addressing CAN_NSR0
+	CAN_DATA0   =  ~(ubNSRL & ubResetLEC);       // load CAN_NSR0 status register[7-0]
+	CAN_DATA1   =  ~(ubNSRH);       // load CAN_NSR0 status register[15-8]
+	CAN_vWriteEN(D0_VALID+D1_VALID);  // Data0 and Data1 are Valid for
+
+	SFR_PAGE(_su0, RST0);          // restore the old SCU page
+	CAN_popAMRegs();               // restore the CAN Access Mediator Registers
+
+	EA            =  1;
+}
+
+
+////Ч㷨
+//void Password(void)
+//{
+//	ubyte i;
+////---------------------------------
+//	for(i=0;i<5;i++)
+//	{
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][3];//CAN 0ֽ
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][2];//CAN 1ֽ
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][1];//CAN 2ֽ
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][0];//CAN 3ֽ
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][7];//CAN 4ֽ
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][6];//CAN 5ֽ
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][5];//CAN 6ֽ
+//	}
+//}
+
+
+void CanTransmit(void)
+{
+//	ulong i;
+//-----------------	--------
+	CAN_waitTransmit(DF_SwTx);//ǰȴһ֡ϣᶪ֡
+//	Password();
+
+	CAN_vLoadData(DF_SwTx, (ulong *)(&UnInfCan_1.ArrData.Arr[0][0])); // װ
+	CAN_vTransmit(DF_SwTx);
+}
+
+
+//CANһ֡
+void CanTX(void)
+{
+//-----------------------------------
+	if(1 == SwOut09)UnInfCan_1.ArrData.Arr[0][3] |= (~0x01);else UnInfCan_1.ArrData.Arr[0][3] &= 0x01;		//KGF1		//20200303޸Ϊյһ£յʱΪһ
+	if(1 == SwOut10)UnInfCan_1.ArrData.Arr[0][3] |= (~0x02);else UnInfCan_1.ArrData.Arr[0][3] &= 0x02;		//KGF2		
+	if(1 == SwOut04)UnInfCan_1.ArrData.Arr[0][3] |= (~0x04);else UnInfCan_1.ArrData.Arr[0][3] &= 0x04;		//KGF3
+	if(1 == SwOut03)UnInfCan_1.ArrData.Arr[0][3] |= (~0x08);else UnInfCan_1.ArrData.Arr[0][3] &= 0x08;		//KGF4
+	if(1 == SwOut06)UnInfCan_1.ArrData.Arr[0][3] |= (~0x10);else UnInfCan_1.ArrData.Arr[0][3] &= 0x10;		//KGF5
+	if(1 == SwOut05)UnInfCan_1.ArrData.Arr[0][3] |= (~0x20);else UnInfCan_1.ArrData.Arr[0][3] &= 0x20;		//KGF6
+	if(1 == SwOut15)UnInfCan_1.ArrData.Arr[0][3] |= (~0x40);else UnInfCan_1.ArrData.Arr[0][3] &= 0x40;		//KGF7
+	if(1 == SwOut16)UnInfCan_1.ArrData.Arr[0][3] |= (~0x80);else UnInfCan_1.ArrData.Arr[0][3] &= 0x80;		//KGF8
+	if(1 == SwOut13)UnInfCan_1.ArrData.Arr[0][2] |= (~0x01);else UnInfCan_1.ArrData.Arr[0][2] &= 0x01;		//KGF9
+	if(1 == SwOut14)UnInfCan_1.ArrData.Arr[0][2] |= (~0x02);else UnInfCan_1.ArrData.Arr[0][2] &= 0x02;		//KGF10
+	if(1 == SwOut08)UnInfCan_1.ArrData.Arr[0][2] |= (~0x04);else UnInfCan_1.ArrData.Arr[0][2] &= 0x04;		//KGF11
+	if(1 == SwOut07)UnInfCan_1.ArrData.Arr[0][2] |= (~0x08);else UnInfCan_1.ArrData.Arr[0][2] &= 0x08;		//KGF12
+	if(1 == SwOut02)UnInfCan_1.ArrData.Arr[0][2] |= (~0x10);else UnInfCan_1.ArrData.Arr[0][2] &= 0x10;		//KGF13
+	if(1 == SwOut01)UnInfCan_1.ArrData.Arr[0][2] |= (~0x20);else UnInfCan_1.ArrData.Arr[0][2] &= 0x20;		//KGF14
+	if(1 == SwOut11)UnInfCan_1.ArrData.Arr[0][2] |= (~0x40);else UnInfCan_1.ArrData.Arr[0][2] &= 0x40;		//KGF15
+	if(1 == SwOut12)UnInfCan_1.ArrData.Arr[0][2] |= (~0x80);else UnInfCan_1.ArrData.Arr[0][2] &= 0x80;		//KGF16
+
+	if(1 == SwIn01 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x01);else UnInfCan_1.ArrData.Arr[0][1] |= 0x01;		//Dia01  20200225޸Ϊ0ݱΪ1,1ݱΪ0CPU㴦
+	if(1 == SwIn02 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x02);else UnInfCan_1.ArrData.Arr[0][1] |= 0x02;		//Dia02
+	if(1 == SwIn03 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x04);else UnInfCan_1.ArrData.Arr[0][1] |= 0x04;		//Dia03
+	if(1 == SwIn04 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x08);else UnInfCan_1.ArrData.Arr[0][1] |= 0x08;		//Dia04
+	if(1 == SwIn05 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x10);else UnInfCan_1.ArrData.Arr[0][1] |= 0x10;		//Dia05
+	if(1 == SwIn06 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x20);else UnInfCan_1.ArrData.Arr[0][1] |= 0x20;		//Dia06
+	if(1 == SwIn07 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x40);else UnInfCan_1.ArrData.Arr[0][1] |= 0x40;		//Dia07	  
+	if(1 == SwIn08 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x80);else UnInfCan_1.ArrData.Arr[0][1] |= 0x80;		//Dia08			
+                               
+	UnInfCan_1.ArrData.Arr[0][0] = 0;
+	UnInfCan_1.ArrData.Arr[0][7] = 0;
+	UnInfCan_1.ArrData.Arr[0][6] = 0;
+	UnInfCan_1.ArrData.Arr[0][5] = (ubyte)(RgCanPerid>>8);
+	UnInfCan_1.ArrData.Arr[0][4] = (ubyte)(RgCanPerid);
+
+	CanTransmit();
+}
+
+//CANͽ
+void CanRXTX(void)
+{
+	stCAN_SWObj StrCanRx = {0};
+	uword tmp = 0;
+	ubyte i = 0,j = 0;
+//------------------------------------
+	if(CAN_ubNewData(DF_SwRx))
+	{
+		CAN_vGetMsgObj(DF_SwRx, &StrCanRx);
+
+		UnInfCan_1.ArrData.ArrRX[0][3] = StrCanRx.ulDATAL.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[0][2] = StrCanRx.ulDATAL.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[0][1] = StrCanRx.ulDATAL.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[0][0] = StrCanRx.ulDATAL.ubDB[3];
+		UnInfCan_1.ArrData.ArrRX[0][7] = StrCanRx.ulDATAH.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[0][6] = StrCanRx.ulDATAH.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[0][5] = StrCanRx.ulDATAH.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[0][4] = StrCanRx.ulDATAH.ubDB[3];
+
+		CAN_vReleaseObj(DF_SwRx);
+
+		//CAN	50-5000ms
+		tmp = (uword)UnInfCan_1.ArrData.ArrRX[0][6];
+		tmp = (tmp << 8);
+		tmp |= ((uword)UnInfCan_1.ArrData.ArrRX[0][7]);
+		if(tmp >= 50)RgCanPerid = tmp;
+		if(tmp >= 5000)RgCanPerid = 5000;
+
+//		UnInfCan_1.ArrData.Arr[0][3] = UnInfCan_1.ArrData.ArrRX[0][0];
+//		UnInfCan_1.ArrData.Arr[0][2] = UnInfCan_1.ArrData.ArrRX[0][1];
+//		UnInfCan_1.ArrData.Arr[0][1] = UnInfCan_1.ArrData.ArrRX[0][2]; 20200225עͲ
+//		UnInfCan_1.ArrData.Arr[0][0] = UnInfCan_1.ArrData.ArrRX[0][3];
+//		UnInfCan_1.ArrData.Arr[0][7] = UnInfCan_1.ArrData.ArrRX[0][4];
+//		UnInfCan_1.ArrData.Arr[0][6] = UnInfCan_1.ArrData.ArrRX[0][5];
+//		UnInfCan_1.ArrData.Arr[0][5] = (ubyte)(RgCanPerid>>8);
+//		UnInfCan_1.ArrData.Arr[0][4] = (ubyte)(RgCanPerid);
+//		CanTransmit();	 20200730͸
+	}
+
+	if(CAN_ubNewData(DF_SwRxPwm))
+	{
+		CAN_vGetMsgObj(DF_SwRxPwm, &StrCanRx);
+
+		UnInfCan_1.ArrData.ArrRX[1][2] = StrCanRx.ulDATAL.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[1][3] = StrCanRx.ulDATAL.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[1][0] = StrCanRx.ulDATAL.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[1][1] = StrCanRx.ulDATAL.ubDB[3];
+		UnInfCan_1.ArrData.ArrRX[1][6] = StrCanRx.ulDATAH.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[1][7] = StrCanRx.ulDATAH.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[1][4] = StrCanRx.ulDATAH.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[1][5] = StrCanRx.ulDATAH.ubDB[3];
+
+		CAN_vReleaseObj(DF_SwRxPwm);
+		//յݱ浽PWMݽṹ20181227
+		PwmH[0 ] = (ubyte)UnInfCan_1.BitData.Pwm_01;
+		PwmH[1 ] = (ubyte)UnInfCan_1.BitData.Pwm_02;
+		PwmH[2 ] = (ubyte)UnInfCan_1.BitData.Pwm_03;
+		PwmH[3 ] = (ubyte)UnInfCan_1.BitData.Pwm_04;
+		PwmH[4 ] = (ubyte)UnInfCan_1.BitData.Pwm_05;
+		PwmH[5 ] = (ubyte)UnInfCan_1.BitData.Pwm_06;
+		PwmH[6 ] = (ubyte)UnInfCan_1.BitData.Pwm_07;
+		PwmH[7 ] = (ubyte)UnInfCan_1.BitData.Pwm_08;
+		PwmH[8 ] = (ubyte)UnInfCan_1.BitData.Pwm_09;
+		PwmH[9 ] = (ubyte)UnInfCan_1.BitData.Pwm_10;
+		PwmH[10] = (ubyte)UnInfCan_1.BitData.Pwm_11;
+		PwmH[11] = (ubyte)UnInfCan_1.BitData.Pwm_12;
+		PwmH[12] = (ubyte)UnInfCan_1.BitData.Pwm_13;
+		PwmH[13] = (ubyte)UnInfCan_1.BitData.Pwm_14;
+		PwmH[14] = (ubyte)UnInfCan_1.BitData.Pwm_15;
+		PwmH[15] = (ubyte)UnInfCan_1.BitData.Pwm_16;
+
+
+//		UnInfCan_1.ArrData.Arr[0][3] = UnInfCan_1.ArrData.ArrRX[1][0];
+//		UnInfCan_1.ArrData.Arr[0][2] = UnInfCan_1.ArrData.ArrRX[1][1];
+//		UnInfCan_1.ArrData.Arr[0][1] = UnInfCan_1.ArrData.ArrRX[1][2];	20200225עͲ
+//		UnInfCan_1.ArrData.Arr[0][0] = UnInfCan_1.ArrData.ArrRX[1][3];
+//		UnInfCan_1.ArrData.Arr[0][7] = UnInfCan_1.ArrData.ArrRX[1][4];
+//		UnInfCan_1.ArrData.Arr[0][6] = UnInfCan_1.ArrData.ArrRX[1][5];
+//		UnInfCan_1.ArrData.Arr[0][5] = UnInfCan_1.ArrData.ArrRX[1][6];
+//		UnInfCan_1.ArrData.Arr[0][4] = UnInfCan_1.ArrData.ArrRX[1][7];
+//		CanTransmit();
+
+	}
+		//һ֡һεƳ
+		LedDr();
+
+//100msһ֡
+	if(!FlgCan_1)
+	{
+		FlgCan_1 = 1;
+		CanTX();
+	}
+
+}
diff --git a/WDT.C b/WDT.C
new file mode 100644
index 0000000..2508eb8
--- /dev/null
+++ b/WDT.C
@@ -0,0 +1,206 @@
+//****************************************************************************
+// @Module        Watch Dog Timer
+// @Filename      WDT.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the WDT module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:32
+//
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (WDT_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void WDT_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the 'Watch Dog 
+//                Timer' function library. It is assumed that the SFRs used 
+//                by this library are in their reset state. 
+//                
+//                The watchdog timer is used.
+//                The following SFR fields will be initialized:
+//                WDTREL - WDT reload value
+//                WDTIN  - WDT input frequency selection
+//                Then the watchdog timer will be refreshed.
+//                Note: The user has to take care that RMAP bit in SYSCON0 is 
+//                to be set while using the registers of Watch dog timer.
+//                Registers are WDTCON,WDTWINB,WDTREL,WDTH,WDTL
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Init,1)
+
+// USER CODE END
+
+void WDT_vInit(void)
+{
+  // USER CODE BEGIN (WDT_Init,2)
+
+  // USER CODE END
+
+  ///  the watchdog timer is used and it is enabled in INIT function,user has 
+  ///  to take care of WDT refresh
+  ///  the RMAP bit of SYSCON0 is set
+  ///  the input frequency is fSYS/128
+  ///  the watchdog timer reload value is 0xDB
+  ///  the watchdog timeout period is 50 ms
+
+  SFR_PAGE(_su1, noSST);         // switch to page1 without saving
+
+  MAIN_vUnlockProtecReg();       // open access to protected register
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+
+  SYSCON0 |= 0x01;    //   set   RMAP
+  WDTREL = 0xDB;      //Watch dog timer reload register
+  WDTCON |= 0x04;     //   set   WDTEN
+  WDTCON |= 0x03;                // set WDTRS,set WDTIN
+  SYSCON0 &= ~(ubyte)0x01; //   clear RMAP
+  SFR_PAGE(_su1, noSST);         // switch to page1 without saving
+
+  MAIN_vlockProtecReg();         // close access to protected register
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+
+  // USER CODE BEGIN (WDT_Init,3)
+
+  // USER CODE END
+
+
+
+} //  End of function WDT_vInit
+
+
+//****************************************************************************
+// @Function      void WDT_vDisable(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function disables the WDT.
+//                pls refer to the Note on WDT_vInit function Description
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+void WDT_vDisable(void)
+{
+  SFR_PAGE(_su1, noSST);         // switch to page1 without saving
+
+  MAIN_vUnlockProtecReg();       // open access to protected register
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+
+  SET_RMAP();
+  WDTCON &= ~(ubyte)0x04; //   clear WDTEN
+  RESET_RMAP();
+  SFR_PAGE(_su1, noSST);         // switch to page1 without saving
+
+  MAIN_vlockProtecReg();         // close access to protected register
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+} //  End of function WDT_vDisable
+
+
+// USER CODE BEGIN (WDT_General,10)
+
+// USER CODE END
+
diff --git a/WDT.H b/WDT.H
new file mode 100644
index 0000000..8baf9f5
--- /dev/null
+++ b/WDT.H
@@ -0,0 +1,130 @@
+//****************************************************************************
+// @Module        Watch Dog Timer
+// @Filename      WDT.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the WDT module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:32
+//
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _WDT_H_
+#define _WDT_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void WDT_vInit(void);
+void WDT_vDisable(void);
+
+// USER CODE BEGIN (WDT_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         WDT_vRefresh() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro refreshes the watchdog timer to the reload 
+//                value. The interrupts are disabled during execution of the 
+//                instructions that set bit WDTRS. 
+//                Note: The user has to take care that this macro is called 
+//                before expiry of the watchdog timer.
+//                pls refer to the Note on WDT_vInit function Description
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define WDT_vRefresh()  { EA = 0; SET_RMAP(); WDTCON |= 0x02; \
+   RESET_RMAP(); EA = 1; }
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+
+// USER CODE BEGIN (WDT_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _WDT_H_
diff --git a/XC88x_FLADDR.H b/XC88x_FLADDR.H
new file mode 100644
index 0000000..8bd905e
--- /dev/null
+++ b/XC88x_FLADDR.H
@@ -0,0 +1,876 @@
+//***************************************************************************
+//*     BootROM entries for XC88x-AA and AB Step                            *
+//*     Updated  : 2006-03-14                                               *
+//*     Copyright: (c) 2006 Infineon Technologies AG                        *
+//***************************************************************************
+
+#ifndef  __XC88x_FLADDR_H__
+#define  __XC88x_FLADDR_H__
+
+// User Configuration //
+#define XC88xAA           1    // Must be set to '1/0' (for AA step)
+#define XC88xAB           0    // Must be set to '1/0' (set to '1' for AB step)
+#define XC88xAC           0    // Must be set to '1/0' (Set to '1' for AC step)
+
+#define USE_BANK          3    // Register Bank used during Program / Erase
+                               // Default = 3
+#define WORDLINE_BUFFER_ADDRESS  0x80  // Starting address of the Buffer in the IRAM
+                                       // This Buffer will be used to store data
+                                       // before it is being programmed to flash
+#define USE_64BYTE_BUFFER 0	   // If PFlash will be programmed, set this to '1'
+                               // Programming PFLash will need 64Byte WordLine Buffer
+                               // Else, default buffer size is set to 32byte.
+#define USE_PFLERASE      1    // Set to '1' if PFlErase() routine is to be used.
+                               // Set to '0' if not used, to save some code space.
+#define USE_DLFERASE      1    // Set to '1' if DFlErase() routine is to be used.
+                               // Set to '0' if not used, to save some code space.
+
+// End of user configuration
+
+
+//+----------------------------------------------+
+//|   ROM entries taken from manual              |
+//|   and AppNote aboute programming the FLASH   |
+//|   used in XC88x_FLHANDLER.ASM                |
+//+----------------------------------------------+
+
+//====================================================================================
+#if (XC88xAA || XC88xAB || XC88xAC)             // Use the FSM to program / erase flash
+#define FLASH_ERASE_BROM_ENTRY          0xDFF9  // Erase Flash Bank
+#define FLASH_PROGRAM_BROM_ENTRY        0xDFF6  // Program Flash Bank.
+#define FLASH_ERASE_ABORT_BROM_ENTRY    0xDFF3  // Abort the on going erase process
+#define FLASH_READ_STATUS_BROM_ENTRY    0xDFF0  // Read Flash Status
+#endif
+#if (XC88xAA)
+#define FLASH_PROTECT_BROM_ENTRY        0xDB06
+#endif
+#if (XC88xAB || XC88xAC)
+#define FLASH_PROTECT_BROM_ENTRY        0xDFD8
+#endif
+//====================================================================================
+
+//+-----------------------------------------+
+//|   General definitions of used sources   |
+//+-----------------------------------------+
+// used buffer address in IRAM for Wordline erase/program 
+#if (XC88xAA || XC88xAB || XC88xAC)  
+#define MAGIC_MEMORY                  0x36  // reserve magic memory from D:0x36 .. D:0x3E
+#if (USE_64BYTE_BUFFER == 1)
+#define BYTES_PER_WORDLINE            64    //
+#else
+#define BYTES_PER_WORDLINE            32    //
+#endif
+#define RESERVED_BYTES                0x08
+#define PFLASH0                       0     // PFlash 0
+#define PFLASH1                       1     // PFlash 1
+#define PFLASH2	                      2     // PFlash 2
+#define DFLASH0                       3     // DFlash 0
+#define DFLASH1                       4     // DFlash 1
+
+#endif
+//+------------------------------------------------+
+//|   End of general definitions of used sources   |
+//+------------------------------------------------+
+
+
+
+//************************************************************************************************
+//*   Definitions of Bank-, Sector- and Wordlineaddresses
+//* 
+//************************************************************************************************
+// Sectors of PFlash0 for erasing -- transferred in  PFlErase() first parameter
+
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/ Sector.01/ Sector.00 /
+// ---------/---------/---------/---------/---------/Pfl0Sec02/ Pfl0Sec01/ Pfl0Sec00 /
+// ---------/---------/---------/---------/---------/-256B-4WL/-256B--4WL/-7.5k-120WL/
+// ---------/---------/---------/---------/---------/-0x1F00--/--0x1E00--/--0x0000----/
+#define PFL0_SEC0   0x0001
+#define PFL0_SEC1   0x0002
+#define PFL0_SEC2   0x0004
+
+// Sectors of PFlash1 for erasing -- transferred in  PFlErase() Second parameter
+
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/ Sector.01/ Sector.00  /
+// ---------/---------/---------/---------/---------/Pfl1Sec02/ Pfl1Sec01/ Pfl1Sec00  /
+// ---------/---------/---------/---------/---------/-256B-4WL/-256B--4WL/-7.5k-120WL/
+// ---------/---------/---------/---------/---------/-0x3F00--/--0x3E00--/--0x2000----/
+#define PFL1_SEC0   0x0001
+#define PFL1_SEC1   0x0002
+#define PFL1_SEC2   0x0004
+
+// Sectors of PFlash2 for erasing -- transferred in  PFlErase() Third parameter
+
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/ Sector.01/ Sector.00  /
+// ---------/---------/---------/---------/---------/Pfl2Sec02/ Pfl2Sec01/ Pfl2Sec00  /
+// ---------/---------/---------/---------/---------/-256B-4WL/-256B--4WL/-7.5k-120WL/
+// ---------/---------/---------/---------/---------/-0x5F00--/--0x5E00--/--0x4000----/
+#define PFL2_SEC0   0x0001
+#define PFL2_SEC1   0x0002
+#define PFL2_SEC2   0x0004
+
+// Sectors of DFlash 0 for erasing -- transfered in DFlErase() First parameter
+// DFlash 0 address is also mirrorred to 0x7xxx
+
+// Sector.15/Sector.14/Sector.13/Sector.12/Sector.11/Sector.10/Sector.09/Sector.08/
+// ---------/---------/---------/---------/---------/---------/Dfl0Sec09/Dfl0Sec08/
+// ---------/---------/---------/---------/---------/---------/-128-4WL-/-128-4WL-/
+// ---------/---------/---------/---------/---------/---------/--0xAF80-/--0xAF00-/
+ 
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/Sector.01/Sector.00/
+// Dfl0Sec07/Dfl0Sec06/Dfl0Sec05/Dfl0Sec04/Dfl0Sec03/Dfl0Sec02/Dfl0Sec01/Dfl0Sec00/
+// -128-4WL-/-128-4WL-/-256-8WL-/-256-8WL-/-512-16WL/-512-16WL/-1k--32WL/-1k--32WL/
+// --0xAE80-/--0xAE00-/--0xAD00-/--0xAC00-/-0xAA00--/-0xA800--/--0xA400-/--0xA000-/
+
+#define DFL0_SEC0   0x0001
+#define DFL0_SEC1   0x0002
+#define DFL0_SEC2   0x0004
+#define DFL0_SEC3   0x0008
+#define DFL0_SEC4   0x0010
+#define DFL0_SEC5   0x0020
+#define DFL0_SEC6   0x0040
+#define DFL0_SEC7   0x0080
+#define DFL0_SEC8   0x0100
+#define DFL0_SEC9   0x0200
+#define DFL0_SECALL 0x3FF
+
+// Sectors of DFlash 1 for erasing -- transfered in DFlErase() Second parameter
+// DFlash 1 address is also mirrorred to 0x6xxx
+
+// Sector.15/Sector.14/Sector.13/Sector.12/Sector.11/Sector.10/Sector.09/Sector.08/
+// ---------/---------/---------/---------/---------/---------/Dfl1Sec09/Dfl1Sec08/
+// ---------/---------/---------/---------/---------/---------/-128-4WL-/-128-4WL-/
+// ---------/---------/---------/---------/---------/---------/--0xAF80-/--0xAF00-/
+ 
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/Sector.01/Sector.00/
+// Dfl1Sec07/Dfl1Sec06/Dfl1Sec05/Dfl1Sec04/Dfl1Sec03/Dfl1Sec02/Dfl1Sec01/Dfl1Sec00/
+// -128-4WL-/-128-4WL-/-256-8WL-/-256-8WL-/-512-16WL/-512-16WL/-1k--32WL/-1k--32WL/
+// --0xAE80-/--0xAE00-/--0xAD00-/--0xAC00-/-0xAA00--/-0xA800--/--0xA400-/--0xA000-/
+
+#define DFL1_SEC0   0x0001
+#define DFL1_SEC1   0x0002
+#define DFL1_SEC2   0x0004
+#define DFL1_SEC3   0x0008
+#define DFL1_SEC4   0x0010
+#define DFL1_SEC5   0x0020
+#define DFL1_SEC6   0x0040
+#define DFL1_SEC7   0x0080
+#define DFL1_SEC8   0x0100
+#define DFL1_SEC9   0x0200
+#define DFL1_SECALL 0x3FF
+
+//###################################################################################
+// WordLine startaddresses for Sectors in PFlas 0, each WL with 64bytes
+
+// Sector 0 -- 7.5 kbytes -- 120 Wordlines
+#define PFL0_SEC0_WL00  0x0000
+#define PFL0_SEC0_WL01  0x0040
+#define PFL0_SEC0_WL02  0x0080
+#define PFL0_SEC0_WL03  0x00C0
+#define PFL0_SEC0_WL04  0x0100
+#define PFL0_SEC0_WL05  0x0140
+#define PFL0_SEC0_WL06  0x0180
+#define PFL0_SEC0_WL07  0x01C0
+#define PFL0_SEC0_WL08  0x0200
+#define PFL0_SEC0_WL09  0x0240
+#define PFL0_SEC0_WL10  0x0280
+#define PFL0_SEC0_WL11  0x02C0
+#define PFL0_SEC0_WL12  0x0300
+#define PFL0_SEC0_WL13  0x0340
+#define PFL0_SEC0_WL14  0x0380
+#define PFL0_SEC0_WL15  0x03C0
+#define PFL0_SEC0_WL16  0x0400
+#define PFL0_SEC0_WL17  0x0440
+#define PFL0_SEC0_WL18  0x0480
+#define PFL0_SEC0_WL19  0x04C0
+#define PFL0_SEC0_WL20  0x0500
+#define PFL0_SEC0_WL21  0x0540
+#define PFL0_SEC0_WL22  0x0580
+#define PFL0_SEC0_WL23  0x05C0
+#define PFL0_SEC0_WL24  0x0600
+#define PFL0_SEC0_WL25  0x0640
+#define PFL0_SEC0_WL26  0x0680
+#define PFL0_SEC0_WL27  0x06C0
+#define PFL0_SEC0_WL28  0x0700
+#define PFL0_SEC0_WL29  0x0740
+#define PFL0_SEC0_WL30  0x0780
+#define PFL0_SEC0_WL31  0x07C0
+#define PFL0_SEC0_WL32  0x0800
+#define PFL0_SEC0_WL33  0x0840
+#define PFL0_SEC0_WL34  0x0880
+#define PFL0_SEC0_WL35  0x08C0
+#define PFL0_SEC0_WL36  0x0900
+#define PFL0_SEC0_WL37  0x0940
+#define PFL0_SEC0_WL38  0x0980
+#define PFL0_SEC0_WL39  0x09C0
+#define PFL0_SEC0_WL40  0x0A00
+#define PFL0_SEC0_WL41  0x0A40
+#define PFL0_SEC0_WL42  0x0A80
+#define PFL0_SEC0_WL43  0x0AC0
+#define PFL0_SEC0_WL44  0x0B00
+#define PFL0_SEC0_WL45  0x0B40
+#define PFL0_SEC0_WL46  0x0B80
+#define PFL0_SEC0_WL47  0x0BC0
+#define PFL0_SEC0_WL48  0x0C00
+#define PFL0_SEC0_WL49  0x0C40
+#define PFL0_SEC0_WL50  0x0C80
+#define PFL0_SEC0_WL51  0x0CC0
+#define PFL0_SEC0_WL52  0x0D00
+#define PFL0_SEC0_WL53  0x0D40
+#define PFL0_SEC0_WL54  0x0D80
+#define PFL0_SEC0_WL55  0x0DC0
+#define PFL0_SEC0_WL56  0x0E00
+#define PFL0_SEC0_WL57  0x0E40
+#define PFL0_SEC0_WL58  0x0E80
+#define PFL0_SEC0_WL59  0x0EC0
+#define PFL0_SEC0_WL60  0x0F00
+#define PFL0_SEC0_WL61  0x0F40
+#define PFL0_SEC0_WL62  0x0F80
+#define PFL0_SEC0_WL63  0x0FC0
+#define PFL0_SEC0_WL64  0x1000
+#define PFL0_SEC0_WL65  0x1040
+#define PFL0_SEC0_WL66  0x1080
+#define PFL0_SEC0_WL67  0x10C0
+#define PFL0_SEC0_WL68  0x1100
+#define PFL0_SEC0_WL69  0x1140
+#define PFL0_SEC0_WL70  0x1180
+#define PFL0_SEC0_WL71  0x11C0
+#define PFL0_SEC0_WL72  0x1200
+#define PFL0_SEC0_WL73  0x1240
+#define PFL0_SEC0_WL74  0x1280
+#define PFL0_SEC0_WL75  0x12C0
+#define PFL0_SEC0_WL76  0x1300
+#define PFL0_SEC0_WL77  0x1340
+#define PFL0_SEC0_WL78  0x1380
+#define PFL0_SEC0_WL79  0x13C0
+#define PFL0_SEC0_WL80  0x1400
+#define PFL0_SEC0_WL81  0x1440
+#define PFL0_SEC0_WL82  0x1480
+#define PFL0_SEC0_WL83  0x14C0
+#define PFL0_SEC0_WL84  0x1500
+#define PFL0_SEC0_WL85  0x1540
+#define PFL0_SEC0_WL86  0x1580
+#define PFL0_SEC0_WL87  0x15C0
+#define PFL0_SEC0_WL88  0x1600
+#define PFL0_SEC0_WL89  0x1640
+#define PFL0_SEC0_WL90  0x1680
+#define PFL0_SEC0_WL91  0x16C0
+#define PFL0_SEC0_WL92  0x1700
+#define PFL0_SEC0_WL93  0x1740
+#define PFL0_SEC0_WL94  0x1780
+#define PFL0_SEC0_WL95  0x17C0
+#define PFL0_SEC0_WL96  0x1800
+#define PFL0_SEC0_WL97  0x1840
+#define PFL0_SEC0_WL98  0x1880
+#define PFL0_SEC0_WL99  0x18C0
+#define PFL0_SEC0_WL100 0x1900
+#define PFL0_SEC0_WL101 0x1940
+#define PFL0_SEC0_WL102 0x1980
+#define PFL0_SEC0_WL103 0x19C0
+#define PFL0_SEC0_WL104 0x1A00
+#define PFL0_SEC0_WL105 0x1A40
+#define PFL0_SEC0_WL106 0x1A80
+#define PFL0_SEC0_WL107 0x1AC0
+#define PFL0_SEC0_WL108 0x1B00
+#define PFL0_SEC0_WL109 0x1B40
+#define PFL0_SEC0_WL110 0x1B80
+#define PFL0_SEC0_WL111 0x1BC0
+#define PFL0_SEC0_WL112 0x1C00
+#define PFL0_SEC0_WL113 0x1C40
+#define PFL0_SEC0_WL114 0x1C80
+#define PFL0_SEC0_WL115 0x1CC0
+#define PFL0_SEC0_WL116 0x1D00
+#define PFL0_SEC0_WL117 0x1D40
+#define PFL0_SEC0_WL118 0x1D80
+#define PFL0_SEC0_WL119 0x1DC0
+
+// Sector 1 -- 256 bytes -- 4 Wordlines
+#define PFL0_SEC1_WL120 0x1E00
+#define PFL0_SEC1_WL121 0x1E40
+#define PFL0_SEC1_WL122 0x1E80
+#define PFL0_SEC1_WL123 0x1EC0
+
+// Sector 2 -- 256 bytes -- 4 Wordlines
+#define PFL0_SEC2_WL124 0x1F00
+#define PFL0_SEC2_WL125 0x1F40
+#define PFL0_SEC2_WL126 0x1F80
+#define PFL0_SEC2_WL127 0x1FC0
+
+//###################################################################################
+// WordLine startaddresses for Sectors in PFlash 1, each _WL with 64bytes
+
+// Sector 0 -- 7.5 kbytes -- 120 Wordlines
+#define PFL1_SEC0_WL00  0x2000
+#define PFL1_SEC0_WL01  0x2040
+#define PFL1_SEC0_WL02  0x2080
+#define PFL1_SEC0_WL03  0x20C0
+#define PFL1_SEC0_WL04  0x2100
+#define PFL1_SEC0_WL05  0x2140
+#define PFL1_SEC0_WL06  0x2180
+#define PFL1_SEC0_WL07  0x21C0
+#define PFL1_SEC0_WL08  0x2200
+#define PFL1_SEC0_WL09  0x2240
+#define PFL1_SEC0_WL10  0x2280
+#define PFL1_SEC0_WL11  0x22C0
+#define PFL1_SEC0_WL12  0x2300
+#define PFL1_SEC0_WL13  0x2340
+#define PFL1_SEC0_WL14  0x2380
+#define PFL1_SEC0_WL15  0x23C0
+#define PFL1_SEC0_WL16  0x2400
+#define PFL1_SEC0_WL17  0x2440
+#define PFL1_SEC0_WL18  0x2480
+#define PFL1_SEC0_WL19  0x24C0
+#define PFL1_SEC0_WL20  0x2500
+#define PFL1_SEC0_WL21  0x2540
+#define PFL1_SEC0_WL22  0x2580
+#define PFL1_SEC0_WL23  0x25C0
+#define PFL1_SEC0_WL24  0x2600
+#define PFL1_SEC0_WL25  0x2640
+#define PFL1_SEC0_WL26  0x2680
+#define PFL1_SEC0_WL27  0x26C0
+#define PFL1_SEC0_WL28  0x2700
+#define PFL1_SEC0_WL29  0x2740
+#define PFL1_SEC0_WL30  0x2780
+#define PFL1_SEC0_WL31  0x27C0
+#define PFL1_SEC0_WL32  0x2800
+#define PFL1_SEC0_WL33  0x2840
+#define PFL1_SEC0_WL34  0x2880
+#define PFL1_SEC0_WL35  0x28C0
+#define PFL1_SEC0_WL36  0x2900
+#define PFL1_SEC0_WL37  0x2940
+#define PFL1_SEC0_WL38  0x2980
+#define PFL1_SEC0_WL39  0x29C0
+#define PFL1_SEC0_WL40  0x2A00
+#define PFL1_SEC0_WL41  0x2A40
+#define PFL1_SEC0_WL42  0x2A80
+#define PFL1_SEC0_WL43  0x2AC0
+#define PFL1_SEC0_WL44  0x2B00
+#define PFL1_SEC0_WL45  0x2B40
+#define PFL1_SEC0_WL46  0x2B80
+#define PFL1_SEC0_WL47  0x2BC0
+#define PFL1_SEC0_WL48  0x2C00
+#define PFL1_SEC0_WL49  0x2C40
+#define PFL1_SEC0_WL50  0x2C80
+#define PFL1_SEC0_WL51  0x2CC0
+#define PFL1_SEC0_WL52  0x2D00
+#define PFL1_SEC0_WL53  0x2D40
+#define PFL1_SEC0_WL54  0x2D80
+#define PFL1_SEC0_WL55  0x2DC0
+#define PFL1_SEC0_WL56  0x2E00
+#define PFL1_SEC0_WL57  0x2E40
+#define PFL1_SEC0_WL58  0x2E80
+#define PFL1_SEC0_WL59  0x2EC0
+#define PFL1_SEC0_WL60  0x2F00
+#define PFL1_SEC0_WL61  0x2F40
+#define PFL1_SEC0_WL62  0x2F80
+#define PFL1_SEC0_WL63  0x2FC0
+#define PFL1_SEC0_WL64  0x3000
+#define PFL1_SEC0_WL65  0x3040
+#define PFL1_SEC0_WL66  0x3080
+#define PFL1_SEC0_WL67  0x30C0
+#define PFL1_SEC0_WL68  0x3100
+#define PFL1_SEC0_WL69  0x3140
+#define PFL1_SEC0_WL70  0x3180
+#define PFL1_SEC0_WL71  0x31C0
+#define PFL1_SEC0_WL72  0x3200
+#define PFL1_SEC0_WL73  0x3240
+#define PFL1_SEC0_WL74  0x3280
+#define PFL1_SEC0_WL75  0x32C0
+#define PFL1_SEC0_WL76  0x3300
+#define PFL1_SEC0_WL77  0x3340
+#define PFL1_SEC0_WL78  0x3380
+#define PFL1_SEC0_WL79  0x33C0
+#define PFL1_SEC0_WL80  0x3400
+#define PFL1_SEC0_WL81  0x3440
+#define PFL1_SEC0_WL82  0x3480
+#define PFL1_SEC0_WL83  0x34C0
+#define PFL1_SEC0_WL84  0x3500
+#define PFL1_SEC0_WL85  0x3540
+#define PFL1_SEC0_WL86  0x3580
+#define PFL1_SEC0_WL87  0x35C0
+#define PFL1_SEC0_WL88  0x3600
+#define PFL1_SEC0_WL89  0x3640
+#define PFL1_SEC0_WL90  0x3680
+#define PFL1_SEC0_WL91  0x36C0
+#define PFL1_SEC0_WL92  0x3700
+#define PFL1_SEC0_WL93  0x3740
+#define PFL1_SEC0_WL94  0x3780
+#define PFL1_SEC0_WL95  0x37C0
+#define PFL1_SEC0_WL96  0x3800
+#define PFL1_SEC0_WL97  0x3840
+#define PFL1_SEC0_WL98  0x3880
+#define PFL1_SEC0_WL99  0x38C0
+#define PFL1_SEC0_WL100 0x3900
+#define PFL1_SEC0_WL101 0x3940
+#define PFL1_SEC0_WL102 0x3980
+#define PFL1_SEC0_WL103 0x39C0
+#define PFL1_SEC0_WL104 0x3A00
+#define PFL1_SEC0_WL105 0x3A40
+#define PFL1_SEC0_WL106 0x3A80
+#define PFL1_SEC0_WL107 0x3AC0
+#define PFL1_SEC0_WL108 0x3B00
+#define PFL1_SEC0_WL109 0x3B40
+#define PFL1_SEC0_WL110 0x3B80
+#define PFL1_SEC0_WL111 0x3BC0
+#define PFL1_SEC0_WL112 0x3C00
+#define PFL1_SEC0_WL113 0x3C40
+#define PFL1_SEC0_WL114 0x3C80
+#define PFL1_SEC0_WL115 0x3CC0
+#define PFL1_SEC0_WL116 0x3D00
+#define PFL1_SEC0_WL117 0x3D40
+#define PFL1_SEC0_WL118 0x3D80
+#define PFL1_SEC0_WL119 0x3DC0
+
+// Sector 1 -- 256 bytes -- 4 Wordlines
+#define PFL1_SEC1_WL120 0x3E00
+#define PFL1_SEC1_WL121 0x3E40
+#define PFL1_SEC1_WL122 0x3E80
+#define PFL1_SEC1_WL123 0x3EC0
+
+// Sector 2 -- 256 bytes -- 4 Wordlines
+#define PFL1_SEC2_WL124 0x3F00
+#define PFL1_SEC2_WL125 0x3F40
+#define PFL1_SEC2_WL126 0x3F80
+#define PFL1_SEC2_WL127 0x3FC0
+
+//###################################################################################
+// WordLine startaddresses for Sectors in PFlash 2, each WL with 64bytes
+
+// Sector 0 -- 7.5 kbytes -- 120 Wordlines
+#define PFL2_SEC0_WL00  0x4000
+#define PFL2_SEC0_WL01  0x4040
+#define PFL2_SEC0_WL02  0x4080
+#define PFL2_SEC0_WL03  0x40C0
+#define PFL2_SEC0_WL04  0x4100
+#define PFL2_SEC0_WL05  0x4140
+#define PFL2_SEC0_WL06  0x4180
+#define PFL2_SEC0_WL07  0x41C0
+#define PFL2_SEC0_WL08  0x4200
+#define PFL2_SEC0_WL09  0x4240
+#define PFL2_SEC0_WL10  0x4280
+#define PFL2_SEC0_WL11  0x42C0
+#define PFL2_SEC0_WL12  0x4300
+#define PFL2_SEC0_WL13  0x4340
+#define PFL2_SEC0_WL14  0x4380
+#define PFL2_SEC0_WL15  0x43C0
+#define PFL2_SEC0_WL16  0x4400
+#define PFL2_SEC0_WL17  0x4440
+#define PFL2_SEC0_WL18  0x4480
+#define PFL2_SEC0_WL19  0x44C0
+#define PFL2_SEC0_WL20  0x4500
+#define PFL2_SEC0_WL21  0x4540
+#define PFL2_SEC0_WL22  0x4580
+#define PFL2_SEC0_WL23  0x45C0
+#define PFL2_SEC0_WL24  0x4600
+#define PFL2_SEC0_WL25  0x4640
+#define PFL2_SEC0_WL26  0x4680
+#define PFL2_SEC0_WL27  0x46C0
+#define PFL2_SEC0_WL28  0x4700
+#define PFL2_SEC0_WL29  0x4740
+#define PFL2_SEC0_WL30  0x4780
+#define PFL2_SEC0_WL31  0x47C0
+#define PFL2_SEC0_WL32  0x4800
+#define PFL2_SEC0_WL33  0x4840
+#define PFL2_SEC0_WL34  0x4880
+#define PFL2_SEC0_WL35  0x48C0
+#define PFL2_SEC0_WL36  0x4900
+#define PFL2_SEC0_WL37  0x4940
+#define PFL2_SEC0_WL38  0x4980
+#define PFL2_SEC0_WL39  0x49C0
+#define PFL2_SEC0_WL40  0x4A00
+#define PFL2_SEC0_WL41  0x4A40
+#define PFL2_SEC0_WL42  0x4A80
+#define PFL2_SEC0_WL43  0x4AC0
+#define PFL2_SEC0_WL44  0x4B00
+#define PFL2_SEC0_WL45  0x4B40
+#define PFL2_SEC0_WL46  0x4B80
+#define PFL2_SEC0_WL47  0x4BC0
+#define PFL2_SEC0_WL48  0x4C00
+#define PFL2_SEC0_WL49  0x4C40
+#define PFL2_SEC0_WL50  0x4C80
+#define PFL2_SEC0_WL51  0x4CC0
+#define PFL2_SEC0_WL52  0x4D00
+#define PFL2_SEC0_WL53  0x4D40
+#define PFL2_SEC0_WL54  0x4D80
+#define PFL2_SEC0_WL55  0x4DC0
+#define PFL2_SEC0_WL56  0x4E00
+#define PFL2_SEC0_WL57  0x4E40
+#define PFL2_SEC0_WL58  0x4E80
+#define PFL2_SEC0_WL59  0x4EC0
+#define PFL2_SEC0_WL60  0x4F00
+#define PFL2_SEC0_WL61  0x4F40
+#define PFL2_SEC0_WL62  0x4F80
+#define PFL2_SEC0_WL63  0x4FC0
+#define PFL2_SEC0_WL64  0x5000
+#define PFL2_SEC0_WL65  0x5040
+#define PFL2_SEC0_WL66  0x5080
+#define PFL2_SEC0_WL67  0x50C0
+#define PFL2_SEC0_WL68  0x5100
+#define PFL2_SEC0_WL69  0x5140
+#define PFL2_SEC0_WL70  0x5180
+#define PFL2_SEC0_WL71  0x51C0
+#define PFL2_SEC0_WL72  0x5200
+#define PFL2_SEC0_WL73  0x5240
+#define PFL2_SEC0_WL74  0x5280
+#define PFL2_SEC0_WL75  0x52C0
+#define PFL2_SEC0_WL76  0x5300
+#define PFL2_SEC0_WL77  0x5340
+#define PFL2_SEC0_WL78  0x5380
+#define PFL2_SEC0_WL79  0x53C0
+#define PFL2_SEC0_WL80  0x5400
+#define PFL2_SEC0_WL81  0x5440
+#define PFL2_SEC0_WL82  0x5480
+#define PFL2_SEC0_WL83  0x54C0
+#define PFL2_SEC0_WL84  0x5500
+#define PFL2_SEC0_WL85  0x5540
+#define PFL2_SEC0_WL86  0x5580
+#define PFL2_SEC0_WL87  0x55C0
+#define PFL2_SEC0_WL88  0x5600
+#define PFL2_SEC0_WL89  0x5640
+#define PFL2_SEC0_WL90  0x5680
+#define PFL2_SEC0_WL91  0x56C0
+#define PFL2_SEC0_WL92  0x5700
+#define PFL2_SEC0_WL93  0x5740
+#define PFL2_SEC0_WL94  0x5780
+#define PFL2_SEC0_WL95  0x57C0
+#define PFL2_SEC0_WL96  0x5800
+#define PFL2_SEC0_WL97  0x5840
+#define PFL2_SEC0_WL98  0x5880
+#define PFL2_SEC0_WL99  0x58C0
+#define PFL2_SEC0_WL100 0x5900
+#define PFL2_SEC0_WL101 0x5940
+#define PFL2_SEC0_WL102 0x5980
+#define PFL2_SEC0_WL103 0x59C0
+#define PFL2_SEC0_WL104 0x5A00
+#define PFL2_SEC0_WL105 0x5A40
+#define PFL2_SEC0_WL106 0x5A80
+#define PFL2_SEC0_WL107 0x5AC0
+#define PFL2_SEC0_WL108 0x5B00
+#define PFL2_SEC0_WL109 0x5B40
+#define PFL2_SEC0_WL110 0x5B80
+#define PFL2_SEC0_WL111 0x5BC0
+#define PFL2_SEC0_WL112 0x5C00
+#define PFL2_SEC0_WL113 0x5C40
+#define PFL2_SEC0_WL114 0x5C80
+#define PFL2_SEC0_WL115 0x5CC0
+#define PFL2_SEC0_WL116 0x5D00
+#define PFL2_SEC0_WL117 0x5D40
+#define PFL2_SEC0_WL118 0x5D80
+#define PFL2_SEC0_WL119 0x5DC0
+
+// Sector 1 -- 256 bytes -- 4 Wordlines
+#define PFL2_SEC1_WL120 0x5E00
+#define PFL2_SEC1_WL121 0x5E40
+#define PFL2_SEC1_WL122 0x5E80
+#define PFL2_SEC1_WL123 0x5EC0
+
+// Sector 2 -- 256 bytes -- 4 Wordlines
+#define PFL2_SEC2_WL124 0x5F00
+#define PFL2_SEC2_WL125 0x5F40
+#define PFL2_SEC2_WL126 0x5F80
+#define PFL2_SEC2_WL127 0x5FC0
+
+//###################################################################################
+// WordLine startaddresses for sectors in DFlash 0, each WL with 32bytes
+// DFlash 0 address is also mirrorred to 0x7xxx
+
+// Sector 0 -- 1024 bytes -- 32 Wordlines
+#define DFL0_SEC0_WL00  0xA000
+#define DFL0_SEC0_WL01  0xA020
+#define DFL0_SEC0_WL02  0xA040
+#define DFL0_SEC0_WL03  0xA060
+#define DFL0_SEC0_WL04  0xA080
+#define DFL0_SEC0_WL05  0xA0A0
+#define DFL0_SEC0_WL06  0xA0C0
+#define DFL0_SEC0_WL07  0xA0E0
+#define DFL0_SEC0_WL08  0xA100
+#define DFL0_SEC0_WL09  0xA120
+#define DFL0_SEC0_WL10  0xA140
+#define DFL0_SEC0_WL11  0xA160
+#define DFL0_SEC0_WL12  0xA180
+#define DFL0_SEC0_WL13  0xA1A0
+#define DFL0_SEC0_WL14  0xA1C0
+#define DFL0_SEC0_WL15  0xA1E0
+#define DFL0_SEC0_WL16  0xA200
+#define DFL0_SEC0_WL17  0xA220
+#define DFL0_SEC0_WL18  0xA240
+#define DFL0_SEC0_WL19  0xA260
+#define DFL0_SEC0_WL20  0xA280
+#define DFL0_SEC0_WL21  0xA2A0
+#define DFL0_SEC0_WL22  0xA2C0
+#define DFL0_SEC0_WL23  0xA2E0
+#define DFL0_SEC0_WL24  0xA300
+#define DFL0_SEC0_WL25  0xA320
+#define DFL0_SEC0_WL26  0xA340
+#define DFL0_SEC0_WL27  0xA360
+#define DFL0_SEC0_WL28  0xA380
+#define DFL0_SEC0_WL29  0xA3A0
+#define DFL0_SEC0_WL30  0xA3C0
+#define DFL0_SEC0_WL31  0xA3E0
+
+// Sector 1 -- 1024 bytes -- 32 Wordlines
+#define DFL0_SEC1_WL32  0xA400
+#define DFL0_SEC1_WL33  0xA420
+#define DFL0_SEC1_WL34  0xA440
+#define DFL0_SEC1_WL35  0xA460
+#define DFL0_SEC1_WL36  0xA480
+#define DFL0_SEC1_WL37  0xA4A0
+#define DFL0_SEC1_WL38  0xA4C0
+#define DFL0_SEC1_WL39  0xA4E0
+#define DFL0_SEC1_WL40  0xA500
+#define DFL0_SEC1_WL41  0xA520
+#define DFL0_SEC1_WL42  0xA540
+#define DFL0_SEC1_WL43  0xA560
+#define DFL0_SEC1_WL44  0xA580
+#define DFL0_SEC1_WL45  0xA5A0
+#define DFL0_SEC1_WL46  0xA5C0
+#define DFL0_SEC1_WL47  0xA5E0
+#define DFL0_SEC1_WL48  0xA600
+#define DFL0_SEC1_WL49  0xA620
+#define DFL0_SEC1_WL50  0xA640
+#define DFL0_SEC1_WL51  0xA660
+#define DFL0_SEC1_WL52  0xA680
+#define DFL0_SEC1_WL53  0xA6A0
+#define DFL0_SEC1_WL54  0xA6C0
+#define DFL0_SEC1_WL55  0xA6E0
+#define DFL0_SEC1_WL56  0xA700
+#define DFL0_SEC1_WL57  0xA720
+#define DFL0_SEC1_WL58  0xA740
+#define DFL0_SEC1_WL59  0xA760
+#define DFL0_SEC1_WL60  0xA780
+#define DFL0_SEC1_WL61  0xA7A0
+#define DFL0_SEC1_WL62  0xA7C0
+#define DFL0_SEC1_WL63  0xA7E0
+
+// Sector 2 -- 512 bytes -- 16 Wordlines
+#define DFL0_SEC2_WL64  0xA800
+#define DFL0_SEC2_WL65  0xA820
+#define DFL0_SEC2_WL66  0xA840
+#define DFL0_SEC2_WL67  0xA860
+#define DFL0_SEC2_WL68  0xA880
+#define DFL0_SEC2_WL69  0xA8A0
+#define DFL0_SEC2_WL70  0xA8C0
+#define DFL0_SEC2_WL71  0xA8E0
+#define DFL0_SEC2_WL72  0xA900
+#define DFL0_SEC2_WL73  0xA920
+#define DFL0_SEC2_WL74  0xA940
+#define DFL0_SEC2_WL75  0xA960
+#define DFL0_SEC2_WL76  0xA980
+#define DFL0_SEC2_WL77  0xA9A0
+#define DFL0_SEC2_WL78  0xA9C0
+#define DFL0_SEC2_WL79  0xA9E0
+
+// Sector 3 -- 512 bytes -- 16 Wordlines
+#define DFL0_SEC3_WL80  0xAA00
+#define DFL0_SEC3_WL81  0xAA20
+#define DFL0_SEC3_WL82  0xAA40
+#define DFL0_SEC3_WL83  0xAA60
+#define DFL0_SEC3_WL84  0xAA80
+#define DFL0_SEC3_WL85  0xAAA0
+#define DFL0_SEC3_WL86  0xAAC0
+#define DFL0_SEC3_WL87  0xAAE0
+#define DFL0_SEC3_WL88  0xAB00
+#define DFL0_SEC3_WL89  0xAB20
+#define DFL0_SEC3_WL90  0xAB40
+#define DFL0_SEC3_WL91  0xAB60
+#define DFL0_SEC3_WL92  0xAB80
+#define DFL0_SEC3_WL93  0xABA0
+#define DFL0_SEC3_WL94  0xABC0
+#define DFL0_SEC3_WL95  0xABE0
+
+// Sector 4 -- 256 bytes -- 8 Wordlines
+#define DFL0_SEC4_WL96  0xAC00
+#define DFL0_SEC4_WL97  0xAC20
+#define DFL0_SEC4_WL98  0xAC40
+#define DFL0_SEC4_WL99  0xAC60
+#define DFL0_SEC4_WL100 0xAC80
+#define DFL0_SEC4_WL101 0xACA0
+#define DFL0_SEC4_WL102 0xACC0
+#define DFL0_SEC4_WL103 0xACE0
+
+// Sector 5 -- 256 bytes -- 8 Wordlines
+#define DFL0_SEC5_WL104 0xAD00
+#define DFL0_SEC5_WL105 0xAD20
+#define DFL0_SEC5_WL106 0xAD40
+#define DFL0_SEC5_WL107 0xAD60
+#define DFL0_SEC5_WL108 0xAD80
+#define DFL0_SEC5_WL109 0xADA0
+#define DFL0_SEC5_WL110 0xADC0
+#define DFL0_SEC5_WL111 0xADE0
+
+// Sector 6 -- 128 bytes -- 4 Wordlines
+#define DFL0_SEC6_WL112 0xAE00
+#define DFL0_SEC6_WL113 0xAE20
+#define DFL0_SEC6_WL114 0xAE40
+#define DFL0_SEC6_WL115 0xAE60
+
+// Sector 7 -- 128 bytes -- 4 Wordlines
+#define DFL0_SEC7_WL116 0xAE80
+#define DFL0_SEC7_WL117 0xAEA0
+#define DFL0_SEC7_WL118 0xAEC0
+#define DFL0_SEC7_WL119 0xAEE0
+
+// Sector 8 -- 128 bytes -- 4 Wordlines
+#define DFL0_SEC8_WL120 0xAF00
+#define DFL0_SEC8_WL121 0xAF20
+#define DFL0_SEC8_WL122 0xAF40
+#define DFL0_SEC8_WL123 0xAF60
+
+// Sector 9 -- 128 bytes -- 4 Wordlines
+#define DFL0_SEC9_WL124 0xAF80
+#define DFL0_SEC9_WL125 0xAFA0
+#define DFL0_SEC9_WL126 0xAFC0
+#define DFL0_SEC9_WL127 0xAFE0
+
+//###################################################################################
+// WordLine startaddresses for sectors in DFlash 1, each WL with 32bytes
+// DFlash 0 address is also mirrorred to 0x6xxx
+
+// Sector 0 -- 1024 bytes -- 32 Wordlines
+#define DFL1_SEC0_WL00  0xA000
+#define DFL1_SEC0_WL01  0xA020
+#define DFL1_SEC0_WL02  0xA040
+#define DFL1_SEC0_WL03  0xA060
+#define DFL1_SEC0_WL04  0xA080
+#define DFL1_SEC0_WL05  0xA0A0
+#define DFL1_SEC0_WL06  0xA0C0
+#define DFL1_SEC0_WL07  0xA0E0
+#define DFL1_SEC0_WL08  0xA100
+#define DFL1_SEC0_WL09  0xA120
+#define DFL1_SEC0_WL10  0xA140
+#define DFL1_SEC0_WL11  0xA160
+#define DFL1_SEC0_WL12  0xA180
+#define DFL1_SEC0_WL13  0xA1A0
+#define DFL1_SEC0_WL14  0xA1C0
+#define DFL1_SEC0_WL15  0xA1E0
+#define DFL1_SEC0_WL16  0xA200
+#define DFL1_SEC0_WL17  0xA220
+#define DFL1_SEC0_WL18  0xA240
+#define DFL1_SEC0_WL19  0xA260
+#define DFL1_SEC0_WL20  0xA280
+#define DFL1_SEC0_WL21  0xA2A0
+#define DFL1_SEC0_WL22  0xA2C0
+#define DFL1_SEC0_WL23  0xA2E0
+#define DFL1_SEC0_WL24  0xA300
+#define DFL1_SEC0_WL25  0xA320
+#define DFL1_SEC0_WL26  0xA340
+#define DFL1_SEC0_WL27  0xA360
+#define DFL1_SEC0_WL28  0xA380
+#define DFL1_SEC0_WL29  0xA3A0
+#define DFL1_SEC0_WL30  0xA3C0
+#define DFL1_SEC0_WL31  0xA3E0
+
+// Sector 1 -- 1024 bytes -- 32 Wordlines
+#define DFL1_SEC1_WL32  0xA400
+#define DFL1_SEC1_WL33  0xA420
+#define DFL1_SEC1_WL34  0xA440
+#define DFL1_SEC1_WL35  0xA460
+#define DFL1_SEC1_WL36  0xA480
+#define DFL1_SEC1_WL37  0xA4A0
+#define DFL1_SEC1_WL38  0xA4C0
+#define DFL1_SEC1_WL39  0xA4E0
+#define DFL1_SEC1_WL40  0xA500
+#define DFL1_SEC1_WL41  0xA520
+#define DFL1_SEC1_WL42  0xA540
+#define DFL1_SEC1_WL43  0xA560
+#define DFL1_SEC1_WL44  0xA580
+#define DFL1_SEC1_WL45  0xA5A0
+#define DFL1_SEC1_WL46  0xA5C0
+#define DFL1_SEC1_WL47  0xA5E0
+#define DFL1_SEC1_WL48  0xA600
+#define DFL1_SEC1_WL49  0xA620
+#define DFL1_SEC1_WL50  0xA640
+#define DFL1_SEC1_WL51  0xA660
+#define DFL1_SEC1_WL52  0xA680
+#define DFL1_SEC1_WL53  0xA6A0
+#define DFL1_SEC1_WL54  0xA6C0
+#define DFL1_SEC1_WL55  0xA6E0
+#define DFL1_SEC1_WL56  0xA700
+#define DFL1_SEC1_WL57  0xA720
+#define DFL1_SEC1_WL58  0xA740
+#define DFL1_SEC1_WL59  0xA760
+#define DFL1_SEC1_WL60  0xA780
+#define DFL1_SEC1_WL61  0xA7A0
+#define DFL1_SEC1_WL62  0xA7C0
+#define DFL1_SEC1_WL63  0xA7E0
+
+// Sector 2 -- 512 bytes -- 16 Wordlines
+#define DFL1_SEC2_WL64  0xA800
+#define DFL1_SEC2_WL65  0xA820
+#define DFL1_SEC2_WL66  0xA840
+#define DFL1_SEC2_WL67  0xA860
+#define DFL1_SEC2_WL68  0xA880
+#define DFL1_SEC2_WL69  0xA8A0
+#define DFL1_SEC2_WL70  0xA8C0
+#define DFL1_SEC2_WL71  0xA8E0
+#define DFL1_SEC2_WL72  0xA900
+#define DFL1_SEC2_WL73  0xA920
+#define DFL1_SEC2_WL74  0xA940
+#define DFL1_SEC2_WL75  0xA960
+#define DFL1_SEC2_WL76  0xA980
+#define DFL1_SEC2_WL77  0xA9A0
+#define DFL1_SEC2_WL78  0xA9C0
+#define DFL1_SEC2_WL79  0xA9E0
+
+// Sector 3 -- 512 bytes -- 16 Wordlines
+#define DFL1_SEC3_WL80  0xAA00
+#define DFL1_SEC3_WL81  0xAA20
+#define DFL1_SEC3_WL82  0xAA40
+#define DFL1_SEC3_WL83  0xAA60
+#define DFL1_SEC3_WL84  0xAA80
+#define DFL1_SEC3_WL85  0xAAA0
+#define DFL1_SEC3_WL86  0xAAC0
+#define DFL1_SEC3_WL87  0xAAE0
+#define DFL1_SEC3_WL88  0xAB00
+#define DFL1_SEC3_WL89  0xAB20
+#define DFL1_SEC3_WL90  0xAB40
+#define DFL1_SEC3_WL91  0xAB60
+#define DFL1_SEC3_WL92  0xAB80
+#define DFL1_SEC3_WL93  0xABA0
+#define DFL1_SEC3_WL94  0xABC0
+#define DFL1_SEC3_WL95  0xABE0
+
+// Sector 4 -- 256 bytes -- 8 Wordlines
+#define DFL1_SEC4_WL96  0xAC00
+#define DFL1_SEC4_WL97  0xAC20
+#define DFL1_SEC4_WL98  0xAC40
+#define DFL1_SEC4_WL99  0xAC60
+#define DFL1_SEC4_WL100 0xAC80
+#define DFL1_SEC4_WL101 0xACA0
+#define DFL1_SEC4_WL102 0xACC0
+#define DFL1_SEC4_WL103 0xACE0
+
+// Sector 5 -- 256 bytes -- 8 Wordlines
+#define DFL1_SEC5_WL104 0xAD00
+#define DFL1_SEC5_WL105 0xAD20
+#define DFL1_SEC5_WL106 0xAD40
+#define DFL1_SEC5_WL107 0xAD60
+#define DFL1_SEC5_WL108 0xAD80
+#define DFL1_SEC5_WL109 0xADA0
+#define DFL1_SEC5_WL110 0xADC0
+#define DFL1_SEC5_WL111 0xADE0
+
+// Sector 6 -- 128 bytes -- 4 Wordlines
+#define DFL1_SEC6_WL112 0xAE00
+#define DFL1_SEC6_WL113 0xAE20
+#define DFL1_SEC6_WL114 0xAE40
+#define DFL1_SEC6_WL115 0xAE60
+
+// Sector 7 -- 128 bytes -- 4 Wordlines
+#define DFL1_SEC7_WL116 0xAE80
+#define DFL1_SEC7_WL117 0xAEA0
+#define DFL1_SEC7_WL118 0xAEC0
+#define DFL1_SEC7_WL119 0xAEE0
+
+// Sector 8 -- 128 bytes -- 4 Wordlines
+#define DFL1_SEC8_WL120 0xAF00
+#define DFL1_SEC8_WL121 0xAF20
+#define DFL1_SEC8_WL122 0xAF40
+#define DFL1_SEC8_WL123 0xAF60
+
+// Sector 9 -- 128 bytes -- 4 Wordlines
+#define DFL1_SEC9_WL124 0xAF80
+#define DFL1_SEC9_WL125 0xAFA0
+#define DFL1_SEC9_WL126 0xAFC0
+#define DFL1_SEC9_WL127 0xAFE0
+
+#endif  // #ifndef  __XC88x_FLADDR_H__
diff --git a/XC88x_FLHANDLER.ASM b/XC88x_FLHANDLER.ASM
new file mode 100644
index 0000000..6c49a6b
--- /dev/null
+++ b/XC88x_FLHANDLER.ASM
@@ -0,0 +1,166 @@
+;************************************************************************************
+;*  FILE        : XC88x_FLHANDLER.ASM                                               *
+;*  DESCRIPTION : Flash handler routine for XC88x AA and AB                                *
+;*  COPYRIGHT   : (c) 2006 Infineon Technologies AG                                 *
+;*  UPDATED     : 14/03/2006                                                        *
+;************************************************************************************
+$ NOMOD51
+$ DEBUG
+#include "XC88x_FLADDR.H"  
+
+FLASH_ERASE        CODE  FLASH_ERASE_BROM_ENTRY
+FLASH_PROG         CODE  FLASH_PROGRAM_BROM_ENTRY
+FLASH_ERASE_ABORT  CODE  FLASH_ERASE_ABORT_BROM_ENTRY
+FLASH_READ_STATUS  CODE  FLASH_READ_STATUS_BROM_ENTRY
+FLASH_PROTECT      CODE  FLASH_PROTECT_BROM_ENTRY
+     
+DSEG AT  MAGIC_MEMORY
+DS   RESERVED_BYTES                        ; Reserved for FLASH Handler in Boot ROM
+
+
+
+
+;------------------------------------------------------------------------------------------
+; Function Name   : bit DFlErase (unsigned int DFlash0Sector, unsigned int DFlash1Sector)
+; Description     : Erase DFlash Sectors (Bank3 and Bank4)
+; Input Parameter : DFlash0Sector => Bit0 = Erase Sector0
+;                                    Bit1 = Erase Sector1
+;                                    Bit2 = Erase Sector2
+;                                    Bit3 = Erase Sector3
+;                                    Bit4 = Erase Sector4
+;                                    Bit5 = Erase Sector5
+;                                    Bit6 = Erase Sector6
+;                                    Bit7 = Erase Sector7
+;                                    Bit8 = Erase Sector8
+;                                    Bit9 = Erase Sector9
+;                   DFlash1Sector => Bit0 = Erase Sector0
+;                                    Bit1 = Erase Sector1
+;                                    Bit2 = Erase Sector2
+;                                    Bit3 = Erase Sector3
+;                                    Bit4 = Erase Sector4
+;                                    Bit5 = Erase Sector5
+;                                    Bit6 = Erase Sector6
+;                                    Bit7 = Erase Sector7
+;                                    Bit8 = Erase Sector8
+;                                    Bit9 = Erase Sector9
+;                                                   
+;                   e.g: DFlash0Sector = 0x202
+;                        DFlash1Sector = 0x380
+;                         ==> Will erase Bank3 Sector 1
+;                                  erase Bank3 Sector 9
+;                                  erase Bank4 Sector 7
+;                                  erase Bank4 Sector 8
+;                                  erase Bank4 Sector 9
+; Return Value    : Bit => 1 = Successfull
+;                          0 = Fail
+; Required Stack Size = 12
+;------------------------------------------------------------------------------------------
+#if USE_DLFERASE
+?PR?_DFlErase?XC88x_FLHANDLER SEGMENT CODE    
+RSEG ?PR?_DFlErase?XC88x_FLHANDLER
+PUBLIC _DFlErase
+_DFlErase:
+  USING  USE_BANK
+  MOV  AR1,R6  ; BANK3
+  MOV  AR0,R7  ; BANK3
+
+  MOV  AR4,R4 ; BANK4
+  MOV  AR3,R5 ; BANK4
+
+  CLR    A
+  MOV    AR5, A ; BANK0
+  MOV    AR6, A ; BANK1
+  MOV    AR7, A ; BANK2
+
+  PUSH   PSW
+	PUSH   ACC
+	PUSH   B
+#if (USE_BANK == 0)
+  ANL    PSW, #0xE7      ; Set to Bank0
+#elseif (USE_BANK == 1)
+  SETB   PSW.3
+  CLR    PSW.4
+#elif (USE_BANK == 2)
+  CLR    PSW.3
+  SETB   PSW.4
+#elif (USE_BANK == 3)
+  ORL    PSW, #0x18
+#endif 
+
+  LCALL  FLASH_ERASE
+  JC     _derase_fail
+	POP    B
+	POP    ACC
+  POP    PSW
+  SETB   C
+  RET
+_derase_fail:
+	POP    B
+	POP    ACC
+  POP    PSW
+  CLR    C
+RET
+#endif
+
+;------------------------------------------------------------------------------------------
+; Function Name:   bit FlProg(unsigned char idata *WlBuf)
+; Description:     Program the 32byte data in the WlBuf to the EEPROM
+;                  When calling this function, user should already programmed
+;                  the DPTR with the EEPROM address (aligned to 32byte boundary)
+; Input Parameter: *WlBuf  ==> The pointer to the starting location of the buffer
+;                              in the IDATA memory.
+; Return Value:    Bit => 1 = Successfull
+;                         0 = Fail
+; Required Stack Size = 12
+;------------------------------------------------------------------------------------------
+?PR?_FlProg?XC88x_FLHANDLER SEGMENT CODE    
+RSEG ?PR?_FlProg?XC88x_FLHANDLER
+PUBLIC _FlProg
+_FlProg:
+using USE_BANK
+  MOV   AR0,R7          ; move C51 parameter registers to AR0
+                       ; this is the pointer to the WLBuf
+											 
+;	MOV		A,#0x6F			
+;	MOV		DPH,A
+;	MOV		A,#0x0		; the DPL will = DPL+0x20 after one successful program	
+;	MOV		DPL,A											 
+											 
+  PUSH   PSW
+	PUSH   ACC
+	PUSH   B
+#if (USE_BANK == 0)
+  ANL    PSW, #0xE7      ; Set to Bank0
+#elif (USE_BANK == 1)
+  SETB   PSW.3
+  CLR    PSW.4
+#elif (USE_BANK == 2)
+  CLR    PSW.3
+  SETB   PSW.4
+#elif (USE_BANK == 3)
+  ORL    PSW, #0x18
+#endif
+	
+  LCALL  FLASH_PROG     ; LCALL FLASH_PROG
+  JC     _prog_fail
+	POP    B
+	POP    ACC
+  POP    PSW
+  SETB   C
+  RET
+_prog_fail:
+	POP    B
+	POP    ACC
+  POP    PSW
+  CLR    C
+RET
+
+
+
+
+
+
+
+END
+        
+;;#endif    ;;#if (XC88xAA)
diff --git a/XC8Memory.c b/XC8Memory.c
new file mode 100644
index 0000000..deab615
--- /dev/null
+++ b/XC8Memory.c
@@ -0,0 +1,134 @@
+//****************************************************************************
+// File Name     XC8Memory.c
+//----------------------------------------------------------------------------
+// Derivatives   Infineon XC88x AA and AB
+//
+// Description   Sets of function to handle the memory in the XC88x AA.
+//               In particular, the Flash handling is taken care of here.
+//
+//----------------------------------------------------------------------------
+// Date          14.03.2006 10:48:38
+// Copyright     (c) 2006 Infineon Technologies
+//****************************************************************************
+
+#include "XC8Memory.h"
+
+/*
+// **************************************************************************
+// Function Name:    void LoadXD2WLBuf (unsigned char xdata *address)
+// Description:      Load  32byte of data from the XDATA to the WLBuf
+//                   WLBuf is a buffer that is located in the IDATA-space
+// Input Parameter:  *address ==>  pointer to the address
+//                                 in the XDATA memory
+// Output Parameter: none
+
+// NOTE: Execution time and code can saved, 
+//       if you have the possibility to write directly in
+//       the buffer
+// **************************************************************************
+void LoadXD2WLBuf(unsigned char xdata *address)
+{
+// Loads Wordline Buffer with 32bytes from given address in XDATA
+unsigned char i;
+ for (i=0; i  pointer to the address
+//            in the CODE memory
+// Output Parameter: none
+
+// NOTE: Execution time and code can saved, 
+//       if you have the possibility to write directly in
+//       the buffer
+// ***********************************************************************
+void LoadConst2WLBuf(unsigned char code *address)
+{
+// Loads Wordline Buffer with 32bytes from given address in CODE
+unsigned char i;
+ for (i=0; i pointer to the location in the FLASH.
+//                                       The address must be aligned to a 32byte boundary
+// Output Parameter: 1 = Success
+//                   0 = Fail
+// Note:             used Stack Size = 12
+// **************************************************************************************
+bit ProgWL(unsigned char code *AdrBnkXSecYWLZ)
+{
+unsigned int i;
+ i = AdrBnkXSecYWLZ;
+ MEM_DPH = i>>8;
+ MEM_DPL = i;
+ return (FlProg(&WLBuf[0]));
+}
+
+// *************************************************************************************
+// Function Name:    void LoadConst2XD (unsigned char xdata *dstaddress, 
+//                   unsigned char code *srcaddress, unsigned int length)
+// Description:      Copy the data from the CODE memory to XDATA memory
+// Input Parameter:  *srcaddress ==> pointer to the location in the FLASH/EEPROM.
+//                   lenght      ==> The number of byte to be copied
+// Output Parameter: *dstaddress ==> pointer to the location in the XDATA memory.
+//                                   The data will be copied to this location
+
+// NOTE: Execution time and code can saved, 
+//       if you have the possibility to write directly in
+//       the buffer
+// *************************************************************************************
+void LoadConst2XD(unsigned char xdata *dstaddress, unsigned char code *srcaddress, unsigned char length)
+{
+// Loads number of constants to XDATA at given addresses
+unsigned char i;
+ for (i=0; i pointer to the location in the XDATA memory.
+//                                   No byte alignment is necessary
+//                   lenght      ==> The number of byte to be copied
+// Output Parameter: *dstaddress ==> pointer to the location in the XDATA memory.
+//                                   The data will be copied to this location
+//
+// NOTE: Execution time and code can saved, 
+//       if you have the possibility to write directly in
+//       the buffer
+// *************************************************************************************
+void LoadXD2XD(unsigned char xdata *dstaddress, unsigned char xdata *srcaddress, unsigned int length)
+{
+// Copies number of bytes in XDATA to XDATA at given addresses
+unsigned int i;
+ for (i=0; i pointer to the location in the CODE memory.
+//                                No byte alignment is necessary
+// Return Value:  Data Byte
+// *************************************************************************************
+unsigned char ReadConst(unsigned char code *address)
+{
+ return (*address);
+}
+
+*/
\ No newline at end of file
diff --git a/XC8Memory.h b/XC8Memory.h
new file mode 100644
index 0000000..0b13e87
--- /dev/null
+++ b/XC8Memory.h
@@ -0,0 +1,72 @@
+//****************************************************************************
+// File Name     XC8Memory.h
+//----------------------------------------------------------------------------
+// Derivatives   Infineon XC88x AA and AB
+//
+// Description   Sets of function to handle the memory in the XC88x AA.
+//               In particular, the Flash handling is taken care of here.
+//
+//----------------------------------------------------------------------------
+// Date          14.03.2006 10:48:38
+// Copyright     (c) 2006 Infineon Technologies
+//****************************************************************************
+
+// Header for XC8Memory.c
+// Memory handling of XC88x AA derivatives
+
+#ifndef _XC8MEMORY_H_
+#define _XC8MEMORY_H_
+
+#include "XC88x_FLADDR.H"
+
+
+//+------------------------------------------------+
+//|   Global variables needed
+//+------------------------------------------------+
+// Buffer for the 32byte data before being written to eEPROM
+extern unsigned char idata WLBuf[BYTES_PER_WORDLINE];
+
+// Function to program the WLBuf to Flash Memory
+bit ProgWL(unsigned char code *AdrBnkXSecYWLZ);
+// Function to load the data from XDATA memory to WLBuf
+void LoadXD2WLBuf(unsigned char xdata *address);
+// Function to load the data from CODE memory to WLBuf
+// This is used to copy data from one Flash location to another.
+void LoadConst2WLBuf(unsigned char code *address);
+// Function to load the data from CODE memory to XDATA memory
+void LoadConst2XD(unsigned char xdata *dstaddress, unsigned char code *srcaddress, unsigned char length);
+// Function to read a byte from CODE memory
+unsigned char ReadConst(unsigned char code *address);
+
+// All of the description of the functions below is done in XC88x_FLHANDER.ASM
+// Erase Flash Sectors
+// Required Stack Size = 12
+extern bit PFlErase (unsigned char Bank0Sector, unsigned char Bank1Sector, unsigned char Bank2Sector);
+extern bit DFlErase (unsigned int DFlash0Sector, unsigned int DFlash1Sector);
+
+// Program Flash
+// Required Stack Size = 12
+extern bit FlProg(unsigned char idata *SrcBuf);
+
+// Check if Flash is ready to read
+// Bank = Bank Number to be checked
+// Required Stack Size = 6
+extern bit FlReady(unsigned char Bank);
+
+// Abort the existing erase process
+// Required Stack Size = 6
+extern bit FlEraseAbort(void);
+
+// Program / Remove Password.
+// Detail is available in FLHANDLER.asm
+extern bit FlProtect(unsigned char Password);
+
+extern unsigned char _FlReadByte(void);
+extern void FlExecute(unsigned char AddrH, unsigned char AddrL);
+
+sfr MEM_DPH    = 0x83;    
+sfr MEM_DPL    = 0x82;
+sfr MEM_NMICON = 0xBB;
+sfr MEM_NMISR  = 0xBC;
+
+#endif  // _XC8MEMORY_H_
diff --git a/boot.H b/boot.H
new file mode 100644
index 0000000..b11c0cf
--- /dev/null
+++ b/boot.H
@@ -0,0 +1,79 @@
+#ifndef _BOOT_H_
+#define _BOOT_H_
+#include "XC88x_FLADDR.H"
+
+#define ArrXram ((ubyte volatile xdata *)0xf000)
+#define DF_XramLenth 0x600
+#define ArrBootCode ((ubyte volatile code *)0x7000)
+#define DF_BootCodeLenth 0x600
+
+
+
+#define ACKNOWLEDGE      0x55
+#define BLOCK_ERROR      0xFF
+#define TIMEOUT_ERROR    0xF0
+#define PROTECTION_ERROR 0xFD
+
+#define RX_MSGOBJ        5
+#define TX_MSGOBJ        9		  // Define the Message Object for Transmit (No FIFO// is supported for Transmit)
+
+
+//---ⲿҪʹñ---------------------------------------------------------------------
+void BootMain(void);
+void CAN_waitTransmit(ubyte RgMsgobj);
+
+
+
+//+------------------------------------------------+
+//|   Global variables needed
+//+------------------------------------------------+
+// Buffer for the 32byte data before being written to eEPROM
+extern unsigned char idata WLBuf[BYTES_PER_WORDLINE];
+
+// Function to program the WLBuf to Flash Memory
+bit ProgWL(unsigned char code *AdrBnkXSecYWLZ);
+// Function to load the data from XDATA memory to WLBuf
+void LoadXD2WLBuf(unsigned char xdata *address);
+// Function to load the data from CODE memory to WLBuf
+// This is used to copy data from one Flash location to another.
+void LoadConst2WLBuf(unsigned char code *address);
+// Function to load the data from CODE memory to XDATA memory
+void LoadConst2XD(unsigned char xdata *dstaddress, unsigned char code *srcaddress, unsigned char length);
+// Function to read a byte from CODE memory
+unsigned char ReadConst(unsigned char code *address);
+
+// All of the description of the functions below is done in XC88x_FLHANDER.ASM
+// Erase Flash Sectors
+// Required Stack Size = 12
+extern bit PFlErase (unsigned char Bank0Sector, unsigned char Bank1Sector, unsigned char Bank2Sector);
+extern bit DFlErase (unsigned int DFlash0Sector, unsigned int DFlash1Sector);
+
+// Program Flash
+// Required Stack Size = 12
+extern bit FlProg(unsigned char idata *SrcBuf);
+
+// Check if Flash is ready to read
+// Bank = Bank Number to be checked
+// Required Stack Size = 6
+extern bit FlReady(unsigned char Bank);
+
+// Abort the existing erase process
+// Required Stack Size = 6
+extern bit FlEraseAbort(void);
+
+// Program / Remove Password.
+// Detail is available in FLHANDLER.asm
+extern bit FlProtect(unsigned char Password);
+
+extern unsigned char _FlReadByte(void);
+extern void FlExecute(unsigned char AddrH, unsigned char AddrL);
+
+sfr MEM_DPH    = 0x83;    
+sfr MEM_DPL    = 0x82;
+sfr MEM_NMICON = 0xBB;
+sfr MEM_NMISR  = 0xBC;
+
+
+
+
+#endif
\ No newline at end of file
diff --git a/boot.c b/boot.c
new file mode 100644
index 0000000..a292d16
--- /dev/null
+++ b/boot.c
@@ -0,0 +1,128 @@
+#include "MAIN.H" 
+	ubyte idata WLBuf[32] _at_ 0x80;
+// This function will generate a Watchdog Reset
+// The reset will be generated in about 21 us
+void CAN_setWDTReset(void)
+{
+  SFR_PAGE(_su1, noSST);         // switch to page1 without saving
+  MAIN_vUnlockProtecReg();       // open access to protected register
+
+  SET_RMAP(); 
+  WDTCON |= 0x04;     //   set   WDTEN
+  WDTREL = 0xFF;      //Watch dog timer reload register
+  WDTCON |= 0x03;                // set WDTRS,set WDTIN
+  RESET_RMAP(); 
+
+  MAIN_vlockProtecReg();         // close access to protected register
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+	
+   while(1);
+}
+
+
+void CAN_waitTransmit(ubyte RgMsgobj)
+{
+	ulong i;
+	for(i=0;(i<6000)&&(!CAN_ubRequestMsgObj(RgMsgobj));i++)WDT_vRefresh();
+}
+
+
+// CAN Acknowledge Frame consist of 2 data bytes.
+// The first data byte is the Acknowledge Code
+// The second data byte is the valid data depending on the Acknowledge Code
+// TX_MSGOBJ is set to one Message object only.
+void CAN_sendAck(ubyte Ack0,ubyte Ack1)
+{
+	ubyte Arrtmp[8] = {0};
+//--------------------------------------------
+	Arrtmp[3] = Ack0;
+	Arrtmp[2] = Ack1;
+
+	CAN_vLoadData(TX_MSGOBJ, (ulong *)(Arrtmp)); // Add this Line			
+	CAN_vTransmit(TX_MSGOBJ);
+	CAN_waitTransmit(TX_MSGOBJ);
+}
+
+
+
+
+// Flash_Wait does not take care of the timeout.
+// In case programming / erasing fail, it will automatically reset the chip.
+// (to be implemented)
+void Flash_Wait(void)
+{
+	ubyte ubCount0, ubCount1, ubCount2;
+
+	SYSCON0  = SYSCON0 & 0xFE;
+	SCU_PAGE = 0;                 // Mandatory
+	for (ubCount2=0; ubCount2 < 50; ubCount2++) 
+		{
+			for (ubCount1=0; ubCount1 < 255; ubCount1++) 
+			{
+				for (ubCount0=0; ubCount0 < 255; ubCount0++) 
+				{
+					if (NMISR & 0x4) 
+					{
+						NMISR &= ~0x04;
+						return;
+					}
+				}
+			}
+		}
+	CAN_setWDTReset();
+}
+
+
+
+void BootMain(void)
+{
+	stCAN_SWObj  StrBootRx;
+	ubyte  ulCANData[8];
+	ubyte i;
+
+//------------------------------------	
+	if(CAN_ubNewData(RX_MSGOBJ))
+	{
+		CAN_vGetMsgObj(RX_MSGOBJ, &StrBootRx);	
+		ulCANData[3] = StrBootRx.ulDATAL.ubDB[0];
+		ulCANData[2] = StrBootRx.ulDATAL.ubDB[1];
+		ulCANData[1] = StrBootRx.ulDATAL.ubDB[2];
+		ulCANData[0] = StrBootRx.ulDATAL.ubDB[3];
+		ulCANData[7] = StrBootRx.ulDATAH.ubDB[0];
+		ulCANData[6] = StrBootRx.ulDATAH.ubDB[1];
+		ulCANData[5] = StrBootRx.ulDATAH.ubDB[2];
+		ulCANData[4] = StrBootRx.ulDATAH.ubDB[3];
+		CAN_vReleaseObj(RX_MSGOBJ);
+		
+		EA = 0;
+		TR2 = 0;
+		WDT_vDisable();//WDTbootлλ	
+//------------------------------------------------------------				
+		if((ulCANData[0] == 0xaa) && (ulCANData[1] == 0xaa))//
+		{
+			CAN_sendAck(ACKNOWLEDGE, 0x01);
+			CAN_setWDTReset();
+		}	
+//------------------------------------------------------------	
+		else if((ulCANData[0] == 0x33) && (ulCANData[1] == 0x33))//11
+		{
+			SCU_PAGE = 0;	
+	    NMISR    = 0;	
+      DFlErase(0x0, 0x0300);//bank1 sector 89
+      Flash_Wait();  // In case fail, the chip will generate WDT Reset			
+			
+			for(i=0;i<32;i++)
+			{
+				WLBuf[i] = 0;
+			}			
+			WLBuf[0] = 0x11;//̱ʶ,0x6F00
+			DPH = 0x6F;
+			DPL = 0;	
+			FlProg(&WLBuf[0]);
+      Flash_Wait();  // In case fail, the chip will generate WDT Reset					
+			CAN_sendAck(ACKNOWLEDGE, 0x04);
+		}	
+//------------------------------------------------------------			
+		else ;
+	}		
+}
\ No newline at end of file
diff --git a/temperature.C b/temperature.C
new file mode 100644
index 0000000..46903d6
--- /dev/null
+++ b/temperature.C
@@ -0,0 +1,522 @@
+#include "temperature.H"
+#include 
+#include 
+
+UnSwSample  UnSwSample_1 = {0};
+#define Measure_Period 11000
+
+unsigned char romid[MAXNUM][8];
+int RomNum;
+
+/**
+  * @brief  ֽеУ
+  * @param  serialָֽ
+  * @param  lengthֽij
+  * @retval УͣCRC
+*/
+#define POLYNOMIAL 	0x131 //100110001
+ubyte MY_OW_CRC8(ubyte *serial, ubyte length) 
+{
+    ubyte result = 0x00;
+    ubyte pDataBuf;
+    ubyte i;
+
+    while(length--) {
+        pDataBuf = *serial++;
+        for(i=0; i<8; i++) {
+            if((result^(pDataBuf))&0x01) {
+                result ^= 0x18;
+                result >>= 1;
+                result |= 0x80;
+            }
+            else {
+                result >>= 1;
+            }
+            pDataBuf >>= 1;
+        }
+    }
+		
+    return result;
+}
+
+
+//Ǿȷʱ2*X us̶10us
+//@12.000MHz 12Tģʽ
+void Delay_us(uword x)
+{
+	for (; x > 0; x--)
+	{
+		_nop_();
+		_nop_();
+	}
+}
+
+////////////////////////////////////////////////////////////////////
+//  λ壨  480 us ͵ƽ   
+unsigned char OW_ResetPresence(void)
+{
+	unsigned char presence; int count=0;
+
+	SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  P3_DIR | 0x20;      // load direction register	 P3.5лΪ
+	
+	DQ = 0;                        //  DQ 
+	Delay_us(240);                 //  DQ   480us
+	DQ = 1;                        // ͷߣ
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  P3_DIR & 0xDF;// load direction register	
+	
+	Delay_us(40);                                // ȴ 80us  presence
+	presence = DQ;                               //  
+	while( presence && (count< 17) )
+	{
+		Delay_us(5);
+		presence = DQ;
+		count++;
+	}
+	Delay_us(200);                             // ʱĩβ ȴ
+	return (presence ? FALSE : TRUE); 
+}                                              // presence =0 ʱ M6 01  , presence =1 ʱ M601 
+
+////////////////////////////////////////////////////////////////////
+//// READ_BIT C  M601 ȡ һλ
+unsigned char read_bit(void) 
+{
+	unsigned char res;
+
+	SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  P3_DIR | 0x20;      // load direction register	 лΪ״̬	
+	
+  DQ = 0;                        //  DQ 
+  Delay_us(1);                   //  DQ   3us
+  DQ = 1;                        // ͷ DQ ߣ
+	SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  P3_DIR & 0xDF;// load direction register
+	
+  Delay_us(3);                   // ȴ 10us ȷȶ
+
+  res = DQ;                     
+  Delay_us(27);                        // ʱĩβ ȴ
+  return(res);                           // ضȡ ֵ
+}
+
+////////////////////////////////////////////////////////////////////
+//// WRITE_BIT C  дһλ  M601
+void write_bit(char bitval) 
+{
+	SFR_PAGE(_pp0, noSST);                // switch to page 0
+  P3_DIR  =  P3_DIR | 0x20;             // load direction register	 лΪ״̬
+	
+	DQ = 0;                              	//  DQ 
+  Delay_us(2);                          //  DQ   5us
+	if(bitval == 1) DQ =1;                //  д 1ʱ DQ 
+  Delay_us(25);                         //  д 0 DQ  60 us
+  DQ = 1;                               // ͷ DQ 
+  Delay_us(5);                          // д 0ָ ʱ 10us
+}
+
+/////////////////////////////////////////////////////////////////////
+//// READ_BYTE -  M601 ȡ һֽ 
+unsigned char OW_ReadByte(void) 
+{
+	unsigned char i, j;
+	unsigned char value = 0;
+	for (i = 0;i < 8;i++) {
+		j = read_bit();
+		value = (value) | (j<> i;
+		temp &= 0x01;                                  // λ 
+		write_bit(temp);
+	}
+}
+
+
+/**
+  * @brief  оƬĴݴ
+  * @param  scrָֽ룬 Ϊ @sizeofM601_SCRATCHPAD_READ
+  * @retval ״̬
+*/
+BOOL M601_ReadScratchpad_SkipRom(ubyte *scr)
+{
+    int i;
+
+//	/*size < sizeof(M601_SCRATCHPAD_READ)*/
+    if(OW_ResetPresence() == FALSE)					
+			return FALSE;
+		
+    OW_WriteByte(SKIP_ROM);
+    OW_WriteByte(READ_SCRATCHPAD);
+		
+		for(i=0; i < sizeof(M601_SCRATCHPAD_READ); i++)
+    {
+			*scr++ = OW_ReadByte();
+		}
+
+    return TRUE;
+}
+
+/**
+  * @brief  доƬĴݴ
+  * @param  scrָֽ룬 Ϊ @sizeofM601_SCRATCHPAD_WRITE
+  * @retval д״̬
+**/
+BOOL M601_WriteScratchpad_SkipRom(ubyte *scr)
+{
+    int i;
+
+    if(OW_ResetPresence() == FALSE)						
+			return FALSE;
+		
+    OW_WriteByte(SKIP_ROM);
+    OW_WriteByte(WRITE_SCRATCHPAD);
+		
+		for(i=0; i < sizeof(M601_SCRATCHPAD_WRITE); i++)
+    {
+			OW_WriteByte(*scr++);
+		}
+
+    return TRUE;
+}
+
+
+
+/**
+  * @brief  ڲƵʺظ
+  * @param  mps ҪõڲƵʣÿΪһ
+	*				@arg CFG_MPS_Single		ÿִConvertTempһΣһ¶Ȳ
+	*				@arg CFG_MPS_Half			ÿִConvertTempһΣÿ0.5ظ
+	*				@arg CFG_MPS_1				ÿִConvertTempһΣÿ1ظ
+	*				@arg CFG_MPS_2				ÿִConvertTempһΣÿ2ظ
+	*				@arg CFG_MPS_4				ÿִConvertTempһΣÿ4ظ
+	*				@arg CFG_MPS_10				ÿִConvertTempһΣÿ10ظ
+  * @param  repeatabilityҪõظֵΪһ
+	*				@arg CFG_Repeatbility_Low				õظ
+	*				@arg CFG_Repeatbility_Medium		ظ
+	*				@arg CFG_Repeatbility_High			øظ
+  * @retval 
+*/
+BOOL SetConfig(ubyte mps, ubyte repeatability)
+{ 
+	ubyte scrb[sizeof(M601_SCRATCHPAD_READ)];
+	M601_SCRATCHPAD_READ *scr = (M601_SCRATCHPAD_READ *) scrb;
+
+	/*9ֽڡ7ֽϵͳüĴ8ֽϵͳ״̬Ĵֽǰ8У--CRC*/	
+	if(M601_ReadScratchpad_SkipRom(scrb) == FALSE)
+	{	
+		return FALSE;  /*ݴˮƽ*/
+	}
+
+	/*յǰ8ֽڵУͣյĵ9CRCֽڱȽϡ*/	
+  if(scrb[8] != MY_OW_CRC8(scrb, 8))
+  {			
+		return FALSE;  /*CRC֤δͨ*/
+  }
+	
+	scr->Cfg &= ~CFG_Repeatbility_Mask;
+	scr->Cfg |= repeatability;
+	scr->Cfg &= ~CFG_MPS_Mask;
+	scr->Cfg |= mps;		
+	
+	M601_WriteScratchpad_SkipRom(scrb+4);
+	
+	return TRUE;
+}
+
+/**
+  * @brief  16λƲʾ¶תΪ϶Ϊλ¶ȶ
+  * @param  outзŵ16λ¶
+  * @retval ϶Ϊλĸ¶
+*/
+float M601_OutputtoTemp(int out)
+{
+	
+	
+	
+	return ((float)(out/256.0) + 40.0);	
+}
+
+/**
+  * @brief  ¶Ȳ
+  * @param  
+  * @retval ߷״̬
+*/
+BOOL ConvertTemp(void)
+{	 
+	if(OW_ResetPresence() == FALSE)					
+		return FALSE;
+
+  OW_WriteByte(SKIP_ROM);
+  OW_WriteByte(CONVERT_T);
+		
+  return TRUE;
+}
+
+/**
+  * @brief  ȴת@ConvertTempʹ
+  * @param  iTempص16λ¶Ȳ
+  * @retval ״̬
+*/
+BOOL ReadTempWaiting(uword *iTemp)
+{
+	ubyte scrb[sizeof(M601_SCRATCHPAD_READ)];
+	M601_SCRATCHPAD_READ *scr = (M601_SCRATCHPAD_READ *) scrb;
+
+	/*9ֽڡǰ¶תֽǰ8У--CRC*/	
+	if(M601_ReadScratchpad_SkipRom(scrb) == FALSE)
+	{		
+		UnSwSample_1.bit_data.temperature[1] = 1;	
+		return FALSE;  /*Ĵʧ*/
+	}
+
+	/*յǰ8ֽڵУͣյĵ9CRCֽڱȽϡ*/	
+		UnSwSample_1.bit_data.temperature[1] = scrb[8];	
+  if(scrb[8] != MY_OW_CRC8(scrb, 8))
+  {	
+
+		return FALSE;  /*CRC֤δͨ*/
+  }
+//					UnSwSample_1.bit_data.temperature[1] = *iTemp;	
+	/*¶ȲֽںϳΪ16λ֡*/	
+	*iTemp = ((uword)(scr->T_msb) << 8) | scr->T_lsb; 
+	
+  return TRUE;		
+}
+
+
+
+
+/**-----------------------------------------------------------------------
+  * @brief  оƬȡbitȡ˳򣺵λ->λ
+  * @param  
+  * @retval ȡbit
+-------------------------------------------------------------------------*/
+unsigned char OW_Read2Bits(void)
+{
+	unsigned char i, dq, owdata;
+	owdata = 0;
+
+	for (i = 0; i < 2; i++)
+	{
+		dq = read_bit();
+		owdata = (owdata) | (dq << i);
+	}
+	return owdata;
+}
+
+
+// 㷨 
+/**
+  * @brief  ϽоƬROM ID
+  * @param  ROM IDĶά
+  * @retval M601ĸ
+*/
+int Search_ROM(unsigned char(*romID)[8])
+{
+	unsigned char k, l = 0, ConflictBit, m, n;
+	unsigned char BUFFER[MAXNUM]={0};
+	unsigned char ss[64];
+	unsigned char s = 0;
+	int num = 0;
+	do
+	{
+		if (OW_ResetPresence() == 0)//ϴӻǷ
+		{
+			return 0;
+		}
+		OW_WriteByte(0xF0);// ROM кָ
+		for (m = 0; m < 8; m++)
+		{
+			for (n = 0; n < 8; n++)
+			{
+				k = OW_Read2Bits(); // DQ ϶λ
+				k = k & 0x03;
+				s = s >> 1;
+
+				if (k == 0x02)
+				{ //ʱϵǰλΪ 0
+					write_bit(0); //д 0, ʹλΪ 0 豸Ӧ
+					ss[(m * 8 + n)] = 0;
+				}
+				else if (k == 0x01)
+				{ //ʱϵǰλΪ 1
+					s = s | 0x80;
+					write_bit(1); //д 1, ʹλΪ 1 豸Ӧ
+					ss[(m * 8 + n)] = 1;
+				}
+				else if (k == 0x00)
+				{// 00, λгͻѡ
+					ConflictBit = m * 8 + n + 1;
+					if (ConflictBit > BUFFER[l])
+					{ //µIJλѡ 0
+						write_bit(0);
+						ss[(m * 8 + n)] = 0;
+						BUFFER[++l] = ConflictBit;
+					}
+					else if (ConflictBit < BUFFER[l])
+					{//ϴαʱһ 0 IJλ֮ǰIJλ԰ϴα·
+						s = s | ((ss[(m * 8 + n)] & 0x01) << 7);
+						write_bit(ss[(m * 8 + n)]);
+					}
+					else if (ConflictBit == BUFFER[l])
+					{	//ϴαʱһ 0 IJλӦ 1
+						s = s | 0x80;
+						write_bit(1);
+						ss[(m * 8 + n)] = 1;
+						l = l - 1;
+					}
+				}
+				else
+				{ // 11˵ϲ豸
+					return num; //
+				}
+			}
+			romID[num][m] = s;
+			s = 0;
+		}
+		num = num + 1;
+	} while (BUFFER[l] != 0 && (num < MAXNUM));
+	return num; // M601 
+}
+
+/**
+  * @brief  оƬĴݴ
+  * @param  scrָֽ룬 Ϊ @sizeofM601_SCRATCHPAD_READ
+  * @param  j  searchоƬţֻһоƬjֵ0
+  * @retval ״̬
+*/
+BOOL M601_ReadScratchpad(unsigned char* scr, unsigned char j)
+{
+	unsigned char i, k;
+
+	/*size < sizeof(M601_SCRATCHPAD_READ)*/
+	if (OW_ResetPresence() == FALSE)
+	{
+		return FALSE;
+	}
+
+//#ifdef  SingleIC
+//	OW_WriteByte(SKIP_ROM);
+
+//#else
+	OW_WriteByte(MATCH_ROM);
+	for (k = 0; k < 8; k++)
+	{
+		OW_WriteByte(romid[j][k]);
+	}
+//#endif
+	OW_WriteByte(READ_SCRATCHPAD);
+
+	for (i = 0; i < sizeof(M601_SCRATCHPAD_READ); i++)
+	{
+		*scr++ = OW_ReadByte();
+	}
+	return TRUE;
+}
+
+
+/**
+  * @brief  ȴת@ConvertTempʹ
+  * @param  iTempص16λ¶Ȳ
+  * @param  j  searchоƬţֻһоƬjֵ0
+  * @retval ״̬
+*/
+//BOOL ReadTempWaiting(unsigned short* iTemp, unsigned char j)
+//{
+//	unsigned char scrb[sizeof(M601_SCRATCHPAD_READ)];
+//	M601_SCRATCHPAD_READ* scr = (M601_SCRATCHPAD_READ*)scrb;
+
+//	/*9ֽڡǰ¶תֽǰ8У--CRC*/
+//	if (M601_ReadScratchpad(scrb, j) == 0)
+//	{
+//		return FALSE;  /*Ĵʧ*/
+//	}
+
+//	/*յǰ8ֽڵУͣյĵ9CRCֽڱȽϡ*/
+//	if (scrb[8] != MY_OW_CRC8(scrb, 8))
+//	{
+//		return FALSE;  /*CRC֤δͨ*/
+//	}
+
+//	/*¶ȲֽںϳΪ16λ֡*/
+//	*iTemp = (unsigned short)scr->T_msb << 8 | scr->T_lsb;
+
+//	return TRUE;
+//}
+
+
+
+/**
+  * @brief  ¶Ȳ
+  * @param  
+  * @retval ״̬
+*/
+
+BOOL GetTemp(void)
+{ 
+	static uword intTemp = 0;//Ϊֵ̬Լ仯
+	float fTemp;
+	int signedInt_f_tem = 0;	
+//---------------------------------------	
+//	intTemp = 0;
+	if(ConvertTemp() == FALSE) return FALSE;
+	Delay_us(6500);
+	ReadTempWaiting(&intTemp);
+
+	signedInt_f_tem = (int)intTemp;
+	
+	fTemp = ( (float)(signedInt_f_tem)/256.0 ) + 40.0;
+	
+	
+//	fTemp = M601_OutputtoTemp(signedInt_f_tem);
+// תΪз
+  signedInt_f_tem = (int)(fTemp*10);
+// ¶ зת޷	
+  UnSwSample_1.bit_data.temperature[0] = signedInt_f_tem;				
+	return TRUE;
+}
+/**
+  * @brief  ¶
+  * @param  
+  * @retval ״̬
+*/
+//BOOL GetTemp(void)
+//{
+//	float fTemp;
+//	static unsigned int iTemp[MAXNUM];
+//	int i;
+//	int signedInt_f_tem = 0;
+////----------------------------------------------------	
+////	memset(romid, 0, sizeof(romid));//
+//	
+//	/*оƬһ*/
+//	if(ConvertTemp() == FALSE) return FALSE;
+//	Delay_us(6500);
+
+//	
+//	for (i = 0; i < RomNum; i++)      //оƬ
+//	{
+//		iTemp[i] = 0;
+//		/**/
+//		ReadTempWaiting(&iTemp[i], i);
+
+//		fTemp = M601_OutputtoTemp((int)iTemp[i]);		//¶ĸ
+
+//		// תΪз
+//		signedInt_f_tem = (int)(fTemp*10);
+//		// ¶ зת޷	
+//		UnSwSample_1.bit_data.temperature[i] = (unsigned int)signedInt_f_tem;	
+//	}
+//	return TRUE;
+//}
diff --git a/temperature.h b/temperature.h
new file mode 100644
index 0000000..6722106
--- /dev/null
+++ b/temperature.h
@@ -0,0 +1,164 @@
+#ifndef _TEMPERATURE_H_
+#define _TEMPERATURE_H_
+
+#include "MAIN.H"
+
+
+#define DQ       P3_5
+
+///*Bit definition of config register*/
+#define CFG_CLKSTRETCH_Mask   	0x20
+#define CFG_MPS_Mask   		  		0x1C
+#define CFG_Repeatbility_Mask 	0x03
+
+#define CFG_ClkStreatch_Disable (0x00 << 5)
+#define CFG_ClkStreatch_Enable 	(0x01 << 5)
+
+#define CFG_MPS_Single  	      0x00
+#define CFG_MPS_Half  		      0x04
+#define CFG_MPS_1  			        0x08
+#define CFG_MPS_2 			        0x0C
+#define CFG_MPS_4 			        0x10
+#define CFG_MPS_10 			        0x14
+
+#define CFG_Repeatbility_Low   	0x00
+#define CFG_Repeatbility_Medium 0x01
+#define CFG_Repeatbility_High 	0x02
+
+
+#define MAXNUM    5 /*߼оƬ*/
+
+typedef enum {
+    FALSE = 0,
+    TRUE = !FALSE
+} BOOL;
+
+
+typedef struct
+{	
+	char Tha_set_lsb;				
+	char Tla_set_lsb;			
+	ubyte Cfg;						/*ϵͳüĴ, RW*/
+} M601_SCRATCHPAD_WRITE;
+
+
+/* M601/01 ow Commands-------------------------------------------------------*/
+typedef enum
+{
+	//ROM command
+  SKIP_ROM            	= 0xcc,
+  READ_ROM            	= 0x33,
+  MATCH_ROM           	= 0x55,
+	SEARCH_ROM           	= 0xf0, 
+	ALARM_SEARCH					= 0xec,
+	//Function command
+  CONVERT_T           	= 0x44,
+	READ_SCRATCHPAD     	= 0xbe,
+	WRITE_SCRATCHPAD     	= 0x4e,	
+} M601_OW_CMD;
+
+
+
+
+/******************  Scratchpad/SRAM  ******************/
+/*SRAM scratchpad*/
+typedef struct
+{
+	ubyte T_lsb;					/*The LSB of ¶Ƚ, RO*/
+	ubyte T_msb;					/*The MSB of ¶Ƚ, RO*/
+	ubyte C1_lsb;					/*The LSB of ͨC1, RO*/
+	ubyte C1_msb;					/*The MSB of ͨC1, Ro*/	
+	ubyte Tha_set_lsb;		
+	ubyte Tla_set_lsb;		
+	ubyte Cfg;						/*ϵͳüĴ, RW*/
+	ubyte Status;					/*ϵͳ״̬Ĵ, RO*/
+	ubyte crc_scr;				/*CRC for byte0-7, RO*/
+} M601_SCRATCHPAD_READ;
+
+
+
+
+
+//20250116 ¶Ȳɼֽ
+typedef struct _StrSwSample       
+{
+    unsigned int emergency_stop_switch : 1;  // ͨ1ͣ
+    unsigned int High_voltage_switch   : 1;  // ͨ2ѹ
+    unsigned int CH03                  : 1;  // ͨ3
+    unsigned int CH04                  : 1;  // ͨ4
+    unsigned int CH05                  : 1;  // ͨ5
+    unsigned int CH06                  : 1;  // ͨ6
+    unsigned int CH07                  : 1;  // ͨ7
+    unsigned int CH08                  : 1;  // ͨ8
+    unsigned int CH09                  : 1;  // ͨ9
+    unsigned int CH10                  : 1;  // ͨ10
+    unsigned int CH11                  : 1;  // ͨ11
+    unsigned int CH12                  : 1;  // ͨ12
+    unsigned int CH13                  : 1;  // ͨ13
+    unsigned int CH14                  : 1;  // ͨ14
+    unsigned int CH15                  : 1;  // ͨ15
+    unsigned int CH16                  : 1;  // ͨ16
+    unsigned int CH17                  : 1;  // ͨ17
+    unsigned int CH18                  : 1;  // ͨ18
+    unsigned int CH19                  : 1;  // ͨ19
+    unsigned int CH20                  : 1;  // ͨ20
+    unsigned int CH21                  : 1;  // ͨ21
+    unsigned int CH22                  : 1;  // ͨ22
+    unsigned int CH23                  : 1;  // ͨ23
+    unsigned int CH24                  : 1;  // ͨ24
+    unsigned int CH25                  : 1;  // ͨ25
+    unsigned int CH26                  : 1;  // ͨ26
+    unsigned int CH27                  : 1;  // ͨ27
+    unsigned int CH28                  : 1;  // ͨ28
+    unsigned int CH29                  : 1;  // ͨ29
+    unsigned int CH30                  : 1;  // ͨ30
+    unsigned int CH31                  : 1;  // ͨ31
+    unsigned int CH32                  : 1;  // ͨ32
+		
+//    unsigned int CH33                  : 1;  // ͨ33
+//    unsigned int CH34                  : 1;  // ͨ34
+//    unsigned int CH35                  : 1;  // ͨ35
+//    unsigned int CH36                  : 1;  // ͨ36
+//    unsigned int CH37                  : 1;  // ͨ37
+//    unsigned int CH38                  : 1;  // ͨ38
+//    unsigned int CH39                  : 1;  // ͨ39
+//    unsigned int CH40                  : 1;  // ͨ40
+//    unsigned int CH41                  : 1;  // ͨ41
+//    unsigned int CH42                  : 1;  // ͨ42
+//    unsigned int CH43                  : 1;  // ͨ43
+//    unsigned int CH44                  : 1;  // ͨ44
+//    unsigned int reserve               : 4;
+
+	  unsigned int temperature[2]; // ¶
+		
+} StrSwSample;
+
+typedef union _UnSwSample
+{
+    StrSwSample bit_data;              // ʹöĽṹ
+    unsigned char arr[sizeof(StrSwSample)];  // ͨṹȷС
+} UnSwSample;
+
+
+
+
+extern UnSwSample  UnSwSample_1 ;
+
+
+
+BOOL GetTemp(void);
+BOOL SetConfig(ubyte mps, ubyte repeatability);
+
+
+int Search_ROM(unsigned char(*romID)[8]);
+extern unsigned char romid[MAXNUM][8];
+extern int RomNum;
+	
+
+
+
+
+
+
+
+#endif // _TEMPERATURE_H_
diff --git a/user.H b/user.H
new file mode 100644
index 0000000..d43f070
--- /dev/null
+++ b/user.H
@@ -0,0 +1,177 @@
+#ifndef _user_H_
+#define _user_H_
+
+#define DF_SwTx           6
+#define DF_SwRx           7
+#define DF_RXTIME         11
+#define DF_SwTxKGF1       8
+#define DF_SwTxKGF2       10
+#define DF_SwTxTemp       12
+
+#define DF_SwRxPwm        8
+
+
+#define   dfCmd_01   UnInfCan_1.BitData.D21      //KGF1  
+#define   dfCmd_02   UnInfCan_1.BitData.D22      //KGF2	
+#define   dfCmd_03   UnInfCan_1.BitData.D23      //KGF3  
+#define   dfCmd_04   UnInfCan_1.BitData.D24      //KGF4  
+#define   dfCmd_05   UnInfCan_1.BitData.D25      //KGF5  
+#define   dfCmd_06   UnInfCan_1.BitData.D26      //KGF6  
+#define   dfCmd_07   UnInfCan_1.BitData.D27      //KGF7  
+#define   dfCmd_08   UnInfCan_1.BitData.D28      //KGF8  
+#define   dfCmd_09   UnInfCan_1.BitData.D29      //KGF9  
+#define   dfCmd_10   UnInfCan_1.BitData.D30      //KGF10 
+#define   dfCmd_11   UnInfCan_1.BitData.D31      //KGF11 
+#define   dfCmd_12   UnInfCan_1.BitData.D32      //KGF12 
+#define   dfCmd_13   UnInfCan_1.BitData.D33      //KGF13 
+#define   dfCmd_14   UnInfCan_1.BitData.D34      //KGF14 
+#define   dfCmd_15   UnInfCan_1.BitData.D35      //KGF15 
+#define   dfCmd_16   UnInfCan_1.BitData.D36      //KGF16 
+
+#define   dfOut_01   SwOut09                     //KGF1  
+#define   dfOut_02   SwOut10                     //KGF2	
+#define   dfOut_03   SwOut04                     //KGF3  
+#define   dfOut_04   SwOut03                     //KGF4  
+#define   dfOut_05   SwOut06                     //KGF5  
+#define   dfOut_06   SwOut05                     //KGF6  
+#define   dfOut_07   SwOut15                     //KGF7  
+#define   dfOut_08   SwOut16                     //KGF8  
+#define   dfOut_09   SwOut13                     //KGF9  
+#define   dfOut_10   SwOut14                     //KGF10 
+#define   dfOut_11   SwOut08                     //KGF11 
+#define   dfOut_12   SwOut07                     //KGF12 
+#define   dfOut_13   SwOut02                     //KGF13 
+#define   dfOut_14   SwOut01                     //KGF14 
+#define   dfOut_15   SwOut11                     //KGF15 
+#define   dfOut_16   SwOut12                     //KGF16 
+
+#define   dfPwmH		 10	 //PWMĸߵƽʱ䣬1010msңҪ20181227
+
+
+#define   WAKE_UP_PIN       P1_5                 //ѹ
+#define   KGF_PIN           P0_0                 //
+#define   CAN_PIN           P1_6                 //
+#define   STOP_PIN          P3_6                 //ͣ
+
+
+#define   ON                0                    //
+#define   OFF               1                    //ɿ
+
+#define  FAULT             0
+#define  NORMAL            1
+
+
+#define  HERTER_CMD(A)      dfOut_05 = A;dfOut_06 = A;dfOut_07 = A;dfOut_08 = A 
+#define  PC_CMD(A)          dfOut_09 = A;dfOut_10 = A 
+
+// ״̬壨ʼ״̬
+typedef enum {
+    STATE_INIT_CHECK,   // ʼ״̬жǷ<0C
+    STATE_HEATING,      // ״̬
+    STATE_COOLING,      // ֹͣ״̬
+	  STATE_INIT_HEATING
+} SystemState;
+
+
+
+// Ʋãҳ1Ƽã
+#define TEMP_HYSTERESIS     0.5f    // زֹ[1,3](@ref)
+#define INIT_THRESHOLD      0.0f    // ʼ״ֵ̬  0
+#define HEATING_STOP        10.0f   // ֹͣ¶   10
+#define COOLING_RESTART     5.0f    // ¶   5
+
+
+
+
+
+
+// Դ״̬ö
+typedef enum {
+    POWER_STANDBY,
+    POWER_WORKING,
+    POWER_EMERGENCY,
+    POWER_PRE_CHARGE,
+    POWER_NEUTRAL,    
+    POWER_SLEEP
+} PowerState;
+
+
+
+// طģ
+typedef struct _StrInfCanKGFOutput
+{
+    //----------0x11000002 --------------------------------------------
+    unsigned int KGF01         : 1;  // ͨ1
+    unsigned int KGF02         : 1;  // ͨ2
+    unsigned int KGF03         : 1;  // ͨ3
+    unsigned int KGF04         : 1;  // ͨ4
+    unsigned int KGF05         : 1;  // ͨ5
+    unsigned int KGF06         : 1;  // ͨ6
+    unsigned int KGF07         : 1;  // ͨ7
+    unsigned int KGF08         : 1;  // ͨ8
+    unsigned int KGF09         : 1;  // ͨ9
+    unsigned int KGF10         : 1;  // ͨ10
+    unsigned int KGF11         : 1;  // ͨ11
+    unsigned int KGF12         : 1;  // ͨ12
+    unsigned int KGF13         : 1;  // ͨ13
+    unsigned int KGF14         : 1;  // ͨ14
+    unsigned int KGF15         : 1;  // ͨ15
+    unsigned int KGF16         : 1;  // ͨ16
+
+    unsigned int can_rx2       : 8;  // 
+    unsigned int can_rx3       : 8;  // 
+    unsigned int can_rx4       : 8;  // 
+    unsigned int can_rx5       : 8;  // 
+    unsigned int can_period_h  : 8;  // ڸλ
+    unsigned int can_period_l  : 8;  // ڵλ
+
+    //----------0x11000003 ---------------------------------------------------
+    unsigned int pwm_01        : 4;  // PWMͨ1
+    unsigned int pwm_02        : 4;  // PWMͨ2
+    unsigned int pwm_03        : 4;  // PWMͨ3
+    unsigned int pwm_04        : 4;  // PWMͨ4
+    unsigned int pwm_05        : 4;  // PWMͨ5
+    unsigned int pwm_06        : 4;  // PWMͨ6
+    unsigned int pwm_07        : 4;  // PWMͨ7
+    unsigned int pwm_08        : 4;  // PWMͨ8
+    unsigned int pwm_09        : 4;  // PWMͨ9
+    unsigned int pwm_10        : 4;  // PWMͨ10
+    unsigned int pwm_11        : 4;  // PWMͨ11
+    unsigned int pwm_12        : 4;  // PWMͨ12
+    unsigned int pwm_13        : 4;  // PWMͨ13
+    unsigned int pwm_14        : 4;  // PWMͨ14
+    unsigned int pwm_15        : 4;  // PWMͨ15
+    unsigned int pwm_16        : 4;  // PWMͨ16
+} StrInfCanKGFOutput;
+
+typedef union _UnInfCanKGFOutput
+{
+    StrInfCanKGFOutput bit_data;             // ʹöĽṹ
+    ubyte arr[sizeof(StrInfCanKGFOutput)]; // ͨṹȷС
+} UnInfCanKGFOutput;
+
+
+
+
+
+
+//---ⲿҪʹñ---------------------------------------------------------------------
+extern  UnSwOut	 UnSwOut_1;
+extern  UnInfCan UnInfCan_1;
+extern  uword    CntCan_1;
+extern  bit      FlgCan_1;
+
+extern  ubyte    RestartDataFlg1;
+extern  ubyte    RestartDataFlg2;
+extern  uword    RestartDataKGF;
+
+extern  UnInfCanKGFOutput    un_inf_can_kgf_output1;//kgf
+
+void CanRXTX(void);
+void SwSample(void);
+void LedDr(void);
+void RTCProcess(void);
+void CanErrorProcess(void);
+void CanTransmit(void);
+void canSendTo(ubyte index, ubyte *buff);
+#endif
\ No newline at end of file
diff --git a/user.H.bak b/user.H.bak
new file mode 100644
index 0000000..6a13b4d
--- /dev/null
+++ b/user.H.bak
@@ -0,0 +1,57 @@
+#ifndef _user_H_
+#define _user_H_
+
+#define DF_SwTx        6
+#define DF_SwRx        7
+
+#define   dfCmd01   UnInfCan_1.BitData.D21      //KGF1  
+#define   dfCmd02   UnInfCan_1.BitData.D22      //KGF2	
+#define   dfCmd03   UnInfCan_1.BitData.D23      //KGF3  
+#define   dfCmd04   UnInfCan_1.BitData.D24      //KGF4  
+#define   dfCmd05   UnInfCan_1.BitData.D25      //KGF5  
+#define   dfCmd06   UnInfCan_1.BitData.D26      //KGF6  
+#define   dfCmd07   UnInfCan_1.BitData.D27      //KGF7  
+#define   dfCmd08   UnInfCan_1.BitData.D28      //KGF8  
+#define   dfCmd09   UnInfCan_1.BitData.D29      //KGF9  
+#define   dfCmd10   UnInfCan_1.BitData.D30      //KGF10 
+#define   dfCmd11   UnInfCan_1.BitData.D31      //KGF11 
+#define   dfCmd12   UnInfCan_1.BitData.D32      //KGF12 
+#define   dfCmd13   UnInfCan_1.BitData.D33      //KGF13 
+#define   dfCmd14   UnInfCan_1.BitData.D34      //KGF14 
+#define   dfCmd15   UnInfCan_1.BitData.D35      //KGF15 
+#define   dfCmd16   UnInfCan_1.BitData.D36      //KGF16 
+
+#define   dfOut01   SwOut09                     //KGF1  
+#define   dfOut02   SwOut10                     //KGF2	
+#define   dfOut03   SwOut04                     //KGF3  
+#define   dfOut04   SwOut03                     //KGF4  
+#define   dfOut05   SwOut06                     //KGF5  
+#define   dfOut06   SwOut05                     //KGF6  
+#define   dfOut07   SwOut15                     //KGF7  
+#define   dfOut08   SwOut16                     //KGF8  
+#define   dfOut09   SwOut13                     //KGF9  
+#define   dfOut10   SwOut14                     //KGF10 
+#define   dfOut11   SwOut08                     //KGF11 
+#define   dfOut12   SwOut07                     //KGF12 
+#define   dfOut13   SwOut02                     //KGF13 
+#define   dfOut14   SwOut01                     //KGF14 
+#define   dfOut15   SwOut11                     //KGF15 
+#define   dfOut16   SwOut12                     //KGF16 
+
+
+
+
+//---ⲿҪʹñ---------------------------------------------------------------------
+extern  UnSwOut	 UnSwOut_1;
+extern  UnInfCan UnInfCan_1;
+extern  uword    CntCan_1;
+extern  bit      FlgCan_1;
+
+void CanRXTX(void);
+void SwSample(void);
+void LedDr(void);
+void RTCProcess(void);
+void CanErrorProcess(void);
+void CanTransmit(void);
+
+#endif
\ No newline at end of file