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Design Rule Verification Report

Date : 2025/5/25
Time : 18:45:08
Elapsed Time : 00:00:01
Filename : E:\liumin\PCB\HÇÅÄ£¿é\PCB1.PcbDoc
Warnings : 1
Rule Violations : 0

Summary

Warnings Count
Unplated multi-layer pad(s) detected 1
Total 1

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Clearance Constraint (Gap=0.15mm) (All),(All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Width Constraint (Min=0.1mm) (Max=4mm) (Preferred=0.5mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Hole Size Constraint (Min=0.0254mm) (Max=5mm) (All) 0
Hole To Hole Clearance (Gap=0mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mm) (All),(All) 0
Silk To Solder Mask (Clearance=0mm) (IsPad),(All) 0
Silk to Silk (Clearance=0mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Total 0

Warnings

Unplated multi-layer pad(s) detected
Pad P2-1(46.4446mm,41.26mm) Multi-Layer on Net NETLABEL37
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