Protel Design System Design Rule Check
PCB File : E:\liumin\PCB\HÇÅÄ£¿é\PCB1.PcbDoc
Date     : 2025/5/25
Time     : 18:45:08

WARNING: Unplated multi-layer pad(s) detected
   Pad P2-1(46.4446mm,41.26mm)  Multi-Layer on Net NETLABEL37

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.15mm) (All),(All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.1mm) (Max=4mm) (Preferred=0.5mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=5mm) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=0mm) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0mm) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=0mm) (IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=0mm) (All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:01