44 lines
1.3 KiB
Plaintext
44 lines
1.3 KiB
Plaintext
Protel Design System Design Rule Check
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PCB File : E:\liumin\PCB\20241206¿ØÖÆÆ÷µ×°å\PCB1.PcbDoc
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Date : 2025/3/20
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Time : 21:07:15
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Processing Rule : Net Antennae (Tolerance=0mm) (All)
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Rule Violations :0
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Processing Rule : Silk to Silk (Clearance=0mm) (All),(All)
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Rule Violations :0
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Processing Rule : Silk To Solder Mask (Clearance=0mm) (IsPad),(All)
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Rule Violations :0
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Processing Rule : Minimum Solder Mask Sliver (Gap=0mm) (All),(All)
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Rule Violations :0
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Processing Rule : Hole To Hole Clearance (Gap=0mm) (All),(All)
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Rule Violations :0
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Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=5mm) (All)
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Rule Violations :0
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Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
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Rule Violations :0
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Processing Rule : Width Constraint (Min=0.2mm) (Max=5mm) (Preferred=0.3mm) (All)
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Rule Violations :0
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Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.15mm) (All),(All)
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Rule Violations :0
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Processing Rule : Un-Routed Net Constraint ( (All) )
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Rule Violations :0
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Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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Rule Violations :0
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Violations Detected : 0
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Time Elapsed : 00:00:08 |