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新增底板

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liumin
2025-11-08 12:56:03 +08:00
parent c03d22cd41
commit 058589041e
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20241206控制器底板/Project Outputs for PCB_Project2/Design Rule Check - PCB1.drc Normal file
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Protel Design System Design Rule Check
PCB File : E:\liumin\PCB\20241206<30><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>װ<EFBFBD>\PCB1.PcbDoc
Date : 2025/3/20
Time : 21:07:15
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0mm) (IsPad),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0mm) (All),(All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0mm) (All),(All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=5mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.2mm) (Max=5mm) (Preferred=0.3mm) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.15mm) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:00:08