912 lines
32 KiB
C
912 lines
32 KiB
C
/**
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* @file sdrv_pmu_reg.h
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* @brief Sdrv PMU head source.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_TAISHAN_PMU_REG_H_
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#define SDRV_TAISHAN_PMU_REG_H_
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#define BC_VLD_WINDOW_OFF 0x0U
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#define FM_BC_VLD_WINDOW_BC_OFF_VLD_MAX (0xffU << 24U)
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#define FV_BC_VLD_WINDOW_BC_OFF_VLD_MAX(v) \
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(((v) << 24U) & FM_BC_VLD_WINDOW_BC_OFF_VLD_MAX)
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#define GFV_BC_VLD_WINDOW_BC_OFF_VLD_MAX(v) \
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(((v) & FM_BC_VLD_WINDOW_BC_OFF_VLD_MAX) >> 24U)
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#define FM_BC_VLD_WINDOW_BC_OFF_VLD_MIN (0xffU << 16U)
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#define FV_BC_VLD_WINDOW_BC_OFF_VLD_MIN(v) \
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(((v) << 16U) & FM_BC_VLD_WINDOW_BC_OFF_VLD_MIN)
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#define GFV_BC_VLD_WINDOW_BC_OFF_VLD_MIN(v) \
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(((v) & FM_BC_VLD_WINDOW_BC_OFF_VLD_MIN) >> 16U)
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#define FM_BC_VLD_WINDOW_BC_ON_VLD_MAX (0xffU << 8U)
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#define FV_BC_VLD_WINDOW_BC_ON_VLD_MAX(v) \
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(((v) << 8U) & FM_BC_VLD_WINDOW_BC_ON_VLD_MAX)
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#define GFV_BC_VLD_WINDOW_BC_ON_VLD_MAX(v) \
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(((v) & FM_BC_VLD_WINDOW_BC_ON_VLD_MAX) >> 8U)
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#define FM_BC_VLD_WINDOW_BC_ON_VLD_MIN (0xffU << 0U)
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#define FV_BC_VLD_WINDOW_BC_ON_VLD_MIN(v) \
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(((v) << 0U) & FM_BC_VLD_WINDOW_BC_ON_VLD_MIN)
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#define GFV_BC_VLD_WINDOW_BC_ON_VLD_MIN(v) \
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(((v) & FM_BC_VLD_WINDOW_BC_ON_VLD_MIN) >> 0U)
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#define BC_CTRL_SET_OFF 0x4U
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#define FM_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE (0xffU << 24U)
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#define FV_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE(v) \
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(((v) << 24U) & FM_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE)
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#define GFV_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE(v) \
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(((v) & FM_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE) >> 24U)
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#define BM_BC_CTRL_SET_PWR_DWN_REQ_SOFT (0x01U << 23U)
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#define FM_BC_CTRL_SET_BC_FILTER_EDGE (0x3U << 21U)
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#define FV_BC_CTRL_SET_BC_FILTER_EDGE(v) \
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(((v) << 21U) & FM_BC_CTRL_SET_BC_FILTER_EDGE)
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#define GFV_BC_CTRL_SET_BC_FILTER_EDGE(v) \
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(((v) & FM_BC_CTRL_SET_BC_FILTER_EDGE) >> 21U)
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#define FM_BC_CTRL_SET_BC_FILTER_CNT (0xfU << 17U)
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#define FV_BC_CTRL_SET_BC_FILTER_CNT(v) \
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(((v) << 17U) & FM_BC_CTRL_SET_BC_FILTER_CNT)
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#define GFV_BC_CTRL_SET_BC_FILTER_CNT(v) \
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(((v) & FM_BC_CTRL_SET_BC_FILTER_CNT) >> 17U)
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#define FM_BC_CTRL_SET_BC_SAMPLE_INTERVAL (0x7U << 14U)
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#define FV_BC_CTRL_SET_BC_SAMPLE_INTERVAL(v) \
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(((v) << 14U) & FM_BC_CTRL_SET_BC_SAMPLE_INTERVAL)
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#define GFV_BC_CTRL_SET_BC_SAMPLE_INTERVAL(v) \
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(((v) & FM_BC_CTRL_SET_BC_SAMPLE_INTERVAL) >> 14U)
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#define BM_BC_CTRL_SET_BC_FILTER_BYPASS (0x01U << 13U)
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#define BM_BC_CTRL_SET_BC_DISABLE_LOCK (0x01U << 12U)
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#define BM_BC_CTRL_SET_BC_DISABLE (0x01U << 11U)
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#define BM_BC_CTRL_SET_BC_FSM_ENABLE (0x01U << 10U)
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#define BM_BC_CTRL_SET_BC_OFF_EDGE (0x01U << 9U)
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#define BM_BC_CTRL_SET_BC_ON_EDGE (0x01U << 8U)
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#define BM_BC_CTRL_SET_BC_OFF_POL (0x01U << 7U)
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#define BM_BC_CTRL_SET_BC_ON_POL (0x01U << 6U)
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#define BM_BC_CTRL_SET_BC_OFF_VLD_MAX_DISABLE (0x01U << 5U)
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#define BM_BC_CTRL_SET_BC_ON_VLD_MAX_DISABLE (0x01U << 4U)
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#define FM_BC_CTRL_SET_BC_CNT_UNIT (0xfU << 0U)
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#define FV_BC_CTRL_SET_BC_CNT_UNIT(v) \
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(((v) << 0U) & FM_BC_CTRL_SET_BC_CNT_UNIT)
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#define GFV_BC_CTRL_SET_BC_CNT_UNIT(v) \
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(((v) & FM_BC_CTRL_SET_BC_CNT_UNIT) >> 0U)
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#define WAKEUP_CTRL_OFF 0x8U
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#define BM_WAKEUP_CTRL_WKUP01_AND_ENABLE (0x01U << 31U)
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#define BM_WAKEUP_CTRL_WKUP1_DISABLE (0x01U << 30U)
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#define BM_WAKEUP_CTRL_WKUP0_DISABLE (0x01U << 29U)
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#define BM_WAKEUP_CTRL_WKUP1_POL (0x01U << 28U)
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#define BM_WAKEUP_CTRL_WKUP0_POL (0x01U << 27U)
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#define BM_WAKEUP_CTRL_WKUP1_EDGE (0x01U << 26U)
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#define BM_WAKEUP_CTRL_WKUP0_EDGE (0x01U << 25U)
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#define BM_WAKEUP_CTRL_WAKEUP_IN_RTC_LATCH (0x01U << 22U)
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#define BM_WAKEUP_CTRL_EXT_WAKEUP_EN (0x01U << 21U)
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#define BM_WAKEUP_CTRL_INT_WAKEUP_EN (0x01U << 20U)
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#define FM_WAKEUP_CTRL_WKUP1_FILTER_EDGE (0x3U << 18U)
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#define FV_WAKEUP_CTRL_WKUP1_FILTER_EDGE(v) \
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(((v) << 18U) & FM_WAKEUP_CTRL_WKUP1_FILTER_EDGE)
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#define GFV_WAKEUP_CTRL_WKUP1_FILTER_EDGE(v) \
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(((v) & FM_WAKEUP_CTRL_WKUP1_FILTER_EDGE) >> 18U)
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#define FM_WAKEUP_CTRL_WKUP1_FILTER_CNT (0xfU << 14U)
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#define FV_WAKEUP_CTRL_WKUP1_FILTER_CNT(v) \
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(((v) << 14U) & FM_WAKEUP_CTRL_WKUP1_FILTER_CNT)
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#define GFV_WAKEUP_CTRL_WKUP1_FILTER_CNT(v) \
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(((v) & FM_WAKEUP_CTRL_WKUP1_FILTER_CNT) >> 14U)
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#define FM_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL (0x7U << 11U)
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#define FV_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL(v) \
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(((v) << 11U) & FM_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL)
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#define GFV_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL(v) \
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(((v) & FM_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL) >> 11U)
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#define BM_WAKEUP_CTRL_WKUP1_FILTER_BYPASS (0x01U << 10U)
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#define FM_WAKEUP_CTRL_WKUP0_FILTER_EDGE (0x3U << 8U)
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#define FV_WAKEUP_CTRL_WKUP0_FILTER_EDGE(v) \
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(((v) << 8U) & FM_WAKEUP_CTRL_WKUP0_FILTER_EDGE)
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#define GFV_WAKEUP_CTRL_WKUP0_FILTER_EDGE(v) \
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(((v) & FM_WAKEUP_CTRL_WKUP0_FILTER_EDGE) >> 8U)
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#define FM_WAKEUP_CTRL_WKUP0_FILTER_CNT (0xfU << 4U)
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#define FV_WAKEUP_CTRL_WKUP0_FILTER_CNT(v) \
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(((v) << 4U) & FM_WAKEUP_CTRL_WKUP0_FILTER_CNT)
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#define GFV_WAKEUP_CTRL_WKUP0_FILTER_CNT(v) \
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(((v) & FM_WAKEUP_CTRL_WKUP0_FILTER_CNT) >> 4U)
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#define FM_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL (0x7U << 1U)
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#define FV_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL(v) \
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(((v) << 1U) & FM_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL)
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#define GFV_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL(v) \
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(((v) & FM_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL) >> 1U)
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#define BM_WAKEUP_CTRL_WKUP0_FILTER_BYPASS (0x01U << 0U)
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#define PGM_CTRL_OFF 0xcU
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#define FM_PGM_CTRL_PWR_ON_WDT_EN (0xfU << 28U)
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#define FV_PGM_CTRL_PWR_ON_WDT_EN(v) \
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(((v) << 28U) & FM_PGM_CTRL_PWR_ON_WDT_EN)
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#define GFV_PGM_CTRL_PWR_ON_WDT_EN(v) \
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(((v) & FM_PGM_CTRL_PWR_ON_WDT_EN) >> 28U)
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#define FM_PGM_CTRL_POR_TW (0xfU << 24U)
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#define FV_PGM_CTRL_POR_TW(v) \
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(((v) << 24U) & FM_PGM_CTRL_POR_TW)
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#define GFV_PGM_CTRL_POR_TW(v) \
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(((v) & FM_PGM_CTRL_POR_TW) >> 24U)
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#define FM_PGM_CTRL_POR_TW_ADJ (0x3U << 22U)
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#define FV_PGM_CTRL_POR_TW_ADJ(v) \
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(((v) << 22U) & FM_PGM_CTRL_POR_TW_ADJ)
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#define GFV_PGM_CTRL_POR_TW_ADJ(v) \
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(((v) & FM_PGM_CTRL_POR_TW_ADJ) >> 22U)
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#define FM_PGM_CTRL_HW_REBOOT_REQ_EN (0x3U << 20U)
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#define FV_PGM_CTRL_HW_REBOOT_REQ_EN(v) \
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(((v) << 20U) & FM_PGM_CTRL_HW_REBOOT_REQ_EN)
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#define GFV_PGM_CTRL_HW_REBOOT_REQ_EN(v) \
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(((v) & FM_PGM_CTRL_HW_REBOOT_REQ_EN) >> 20U)
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#define FM_PGM_CTRL_WDT_DIV (0xfU << 16U)
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#define FV_PGM_CTRL_WDT_DIV(v) \
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(((v) << 16U) & FM_PGM_CTRL_WDT_DIV)
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#define GFV_PGM_CTRL_WDT_DIV(v) \
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(((v) & FM_PGM_CTRL_WDT_DIV) >> 16U)
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#define FM_PGM_CTRL_PWR_ON3_WDT_CNT (0xfU << 12U)
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#define FV_PGM_CTRL_PWR_ON3_WDT_CNT(v) \
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(((v) << 12U) & FM_PGM_CTRL_PWR_ON3_WDT_CNT)
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#define GFV_PGM_CTRL_PWR_ON3_WDT_CNT(v) \
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(((v) & FM_PGM_CTRL_PWR_ON3_WDT_CNT) >> 12U)
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#define FM_PGM_CTRL_PWR_ON2_WDT_CNT (0xfU << 8U)
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#define FV_PGM_CTRL_PWR_ON2_WDT_CNT(v) \
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(((v) << 8U) & FM_PGM_CTRL_PWR_ON2_WDT_CNT)
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#define GFV_PGM_CTRL_PWR_ON2_WDT_CNT(v) \
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(((v) & FM_PGM_CTRL_PWR_ON2_WDT_CNT) >> 8U)
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#define FM_PGM_CTRL_PWR_ON1_WDT_CNT (0xfU << 4U)
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#define FV_PGM_CTRL_PWR_ON1_WDT_CNT(v) \
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(((v) << 4U) & FM_PGM_CTRL_PWR_ON1_WDT_CNT)
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#define GFV_PGM_CTRL_PWR_ON1_WDT_CNT(v) \
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(((v) & FM_PGM_CTRL_PWR_ON1_WDT_CNT) >> 4U)
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#define FM_PGM_CTRL_PWR_ON0_WDT_CNT (0xfU << 0U)
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#define FV_PGM_CTRL_PWR_ON0_WDT_CNT(v) \
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(((v) << 0U) & FM_PGM_CTRL_PWR_ON0_WDT_CNT)
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#define GFV_PGM_CTRL_PWR_ON0_WDT_CNT(v) \
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(((v) & FM_PGM_CTRL_PWR_ON0_WDT_CNT) >> 0U)
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#define PWR_CTRL_SET0_OFF 0x10U
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#define FM_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0 (0xffU << 24U)
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#define FV_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0(v) \
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(((v) << 24U) & FM_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0)
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#define GFV_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0(v) \
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(((v) & FM_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0) >> 24U)
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#define FM_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0 (0xffU << 16U)
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#define FV_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0(v) \
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(((v) << 16U) & FM_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0)
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#define GFV_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0(v) \
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(((v) & FM_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0) >> 16U)
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#define FM_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0 (0xffU << 8U)
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#define FV_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0(v) \
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(((v) << 8U) & FM_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0)
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#define GFV_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0(v) \
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(((v) & FM_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0) >> 8U)
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#define FM_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0 (0xffU << 0U)
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#define FV_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0(v) \
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(((v) << 0U) & FM_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0)
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#define GFV_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0(v) \
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(((v) & FM_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0) >> 0U)
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#define PWR_CTRL_SET1_OFF 0x14U
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#define BM_PWR_CTRL_SET1_PWR_UP_RUN_MIN_DELAY_ENABLE (0x01U << 31U)
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#define BM_PWR_CTRL_SET1_SLEEP_RUN_MIN_DELAY_ENABLE (0x01U << 30U)
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#define BM_PWR_CTRL_SET1_HIBERNATE_RUN_MIN_DELAY_ENABLE (0x01U << 29U)
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#define FM_PWR_CTRL_SET1_PWR_CTRL_POL (0xfU << 20U)
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#define FV_PWR_CTRL_SET1_PWR_CTRL_POL(v) \
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(((v) << 20U) & FM_PWR_CTRL_SET1_PWR_CTRL_POL)
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#define GFV_PWR_CTRL_SET1_PWR_CTRL_POL(v) \
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(((v) & FM_PWR_CTRL_SET1_PWR_CTRL_POL) >> 20U)
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#define FM_PWR_CTRL_SET1_SW_PWR_CTRL_EN (0xfU << 12U)
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#define FV_PWR_CTRL_SET1_SW_PWR_CTRL_EN(v) \
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(((v) << 12U) & FM_PWR_CTRL_SET1_SW_PWR_CTRL_EN)
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#define GFV_PWR_CTRL_SET1_SW_PWR_CTRL_EN(v) \
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(((v) & FM_PWR_CTRL_SET1_SW_PWR_CTRL_EN) >> 12U)
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#define FM_PWR_CTRL_SET1_SW_PWR_CTRL (0xfU << 8U)
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#define FV_PWR_CTRL_SET1_SW_PWR_CTRL(v) \
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(((v) << 8U) & FM_PWR_CTRL_SET1_SW_PWR_CTRL)
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#define GFV_PWR_CTRL_SET1_SW_PWR_CTRL(v) \
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(((v) & FM_PWR_CTRL_SET1_SW_PWR_CTRL) >> 8U)
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#define PWR_UP_PWR_CTRL_DELAY_OFF 0x18U
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#define FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX (0x3U << 30U)
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#define FV_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX(v) \
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(((v) << 30U) & FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX)
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#define GFV_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX(v) \
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(((v) & FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX) >> 30U)
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#define FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY (0xffffffU << 0U)
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#define FV_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY(v) \
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(((v) << 0U) & FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY)
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#define GFV_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY(v) \
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(((v) & FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY) >> 0U)
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#define RUN_PWR_CTRL_DELAY_OFF 0x1cU
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#define FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX (0x3U << 30U)
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#define FV_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX(v) \
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(((v) << 30U) & FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX)
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#define GFV_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX(v) \
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(((v) & FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX) >> 30U)
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#define FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY (0xffffffU << 0U)
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#define FV_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY(v) \
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(((v) << 0U) & FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY)
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#define GFV_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY(v) \
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(((v) & FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY) >> 0U)
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#define SLEEP_PWR_CTRL_DELAY_OFF 0x20U
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#define FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX (0x3U << 30U)
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#define FV_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX(v) \
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(((v) << 30U) & FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX)
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#define GFV_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX(v) \
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(((v) & FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX) >> 30U)
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#define FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY (0xffffffU << 0U)
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#define FV_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY(v) \
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(((v) << 0U) & FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY)
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#define GFV_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY(v) \
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(((v) & FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY) >> 0U)
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#define HIBERNATE_PWR_CTRL_DELAY_OFF 0x24U
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#define FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX (0x3U << 30U)
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#define FV_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX(v) \
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(((v) << 30U) & FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX)
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|
#define GFV_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX(v) \
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(((v) & FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX) >> 30U)
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#define FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY (0xffffffU << 0U)
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#define FV_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY(v) \
|
|
(((v) << 0U) & FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY)
|
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#define GFV_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY(v) \
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(((v) & FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY) >> 0U)
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#define RTC_PWR_CTRL_DELAY_OFF 0x28U
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#define FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX (0x3U << 30U)
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|
#define FV_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX(v) \
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|
(((v) << 30U) & FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX)
|
|
#define GFV_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX(v) \
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|
(((v) & FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX) >> 30U)
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#define FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY (0xffffffU << 0U)
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#define FV_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY(v) \
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|
(((v) << 0U) & FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY)
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#define GFV_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY(v) \
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(((v) & FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY) >> 0U)
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#define RUN_PWR_ON_SET_OFF 0x30U
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#define FM_RUN_PWR_ON_SET_RUN_PWR_ON_SET (0x3ffffU << 0U)
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#define FV_RUN_PWR_ON_SET_RUN_PWR_ON_SET(v) \
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(((v) << 0U) & FM_RUN_PWR_ON_SET_RUN_PWR_ON_SET)
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#define GFV_RUN_PWR_ON_SET_RUN_PWR_ON_SET(v) \
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(((v) & FM_RUN_PWR_ON_SET_RUN_PWR_ON_SET) >> 0U)
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#define SLEEP_PWR_ON_SET_OFF 0x34U
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#define FM_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET (0x3ffffU << 0U)
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#define FV_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET(v) \
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|
(((v) << 0U) & FM_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET)
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#define GFV_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET(v) \
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(((v) & FM_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET) >> 0U)
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#define HIBERNATE_PWR_ON_SET_OFF 0x38U
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#define FM_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET (0x3ffffU << 0U)
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#define FV_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET(v) \
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|
(((v) << 0U) & FM_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET)
|
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#define GFV_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET(v) \
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(((v) & FM_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET) >> 0U)
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#define RTC_PWR_ON_SET_OFF 0x3cU
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#define BM_RTC_PWR_ON_SET_RTC_TO_OFF_SF_HV_PG_DISABLE (0x01U << 31U)
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#define BM_RTC_PWR_ON_SET_RTC_TO_OFF_SF_LV_PG_DISABLE (0x01U << 30U)
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#define BM_RTC_PWR_ON_SET_RTC_TO_OFF_AP_HV_PG_DISABLE (0x01U << 29U)
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#define BM_RTC_PWR_ON_SET_RTC_TO_OFF_AP_LV_PG_DISABLE (0x01U << 28U)
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#define FM_RTC_PWR_ON_SET_RTC_PWR_ON_SET (0x3ffffU << 0U)
|
|
#define FV_RTC_PWR_ON_SET_RTC_PWR_ON_SET(v) \
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|
(((v) << 0U) & FM_RTC_PWR_ON_SET_RTC_PWR_ON_SET)
|
|
#define GFV_RTC_PWR_ON_SET_RTC_PWR_ON_SET(v) \
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|
(((v) & FM_RTC_PWR_ON_SET_RTC_PWR_ON_SET) >> 0U)
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#define PWR_UP_PWR_ON_DELAY_OFF 0x40U
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|
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#define FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX (0x3U << 30U)
|
|
#define FV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX(v) \
|
|
(((v) << 30U) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX)
|
|
#define GFV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX(v) \
|
|
(((v) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX) >> 30U)
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|
|
#define FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX (0x3U << 28U)
|
|
#define FV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX(v) \
|
|
(((v) << 28U) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX)
|
|
#define GFV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX(v) \
|
|
(((v) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX) >> 28U)
|
|
|
|
#define FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY (0xffffffU << 0U)
|
|
#define FV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY(v) \
|
|
(((v) << 0U) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY)
|
|
#define GFV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY(v) \
|
|
(((v) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY) >> 0U)
|
|
|
|
#define RUN_PWR_ON_DELAY_OFF 0x44U
|
|
|
|
#define FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX (0x3U << 30U)
|
|
#define FV_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX(v) \
|
|
(((v) << 30U) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX)
|
|
#define GFV_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX(v) \
|
|
(((v) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX) >> 30U)
|
|
|
|
#define FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX (0x3U << 28U)
|
|
#define FV_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX(v) \
|
|
(((v) << 28U) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX)
|
|
#define GFV_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX(v) \
|
|
(((v) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX) >> 28U)
|
|
|
|
#define FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY (0xffffffU << 0U)
|
|
#define FV_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY(v) \
|
|
(((v) << 0U) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY)
|
|
#define GFV_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY(v) \
|
|
(((v) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY) >> 0U)
|
|
|
|
#define SLEEP_PWR_ON_DELAY_OFF 0x48U
|
|
|
|
#define FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX (0x3U << 30U)
|
|
#define FV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX(v) \
|
|
(((v) << 30U) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX)
|
|
#define GFV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX(v) \
|
|
(((v) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX) >> 30U)
|
|
|
|
#define FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX (0x3U << 28U)
|
|
#define FV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX(v) \
|
|
(((v) << 28U) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX)
|
|
#define GFV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX(v) \
|
|
(((v) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX) >> 28U)
|
|
|
|
#define FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY (0xffffffU << 0U)
|
|
#define FV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY(v) \
|
|
(((v) << 0U) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY)
|
|
#define GFV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY(v) \
|
|
(((v) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY) >> 0U)
|
|
|
|
#define HIBERNATE_PWR_ON_DELAY_OFF 0x4cU
|
|
|
|
#define FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX (0x3U << 30U)
|
|
#define FV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX(v) \
|
|
(((v) << 30U) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX)
|
|
#define GFV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX(v) \
|
|
(((v) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX) >> 30U)
|
|
|
|
#define FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX (0x3U << 28U)
|
|
#define FV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX(v) \
|
|
(((v) << 28U) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX)
|
|
#define GFV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX(v) \
|
|
(((v) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX) >> 28U)
|
|
|
|
#define FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY (0xffffffU << 0U)
|
|
#define FV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY(v) \
|
|
(((v) << 0U) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY)
|
|
#define GFV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY(v) \
|
|
(((v) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY) >> 0U)
|
|
|
|
#define RTC_PWR_ON_DELAY_OFF 0x50U
|
|
|
|
#define FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX (0x3U << 30U)
|
|
#define FV_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX(v) \
|
|
(((v) << 30U) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX)
|
|
#define GFV_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX(v) \
|
|
(((v) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX) >> 30U)
|
|
|
|
#define FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX (0x3U << 28U)
|
|
#define FV_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX(v) \
|
|
(((v) << 28U) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX)
|
|
#define GFV_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX(v) \
|
|
(((v) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX) >> 28U)
|
|
|
|
#define FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY (0xffffffU << 0U)
|
|
#define FV_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY(v) \
|
|
(((v) << 0U) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY)
|
|
#define GFV_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY(v) \
|
|
(((v) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY) >> 0U)
|
|
|
|
#define SW_OVERRIDE_OFF 0x54U
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_HV_ISO_EN_ASSERT (0x01U << 31U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_HV_ISO_EN_DEASSERT (0x01U << 30U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_HV_ISO_EN_ASSERT (0x01U << 29U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_HV_ISO_EN_DEASSERT (0x01U << 28U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_POR_B_ASSERT (0x01U << 27U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_POR_B_DEASSERT (0x01U << 26U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_ISO_EN_ASSERT (0x01U << 25U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_ISO_EN_DEASSERT (0x01U << 24U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_POR_B_ASSERT (0x01U << 23U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_POR_B_DEASSERT (0x01U << 22U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_ISO_EN_ASSERT (0x01U << 21U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_ISO_EN_DEASSERT (0x01U << 20U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_HV_ISO_EN_EN (0x01U << 19U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_HV_ISO_EN (0x01U << 18U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_HV_ISO_EN_EN (0x01U << 17U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_HV_ISO_EN (0x01U << 16U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_ISO_EN_EN (0x01U << 15U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_ISO_EN (0x01U << 14U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_ISO_EN_EN (0x01U << 13U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_ISO_EN (0x01U << 12U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_POR_B_EN (0x01U << 11U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_AP_POR_B (0x01U << 10U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_POR_B_EN (0x01U << 9U)
|
|
|
|
#define BM_SW_OVERRIDE_SW_SF_POR_B (0x01U << 8U)
|
|
|
|
#define FM_SW_OVERRIDE_SW_PWR_ON_EN (0xfU << 4U)
|
|
#define FV_SW_OVERRIDE_SW_PWR_ON_EN(v) \
|
|
(((v) << 4U) & FM_SW_OVERRIDE_SW_PWR_ON_EN)
|
|
#define GFV_SW_OVERRIDE_SW_PWR_ON_EN(v) \
|
|
(((v) & FM_SW_OVERRIDE_SW_PWR_ON_EN) >> 4U)
|
|
|
|
#define FM_SW_OVERRIDE_SW_PWR_ON (0xfU << 0U)
|
|
#define FV_SW_OVERRIDE_SW_PWR_ON(v) \
|
|
(((v) << 0U) & FM_SW_OVERRIDE_SW_PWR_ON)
|
|
#define GFV_SW_OVERRIDE_SW_PWR_ON(v) \
|
|
(((v) & FM_SW_OVERRIDE_SW_PWR_ON) >> 0U)
|
|
|
|
#define PG_LP_MODE_CTRL_OFF 0x58U
|
|
|
|
#define FM_PG_LP_MODE_CTRL_RUN_LP_MODE (0xfU << 28U)
|
|
#define FV_PG_LP_MODE_CTRL_RUN_LP_MODE(v) \
|
|
(((v) << 28U) & FM_PG_LP_MODE_CTRL_RUN_LP_MODE)
|
|
#define GFV_PG_LP_MODE_CTRL_RUN_LP_MODE(v) \
|
|
(((v) & FM_PG_LP_MODE_CTRL_RUN_LP_MODE) >> 28U)
|
|
|
|
#define FM_PG_LP_MODE_CTRL_SLEEP_LP_MODE (0xfU << 24U)
|
|
#define FV_PG_LP_MODE_CTRL_SLEEP_LP_MODE(v) \
|
|
(((v) << 24U) & FM_PG_LP_MODE_CTRL_SLEEP_LP_MODE)
|
|
#define GFV_PG_LP_MODE_CTRL_SLEEP_LP_MODE(v) \
|
|
(((v) & FM_PG_LP_MODE_CTRL_SLEEP_LP_MODE) >> 24U)
|
|
|
|
#define FM_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE (0xfU << 20U)
|
|
#define FV_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE(v) \
|
|
(((v) << 20U) & FM_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE)
|
|
#define GFV_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE(v) \
|
|
(((v) & FM_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE) >> 20U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_RTC_LV_MONITOR (0x01U << 17U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_RTC_HV_MONITOR (0x01U << 16U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_RTC_SF_HV_PG_DISABLE (0x01U << 15U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_SF_HV_PG_DISABLE (0x01U << 14U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_RTC_AP_HV_PG_DISABLE (0x01U << 13U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_AP_HV_PG_DISABLE (0x01U << 12U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_RTC_SF_LV_PG_DISABLE (0x01U << 11U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_SF_LV_PG_DISABLE (0x01U << 10U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_RTC_AP_LV_PG_DISABLE (0x01U << 9U)
|
|
|
|
#define BM_PG_LP_MODE_CTRL_AP_LV_PG_DISABLE (0x01U << 8U)
|
|
|
|
#define FM_PG_LP_MODE_CTRL_SW_LP_MODE_EN (0xfU << 4U)
|
|
#define FV_PG_LP_MODE_CTRL_SW_LP_MODE_EN(v) \
|
|
(((v) << 4U) & FM_PG_LP_MODE_CTRL_SW_LP_MODE_EN)
|
|
#define GFV_PG_LP_MODE_CTRL_SW_LP_MODE_EN(v) \
|
|
(((v) & FM_PG_LP_MODE_CTRL_SW_LP_MODE_EN) >> 4U)
|
|
|
|
#define FM_PG_LP_MODE_CTRL_SW_LP_MODE (0xfU << 0U)
|
|
#define FV_PG_LP_MODE_CTRL_SW_LP_MODE(v) \
|
|
(((v) << 0U) & FM_PG_LP_MODE_CTRL_SW_LP_MODE)
|
|
#define GFV_PG_LP_MODE_CTRL_SW_LP_MODE(v) \
|
|
(((v) & FM_PG_LP_MODE_CTRL_SW_LP_MODE) >> 0U)
|
|
|
|
#define MIN_DELAY_STATE_TRAN_OFF 0x5cU
|
|
|
|
#define FM_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN (0x3fU << 24U)
|
|
#define FV_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN(v) \
|
|
(((v) << 24U) & FM_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN)
|
|
#define GFV_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN(v) \
|
|
(((v) & FM_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN) >> 24U)
|
|
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#define FM_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN (0x3fU << 16U)
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#define FV_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN(v) \
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(((v) << 16U) & FM_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN)
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#define GFV_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN(v) \
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(((v) & FM_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN) >> 16U)
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#define FM_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN (0x3fU << 8U)
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#define FV_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN(v) \
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(((v) << 8U) & FM_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN)
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#define GFV_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN(v) \
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(((v) & FM_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN) >> 8U)
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#define FM_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY (0x3fU << 0U)
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#define FV_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY(v) \
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(((v) << 0U) & FM_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY)
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#define GFV_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY(v) \
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(((v) & FM_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY) >> 0U)
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#define LP_CTRL_ON_FRC_OFF 0x60U
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#define BM_LP_CTRL_ON_FRC_PWR_ON3_ASSERT (0x01U << 23U)
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#define BM_LP_CTRL_ON_FRC_PWR_ON2_ASSERT (0x01U << 22U)
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#define BM_LP_CTRL_ON_FRC_PWR_ON1_ASSERT (0x01U << 21U)
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#define BM_LP_CTRL_ON_FRC_PWR_ON0_ASSERT (0x01U << 20U)
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#define BM_LP_CTRL_ON_FRC_PWR_ON3_DEASSERT (0x01U << 19U)
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#define BM_LP_CTRL_ON_FRC_PWR_ON2_DEASSERT (0x01U << 18U)
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#define BM_LP_CTRL_ON_FRC_PWR_ON1_DEASSERT (0x01U << 17U)
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#define BM_LP_CTRL_ON_FRC_PWR_ON0_DEASSERT (0x01U << 16U)
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#define BM_LP_CTRL_ON_FRC_PWR_CTRL3_ASSERT (0x01U << 15U)
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#define BM_LP_CTRL_ON_FRC_PWR_CTRL2_ASSERT (0x01U << 14U)
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#define BM_LP_CTRL_ON_FRC_PWR_CTRL1_ASSERT (0x01U << 13U)
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#define BM_LP_CTRL_ON_FRC_PWR_CTRL0_ASSERT (0x01U << 12U)
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#define BM_LP_CTRL_ON_FRC_PWR_CTRL3_DEASSERT (0x01U << 11U)
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#define BM_LP_CTRL_ON_FRC_PWR_CTRL2_DEASSERT (0x01U << 10U)
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#define BM_LP_CTRL_ON_FRC_PWR_CTRL1_DEASSERT (0x01U << 9U)
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#define BM_LP_CTRL_ON_FRC_PWR_CTRL0_DEASSERT (0x01U << 8U)
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#define BM_LP_CTRL_ON_FRC_LP_MODE3_ASSERT (0x01U << 7U)
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#define BM_LP_CTRL_ON_FRC_LP_MODE2_ASSERT (0x01U << 6U)
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#define BM_LP_CTRL_ON_FRC_LP_MODE1_ASSERT (0x01U << 5U)
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#define BM_LP_CTRL_ON_FRC_LP_MODE0_ASSERT (0x01U << 4U)
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#define BM_LP_CTRL_ON_FRC_LP_MODE3_DEASSERT (0x01U << 3U)
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#define BM_LP_CTRL_ON_FRC_LP_MODE2_DEASSERT (0x01U << 2U)
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#define BM_LP_CTRL_ON_FRC_LP_MODE1_DEASSERT (0x01U << 1U)
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#define BM_LP_CTRL_ON_FRC_LP_MODE0_DEASSERT (0x01U << 0U)
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#define PMU_SW_RESET_OFF 0x64U
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#define FM_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN (0x3U << 23U)
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#define FV_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN(v) \
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(((v) << 23U) & FM_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN)
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#define GFV_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN(v) \
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(((v) & FM_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN) >> 23U)
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#define BM_PMU_SW_RESET_PWR_DOWN_WAKEUP_TST (0x01U << 22U)
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#define BM_PMU_SW_RESET_PMU_AP_POR_B_TOGGLE (0x01U << 5U)
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#define BM_PMU_SW_RESET_PMU_SF_POR_B_TOGGLE (0x01U << 4U)
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#define BM_PMU_SW_RESET_PMU_SW_RESET_LOCK (0x01U << 1U)
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#define BM_PMU_SW_RESET_PMU_SW_RESET (0x01U << 0U)
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#define PMU_INT_OFF 0x68U
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#define FM_PMU_INT_PMU_INT_EN (0x1fffU << 16U)
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#define FV_PMU_INT_PMU_INT_EN(v) \
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(((v) << 16U) & FM_PMU_INT_PMU_INT_EN)
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#define GFV_PMU_INT_PMU_INT_EN(v) \
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(((v) & FM_PMU_INT_PMU_INT_EN) >> 16U)
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#define BM_PMU_INT_PWR_DOWN_REQ (0x01U << 12U)
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#define BM_PMU_INT_SWM_FATAL (0x01U << 11U)
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#define BM_PMU_INT_SWM_WARN (0x01U << 10U)
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#define BM_PMU_INT_RSV1 (0x01U << 9U)
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#define BM_PMU_INT_RSV0 (0x01U << 8U)
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#define BM_PMU_INT_LOCKSTEP_ERR_REBOOTED (0x01U << 7U)
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#define BM_PMU_INT_HIBERNATE_TO_RUN_REBOOTED (0x01U << 6U)
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#define BM_PMU_INT_SLEEP_TO_RUN_REBOOTED (0x01U << 5U)
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#define BM_PMU_INT_PWRUP_TO_RUN_REBOOTED (0x01U << 4U)
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#define BM_PMU_INT_PWR_ON3_WDT_ERR (0x01U << 3U)
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#define BM_PMU_INT_PWR_ON2_WDT_ERR (0x01U << 2U)
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#define BM_PMU_INT_PWR_ON1_WDT_ERR (0x01U << 1U)
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#define BM_PMU_INT_PWR_ON0_WDT_ERR (0x01U << 0U)
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#define PMU_COR_UNCOR_INT_OFF 0x6cU
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#define BM_PMU_COR_UNCOR_INT_PMU_COR_INT_EN (0x01U << 24U)
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#define FM_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN (0x1fU << 16U)
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#define FV_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN(v) \
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(((v) << 16U) & FM_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN)
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#define GFV_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN(v) \
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(((v) & FM_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN) >> 16U)
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#define BM_PMU_COR_UNCOR_INT_PMU_PWDATA_COR_ERR (0x01U << 8U)
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#define BM_PMU_COR_UNCOR_INT_PMU_PWDATA_FATAL_ERR (0x01U << 4U)
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#define BM_PMU_COR_UNCOR_INT_PMU_PWDATA_UNC_ERR (0x01U << 3U)
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#define BM_PMU_COR_UNCOR_INT_PMU_PADDR_UNC_ERR (0x01U << 2U)
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#define BM_PMU_COR_UNCOR_INT_PMU_PN_PAIR_ERR (0x01U << 1U)
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#define BM_PMU_COR_UNCOR_INT_PMU_LOCKSTEP_ERR (0x01U << 0U)
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#define SRCS_BITS_OFF 0x70U
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#define FM_SRCS_BITS_SRCS_BITS (0xffffffffU << 0U)
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#define FV_SRCS_BITS_SRCS_BITS(v) \
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(((v) << 0U) & FM_SRCS_BITS_SRCS_BITS)
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#define GFV_SRCS_BITS_SRCS_BITS(v) \
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(((v) & FM_SRCS_BITS_SRCS_BITS) >> 0U)
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#define SRCS_BITS_SET_OFF 0x74U
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#define FM_SRCS_BITS_SET_SRCS_BITS (0xffffffffU << 0U)
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#define FV_SRCS_BITS_SET_SRCS_BITS(v) \
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(((v) << 0U) & FM_SRCS_BITS_SET_SRCS_BITS)
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#define GFV_SRCS_BITS_SET_SRCS_BITS(v) \
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(((v) & FM_SRCS_BITS_SET_SRCS_BITS) >> 0U)
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#define SRCS_BITS_CLR_OFF 0x78U
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#define FM_SRCS_BITS_CLR_SRCS_BITS (0xffffffffU << 0U)
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#define FV_SRCS_BITS_CLR_SRCS_BITS(v) \
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(((v) << 0U) & FM_SRCS_BITS_CLR_SRCS_BITS)
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#define GFV_SRCS_BITS_CLR_SRCS_BITS(v) \
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(((v) & FM_SRCS_BITS_CLR_SRCS_BITS) >> 0U)
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#define SRCS_BITS_TOG_OFF 0x7cU
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#define FM_SRCS_BITS_TOG_SRCS_BITS (0xffffffffU << 0U)
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#define FV_SRCS_BITS_TOG_SRCS_BITS(v) \
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(((v) << 0U) & FM_SRCS_BITS_TOG_SRCS_BITS)
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#define GFV_SRCS_BITS_TOG_SRCS_BITS(v) \
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(((v) & FM_SRCS_BITS_TOG_SRCS_BITS) >> 0U)
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#define PMU_DOWN_UP_STATUS_OFF 0x80U
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE11 (0x01U << 15U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE10 (0x01U << 14U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE9 (0x01U << 13U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE8 (0x01U << 12U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE7 (0x01U << 11U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE6 (0x01U << 10U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE5 (0x01U << 9U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE4 (0x01U << 8U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE3 (0x01U << 7U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE2 (0x01U << 6U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE1 (0x01U << 5U)
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#define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE0 (0x01U << 4U)
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#define BM_PMU_DOWN_UP_STATUS_WAKEUP_SOURCE3 (0x01U << 3U)
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#define BM_PMU_DOWN_UP_STATUS_WAKEUP_SOURCE2 (0x01U << 2U)
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#define BM_PMU_DOWN_UP_STATUS_WAKEUP_SOURCE1 (0x01U << 1U)
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#define BM_PMU_DOWN_UP_STATUS_WAKEUP_SOURCE0 (0x01U << 0U)
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#define PMU_STATE_OFF 0x84U
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#define BM_PMU_STATE_RTC_AP_HV_PG (0x01U << 15U)
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#define BM_PMU_STATE_RTC_AP_LV_PG (0x01U << 14U)
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#define BM_PMU_STATE_RTC_SF_HV_PG (0x01U << 13U)
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#define BM_PMU_STATE_RTC_SF_LV_PG (0x01U << 12U)
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#define BM_PMU_STATE_AP_HV_PG (0x01U << 11U)
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#define BM_PMU_STATE_AP_LV_PG (0x01U << 10U)
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#define BM_PMU_STATE_SF_HV_PG (0x01U << 9U)
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#define BM_PMU_STATE_SF_LV_PG (0x01U << 8U)
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#define FM_PMU_STATE_PWR_RDY (0xfU << 4U)
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#define FV_PMU_STATE_PWR_RDY(v) \
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(((v) << 4U) & FM_PMU_STATE_PWR_RDY)
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#define GFV_PMU_STATE_PWR_RDY(v) \
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(((v) & FM_PMU_STATE_PWR_RDY) >> 4U)
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#define FM_PMU_STATE_PMU_STATE (0x7U << 0U)
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#define FV_PMU_STATE_PMU_STATE(v) \
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(((v) << 0U) & FM_PMU_STATE_PMU_STATE)
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#define GFV_PMU_STATE_PMU_STATE(v) \
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(((v) & FM_PMU_STATE_PMU_STATE) >> 0U)
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#define ERR_INJECTION_OFF 0x88U
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#define BM_ERR_INJECTION_ERR_INJ_EN (0x01U << 31U)
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#define FM_ERR_INJECTION_ERR_INJ_EN_SEL (0xffU << 16U)
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#define FV_ERR_INJECTION_ERR_INJ_EN_SEL(v) \
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(((v) << 16U) & FM_ERR_INJECTION_ERR_INJ_EN_SEL)
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#define GFV_ERR_INJECTION_ERR_INJ_EN_SEL(v) \
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(((v) & FM_ERR_INJECTION_ERR_INJ_EN_SEL) >> 16U)
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#define FM_ERR_INJECTION_ERR_INJECT_BITS (0xffU << 0U)
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#define FV_ERR_INJECTION_ERR_INJECT_BITS(v) \
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(((v) << 0U) & FM_ERR_INJECTION_ERR_INJECT_BITS)
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#define GFV_ERR_INJECTION_ERR_INJECT_BITS(v) \
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(((v) & FM_ERR_INJECTION_ERR_INJECT_BITS) >> 0U)
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#define ERR_INJECTION_WDATA_OFF 0x8cU
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#define FM_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA (0xffffffffU << 0U)
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#define FV_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA(v) \
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(((v) << 0U) & FM_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA)
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#define GFV_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA(v) \
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(((v) & FM_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA) >> 0U)
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#define ISTC_DEBUG_OFF 0xf0U
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#define FM_ISTC_DEBUG_ISTC_DEBUG (0xffffffffU << 0U)
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#define FV_ISTC_DEBUG_ISTC_DEBUG(v) \
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(((v) << 0U) & FM_ISTC_DEBUG_ISTC_DEBUG)
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#define GFV_ISTC_DEBUG_ISTC_DEBUG(v) \
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(((v) & FM_ISTC_DEBUG_ISTC_DEBUG) >> 0U)
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#define PMU_LOCKSTEP_STATUS_OFF 0x8000U
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#define FM_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR (0xffffU << 16U)
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#define FV_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR(v) \
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(((v) << 16U) & FM_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR)
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#define GFV_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR(v) \
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(((v) & FM_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR) >> 16U)
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#define BM_PMU_LOCKSTEP_STATUS_PRE2_RD_UPDATE (0x01U << 2U)
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#define BM_PMU_LOCKSTEP_STATUS_PRE_RD_UPDATE (0x01U << 1U)
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#define BM_PMU_LOCKSTEP_STATUS_CUR_RD_UPDATE (0x01U << 0U)
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#define PMU_APB_INT_OFF 0x8004U
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#define BM_PMU_APB_INT_APB_PN_CHK_ERR (0x01U << 3U)
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#define BM_PMU_APB_INT_APB_PCTL_UNC_ERR (0x01U << 2U)
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#define BM_PMU_APB_INT_APB_PADDR_UNC_ERR (0x01U << 1U)
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#define BM_PMU_APB_INT_APB_LKSTEP_ERR (0x01U << 0U)
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#define PMU_APB_INT_EN_OFF 0x8008U
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#define BM_PMU_APB_INT_EN_APB_PN_CHK_ERR_EN (0x01U << 3U)
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#define BM_PMU_APB_INT_EN_APB_PCTL_UNC_ERR_EN (0x01U << 2U)
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#define BM_PMU_APB_INT_EN_APB_PADDR_UNC_ERR_EN (0x01U << 1U)
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#define BM_PMU_APB_INT_EN_APB_LKSTEP_ERR_EN (0x01U << 0U)
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#define APB_ERR_INJECTION_OFF 0x800cU
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#define BM_APB_ERR_INJECTION_APB_ERROR_INJ_EN (0x01U << 8U)
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#define BM_APB_ERR_INJECTION_APB_ERROR_INJ_SEL (0x01U << 7U)
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#define FM_APB_ERR_INJECTION_APB_ERROR_INJ_BIT (0x7fU << 0U)
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#define FV_APB_ERR_INJECTION_APB_ERROR_INJ_BIT(v) \
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(((v) << 0U) & FM_APB_ERR_INJECTION_APB_ERROR_INJ_BIT)
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#define GFV_APB_ERR_INJECTION_APB_ERROR_INJ_BIT(v) \
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(((v) & FM_APB_ERR_INJECTION_APB_ERROR_INJ_BIT) >> 0U)
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#endif /* SDRV_TAISHAN_PMU_REG_H_ */
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