325 lines
16 KiB
HTML
325 lines
16 KiB
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<div id="projectname">SemiDrive SSDK Appication Program Interface<span id="projectnumber"> PTG3.0</span>
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="headertitle"><div class="title">sdrv_uart_config</div></div>
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<p><code>#include <<a class="el" href="sdrv__uart_8h_source.html">sdrv_uart.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a0523cedff47e2441fc198b7770ec5d3f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#a0523cedff47e2441fc198b7770ec5d3f">base</a></td></tr>
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<tr class="memitem:a17fdd15a71ced1e05faf127882011db3"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#a17fdd15a71ced1e05faf127882011db3">irq</a></td></tr>
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<tr class="memitem:ac6e5ec63505c02923d71f7409cdbf1d1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#ac6e5ec63505c02923d71f7409cdbf1d1">baud</a></td></tr>
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<tr class="memitem:a6e150bf7979f0599e001f893375eb671"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#a6e150bf7979f0599e001f893375eb671">clk_freq</a></td></tr>
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<tr class="memitem:a86d13becfdd428dddd69ba78ccc55790"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__uart_8h.html#a6a452cfa995984224e30587163ede297">sdrv_uart_dls_e</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#a86d13becfdd428dddd69ba78ccc55790">data_bits</a></td></tr>
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<tr class="separator:a86d13becfdd428dddd69ba78ccc55790"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a42413cbb57e015875db04c4efb81e7c8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__uart_8h.html#a35520d0ce6bcc8d5807972259c3e5e45">sdrv_uart_stop_e</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#a42413cbb57e015875db04c4efb81e7c8">stop_bits</a></td></tr>
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<tr class="memitem:a3568ea944bd03911f4cedfbb856a22d1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__uart_8h.html#a3ee70673f8bcf6a1611d65dd55280dcd">sdrv_uart_parity_e</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#a3568ea944bd03911f4cedfbb856a22d1">parity</a></td></tr>
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<tr class="separator:a3568ea944bd03911f4cedfbb856a22d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae191ad594eb05a356e1add8d988d7f55"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__uart_8h.html#a7739e5ba15947aade0de59866f064938">sdrv_uart_fcm_config_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#ae191ad594eb05a356e1add8d988d7f55">fcm</a></td></tr>
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<tr class="memitem:a5282442e30827647f344387456fc9f3e"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#a5282442e30827647f344387456fc9f3e">abr_en</a></td></tr>
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<tr class="memitem:af86c1ef8a75366b784e9f8624f070c13"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__uart_8h.html#a371fe3e74602e812997882500cd168f8">sdrv_abr_max_e</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#af86c1ef8a75366b784e9f8624f070c13">match_num</a></td></tr>
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<tr class="separator:af86c1ef8a75366b784e9f8624f070c13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee6384aa5fb9edaaebe9f6295f41f396"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#aee6384aa5fb9edaaebe9f6295f41f396">txwmlvl</a></td></tr>
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<tr class="memitem:a233b13eb445ab06f57b90be54cab805a"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#a233b13eb445ab06f57b90be54cab805a">rxwmlvl</a></td></tr>
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<tr class="memitem:a4a26d70a133e77961cd49db47521ea14"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#a4a26d70a133e77961cd49db47521ea14">dma_en</a></td></tr>
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<tr class="memitem:afc4b104a152cd6cb42c8ca3ec3c69690"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__uart_8h.html#a8d4d5ad3e43bdba34353fc71019da3d4">sdrv_rxidle_ctl_e</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__uart__config.html#afc4b104a152cd6cb42c8ca3ec3c69690">rx_idle</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<a id="a5282442e30827647f344387456fc9f3e" name="a5282442e30827647f344387456fc9f3e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a5282442e30827647f344387456fc9f3e">◆ </a></span>abr_en</h2>
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<td class="memname">uint8_t abr_en</td>
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<p >Auto baudrate detect enable/disable </p>
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<a id="a0523cedff47e2441fc198b7770ec5d3f" name="a0523cedff47e2441fc198b7770ec5d3f"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a0523cedff47e2441fc198b7770ec5d3f">◆ </a></span>base</h2>
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<td class="memname">uint32_t base</td>
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</div><div class="memdoc">
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<p >Uart module base </p>
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<a id="ac6e5ec63505c02923d71f7409cdbf1d1" name="ac6e5ec63505c02923d71f7409cdbf1d1"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ac6e5ec63505c02923d71f7409cdbf1d1">◆ </a></span>baud</h2>
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<td class="memname">uint32_t baud</td>
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<p >Driver will set the result of clk_freq/baud to the baudrate register. Note : User need to note the baudrate register is an integer, there is an error between the excepted value and the actual value set in the register.The baudrate error interrupt state is generated when the error exceeds 1.5%. When the value of clk_freq/baud is greater than 34, user do not need to consder the above error. </p>
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<a id="a6e150bf7979f0599e001f893375eb671" name="a6e150bf7979f0599e001f893375eb671"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a6e150bf7979f0599e001f893375eb671">◆ </a></span>clk_freq</h2>
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<td class="memname">uint32_t clk_freq</td>
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</div><div class="memdoc">
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<p >Uart clk freq </p>
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<a id="a86d13becfdd428dddd69ba78ccc55790" name="a86d13becfdd428dddd69ba78ccc55790"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a86d13becfdd428dddd69ba78ccc55790">◆ </a></span>data_bits</h2>
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<td class="memname"><a class="el" href="sdrv__uart_8h.html#a6a452cfa995984224e30587163ede297">sdrv_uart_dls_e</a> data_bits</td>
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</table>
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</div><div class="memdoc">
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<p >Number of data bits in one character </p>
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<a id="a4a26d70a133e77961cd49db47521ea14" name="a4a26d70a133e77961cd49db47521ea14"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a4a26d70a133e77961cd49db47521ea14">◆ </a></span>dma_en</h2>
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<td class="memname">bool dma_en</td>
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<p >Uart dma enable status </p>
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<a id="ae191ad594eb05a356e1add8d988d7f55" name="ae191ad594eb05a356e1add8d988d7f55"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ae191ad594eb05a356e1add8d988d7f55">◆ </a></span>fcm</h2>
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<td class="memname"><a class="el" href="sdrv__uart_8h.html#a7739e5ba15947aade0de59866f064938">sdrv_uart_fcm_config_t</a> fcm</td>
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</div><div class="memdoc">
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<p >Flow control mode </p>
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<a id="a17fdd15a71ced1e05faf127882011db3" name="a17fdd15a71ced1e05faf127882011db3"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a17fdd15a71ced1e05faf127882011db3">◆ </a></span>irq</h2>
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<td class="memname">uint32_t irq</td>
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<p >Uart module irq num </p>
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<a id="af86c1ef8a75366b784e9f8624f070c13" name="af86c1ef8a75366b784e9f8624f070c13"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#af86c1ef8a75366b784e9f8624f070c13">◆ </a></span>match_num</h2>
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<td class="memname"><a class="el" href="sdrv__uart_8h.html#a371fe3e74602e812997882500cd168f8">sdrv_abr_max_e</a> match_num</td>
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<p >The character number that abr expect to recv and match </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a3568ea944bd03911f4cedfbb856a22d1">◆ </a></span>parity</h2>
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<td class="memname"><a class="el" href="sdrv__uart_8h.html#a3ee70673f8bcf6a1611d65dd55280dcd">sdrv_uart_parity_e</a> parity</td>
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<p >Parity type </p>
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<h2 class="memtitle"><span class="permalink"><a href="#afc4b104a152cd6cb42c8ca3ec3c69690">◆ </a></span>rx_idle</h2>
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<td class="memname"><a class="el" href="sdrv__uart_8h.html#a8d4d5ad3e43bdba34353fc71019da3d4">sdrv_rxidle_ctl_e</a> rx_idle</td>
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<p >The time of high level on rx line to detect idle. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a233b13eb445ab06f57b90be54cab805a">◆ </a></span>rxwmlvl</h2>
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<td class="memname">uint8_t rxwmlvl</td>
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<p >Receive water level </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a42413cbb57e015875db04c4efb81e7c8">◆ </a></span>stop_bits</h2>
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<td class="memname"><a class="el" href="sdrv__uart_8h.html#a35520d0ce6bcc8d5807972259c3e5e45">sdrv_uart_stop_e</a> stop_bits</td>
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<p >Number of stop bits </p>
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<a id="aee6384aa5fb9edaaebe9f6295f41f396" name="aee6384aa5fb9edaaebe9f6295f41f396"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aee6384aa5fb9edaaebe9f6295f41f396">◆ </a></span>txwmlvl</h2>
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<td class="memname">uint8_t txwmlvl</td>
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<p >Transmit water level </p>
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<hr/>The documentation for this struct was generated from the following file:<ul>
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<li>Z:/01-Code/06-SSDK-DEV-Firewall/ssdk/drivers/include/<a class="el" href="sdrv__uart_8h_source.html">sdrv_uart.h</a></li>
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