481 lines
14 KiB
C
481 lines
14 KiB
C
/**
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* @file sdrv_pvt.c
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* @brief SemiDrive Temperature sensor driver source file.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#include <bits.h>
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#include <debug.h>
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#include <irq.h>
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#include <reg.h>
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#include "sdrv_pvt.h"
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/* Length of PVT DOUT and Threshold register bits. */
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#define PVT_THRESH_BITS (12)
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/* PVT registers */
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#define PVT_CORE_REG_OFFSET (0x34)
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#define PVT_CORE_REGISTER(core, reg) ((core)*PVT_CORE_REG_OFFSET + (reg))
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#define PVT_CTRL (0x0)
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#define PVT_CTRL_PDTSEN 1
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#define PVT_CTRL_PDPSEN 2
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#define PVT_CTRL_PTSEL 4
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#define PVT_CTRL_LPMODE 7
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#define PVT_CTRL_HL_MODE_EN(core) (8 + (core)*2)
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#define PVT_CTRL_RF_MODE_EN(core) (9 + (core)*2)
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#define PVT_DOUT (0x4)
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#define PVT_DOUT_VALID 0
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#define PVT_DOUT_DATA 1
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#define PVT_HYST_H(core) PVT_CORE_REGISTER(core, 0x8)
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#define PVT_HYST_H_THRESH_H 0
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#define PVT_HYST_H_THRESH_L 12
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#define PVT_HYST_L(core) PVT_CORE_REGISTER(core, 0xc)
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#define PVT_HYST_L_THRESH_H 0
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#define PVT_HYST_L_THRESH_L 12
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#define PVT_HYST_R(core) PVT_CORE_REGISTER(core, 0x10)
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#define PVT_HYST_R_ALARM 0
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#define PVT_HYST_R_HYST 12
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#define PVT_HYST_F(core) PVT_CORE_REGISTER(core, 0x14)
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#define PVT_HYST_F_ALARM 0
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#define PVT_HYST_F_HYST 12
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#define PVT_INT_EN(core) PVT_CORE_REGISTER(core, 0x30)
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#define PVT_INT_STATUS(core) PVT_CORE_REGISTER(core, 0x34)
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#define PVT_INT_CLR(core) PVT_CORE_REGISTER(core, 0x38)
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#define PVT_ALARM_INT(alarm) (uint32_t)(alarm)
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static inline sdrv_pvt_core_t *pvt_core(sdrv_pvt_t *dev,
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sdrv_pvt_core_id_e core)
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{
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return &dev->core[core];
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}
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/* Convert DOUT register value to Celsius. */
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static inline sdrv_pvt_type dout_to_celsius(uint32_t dout)
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{
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dout &= BIT_MASK(PVT_THRESH_BITS);
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#if CONFIG_PVT_TYPE_INT
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return (30676 * dout / 4096 - 7598 + 50) / 100;
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#else
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return 306.76f * dout / 4096 - 75.98f;
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#endif
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}
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/* Convert Celsius to DOUT register value. */
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static inline uint32_t celsius_to_dout(sdrv_pvt_type celsius)
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{
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uint32_t dout = (uint32_t)((celsius * 100 + 7598) * 4096 / 30676);
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return dout & BIT_MASK(PVT_THRESH_BITS);
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}
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static int pvt_core_irq_handler(sdrv_pvt_t *dev, sdrv_pvt_core_id_e core)
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{
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sdrv_pvt_core_t *_core = pvt_core(dev, core);
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paddr_t base = dev->base;
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sdrv_pvt_alarm_e alarm;
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uint32_t en, status;
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en = readl(base + PVT_INT_EN(core));
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status = readl(base + PVT_INT_STATUS(core));
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/* Handle alarm IRQ, if it's enabled. */
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for (alarm = PVT_HIGH_LEVEL_ALARM; alarm < PVT_ALARM_NR; alarm++) {
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if (BIT_SET(en, PVT_ALARM_INT(alarm)) &&
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BIT_SET(status, PVT_ALARM_INT(alarm))) {
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if (_core->alarm_cb != NULL) {
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/* Call user alarm callback. */
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_core->alarm_cb(dev, core, alarm, _core->cb_arg);
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}
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/*
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* Try to clear interrupt status. Level interrupt status are
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* cleared when INT_CLR bits are set, and DOUT has returned to
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* normal range. Edge interrupt status are cleared when INT_CLR
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* bits are set.
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*
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* Note that INT_CLR itself is not auto cleared, so we have to
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* clear INT_CLR manually.
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*/
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RMWREG32(base + PVT_INT_CLR(core), PVT_ALARM_INT(alarm), 1, 1);
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RMWREG32(base + PVT_INT_CLR(core), PVT_ALARM_INT(alarm), 1, 0);
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}
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}
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return 0;
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}
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static int pvt_irq_handler(uint32_t irq, void *arg)
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{
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sdrv_pvt_t *dev = arg;
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sdrv_pvt_core_id_e core;
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for (core = PVT_CORE0; core < PVT_CORE_NR; core++) {
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sdrv_pvt_core_t *_core = pvt_core(dev, core);
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if (irq == _core->irq) {
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pvt_core_irq_handler(dev, core);
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break;
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}
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}
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return 0;
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}
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static status_t update_alarm_irq(sdrv_pvt_t *dev, sdrv_pvt_core_id_e core)
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{
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sdrv_pvt_core_t *_core = pvt_core(dev, core);
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paddr_t base = dev->base;
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/* Update High/Low mode bit in PVT_CTRL register, which controls
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* Temperature and Process High/Low modes.
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*/
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if (BIT_SET(_core->alarm_enable_mask, PVT_HIGH_LEVEL_ALARM) ||
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BIT_SET(_core->alarm_enable_mask, PVT_LOW_LEVEL_ALARM)) {
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RMWREG32(base + PVT_CTRL, PVT_CTRL_HL_MODE_EN(core), 1, 1);
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} else {
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RMWREG32(base + PVT_CTRL, PVT_CTRL_HL_MODE_EN(core), 1, 0);
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}
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#if SDRV_PVT_USE_EDGE_ALARM
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/* Update Rising/Falling mode bit in PVT_CTRL register, which controls
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* Temperature and Process Rising/Falling modes.
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*/
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if (BIT_SET(_core->alarm_enable_mask, PVT_RISING_EDGE_ALARM) ||
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BIT_SET(_core->alarm_enable_mask, PVT_FALLING_EDGE_ALARM)) {
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RMWREG32(base + PVT_CTRL, PVT_CTRL_RF_MODE_EN(core), 1, 1);
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} else {
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RMWREG32(base + PVT_CTRL, PVT_CTRL_RF_MODE_EN(core), 1, 0);
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}
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#endif
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/* Enable alarm interrupt if necessary. */
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if (_core->alarm_cb != NULL && _core->alarm_enable_mask != 0) {
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sdrv_pvt_alarm_e alarm;
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for (alarm = PVT_HIGH_LEVEL_ALARM; alarm < PVT_ALARM_NR; alarm++) {
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if (BIT_SET(_core->alarm_enable_mask, alarm)) {
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RMWREG32(base + PVT_INT_EN(core), PVT_ALARM_INT(alarm), 1, 1);
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} else {
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RMWREG32(base + PVT_INT_EN(core), PVT_ALARM_INT(alarm), 1, 0);
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}
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}
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/* Enable PVT interrupt. */
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irq_enable(_core->irq);
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} else {
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/* All alarm disabled. Disable PVT interrupt. */
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irq_disable(_core->irq);
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}
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return SDRV_STATUS_OK;
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}
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static status_t update_alarm_mode(sdrv_pvt_t *dev, sdrv_pvt_core_id_e core,
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sdrv_pvt_alarm_e alarm, bool enable)
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{
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sdrv_pvt_core_t *_core = pvt_core(dev, core);
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if (enable) {
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_core->alarm_enable_mask |= (1ul << alarm);
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} else {
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_core->alarm_enable_mask &= ~(1ul << alarm);
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}
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return update_alarm_irq(dev, core);
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}
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static bool
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is_valid_level_alarm_config(sdrv_pvt_alarm_e alarm,
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const sdrv_pvt_level_alarm_config_t *config)
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{
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(void)alarm;
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return config != NULL && config->thresh_low >= PVT_TEMPERATURE_MIN &&
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config->thresh_high <= PVT_TEMPERATURE_MAX &&
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celsius_to_dout(config->thresh_low) <=
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celsius_to_dout(config->thresh_high);
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}
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#if SDRV_PVT_USE_EDGE_ALARM
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static bool
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is_valid_edge_alarm_config(sdrv_pvt_alarm_e alarm,
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const sdrv_pvt_edge_alarm_config_t *config)
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{
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if (alarm == PVT_RISING_EDGE_ALARM) {
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return config != NULL && config->hyst >= PVT_TEMPERATURE_MIN &&
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config->alarm <= PVT_TEMPERATURE_MAX &&
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celsius_to_dout(config->hyst) < celsius_to_dout(config->alarm);
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} else { /* PVT_FALLING_EDGE_ALARM */
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return config != NULL && config->alarm >= PVT_TEMPERATURE_MIN &&
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config->hyst <= PVT_TEMPERATURE_MAX &&
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celsius_to_dout(config->alarm) < celsius_to_dout(config->hyst);
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}
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}
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#endif
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static status_t enable_level_alarm(sdrv_pvt_t *dev, sdrv_pvt_core_id_e core,
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sdrv_pvt_alarm_e alarm,
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const sdrv_pvt_level_alarm_config_t *config,
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bool enable)
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{
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paddr_t base = dev->base;
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if (enable) {
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if (!is_valid_level_alarm_config(alarm, config)) {
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ssdk_printf(SSDK_ERR, "Invalid level alarm config!\r\n");
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return SDRV_PVT_INVALID_PARAM;
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}
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/* Update High/Low alarm thresholds. */
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if (alarm == PVT_HIGH_LEVEL_ALARM) {
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RMWREG32(base + PVT_HYST_H(core), PVT_HYST_H_THRESH_H,
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PVT_THRESH_BITS, celsius_to_dout(config->thresh_high));
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RMWREG32(base + PVT_HYST_H(core), PVT_HYST_H_THRESH_L,
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PVT_THRESH_BITS, celsius_to_dout(config->thresh_low));
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} else { /* PVT_LOW_LEVEL_ALARM */
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RMWREG32(base + PVT_HYST_L(core), PVT_HYST_L_THRESH_H,
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PVT_THRESH_BITS, celsius_to_dout(config->thresh_high));
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RMWREG32(base + PVT_HYST_L(core), PVT_HYST_L_THRESH_L,
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PVT_THRESH_BITS, celsius_to_dout(config->thresh_low));
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}
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}
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return update_alarm_mode(dev, core, alarm, enable);
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}
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#if SDRV_PVT_USE_EDGE_ALARM
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static status_t enable_edge_alarm(sdrv_pvt_t *dev, sdrv_pvt_core_id_e core,
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sdrv_pvt_alarm_e alarm,
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const sdrv_pvt_edge_alarm_config_t *config,
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bool enable)
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{
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paddr_t base = dev->base;
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if (enable) {
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if (!is_valid_edge_alarm_config(alarm, config)) {
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ssdk_printf(SSDK_ERR, "Invalid edge alarm config!\r\n");
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return SDRV_PVT_INVALID_PARAM;
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}
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/* Update Rising/Falling alarm thresholds. */
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if (alarm == PVT_RISING_EDGE_ALARM) {
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RMWREG32(base + PVT_HYST_R(core), PVT_HYST_R_ALARM, PVT_THRESH_BITS,
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celsius_to_dout(config->alarm));
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RMWREG32(base + PVT_HYST_R(core), PVT_HYST_R_HYST, PVT_THRESH_BITS,
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celsius_to_dout(config->hyst));
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} else { /* PVT_FALLING_EDGE_ALARM */
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RMWREG32(base + PVT_HYST_F(core), PVT_HYST_F_ALARM, PVT_THRESH_BITS,
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celsius_to_dout(config->alarm));
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RMWREG32(base + PVT_HYST_F(core), PVT_HYST_F_HYST, PVT_THRESH_BITS,
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celsius_to_dout(config->hyst));
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}
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}
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return update_alarm_mode(dev, core, alarm, enable);
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}
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#endif
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static bool is_temperature_sensor_running(sdrv_pvt_t *dev)
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{
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uint32_t ctrl = readl(dev->base + PVT_CTRL);
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return !BIT_SET(ctrl, PVT_CTRL_PDTSEN) && !BIT_SET(ctrl, PVT_CTRL_PTSEL);
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}
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status_t sdrv_pvt_init(sdrv_pvt_t *dev)
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{
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ASSERT(dev != NULL);
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paddr_t base = dev->base;
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sdrv_pvt_core_id_e core;
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for (core = PVT_CORE0; core < PVT_CORE_NR; core++) {
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sdrv_pvt_core_t *_core = pvt_core(dev, core);
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/* Disable all interrupts by default. */
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writel(0ul, base + PVT_INT_EN(core));
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_core->alarm_cb = NULL;
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_core->cb_arg = NULL;
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_core->alarm_enable_mask = 0ul;
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irq_attach(_core->irq, pvt_irq_handler, dev);
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irq_disable(_core->irq);
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}
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return SDRV_STATUS_OK;
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}
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status_t sdrv_pvt_deinit(sdrv_pvt_t *dev)
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{
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ASSERT(dev != NULL);
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paddr_t base = dev->base;
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sdrv_pvt_core_id_e core;
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for (core = PVT_CORE0; core < PVT_CORE_NR; core++) {
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sdrv_pvt_core_t *_core = pvt_core(dev, core);
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irq_disable(_core->irq);
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irq_detach(_core->irq);
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/* Disable all interrupts. */
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writel(0, base + PVT_INT_EN(core));
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_core->alarm_cb = NULL;
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_core->cb_arg = NULL;
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_core->alarm_enable_mask = 0ul;
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}
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return SDRV_STATUS_OK;
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}
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status_t sdrv_pvt_start(sdrv_pvt_t *dev)
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{
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ASSERT(dev != NULL);
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paddr_t base = dev->base;
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/* Low power mode disable */
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RMWREG32(base + PVT_CTRL, PVT_CTRL_LPMODE, 1, 0);
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/* Disable T sensor */
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RMWREG32(base + PVT_CTRL, PVT_CTRL_PDTSEN, 1, 1);
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/* Select temperature sensor output. */
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RMWREG32(base + PVT_CTRL, PVT_CTRL_PTSEL, 1, 0);
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/* Enable T sensor. */
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RMWREG32(base + PVT_CTRL, PVT_CTRL_PDTSEN, 1, 0);
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return SDRV_STATUS_OK;
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}
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status_t sdrv_pvt_stop(sdrv_pvt_t *dev)
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{
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ASSERT(dev != NULL);
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/* Disable T sensor */
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RMWREG32(dev->base + PVT_CTRL, PVT_CTRL_PDTSEN, 1, 1);
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return SDRV_STATUS_OK;
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}
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status_t sdrv_pvt_power_down(sdrv_pvt_t *dev)
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{
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ASSERT(dev != NULL);
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paddr_t base = dev->base;
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/* Low power mode enable */
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RMWREG32(base + PVT_CTRL, PVT_CTRL_LPMODE, 1, 1);
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/* Power down T-sensor, P-sensor */
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RMWREG32(base + PVT_CTRL, PVT_CTRL_PDTSEN, 2, 3);
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RMWREG32(base + PVT_CTRL, PVT_CTRL_PDTSEN, 2, 0);
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RMWREG32(base + PVT_CTRL, PVT_CTRL_PDTSEN, 2, 3);
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return SDRV_STATUS_OK;
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}
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status_t sdrv_pvt_get(sdrv_pvt_t *dev, sdrv_pvt_type *temperature)
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{
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uint32_t dout;
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ASSERT(dev != NULL && temperature != NULL);
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if (!is_temperature_sensor_running(dev)) {
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ssdk_printf(SSDK_ERR, "Temperature sensor is not started!\r\n");
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return SDRV_PVT_NOT_STARTED;
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}
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/*
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* Read temperature data. PVT_DOUT is automatically updated every 280ms
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* after sdrv_pvt_start() is called.
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*/
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dout = (readl(dev->base + PVT_DOUT) >> PVT_DOUT_DATA) &
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BIT_MASK(PVT_THRESH_BITS);
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/* Convert data to Celsius. */
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*temperature = dout_to_celsius(dout);
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return SDRV_STATUS_OK;
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}
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status_t sdrv_pvt_register_alarm_cb(sdrv_pvt_t *dev, sdrv_pvt_core_id_e core,
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sdrv_pvt_alarm_cb_t alarm_cb, void *arg)
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{
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ASSERT(dev != NULL && core < PVT_CORE_NR);
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sdrv_pvt_core_t *_core = pvt_core(dev, core);
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_core->alarm_cb = alarm_cb;
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_core->cb_arg = arg;
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return update_alarm_irq(dev, core);
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}
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status_t sdrv_pvt_enable_alarm(sdrv_pvt_t *dev, sdrv_pvt_core_id_e core,
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sdrv_pvt_alarm_e alarm,
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const sdrv_pvt_alarm_config_t *config)
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{
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ASSERT(dev != NULL && core < PVT_CORE_NR && config != NULL);
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status_t ret = SDRV_PVT_INVALID_PARAM;
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if (!is_temperature_sensor_running(dev)) {
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ssdk_printf(SSDK_ERR, "Temperature sensor is not started!\r\n");
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return SDRV_PVT_NOT_STARTED;
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}
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switch (alarm) {
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case PVT_HIGH_LEVEL_ALARM:
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case PVT_LOW_LEVEL_ALARM:
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ret = enable_level_alarm(dev, core, alarm, &config->level_alarm, true);
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break;
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#if SDRV_PVT_USE_EDGE_ALARM
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case PVT_RISING_EDGE_ALARM:
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case PVT_FALLING_EDGE_ALARM:
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ret = enable_edge_alarm(dev, core, alarm, &config->edge_alarm, true);
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break;
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#endif
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default:
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break;
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}
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return ret;
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}
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status_t sdrv_pvt_disable_alarm(sdrv_pvt_t *dev, sdrv_pvt_core_id_e core,
|
|
sdrv_pvt_alarm_e alarm)
|
|
{
|
|
ASSERT(dev != NULL && core < PVT_CORE_NR);
|
|
status_t ret = SDRV_PVT_INVALID_PARAM;
|
|
|
|
switch (alarm) {
|
|
case PVT_HIGH_LEVEL_ALARM:
|
|
case PVT_LOW_LEVEL_ALARM:
|
|
ret = enable_level_alarm(dev, core, alarm, NULL, false);
|
|
break;
|
|
|
|
#if SDRV_PVT_USE_EDGE_ALARM
|
|
case PVT_RISING_EDGE_ALARM:
|
|
case PVT_FALLING_EDGE_ALARM:
|
|
ret = enable_edge_alarm(dev, core, alarm, NULL, false);
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|