217 lines
3.9 KiB
C
217 lines
3.9 KiB
C
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//*****************************************************************************
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//
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// WARNING: Automatically generated file, don't modify anymore!!!
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//
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// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
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// Software License Agreement
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//
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//*****************************************************************************
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#ifndef RESET_IP_H
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#define RESET_IP_H
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#include <sdrv_rstgen.h>
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/* SAF rstgen controller */
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extern sdrv_rstgen_t g_rstgen_saf;
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/* global reset */
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extern sdrv_rstgen_glb_t rstctl_glb;
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/* SAF core */
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extern sdrv_rstgen_sig_t rstsig_cr5_saf;
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/**
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* @brief reset latent
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*
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* latent signals will reset automatically after power on.
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*
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* signals in latent:
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* AHB2APB1
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* AHB2APB2
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* AHB2APB3
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* AHB2APB4
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* APBMUX2
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* APBMUX3
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* IROMC
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* IOMUXC_SF_COMP
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* MAC
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* SCR_SF
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* WDT1
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* SEM1
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* SEM2
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* VD_SF_DIG
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* IOC
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* EIC_SF
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* FUSE_LSP_CMP
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* FAB_SF
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* UART1
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* UART2
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* UART3
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* UART4
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* UART5
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* UART6
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* UART7
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* UART8
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* UART9
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* UART10
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* UART11
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* UART12
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* SPI1
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* SPI2
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* SPI3
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* SPI4
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* SPI5
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* SPI6
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* I2C1
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* I2C2
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* I2C3
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* I2C4
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* I2C5
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* I2C6
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* ETMR1
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* ETMR2
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* EPWM1
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* EPWM2
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* MPC_XSPI1A
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* MPC_XSPI1B
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* AAPB_MPC_XSPI1A
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* AAPB_MPC_XSPI1B
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* AAPB_MPC_SEIP
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* WDT8
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* PPC_APBMUX2
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* PPC_APBMUX3
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* PPC_APBMUX4
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* PPC_APBMUX1
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* MPC_ROMC
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* XB_SF
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* MPC_IRAMC1
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* MPC_CR5_SF
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* POR_SF_DIG
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* PT_SNS_SF_DIG
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* MPC_VIC1
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* BTM1
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* BTM2
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* BTM3
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* BTM4
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* AAPB_XSPI1A
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* AAPB_XSPI1B
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* MPC_SEIP
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* APB_APBMUX1_SLV
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* APB_PMUX2_DEC_SLV
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* AAPB_APBMUX3
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* APB_DCDC1_SLV
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* APB_APBMUX4_SLV
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* AAXI_APSF_MST
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*/
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extern sdrv_rstgen_sig_t rstsig_latent;
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/*
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* @brief reset mission
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*
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* reset mission signals will reset automatically after power on.
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*
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*/
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/**
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* @brief reset mission 0
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*
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* signals in mission 0:
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* GPIO_SF
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* IOMUXC_SF
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* SMC
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* PMU_CORE
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* APB_APBMUX1_MST
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* APB_PMUX2_DEC_MST
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* APB_SEIP_NVM_MST
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*/
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extern sdrv_rstgen_sig_t rstsig_mission0;
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/**
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* @brief reset mission 1
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*
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* signals in mission 1:
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* PLL1
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* PLL2
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* Pll3
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*/
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extern sdrv_rstgen_sig_t rstsig_mission1;
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/**
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* @brief reset mission 2
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*
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* signals in mission 2:
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* ANA_SF_SADC1
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* ANA_SF_SADC2
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* ANA_SF_SADC3
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* ANA_SF_SACMP1
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* ANA_SF_SACMP2
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*/
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extern sdrv_rstgen_sig_t rstsig_mission2;
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/**
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* @brief reset mission 3
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*
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* signals in mission 3:
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* IRAM1
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*/
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extern sdrv_rstgen_sig_t rstsig_mission3;
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/**
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* @brief reset mission 4
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*
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* signals in mission 4:
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* DCDC1
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* APB_DCDC1_MST
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*/
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extern sdrv_rstgen_sig_t rstsig_mission4;
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/**
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* @brief reset mission 5
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*
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* signals in mission 5:
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* APBMUX4
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* PTB
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* AHBDEC_SEIP
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* APB_SEC_STORAGE1_SLV
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* APB_SEIP_NVM_SLV
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* APB_APBMUX4_MST
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* AAXI_APSF_SLV
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*/
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extern sdrv_rstgen_sig_t rstsig_mission5;
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/* reset module */
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extern sdrv_rstgen_sig_t rstsig_canfd16;
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extern sdrv_rstgen_sig_t rstsig_canfd21;
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extern sdrv_rstgen_sig_t rstsig_canfd3;
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extern sdrv_rstgen_sig_t rstsig_canfd4;
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extern sdrv_rstgen_sig_t rstsig_canfd5;
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extern sdrv_rstgen_sig_t rstsig_canfd6;
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extern sdrv_rstgen_sig_t rstsig_canfd7;
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extern sdrv_rstgen_sig_t rstsig_canfd23;
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extern sdrv_rstgen_sig_t rstsig_xspi1a;
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extern sdrv_rstgen_sig_t rstsig_xspi1b;
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extern sdrv_rstgen_sig_t rstsig_dma_rst0;
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extern sdrv_rstgen_sig_t rstsig_dma_rst1;
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extern sdrv_rstgen_sig_t rstsig_enet1;
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extern sdrv_rstgen_sig_t rstsig_vic1;
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extern sdrv_rstgen_sig_t rstsig_xspi_slv;
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extern sdrv_rstgen_sig_t rstsig_xtrg;
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extern sdrv_rstgen_sig_t rstsig_saci2;
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extern sdrv_rstgen_sig_t rstsig_sehc1;
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extern sdrv_rstgen_sig_t rstsig_usb;
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extern sdrv_rstgen_sig_t rstsig_seip;
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extern sdrv_rstgen_sig_t rstsig_cslite;
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/* general register */
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extern sdrv_rstgen_general_reg_t reset_general_reg_sf_remap;
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extern sdrv_rstgen_general_reg_t reset_general_reg_sf_boot;
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extern sdrv_rstgen_general_reg_t reset_general_reg_rom_ctrl;
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/* recovery module */
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extern sdrv_recovery_btm_t recovery_btm_list;
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extern sdrv_recovery_etimer_t recovery_etimer_list;
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extern sdrv_recovery_epwm_t recovery_epwm_list;
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extern sdrv_recovery_module_t recovery_module_array;
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#endif |