sdrv_dma.h

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#ifndef __SDRV_DMA_H__
#define __SDRV_DMA_H__
 
#include <part.h>
#include "common.h"
#include "../source/dma/sdrv_dma_regdef.h"
#include "compiler.h"
#include "regs_base.h"
#include "sdrv_common.h"
#define SDRV_DMA_LP2_TT(n) ((((n)-1) << 4) & 0xfffff0)
#define SDRV_DMA_LP2_LPSIZE(n) ((__builtin_ffs(n) - 1) & 0xf)
/* bit4 ~ bit23 */
#define SDRV_DMA_LP2_LPSIZE_MAX (0x000FFFFF)
 
/* bit12 ~ bit23 */
#define SDRV_DMA_LP1_LP_COUNT_MAX (0X00000FFF)
/* bit0 ~ bit11 */
#define SDRV_DMA_LP1_LPSIZE_MAX (0X00000FFF)
 
/* bit0 ~ bit */
#define SDRV_DMA_LP0_LPSIZE_MAX (0x00FFFFFF)
 
#define SDRV_DMA_MAD_CRC_REGISTERS (7)
enum {
    /* dma channel id is invalid. */
    SDRV_DMA_INVALID_CHANNEL_ID = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_DMA, 0),
    /* dma channel config unsupport*/
    SDRV_DMA_UNSUPPORT_CONFIG = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_DMA, 1),
    /* dma channel invalid muxid*/
    SDRV_DMA_INVALID_MUXID = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_DMA, 2),
};
 
typedef enum {
    SDRV_DMA_CHANNEL_INVALID = -1,
    SDRV_DMA_CHANNEL_0 = 0,
    SDRV_DMA_CHANNEL_1,
    SDRV_DMA_CHANNEL_2,
    SDRV_DMA_CHANNEL_3,
    SDRV_DMA_CHANNEL_4,
    SDRV_DMA_CHANNEL_5,
    SDRV_DMA_CHANNEL_6,
    SDRV_DMA_CHANNEL_7,
    SDRV_DMA_CHANNEL_8,
    SDRV_DMA_CHANNEL_9,
    SDRV_DMA_CHANNEL_10,
    SDRV_DMA_CHANNEL_11,
    SDRV_DMA_CHANNEL_12,
    SDRV_DMA_CHANNEL_13,
    SDRV_DMA_CHANNEL_14,
    SDRV_DMA_CHANNEL_15,
    SDRV_DMA_CHANNEL_16,
    SDRV_DMA_CHANNEL_17,
    SDRV_DMA_CHANNEL_18,
    SDRV_DMA_CHANNEL_19,
    SDRV_DMA_CHANNEL_20,
    SDRV_DMA_CHANNEL_21,
    SDRV_DMA_CHANNEL_22,
    SDRV_DMA_CHANNEL_23,
} sdrv_dma_channel_id_e;
 
typedef enum {
    SDRV_DMA_TRANSFER_MODE_SINGLE = 0,
    SDRV_DMA_TRANSFER_MODE_CONTINUOUS,
    SDRV_DMA_TRANSFER_MODE_LINKLIST,
    SDRV_DMA_TRANSFER_MODE_CHAN_LINK,
    SDRV_DMA_TRANSFER_MODE_NOT_DEFINED,
} sdrv_dma_xfer_mode_e;
 
typedef enum {
    SDRV_DMA_DIR_MEM2MEM = 0, 
    SDRV_DMA_DIR_MEM2DEV,     
    SDRV_DMA_DIR_DEV2MEM,     
    SDRV_DMA_DIR_DEV2DEV,     
    SDRV_DMA_DIR_REG2MEM,     
    SDRV_DMA_DIR_REG2DEV,     
    SDRV_DMA_DIR_MEM2REG,     
    SDRV_DMA_DIR_DEV2REG,     
    SDRV_DMA_DIR_NOT_DEFINED,
} sdrv_dma_xfer_type_e;
 
typedef enum {
    SDRV_DMA_ADDR_INC = 0,
    SDRV_DMA_ADDR_NO_INC,
} sdrv_dma_addr_inc_e;
 
typedef enum {
    SDRV_DMA_BUSWIDTH_1_BYTE = 1,  
    SDRV_DMA_BUSWIDTH_2_BYTES = 2, 
    SDRV_DMA_BUSWIDTH_4_BYTES = 4, 
    SDRV_DMA_BUSWIDTH_8_BYTES = 8, 
} sdrv_dma_bus_width_e;
 
typedef enum {
    SDRV_DMA_BURST_LEN_1 = 0, 
    SDRV_DMA_BURST_LEN_2,     
    SDRV_DMA_BURST_LEN_3,     
    SDRV_DMA_BURST_LEN_4,     
    SDRV_DMA_BURST_LEN_5,     
    SDRV_DMA_BURST_LEN_6,     
    SDRV_DMA_BURST_LEN_7,     
    SDRV_DMA_BURST_LEN_8,     
    SDRV_DMA_BURST_LEN_9,     
    SDRV_DMA_BURST_LEN_10,    
    SDRV_DMA_BURST_LEN_11,    
    SDRV_DMA_BURST_LEN_12,    
    SDRV_DMA_BURST_LEN_13,    
    SDRV_DMA_BURST_LEN_14,    
    SDRV_DMA_BURST_LEN_15,    
    SDRV_DMA_BURST_LEN_16,    
    SDRV_DMA_BURST_LEN_UNDEFINED,
} sdrv_dma_burst_len_e;
 
typedef enum {
    SDRV_DMA_PORT_AXI64 = 0,
    SDRV_DMA_PORT_AHB32,
    SDRV_DMA_PROT_NOT_DEFINED,
} sdrv_dma_port_sel_e;
 
typedef enum {
    SDRV_DMA_SINGLE_BUFFER = 0,
    SDRV_DMA_DOUBLE_BUFFER,
    SDRV_DMA_CIRCULAR_BUFFER,
    SDRV_DMA_2D_BUFFER,
    SDRV_DMA_BUFFER_NOT_DEFINED,
} sdrv_dma_buffer_mode_e;
 
typedef enum {
    SDRV_DMA_SWT_EVT_CTL_STOP_WTH_INT = 0,
    SDRV_DMA_SWT_EVT_CTL_SUSPEND_WTH_INT,
    SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTH_INT,
    SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTHOUT_INT,
    SDRV_DMA_SWT_EVT_CTL_UNDEFINED,
} sdrv_dma_switch_event_ctrl_e;
 
typedef enum {
    SDRV_DMA_TRIGGER_BY_HARDWARE = 0,   
    SDRV_DMA_TRIGGER_BY_SOFTWARE,       
    SDRV_DMA_TRIGGER_BY_GTIMER,         
    SDRV_DMA_TRIGGER_BY_INTERNAL_EVENT, 
    SDRV_DMA_TRIGGER_MODE_NOT_DEFINED,
} sdrv_dma_trigger_mode_e;
 
typedef enum {
    SDRV_DMA_LOOP_MODE_0 = 0, 
    SDRV_DMA_LOOP_MODE_1,     
    SDRV_DMA_LOOP_MODE_2,     
    SDRV_DMA_LOOP_MODE_UNDEFINED,
} sdrv_dma_loop_mode_e;
 
typedef enum {
    SDRV_DMA_MUX_RD = 0x1, 
    SDRV_DMA_MUX_WR = 0x2, 
    SDRV_DMA_MUX_BOTH = (SDRV_DMA_MUX_RD | SDRV_DMA_MUX_WR),
} sdrv_dma_mux_direction_e;
 
typedef enum {
    SDRV_DMA_CH_STATUS_STOP = 0,      
    SDRV_DMA_CH_STATUS_FLUSH = 1,     
    SDRV_DMA_CH_STATUS_REQ_FLUSH = 2, 
    SDRV_DMA_CH_STATUS_HALT = 3,      
    SDRV_DMA_CH_STATUS_ENABLE = 4,    
    SDRV_DMA_CH_STATUS_RESUME = 5,    
    SDRV_DMA_CH_STATUS_ABORT = 6,     
} sdrv_dma_channel_status_e;
 
typedef enum {
    SDRV_DMA_HANDSHAKE_E2E_COR_ERR = (1 << 0),
    SDRV_DMA_HANDSHAKE_E2E_UNCOR_ERR = (1 << 1),
    SDRV_DMA_CHANNEL_FIFO_ECC_COR_ERR = (1 << 2),
    SDRV_DMA_CHANNEL_FIFO_ECC_UNCOR_ERR = (1 << 3),
    SDRV_DMA_AHB_READ_ERR = (1 << 4),
    SDRV_DMA_AHB_WRITE_ERR = (1 << 5),
    SDRV_DMA_AXI_READ_ERR = (1 << 6),
    SDRV_DMA_AXI_WRITE_ERR = (1 << 7),
    SDRV_DMA_CHANNEL_LINK_ERR = (1 << 8),
    SDRV_DMA_MAD_CRC_ERR = (1 << 9),
    SDRV_DMA_FIREWALL_RD_ERR = (1 << 10),
    SDRV_DMA_FIREWALL_WR_ERR = (1 << 11),
    SDRV_DMA_DATA_CRC_ERR = (1 << 12),
    SDRV_DMA_PATTERN_DETECTED = (1 << 13),
    SDRV_DMA_LAST_MAD_DONE = (1 << 14),
    SDRV_DMA_EVERY_MAD_DONE = (1 << 15),
    SDRV_DMA_CH_STOP = (1 << 16),
    SDRV_DMA_CH_FLUSH = (1 << 17),
    SDRV_DMA_CH_REQ_FLUSH = (1 << 18),
    SDRV_DMA_CH_HALT = (1 << 19),
    SDRV_DMA_CH_ABORT = (1 << 20),
    SDRV_DMA_REQ_TIMEOUT = (1 << 21),
    SDRV_DMA_SWITCH_EVENT = (1 << 22),
    SDRV_DMA_HS_COMP = (1 << 23),
    SDRV_DMA_PATTERN_POLL_MISMACTCH = (1 << 24),
    SDRV_DMA_AXI_OUTSTANDING_UTID_ERR = (1 << 26),
    SDRV_DMA_PROGRAMING_SEQUENCE_ERR = (1 << 27),
} sdrv_dma_interrupt_type_e;
 
typedef enum {
    SDRV_DMA_LINKLIST_NORMAL_MAD = 0,
    SDRV_DMA_LINKLIST_FIRST_MAD,
    SDRV_DMA_LINKLIST_LAST_MAD,
} sdrv_dma_linklist_type_e;
 
typedef enum {
    SDRV_DMA_COMPLETED = 0,  
    SDRV_DMA_BLOCK_DONE,     
    SDRV_DMA_IN_PROGRESS,    
    SDRV_DMA_PAUSED,         
    SDRV_DMA_ERR,            
    SDRV_DMA_PENDING,        
} sdrv_dma_status_e;
 
typedef enum {
    SDRV_DMA_CH_FSM_IDLE = 0,      
    SDRV_DMA_CH_FSM_MAD_CHECK,     
    SDRV_DMA_CH_FSM_POLL_OPD2,     
    SDRV_DMA_CH_FSM_DATA_TRANSFER, 
    SDRV_DMA_CH_FSM_STOP,          
    SDRV_DMA_CH_FSM_HALT,          
    SDRV_DMA_CH_FSM_DONE,          
} sdrv_dma_channle_ctrl_fsm_e;
 
typedef enum {
    SDRV_DMA_NO_MAD_CRC = 0,     
    SDRV_DMA_CHECK_CURR_MAD = 1, 
    SDRV_DMA_CHECK_CURR_MAD_AND_PREVIOUS =
        3, 
} sdrv_dma_mad_crc_mode_e;
 
typedef enum {
    SDRV_DMA_NO_DATA_CRC = 0, 
    SDRV_DMA_DATA_CRC_SENSE =
        1, 
    SDRV_DMA_DATA_CRC_VERIFY_WITH_OPD =
        2, 
    SDRV_DMA_DATA_CRC_VERIFY_BETWEEN_WR_RD =
        3, 
} sdrv_dma_data_crc_mode_e;
 
typedef enum {
    CRC32_802P3 = 0,
    CRC16_CCITT = 1,
    CRC8_CCITT = 2,
} sdrv_dma_data_crc_sel_e;
 
typedef struct {
    uint32_t port;                   
    uint64_t start_addr;             
    uint64_t len;                    
    sdrv_dma_mux_direction_e direct; 
} sdrv_dma_mux_param_t;
 
typedef struct {
    sdrv_dma_ch_src_reg src;
    sdrv_dma_ch_dst_reg dst;
    sdrv_dma_ch_tr_ctrl_reg xfer_ctrl;
    sdrv_dma_ch_blk_cfg_reg blk_cfg;
    sdrv_dma_ch_op_mod_reg op_mod;
    sdrv_dma_ch_op_data_reg op_data;
    sdrv_dma_ch_mad_crc_reg mad_crc;
    sdrv_dma_ch_ll_addr_reg link_addr;
} sdrv_dma_linklist_descriptor_t;
 
typedef struct sdrv_dma {
    sdrv_dma_ctrl_t *dma; 
} sdrv_dma_t;
 
typedef struct {
    sdrv_dma_t *instance;
    sdrv_dma_channel_id_e channel_id;
    sdrv_dma_xfer_mode_e xfer_mode;
    sdrv_dma_xfer_type_e xfer_type;
 
    paddr_t src_addr;
    sdrv_dma_bus_width_e src_width;
    sdrv_dma_addr_inc_e src_inc;
    uint32_t src_burst_len;
 
    paddr_t dst_addr;
    sdrv_dma_bus_width_e dst_width;
    sdrv_dma_addr_inc_e dst_inc;
    uint32_t dst_burst_len;
 
    uint32_t xfer_bytes;
 
    int mux_id;
 
    sdrv_dma_port_sel_e src_port_sel;
    sdrv_dma_port_sel_e dst_port_sel;
    uint32_t src_cache;
    uint32_t dst_cache;
    uint32_t interrupt_type;
 
    sdrv_dma_buffer_mode_e buffer_mode;
    sdrv_dma_loop_mode_e loop_mode;
    sdrv_dma_switch_event_ctrl_e switch_event_ctrl;
    sdrv_dma_trigger_mode_e trig_mode;
 
    paddr_t linklist_addr;
    sdrv_dma_linklist_type_e linklist_mad_type;
    sdrv_dma_mad_crc_mode_e mad_crc_mode;
    sdrv_dma_data_crc_mode_e data_crc_mode;
    sdrv_dma_data_crc_sel_e data_crc_sel;
} sdrv_dma_channel_config_t;
 
typedef void (*sdrv_dma_irq_handler)(uint32_t status, uint32_t param,
                                     void *context);
 
typedef struct {
    sdrv_dma_ctrl_t *dma;
    sdrv_dma_channel_id_e channel_id;
    sdrv_dma_channel_ctrl_t *channel;
    sdrv_dma_irq_handler irq_callback;
    void *irq_context;
} sdrv_dma_channel_t;
 
static inline sdrv_dma_channel_ctrl_t *
sdrv_dma_get_channel_ctrl_base(sdrv_dma_ctrl_t *dma_base,
                               sdrv_dma_channel_id_e channel)
{
    paddr_t ch_base = (paddr_t)(dma_base);
 
    return (sdrv_dma_channel_ctrl_t *)(ch_base + SDRV_DMA_CHANNEL_BASE_OFFSET +
                                       SDRV_DMA_CHANNEL_SIZE * channel);
}
 
static inline void
sdrv_dma_set_channel_sw_handshake(sdrv_dma_channel_ctrl_t *channel_base)
{
#define SDRV_DMA_LIMIT_TIMES 5
    int32_t limit = SDRV_DMA_LIMIT_TIMES;
 
    while (limit--) {
        if (channel_base->swhs.v == 0) {
            break;
        }
    }
 
    channel_base->swhs.req = 1;
 
    while (channel_base->ch_status.ctrl_fsm == SDRV_DMA_CH_FSM_DATA_TRANSFER)
        ;
 
    channel_base->swhs.req = 0;
}
 
static inline void sdrv_dma_set_channel_muxid(sdrv_dma_ctrl_t *dma_base,
                                              sdrv_dma_channel_id_e channel,
                                              uint32_t mux_id)
{
    sdrv_dma_channel_ctrl_t *ch_base =
        sdrv_dma_get_channel_ctrl_base(dma_base, channel);
 
    ch_base->port_cfg.csel = mux_id;
}
 
static inline void sdrv_dma_set_channel_rd_outstanding(
    sdrv_dma_ctrl_t *dma_base, sdrv_dma_channel_id_e channel, uint8_t value)
{
    sdrv_dma_channel_ctrl_t *ch_base =
        sdrv_dma_get_channel_ctrl_base(dma_base, channel);
 
    ch_base->port_cfg.rot = value;
}
 
static inline void sdrv_dma_set_channel_wr_outstanding(
    sdrv_dma_ctrl_t *dma_base, sdrv_dma_channel_id_e channel, uint8_t value)
{
    sdrv_dma_channel_ctrl_t *ch_base =
        sdrv_dma_get_channel_ctrl_base(dma_base, channel);
 
    ch_base->port_cfg.wot = value;
}
 
static inline void sdrv_dma_set_channel_interrupt(sdrv_dma_ctrl_t *dma_base,
                                                  sdrv_dma_channel_id_e channel,
                                                  uint32_t int_type)
{
    sdrv_dma_channel_ctrl_t *ch_base =
        sdrv_dma_get_channel_ctrl_base(dma_base, channel);
 
    ch_base->int_en.v = int_type;
}
 
static inline void sdrv_dma_reset_core_int_status(sdrv_dma_ctrl_t *dma_base)
{
    dma_base->int_cfg.cont_int_clr.v = 0xFFFFFFFF;
    dma_base->int_cfg.cont_int_clr.v = 0x00000000;
    dma_base->int_cfg.int_clr.v = 0xFFFFFFFF;
    dma_base->int_cfg.int_clr.v = 0x00000000;
}
 
static inline void sdrv_dma_reset_fifo(sdrv_dma_ctrl_t *dma_base)
{
    uint32_t *dma_fifo_addr =
        (uint32_t *)((paddr_t)dma_base + SDRV_DMA_FIFO_OFFSET);
    int index = 0;
 
    for (index = 0; index < (SDRV_DMA_FIFO_SIZE / sizeof(uint32_t)); index++) {
        dma_fifo_addr[index] = 0;
    }
}
 
static inline void
sdrv_dma_set_channel_status(sdrv_dma_channel_ctrl_t *channel_base,
                            sdrv_dma_channel_status_e status)
{
    switch (status) {
    case SDRV_DMA_CH_STATUS_STOP:
        channel_base->ch_cfg.stop = 1;
        while (channel_base->ch_cfg.stop)
            ;
        break;
    case SDRV_DMA_CH_STATUS_FLUSH:
        channel_base->ch_cfg.flush = 1;
        break;
    case SDRV_DMA_CH_STATUS_REQ_FLUSH:
        channel_base->ch_cfg.req_flush = 1;
        break;
    case SDRV_DMA_CH_STATUS_HALT:
#if CONFIG_E3L
        if (IS_P1)
            channel_base->ch_cfg.halt = 1;
        else if (channel_base->shadow_op_mod.trigger_mode !=
                 SDRV_DMA_TRIGGER_BY_INTERNAL_EVENT)
            channel_base->ch_cfg.halt = 1;
#else
        if (channel_base->shadow_op_mod.trigger_mode !=
            SDRV_DMA_TRIGGER_BY_INTERNAL_EVENT)
            channel_base->ch_cfg.halt = 1;
#endif
        break;
    case SDRV_DMA_CH_STATUS_RESUME:
        channel_base->ch_cfg.resume = 1;
        break;
    case SDRV_DMA_CH_STATUS_ABORT:
        channel_base->ch_cfg.abort = 1;
        break;
    default:
        break;
    }
}
 
void sdrv_dma_init_dmac(paddr_t base);
 
status_t sdrv_dma_create_instance(sdrv_dma_t *dma_instance, paddr_t base);
 
status_t sdrv_dma_init_channel_config(sdrv_dma_channel_config_t *config,
                                      sdrv_dma_t *instance);
 
status_t sdrv_dma_init_channel(sdrv_dma_channel_t *channel,
                               const sdrv_dma_channel_config_t *config);
 
status_t sdrv_dma_start_channel_xfer(sdrv_dma_channel_t *channel);
 
status_t sdrv_dma_stop_channel_xfer(sdrv_dma_channel_t *channel);
 
status_t sdrv_dma_deinit_channel(sdrv_dma_channel_t *channel);
 
status_t sdrv_dma_init_linklist_entry(sdrv_dma_linklist_descriptor_t *desc,
                                      const sdrv_dma_channel_config_t *config);
 
status_t sdrv_dma_set_channel_source_address(sdrv_dma_channel_t *channel,
                                             paddr_t addr);
 
void sdrv_dma_set_channel_buffer_size(sdrv_dma_channel_t *channel,
                                          sdrv_dma_loop_mode_e loop_mode,
                                          uint32_t total_size,
                                          uint32_t loop_size);
 
status_t sdrv_dma_set_channel_destination_address(sdrv_dma_channel_t *channel,
                                                  paddr_t addr);
 
status_t sdrv_dma_set_channel_xfer_bytes(sdrv_dma_channel_t *channel,
                                         uint32_t xfer_bytes);
 
uint32_t sdrv_dma_get_channel_xfer_bytes(sdrv_dma_channel_t *channel);
 
status_t sdrv_dma_clear_channel_xfer_bytes(sdrv_dma_channel_t *channel);
 
uint32_t sdrv_dma_get_channel_xfer_status(sdrv_dma_channel_t *channel);
 
status_t sdrv_dma_clear_channel_xfer_status(sdrv_dma_channel_t *channel,
                                            uint32_t status);
 
#endif