sdrv_ckgen.h

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#ifndef SDRV_CLK_H_
#define SDRV_CLK_H_
 
#include <sdrv_common.h>
#include <lib/list.h>
#include <types.h>
#include <part.h>
#include <sdrv_rtc.h>
 
#define CLK_NODE(node)  (sdrv_ckgen_node_t *)&(node.clk_node)
#define CLK_MHZ(x)      ((x) * 1000 * 1000)
 
#define CONFIG_CKGEN_PARENTS_NUM    5
 
enum sdrv_ckgen_error {
    SDRV_CKGEN_POINTER_IS_NULL             = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 1),
    SDRV_CKGEN_XTAL24M_NOT_READY           = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 2),
    SDRV_CKGEN_FS24M_WAIT_ACTIVE_TIMEOUT   = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 3),
    SDRV_CKGEN_XTAL32K_NOT_READY           = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 4),
    SDRV_CKGEN_FS32K_WAIT_ACTIVE_TIMEOUT   = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 5),
    SDRV_CKGEN_PLL_NOT_LOCK                = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 6),
    SDRV_CKGEN_PLL_RATE_WRONG              = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 7),
    SDRV_CKGEN_PLL_LVDS_DIV2_CHG_BUSY      = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 8),
    SDRV_CKGEN_PLL_LVDS_DIV7_CHG_BUSY      = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 9),
    SDRV_CKGEN_PLL_LVDS_CKGEN_CHG_BUSY     = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 10),
    SDRV_CKGEN_PLL_NOT_DSM_MODE            = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 11),
    SDRV_CKGEN_SLICE_TYPE_ERROR            = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 12),
    SDRV_CKGEN_SLICE_NO_SUITABLE_PARENT    = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 13),
    SDRV_CKGEN_SLICE_MAIN_STATUS_ERROR     = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 14),
    SDRV_CKGEN_SLICE_PRE_STATUS_ERROR      = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 15),
    SDRV_CKGEN_SLICE_D0_ACTIVE_ERROR       = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 16),
    SDRV_CKGEN_SLICE_POST_D0_ACTIVE_ERROR  = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 17),
    SDRV_CKGEN_SLICE_DIV_CHG_BUSY          = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 18),
    SDRV_CKGEN_BEYOND_MAX_DIVIDER          = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 19),
    SDRV_CKGEN_FREQUENCY_INCORRECT         = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 20),
    SDRV_CKGEN_CONSTRUCT_CLKTREE_FAILED    = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 21),
    SDRV_CKGEN_PARENT_NODE_NULL            = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 22),
    SDRV_CKGEN_BEYOND_MAX_AXI_RATE         = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 23),
    SDRV_CKGEN_CLOCK_SET_TIMEOUT           = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 24),
};
 
typedef enum sdrv_fs_src_type {
    FS_SRC_RC = 0,    
    FS_SRC_XTAL = 1   
} sdrv_fs_src_type_e;
 
typedef enum sdrv_ckgen_type {
    CKGEN_IP_SLICE_TYPE = 0,       
    CKGEN_SF_BUS_SLICE_TYPE = 1,   
    CKGEN_BUS_SLICE_TYPE = 2,      
    CKGEN_CORE_SLICE_TYPE = 3,     
    CKGEN_PCG_TYPE = 4,            
    CKGEN_BCG_TYPE = 5,            
    CKGEN_CCG_TYPE = 6,            
    CKGEN_PLL_CG_TYPE = 7,         
    CKGEN_XTAL_CG_TYPE = 8,        
    CKGEN_PLL_CTRL_TYPE = 9,       
    CKGEN_PLL_LVDS_TYPE = 10,      
    CKGEN_RC24M_TYPE = 11,         
    CKGEN_FS24M_TYPE = 12,         
    CKGEN_RC32K_TYPE = 13,         
    CKGEN_FS32K_TYPE = 14          
} sdrv_ckgen_type_e;
 
typedef enum sdrv_ckgen_lp_mode {
    CKGEN_RUN_MODE = 0,            
    CKGEN_HIB_MODE = 1,            
    CKGEN_SLP_MODE = 2             
} sdrv_ckgen_lp_mode_e;
 
typedef enum sdrv_ckgen_bus_out_type {
    CKGEN_BUS_CLK_OUT = 0,          
    CKGEN_BUS_CLK_OUT_M = 1,        
    CKGEN_BUS_CLK_OUT_N = 2,        
    CKGEN_BUS_CLK_OUT_P = 3,        
    CKGEN_BUS_CLK_OUT_Q = 4         
} sdrv_ckgen_bus_out_type_e;
 
typedef enum sdrv_ckgen_bus_post_div {
    CKGEN_BUS_DIV_4_2_1 = 0,    
    CKGEN_BUS_DIV_2_2_1 = 1     
} sdrv_ckgen_bus_post_div_e;
 
typedef enum sdrv_ckgen_ssc_amplitude {
    CKGEN_SSC_0P0_PERCENT = 0,     
    CKGEN_SSC_0P1_PERCENT,         
    CKGEN_SSC_0P2_PERCENT,         
    CKGEN_SSC_0P3_PERCENT,         
    CKGEN_SSC_0P4_PERCENT,         
    CKGEN_SSC_0P5_PERCENT,         
    CKGEN_SSC_0P6_PERCENT,         
    CKGEN_SSC_0P7_PERCENT,         
    CKGEN_SSC_0P8_PERCENT,         
    CKGEN_SSC_0P9_PERCENT,         
    CKGEN_SSC_1P0_PERCENT,         
    CKGEN_SSC_1P1_PERCENT,         
    CKGEN_SSC_1P2_PERCENT,         
    CKGEN_SSC_1P3_PERCENT,         
    CKGEN_SSC_1P4_PERCENT,         
    CKGEN_SSC_1P5_PERCENT,         
    CKGEN_SSC_1P6_PERCENT,         
    CKGEN_SSC_1P7_PERCENT,         
    CKGEN_SSC_1P8_PERCENT,         
    CKGEN_SSC_1P9_PERCENT,         
    CKGEN_SSC_2P0_PERCENT,         
    CKGEN_SSC_2P1_PERCENT,         
    CKGEN_SSC_2P2_PERCENT,         
    CKGEN_SSC_2P3_PERCENT,         
    CKGEN_SSC_2P4_PERCENT,         
    CKGEN_SSC_2P5_PERCENT,         
    CKGEN_SSC_2P6_PERCENT,         
    CKGEN_SSC_2P7_PERCENT,         
    CKGEN_SSC_2P8_PERCENT,         
    CKGEN_SSC_2P9_PERCENT,         
    CKGEN_SSC_3P0_PERCENT,         
    CKGEN_SSC_3P1_PERCENT,         
} sdrv_ckgen_ssc_amplitude_e;
 
typedef enum sdrv_ckgen_ssc_mode {
    CKGEN_NO_SSC = 0,         
    CKGEN_DOWN_SPREADING,     
    CKGEN_CENTER_SPREADING,   
} sdrv_ckgen_ssc_mode_e;
 
typedef enum sdrv_ckgen_ssc_freq {
    CKGEN_FREF_DIV_507 = 0,     
    CKGEN_FREF_DIV_761,         
    CKGEN_FREF_DIV_793,         
    CKGEN_FREF_DIV_857,         
} sdrv_ckgen_ssc_freq_e;
 
typedef struct sdrv_ckgen_node {
    uint32_t base;              
    uint16_t type;              
    uint16_t id;                
} sdrv_ckgen_node_t;
 
typedef struct sdrv_ckgen_slice_node {
    sdrv_ckgen_node_t clk_node;            
    uint8_t parents_num;                   
    const sdrv_ckgen_node_t *
        parents[CONFIG_CKGEN_PARENTS_NUM]; 
} sdrv_ckgen_slice_node_t;
 
typedef struct sdrv_ckgen_cg_node {
    sdrv_ckgen_node_t clk_node;           
    const sdrv_ckgen_node_t *parent;      
} sdrv_ckgen_cg_node_t;
 
typedef struct sdrv_pll_node {
    sdrv_ckgen_node_t clk_node;          
    const sdrv_ckgen_node_t *parent;     
} sdrv_pll_node_t;
 
typedef struct sdrv_ckgen_rate_config_node {
    sdrv_ckgen_node_t *clk_node;    
    uint32_t rate;                  
    bool dsm_en;                    
} sdrv_ckgen_rate_config_node_t;
 
typedef struct sdrv_ckgen_rate_config {
    uint32_t config_num;    
    sdrv_ckgen_rate_config_node_t config_nodes[];  
} sdrv_ckgen_rate_config_t;
 
typedef struct sdrv_ckgen_bus_config_node {
    sdrv_ckgen_node_t *clk_node;  
    uint32_t rate;                
    sdrv_ckgen_bus_post_div_e post_div;  
} sdrv_ckgen_bus_config_node_t;
 
typedef struct sdrv_ckgen_bus_config {
    uint32_t config_num;  
    sdrv_ckgen_bus_config_node_t config_nodes[];  
} sdrv_ckgen_bus_config_t;
 
typedef struct sdrv_ckgen_gating_config_node {
    sdrv_ckgen_node_t *clk_node;  
    sdrv_ckgen_lp_mode_e mode;    
    bool gating;                  
} sdrv_ckgen_gating_config_node_t;
 
typedef struct sdrv_ckgen_gating_config {
    uint32_t config_num;  
    sdrv_ckgen_gating_config_node_t config_nodes[];  
} sdrv_ckgen_gating_config_t;
 
typedef struct sdrv_ckgen_ip_clock_config_node {
    const sdrv_ckgen_node_t **ip_nodes; 
    sdrv_ckgen_lp_mode_e mode;    
    bool enable;                  
} sdrv_ckgen_ip_clock_config_node_t;
 
typedef struct sdrv_ckgen_ip_clock_config {
    uint32_t config_num;  
    sdrv_ckgen_ip_clock_config_node_t config_nodes[];  
} sdrv_ckgen_ip_clock_config_t;
 
typedef struct sdrv_ckgen_config {
    sdrv_ckgen_bus_config_t const *pre_bus_config; 
    sdrv_ckgen_rate_config_t const *pll_config; 
    sdrv_ckgen_bus_config_t const *bus_config;  
    sdrv_ckgen_rate_config_t const *core_config; 
    sdrv_ckgen_rate_config_t const *ip_config;  
    sdrv_ckgen_ip_clock_config_t const *enable_config; 
    sdrv_ckgen_gating_config_t const *gating_config;  
} sdrv_ckgen_config_t;
 
#if CONFIG_CLK_DUMP
 
typedef struct sdrv_clk {
    const char *name;
    const sdrv_ckgen_node_t *ckgen_ref;
    struct list_node node;
    struct list_node child;
} sdrv_clk_t;
 
typedef struct sdrv_clk_config {
    uint32_t config_num;
    sdrv_clk_t config_nodes[];
} sdrv_clk_config_t;
 
status_t sdrv_clktree_dump(sdrv_clk_config_t *clk_config, sdrv_clk_t *clk_node);
 
#endif /* CONFIG_CLK_DUMP */
 
typedef struct sdrv_ckgen_xcg_set {
    uint32_t base;  
    sdrv_ckgen_type_e cg_type;  
    uint32_t num;   
} sdrv_ckgen_xcg_set_t;
 
#if CONFIG_RTC_SS_DYNAMIC_PCLK
#include <armv7-r/irq.h>
#include <clock_ip.h>
 
#if CONFIG_RTC_SS_DYNAMIC_PCLK_IRQ_DISABLE
 
#define RTC_SS_ACCESS_START()  \
    irq_state_t _state = arch_irq_save();  \
    sdrv_ckgen_clock_config(CLK_NODE(g_ckgen_gating_rtc_pclk), true); \
    SDRV_RTC_REG_PARITY_ERR_ENABLE();
 
#define RTC_SS_ACCESS_END()  \
    SDRV_RTC_REG_PARITY_ERR_DISABLE(); \
    sdrv_ckgen_clock_config(CLK_NODE(g_ckgen_gating_rtc_pclk), false);  \
    arch_irq_restore(_state);
 
#else /* CONFIG_RTC_SS_DYNAMIC_PCLK_IRQ_DISABLE */
 
int sdrv_rtc_ss_pclk_enable(void);
int sdrv_rtc_ss_pclk_disable(void);
 
#define RTC_SS_ACCESS_START()  sdrv_rtc_ss_pclk_enable();
#define RTC_SS_ACCESS_END()  sdrv_rtc_ss_pclk_disable();
 
#endif /* CONFIG_RTC_SS_DYNAMIC_PCLK_IRQ_DISABLE */
 
#else
 
#define RTC_SS_ACCESS_START()
#define RTC_SS_ACCESS_END()
#endif /* CONFIG_RTC_SS_DYNAMIC_PCLK */
 
int sdrv_xtal24m_enable(sdrv_ckgen_node_t *ckgen, bool enable);
 
int sdrv_xtal24m_from_active_crystal(sdrv_ckgen_node_t *ckgen);
 
int sdrv_fs24m_change_src(sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src);
 
uint32_t sdrv_ckgen_get_fs32k_real_frequency(sdrv_ckgen_node_t *ckgen);
 
int sdrv_xtal32k_enable(sdrv_ckgen_node_t *ckgen, bool enable);
 
int sdrv_xtal32k_enable_nowait(sdrv_ckgen_node_t *ckgen, bool enable);
 
bool sdrv_xtal32k_get_ready_status(sdrv_ckgen_node_t *ckgen);
 
int sdrv_xtal32k_from_active_crystal(sdrv_ckgen_node_t *ckgen);
 
int sdrv_fs32k_change_src(sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src);
 
int sdrv_fs32k_change_src_nowait(sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src);
 
bool sdrv_fs32k_get_src_active_status(sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src);
 
int sdrv_fs32k_lpvd_power_ctrl(sdrv_ckgen_node_t *ckgen, bool power_on);
 
status_t sdrv_pll_set_rate(sdrv_ckgen_node_t *ckgen, uint32_t rate);
 
status_t sdrv_pll_set_rate_with_dsm(sdrv_ckgen_node_t *ckgen, uint32_t rate, bool dsm_en);
 
uint32_t sdrv_pll_get_rate(sdrv_ckgen_node_t *ckgen);
 
status_t sdrv_pll_is_locked(sdrv_ckgen_node_t *ckgen);
 
status_t sdrv_pll_set_ssc_amplitude(sdrv_ckgen_node_t *ckgen, sdrv_ckgen_ssc_amplitude_e amplitude);
 
status_t sdrv_pll_set_ssc_frequency(sdrv_ckgen_node_t *ckgen, sdrv_ckgen_ssc_freq_e ssc_freq);
 
status_t sdrv_pll_set_ssc_mode(sdrv_ckgen_node_t *ckgen, sdrv_ckgen_ssc_mode_e ssc_mode);
 
status_t sdrv_ckgen_set_rate(sdrv_ckgen_node_t *ckgen, uint32_t rate);
 
uint32_t sdrv_ckgen_get_rate(sdrv_ckgen_node_t *ckgen);
 
status_t sdrv_ckgen_bus_set_rate(sdrv_ckgen_node_t *ckgen, uint32_t rate,
                                 sdrv_ckgen_bus_post_div_e div);
 
uint32_t sdrv_ckgen_bus_get_rate(sdrv_ckgen_node_t *ckgen,
                                 sdrv_ckgen_bus_out_type_e clk_out);
 
status_t sdrv_ckgen_cg_mask(sdrv_ckgen_node_t *ckgen, bool mask);
 
status_t sdrv_ckgen_set_gate(sdrv_ckgen_node_t *ckgen,
                             sdrv_ckgen_lp_mode_e lp_mode, bool gating);
 
status_t sdrv_ckgen_clock_config(sdrv_ckgen_node_t *ckgen, bool enable);
 
status_t sdrv_ckgen_ip_clock_enable(const sdrv_ckgen_node_t *ckgen_ip[],
                                    sdrv_ckgen_lp_mode_e mode, bool enable);
 
status_t sdrv_ckgen_set_pll_power(sdrv_ckgen_node_t *ckgen,
                                  sdrv_ckgen_lp_mode_e lp_mode, bool power_down);
 
status_t sdrv_ckgen_is_gated(sdrv_ckgen_node_t *ckgen);
 
status_t sdrv_ckgen_slice_gated(sdrv_ckgen_node_t *ckgen);
 
status_t sdrv_ckgen_xcg_type_set(sdrv_ckgen_xcg_set_t *xcg, sdrv_ckgen_lp_mode_e mode, bool gate);
 
status_t sdrv_ckgen_init(sdrv_ckgen_config_t *config);
 
#endif /* SDRV_CLK_H_ */