//*****************************************************************************
//
// WARNING: Automatically generated file, don't modify anymore!!!
//
// Copyright (c) 2021-2029 Semidrive Incorporated.  All rights reserved.
// Software License Agreement
//
//*****************************************************************************

#ifndef IRQ_NUM_H
#define IRQ_NUM_H

#define GPIO_SF_SYNC_DGPIO_INTR_NUM                                  4
#define GPIO_SF_ASYNC_DGPIO_INTR_NUM                                 4
#define GPIO_SF_SYNC_GRP_0_INTR_NUM                                  5
#define GPIO_SF_ASYNC_GRP_0_INTR_NUM                                 5
#define GPIO_SF_SYNC_GRP_1_INTR_NUM                                  6
#define GPIO_SF_ASYNC_GRP_1_INTR_NUM                                 6
#define GPIO_SF_SYNC_GRP_2_INTR_NUM                                  7
#define GPIO_SF_ASYNC_GRP_2_INTR_NUM                                 7
#define GPIO_SF_SYNC_GRP_3_INTR_NUM                                  8
#define GPIO_SF_ASYNC_GRP_3_INTR_NUM                                 8

#define CR5_SF_NPMUIRQ0_INTR_NUM                                     10

#define SMC_SMC_WAKEUP_0_INTR_NUM                                    15
#define WDT1_WDT_INTR_NUM                                            16
#define WDT2_WDT_INTR_NUM                                            17

#define WDT8_WDT_INTR_NUM                                            20
#define DMA_SF_DMA0_CH_0_INTR_NUM                                    21
#define DMA_SF_DMA0_CH_1_INTR_NUM                                    22
#define DMA_SF_DMA0_CH_2_INTR_NUM                                    23
#define DMA_SF_DMA0_CH_3_INTR_NUM                                    24
#define DMA_SF_DMA0_CH_4_INTR_NUM                                    25
#define DMA_SF_DMA0_CH_5_INTR_NUM                                    26
#define DMA_SF_DMA0_CH_6_INTR_NUM                                    27
#define DMA_SF_DMA0_CH_7_INTR_NUM                                    28
#define DMA_SF_DMA0_CH_8_INTR_NUM                                    29
#define DMA_SF_DMA0_CH_9_INTR_NUM                                    30
#define DMA_SF_DMA0_CH_10_INTR_NUM                                   31
#define DMA_SF_DMA0_CH_11_INTR_NUM                                   32
#define DMA_SF_DMA0_CH_12_INTR_NUM                                   33
#define DMA_SF_DMA0_CH_13_INTR_NUM                                   34
#define DMA_SF_DMA0_CH_14_INTR_NUM                                   35
#define DMA_SF_DMA0_CH_15_INTR_NUM                                   36
#define DMA_SF_DMA0_INTR_NUM                                         37
#define DMA_SF_DMA1_CH_0_INTR_NUM                                    38
#define DMA_SF_DMA1_CH_1_INTR_NUM                                    39
#define DMA_SF_DMA1_CH_2_INTR_NUM                                    40
#define DMA_SF_DMA1_CH_3_INTR_NUM                                    41
#define DMA_SF_DMA1_CH_4_INTR_NUM                                    42
#define DMA_SF_DMA1_CH_5_INTR_NUM                                    43
#define DMA_SF_DMA1_CH_6_INTR_NUM                                    44
#define DMA_SF_DMA1_CH_7_INTR_NUM                                    45
#define DMA_SF_DMA1_CH_8_INTR_NUM                                    46
#define DMA_SF_DMA1_CH_9_INTR_NUM                                    47
#define DMA_SF_DMA1_CH_10_INTR_NUM                                   48
#define DMA_SF_DMA1_CH_11_INTR_NUM                                   49
#define DMA_SF_DMA1_CH_12_INTR_NUM                                   50
#define DMA_SF_DMA1_CH_13_INTR_NUM                                   51
#define DMA_SF_DMA1_CH_14_INTR_NUM                                   52
#define DMA_SF_DMA1_CH_15_INTR_NUM                                   53
#define DMA_SF_DMA1_INTR_NUM                                         54

#define SEM1_O_SEM_CPU_INTR_NUM                                      57
#define SEM2_O_SEM_CPU_INTR_NUM                                      58
#define UART1_INTR_NUM                                               59
#define UART2_INTR_NUM                                               60
#define UART3_INTR_NUM                                               61
#define UART4_INTR_NUM                                               62
#define UART5_INTR_NUM                                               63
#define UART6_INTR_NUM                                               64
#define UART7_INTR_NUM                                               65
#define UART8_INTR_NUM                                               66
#define UART9_INTR_NUM                                               67
#define UART10_INTR_NUM                                              68
#define UART11_INTR_NUM                                              69
#define UART12_INTR_NUM                                              70

#define I2C1_INTR_NUM                                                75
#define I2C2_INTR_NUM                                                76
#define I2C3_INTR_NUM                                                77
#define I2C4_INTR_NUM                                                78
#define I2C5_INTR_NUM                                                79
#define I2C6_INTR_NUM                                                80

#define SPI1_SPI_INTR_NUM                                            83
#define SPI2_SPI_INTR_NUM                                            84
#define SPI3_SPI_INTR_NUM                                            85
#define SPI4_SPI_INTR_NUM                                            86
#define SPI5_SPI_INTR_NUM                                            87
#define SPI6_SPI_INTR_NUM                                            88

#define XSPI1_IRQ0_INTR_NUM                                          91
#define XSPI1_IRQ1_INTR_NUM                                          92

#define XSPI_SLV_INTR_NUM                                            95
#define SACI2_I2S_INTR_NUM                                           96
#define SACI2_PDM_INTR_NUM                                           97

#define USB_INTR_NUM                                                 100
#define ENET1_SBD_INTR_NUM                                           101
#define ENET1_SBD_PERCH_TX_O0_INTR_NUM                               102
#define ENET1_SBD_PERCH_TX_O1_INTR_NUM                               102
#define ENET1_SBD_PERCH_TX_O2_INTR_NUM                               102
#define ENET1_SBD_PERCH_TX_O3_INTR_NUM                               102
#define ENET1_SBD_PERCH_TX_O4_INTR_NUM                               102
#define ENET1_SBD_PERCH_RX_O0_INTR_NUM                               102
#define ENET1_SBD_PERCH_RX_O1_INTR_NUM                               102
#define ENET1_SBD_PERCH_RX_O2_INTR_NUM                               102
#define ENET1_SBD_PERCH_RX_O3_INTR_NUM                               102
#define ENET1_SBD_PERCH_RX_O4_INTR_NUM                               102
#define ENET1_LPI_INTR_NUM                                           103
#define ENET1_PMT_INTR_NUM                                           103

#define SEHC1_SEHC_INTR_NUM                                          106
#define SEHC1_SEHC_WAKEUP_INTR_NUM                                   107

#define CANFD16_CANFD_INTR_NUM                                        110
#define CANFD21_CANFD_INTR_NUM                                        111
#define CANFD3_CANFD_INTR_NUM                                        112
#define CANFD4_CANFD_INTR_NUM                                        113
#define CANFD5_CANFD_INTR_NUM                                        114
#define CANFD6_CANFD_INTR_NUM                                        115
#define CANFD7_CANFD_INTR_NUM                                        116
#define CANFD23_CANFD_INTR_NUM                                        117

#define SEIP_PKE_INTR_NUM                                            120
#define SEIP_SKE_INTR_NUM                                            121
#define SEIP_HASH_INTR_NUM                                           122
#define SEIP_TRNG_INTR_NUM                                           123
#define SEIP_KEY_CHK_INTR_NUM                                        124
#define SEIP_SOC_INTR_NUM                                            125
#define SEIP_UART_INTR_NUM                                           126
#define SEIP_SENSOR_INTR_NUM                                         127
#define SEIP_O_INTR_SE2SOC_MBOX_INTR_NUM                             128
#define SEIP_SEIP_ERR_INTR_NUM                                       129

#define BTM1_O_BTM_INTR_NUM                                          131
#define BTM2_O_BTM_INTR_NUM                                          132
#define BTM3_O_BTM_INTR_NUM                                          133
#define BTM4_O_BTM_INTR_NUM                                          134

#define ETMR1_CHN_A_INTR_NUM                                         135
#define ETMR1_CHN_B_INTR_NUM                                         135
#define ETMR1_CHN_C_INTR_NUM                                         135
#define ETMR1_CHN_D_INTR_NUM                                         135
#define ETMR1_CNT_OVF_INTR_NUM                                       136
#define ETMR2_CHN_A_INTR_NUM                                         137
#define ETMR2_CHN_B_INTR_NUM                                         137
#define ETMR2_CHN_C_INTR_NUM                                         137
#define ETMR2_CHN_D_INTR_NUM                                         137
#define ETMR2_CNT_OVF_INTR_NUM                                       138

#define EPWM1_CHN_A_INTR_NUM                                         141
#define EPWM1_CHN_B_INTR_NUM                                         141
#define EPWM1_CHN_C_INTR_NUM                                         141
#define EPWM1_CHN_D_INTR_NUM                                         141
#define EPWM1_CNT_OVF_INTR_NUM                                       142
#define EPWM2_CHN_A_INTR_NUM                                         143
#define EPWM2_CHN_B_INTR_NUM                                         143
#define EPWM2_CHN_C_INTR_NUM                                         143
#define EPWM2_CHN_D_INTR_NUM                                         143
#define EPWM2_CNT_OVF_INTR_NUM                                       144

#define XTRG_FUNC_INTR_NUM                                           147
#define IOC_GPIO_SYNC_INTR_NUM                                       148
#define IOC_GPIO_ASYNC_INTR_NUM                                      148
#define RTC1_RTC_WAKEUP_INTR_NUM                                     149
#define RTC1_RTC_PERIODICAL_INTR_NUM                                 150
#define RTC1_VIOLATION_INTR_NUM                                      151
#define RTC2_RTC_WAKEUP_INTR_NUM                                     152
#define RTC2_RTC_PERIODICAL_INTR_NUM                                 153
#define RTC2_VIOLATION_INTR_NUM                                      154
#define TM_VIOLATION_INTR_NUM                                        155

#define VD_SF_DIG_O_VDC_FUNC_INTR_NUM                                157
#define PT_SNS_SF_DIG_PVT_0_INTR_NUM                                 158
#define PT_SNS_SF_DIG_PVT_1_INTR_NUM                                 159
#define SCR_SF_SCR_APB_PSLVERR_INTR_NUM                              160

#define PMU_CORE_PMU_INTR_NUM                                        162
#define RSTGEN_SF_RSTGEN_INTR_NUM                                    163
#define U_CKGEN_SF_CKGEN_INTR_NUM                                    164

#define SMC_SMC_INTR_NUM                                             165
#define SADC1_O_SADC_INTR_NUM                                        166
#define SADC2_O_SADC_INTR_NUM                                        167
#define SADC3_O_SADC_INTR_NUM                                        168
#define ACMP1_O_ACMP_INTR_NUM                                        169
#define ACMP2_O_ACMP_INTR_NUM                                        170
#define ACMP3_O_ACMP_INTR_NUM                                        171
#define ACMP4_O_ACMP_INTR_NUM                                        172
#define DCDC1_O_DCDC_FUNC_INTR_NUM                                   173

#define FS_32K_FS_32K_INTR_NUM                                       175
#define ISTC_INTR_NUM                                                176
#define MPC_XSPI1A_FUNC_INTR_NUM                                     177
#define MPC_XSPI1B_FUNC_INTR_NUM                                     177
#define MPC_R5SF_S_FUNC_INTR_NUM                                     177
#define MPC_ROMC_FUNC_INTR_NUM                                       177
#define MPC_IRAMC1_FUNC_INTR_NUM                                     177
#define MPC_IRAMC2_FUNC_INTR_NUM                                     177
#define MPC_VIC1_FUNC_INTR_NUM                                       177
#define MAC_FUNC_INTR_NUM                                            177
#define PPC_APBMUX2_FUNC_INTR_NUM                                    177
#define PPC_APBMUX3_FUNC_INTR_NUM                                    177
#define PPC_APBMUX4_FUNC_INTR_NUM                                    177
#define MPC_SEIP_FUNC_INTR_NUM                                       177
#define PPC_APBMUX1_FUNC_INTR_NUM                                    177
#define GPIO_SF_SGPIO_INTR_NUM                                       178
#define IRQ_MAX_INTR_NUM                                             178


#endif /* IRQ_NUM_H */