修改喂狗芯片为100ms

This commit is contained in:
2026-04-26 15:54:52 +08:00
parent 9af585b664
commit f27cebde4d
12 changed files with 103 additions and 26 deletions

View File

@@ -173,18 +173,17 @@ static void eth_mac_init(dwc_eth_config_t *cfg, struct eqos_priv *eqos)
uint32_t skip_len = eqos->desc_size - sizeof(struct eqos_desc);
uint8_t bus_width = cfg->dma_bus_width ? cfg->dma_bus_width : 64;
eqos->dsl = skip_len * 8 / bus_width;
//DMA init
mac_init_dma(cfg->base, eqos);
//MTL init
mac_init_mtl(cfg->base);
//core init
phy_speed_t speed = (cfg->phy[0].phy_addr == ~0) ?
PHY_SPEED_1000 : cfg->phy[0].speed;
dwmac_core_init(cfg->base, cfg->mtu, speed, cfg->mac_addr);
dwmac_mac_rx_queue_mcbc_routing(cfg->base, 0);
}
@@ -285,13 +284,14 @@ static err_t dwc_eth_init(struct net_driver_s *dev)
#endif
ASSERT(eqos->rx_dma_buf);
memset(eqos->rx_dma_buf, 0, EQOS_RX_BUFFER_SIZE);
#endif
#endif
//init phy
phy_init(&eth_dev->phy_bus);
//init mac
eth_mac_init(cfg, eqos);
// set up dma tx/rx descriptors
memset(eqos->descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_NUM);
@@ -309,7 +309,7 @@ static err_t dwc_eth_init(struct net_driver_s *dev)
arch_clean_cache_range((addr_t)rx_desc, sizeof(struct eqos_desc));
arch_invalidate_cache_range((addr_t)((char *)eqos->rx_dma_buf +
(i * EQOS_MAX_PACKET_SIZE)), EQOS_MAX_PACKET_SIZE);
}
}
//enable rx/tx
mac_start(cfg->base, true);
@@ -775,11 +775,11 @@ int dwc_eth_probe(struct net_driver_s *dev, dwc_eth_config_t *cfg)
for (int i = 0; cfg->phy[i].phy_addr != ~0; i++) {
phy_dev_register(&dw_eth_dev->phy_bus, &cfg->phy[i]);
}
int ret = netdev_register(dev, NET_LL_ETHERNET);
External_wdt_refresh();
int ret = netdev_register(dev, NET_LL_ETHERNET);
External_wdt_refresh();
irq_attach(cfg->irq_num, dwc_eth_irq_handler, dev);
irq_enable(cfg->irq_num);
return ret;

View File

@@ -18,7 +18,6 @@
#include "regs_base.h"
#include "phy/phy.h"
#include "sdrv_mac_lld.h"
#include <wdt_refresh.h>
static uint8_t deafult_mac_addr[6] = {0x00, 0x1f, 0x29, 0x00, 0x12, 0x15};
@@ -658,7 +657,7 @@ int32_t dwmac_dma_reset(uint32_t regbase)
if (!(readl(regbase + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
break;
mdelay(1); //20251106 <20>޸<EFBFBD>Ϊ1<CEAA><31>10ʵ<30><CAB5><EFBFBD><EFBFBD>ʱΪ140ms
mdelay(1);//20251106 <20>޸<EFBFBD>Ϊ1<CEAA><31>10ʵ<30><CAB5><EFBFBD><EFBFBD>ʱΪ140ms
}
if (limit <= 0) {

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@@ -272,7 +272,7 @@ static int sdrv_hyperbus_wait_idle(struct spi_nor *nor)
}
// ssdk_printf(SSDK_INFO, "flash_status = 0x%x \r\n", flash_status);
ssdk_printf(SSDK_INFO, "flash_status = 0x%x \r\n", flash_status);
if ((flash_status & BIT(7)))
break;

View File

@@ -624,7 +624,7 @@ static int sdrv_spibus_wait_idle(struct spi_nor *nor)
}
}
// ssdk_printf(SSDK_INFO, "flash_status = 0x%x \r\n", flash_status);
ssdk_printf(SSDK_INFO, "flash_status = 0x%x \r\n", flash_status);
if (!(flash_status & BIT(0)))
break;
@@ -1123,7 +1123,7 @@ static int sdrv_spibus_write(struct spi_nor *nor, flash_addr_t addr,
{
int ret;
if (!IS_ALIGNED(addr, 4) || !IS_ALIGNED(buf, 4)) {
if (!IS_ALIGNED(addr, 4) || !IS_ALIGNED(buf, 4)) {
return SPI_NOR_ERR_STATUS(SPI_NOR_WRITE, SPI_NOR_ADDRESS_INVALID);
} else if (!IS_ALIGNED(size, 4)) {
return SPI_NOR_ERR_STATUS(SPI_NOR_WRITE, SPI_NOR_LENGTH_INVALID);

View File

@@ -1098,9 +1098,9 @@ static void sdrv_xspi_polling_handler(void *arg)
}
nor->xfer_info_bottom.opt_result = ret ? FLASH_OPT_FAILED : FLASH_OPT_PENDING;
// ssdk_printf(SSDK_DEBUG, "xfer_type = %d, xfer size = %lld, xfer result = %d\r\n",
// nor->xfer_info_bottom.opt_type == FLASH_OPT_READ, nor->xfer_info_bottom.size,
// nor->xfer_info_bottom.opt_result);
ssdk_printf(SSDK_DEBUG, "xfer_type = %d, xfer size = %lld, xfer result = %d\r\n",
nor->xfer_info_bottom.opt_type == FLASH_OPT_READ, nor->xfer_info_bottom.size,
nor->xfer_info_bottom.opt_result);
if ((nor->xfer_info_bottom.size == 0 || nor->xfer_info_bottom.buf == NULL) &&
nor->xfer_info_bottom.opt_result == FLASH_OPT_PENDING) {