From 3159b3723bd3c34c4ce3f33be6f900f3ad606ec9 Mon Sep 17 00:00:00 2001 From: liumin Date: Sun, 26 Apr 2026 16:09:11 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=B7=A5=E7=A8=8B=E6=96=87?= =?UTF-8?q?=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 1 - boards/e3_176_ref/driver_demo/gpio/.gitignore | 9 - .../driver_demo/gpio/IAR/gpio.custom_argvars | 9 + .../e3_176_ref/driver_demo/gpio/IAR/gpio.ewd | 2974 ++++++++++++++++ .../e3_176_ref/driver_demo/gpio/IAR/gpio.ewp | 2469 +++++++++++++ .../e3_176_ref/driver_demo/gpio/IAR/gpio.ewt | 3151 +++++++++++++++++ .../e3_176_ref/driver_demo/gpio/IAR/gpio.eww | 7 + .../driver_demo/gpio/configs/clock_cfg.c | 51 + .../driver_demo/gpio/configs/clock_cfg.h | 9 + .../driver_demo/gpio/configs/config.h | 153 + .../driver_demo/gpio/configs/eth_cfg.c | 82 + .../driver_demo/gpio/configs/eth_cfg.h | 12 + .../driver_demo/gpio/configs/flexcan_cfg.c | 174 + .../driver_demo/gpio/configs/flexcan_cfg.h | 53 + .../driver_demo/gpio/configs/pinmux_cfg.c | 677 ++++ .../driver_demo/gpio/configs/pinmux_cfg.h | 11 + .../driver_demo/gpio/configs/reset_cfg.c | 12 + .../driver_demo/gpio/configs/reset_cfg.h | 11 + .../driver_demo/gpio/configs/scr_cfg.c | 7 + .../driver_demo/gpio/configs/scr_cfg.h | 4 + 20 files changed, 9866 insertions(+), 10 deletions(-) delete mode 100644 boards/e3_176_ref/driver_demo/gpio/.gitignore create mode 100644 boards/e3_176_ref/driver_demo/gpio/IAR/gpio.custom_argvars create mode 100644 boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewd create mode 100644 boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewp create mode 100644 boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewt create mode 100644 boards/e3_176_ref/driver_demo/gpio/IAR/gpio.eww create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/clock_cfg.c create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/clock_cfg.h create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/config.h create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/eth_cfg.c create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/eth_cfg.h create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/flexcan_cfg.c create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/flexcan_cfg.h create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/pinmux_cfg.c create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/pinmux_cfg.h create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/reset_cfg.c create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/reset_cfg.h create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/scr_cfg.c create mode 100644 boards/e3_176_ref/driver_demo/gpio/configs/scr_cfg.h diff --git a/.gitignore b/.gitignore index 1f28b7f..73bed5f 100644 --- a/.gitignore +++ b/.gitignore @@ -1,7 +1,6 @@ # ############################## # 1. 忽略所有编译目录（不管层级） # ############################## -**/IAR/ **/IAR_*/ **/Debug/ **/FlashDebug/ diff --git a/boards/e3_176_ref/driver_demo/gpio/.gitignore b/boards/e3_176_ref/driver_demo/gpio/.gitignore deleted file mode 100644 index c097e3a..0000000 --- a/boards/e3_176_ref/driver_demo/gpio/.gitignore +++ /dev/null @@ -1,9 +0,0 @@ -# 忽略整个目录及其所有子文件和子目录 -/configs/ -/IAR/ -/IAR_Norflash/ -/SES/ -/configs/** -/IAR/** -/IAR_Norflash/** -/SES/** \ No newline at end of file diff --git a/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.custom_argvars b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.custom_argvars new file mode 100644 index 0000000..e37b737 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.custom_argvars @@ -0,0 +1,9 @@ + + + + + PART_ID + E3106 + + + diff --git a/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewd b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewd new file mode 100644 index 0000000..1cb8bb5 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + FlashDebug + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewp b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewp new file mode 100644 index 0000000..a65fad7 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewp @@ -0,0 +1,2469 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + 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+ + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + app + + $PROJ_DIR$\..\24c02.c + + + $PROJ_DIR$\..\btm_init.c + + + $PROJ_DIR$\..\flexcan_init.c + + + $PROJ_DIR$\..\IAP_Task.c + + + $PROJ_DIR$\..\interface_ethernet.c + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\wdt_refresh.c + + + + arch + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\iar\arm_atomic.S + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\iar\arm_cache.S + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\iar\arm_exceptions.S + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\arm_faults.c + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\arm_fpu.c + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\iar\arm_fullcontextrestore.S + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\arm_irq.c + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\arm_mpu.c + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\iar\arm_saveusercontext.S + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\iar\arm_switchcontext.S + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\arm_tcm.c + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\iar\arm_tcm_asm.S + + + + board + + $PROJ_DIR$\..\..\..\board.c + + + + configs + + $PROJ_DIR$\..\configs\clock_cfg.c + + + $PROJ_DIR$\..\configs\eth_cfg.c + + + $PROJ_DIR$\..\configs\flexcan_cfg.c + + + $PROJ_DIR$\..\configs\pinmux_cfg.c + + + $PROJ_DIR$\..\configs\reset_cfg.c + + + $PROJ_DIR$\..\configs\scr_cfg.c + + + + drivers + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\clock_default_cfg.c + + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\clock_ip.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\vic\irq.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\eth\phy\phy.c + + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\reset_ip.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\btm\sdrv_btm.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\btm\sdrv_btm_hw.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_ckgen.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_ckgen_hw_access.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\eth\sdrv_eth.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\flexcan\sdrv_flexcan.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_fs24m_hw_access.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_fs32k_hw_access.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\gpio\sdrv_gpio.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\spi_nor\sdrv_hyperbus.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\eth\sdrv_mac_lld.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\pinctrl\sdrv_pinctrl.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_pll_hw_access.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\reset\sdrv_rstgen.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\scr\sdrv_scr.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\spi\sdrv_spi.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\spi_nor\sdrv_spi_nor.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\uart\sdrv_uart.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\vic\sdrv_vic.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\vic\sdrv_vic_s.S + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\watchdog\sdrv_watchdog.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\spi_nor\sdrv_xspi.c + + + + middleware + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\acd.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\altcp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\altcp_alloc.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\altcp_tcp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\autoip.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\CLI\CLI_console.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\def.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\dhcp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\dns.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\etharp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\netif\ethernet.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\CLI\FreeRTOS_CLI.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\icmp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\igmp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\inet_chksum.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\init.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ip.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\ip4.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\ip4_addr.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\ip4_frag.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\apps\lwiperf\lwiperf.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\mem.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\memp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\contrib\ports\baremetal\net_tool.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\contrib\ports\baremetal\netdev.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\netif.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\pbuf.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\contrib\apps\ping\ping.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\printf\printf.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\raw.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\remap\remap.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\rom_ctrl\rom_ctrl.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\stats.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\sys.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\contrib\ports\baremetal\sys_arch.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\tcp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\tcp_in.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\tcp_out.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\timeouts.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\udelay\udelay.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\udp.c + + + + startup + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\device_init.c + + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\startup\iar\startup.S + + + diff --git a/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewt b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewt new file mode 100644 index 0000000..013d9d4 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.ewt @@ -0,0 +1,3151 @@ + + + 3 + + Debug + + ARM + + 1 + + C-STAT + 264 + + 264 + + 0 + + 1 + 600 + 1 + 2 + 0 + 1 + 100 + + + 1.8.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\..\arch\armv7-r\arm_tcm.c + + + $PROJ_DIR$\..\..\..\..\..\arch\armv7-r\iar\arm_tcm_asm.S + + + + board + + $PROJ_DIR$\..\..\..\board.c + + + + configs + + $PROJ_DIR$\..\configs\clock_cfg.c + + + $PROJ_DIR$\..\configs\eth_cfg.c + + + $PROJ_DIR$\..\configs\flexcan_cfg.c + + + $PROJ_DIR$\..\configs\pinmux_cfg.c + + + $PROJ_DIR$\..\configs\reset_cfg.c + + + $PROJ_DIR$\..\configs\scr_cfg.c + + + + drivers + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\clock_default_cfg.c + + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\clock_ip.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\vic\irq.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\eth\phy\phy.c + + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\reset_ip.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\btm\sdrv_btm.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\btm\sdrv_btm_hw.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_ckgen.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_ckgen_hw_access.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\eth\sdrv_eth.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\flexcan\sdrv_flexcan.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_fs24m_hw_access.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_fs32k_hw_access.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\gpio\sdrv_gpio.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\spi_nor\sdrv_hyperbus.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\eth\sdrv_mac_lld.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\pinctrl\sdrv_pinctrl.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\clk\sdrv_pll_hw_access.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\reset\sdrv_rstgen.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\scr\sdrv_scr.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\spi\sdrv_spi.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\spi_nor\sdrv_spi_nor.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\uart\sdrv_uart.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\vic\sdrv_vic.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\vic\sdrv_vic_s.S + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\watchdog\sdrv_watchdog.c + + + $PROJ_DIR$\..\..\..\..\..\drivers\source\spi_nor\sdrv_xspi.c + + + + middleware + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\acd.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\altcp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\altcp_alloc.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\altcp_tcp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\autoip.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\CLI\CLI_console.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\def.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\dhcp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\dns.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\etharp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\netif\ethernet.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\CLI\FreeRTOS_CLI.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\icmp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\igmp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\inet_chksum.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\init.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ip.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\ip4.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\ip4_addr.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\ipv4\ip4_frag.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\apps\lwiperf\lwiperf.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\mem.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\memp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\contrib\ports\baremetal\net_tool.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\contrib\ports\baremetal\netdev.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\netif.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\pbuf.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\contrib\apps\ping\ping.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\printf\printf.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\raw.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\remap\remap.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\rom_ctrl\rom_ctrl.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\stats.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\sys.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\contrib\ports\baremetal\sys_arch.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\tcp.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\tcp_in.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\tcp_out.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\timeouts.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\udelay\udelay.c + + + $PROJ_DIR$\..\..\..\..\..\middleware\lwip\src\core\udp.c + + + + startup + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\device_init.c + + + $PROJ_DIR$\..\..\..\..\..\devices\E3106\startup\iar\startup.S + + + diff --git a/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.eww b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.eww new file mode 100644 index 0000000..ad387f8 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/IAR/gpio.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\gpio.ewp + + + diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/clock_cfg.c b/boards/e3_176_ref/driver_demo/gpio/configs/clock_cfg.c new file mode 100644 index 0000000..72f54d5 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/clock_cfg.c @@ -0,0 +1,51 @@ +#include +#include +#include + +#if ((CONFIG_E3210) || (CONFIG_E3110)) +const sdrv_ckgen_rate_config_t g_ip_config = { + .config_num = 7, + .config_nodes[0].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_1_to_8), + .config_nodes[0].rate = 83000000, + .config_nodes[1].clk_node = CLK_NODE(g_ckgen_ip_enet1_tx), + .config_nodes[1].rate = 250000000, + .config_nodes[2].clk_node = CLK_NODE(g_ckgen_ip_enet1_rmii), + .config_nodes[2].rate = 50000000, + .config_nodes[3].clk_node = CLK_NODE(g_ckgen_ip_enet1_phy_ref), + .config_nodes[3].rate = 125000000, + .config_nodes[4].clk_node = CLK_NODE(g_ckgen_ip_enet1_timer_sec), + .config_nodes[4].rate = 125000000, + .config_nodes[5].clk_node = CLK_NODE(g_ckgen_ip_can), + .config_nodes[5].rate = 40000000, + .config_nodes[6].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_7_to_12), + .config_nodes[6].rate = 83000000, +}; +#else +const sdrv_ckgen_rate_config_t g_ip_config = { + .config_num = 7, + .config_nodes[0].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_1_to_6), + .config_nodes[0].rate = 83000000, + .config_nodes[1].clk_node = CLK_NODE(g_ckgen_ip_enet1_tx), + .config_nodes[1].rate = 250000000, + .config_nodes[2].clk_node = CLK_NODE(g_ckgen_ip_enet1_rmii), + .config_nodes[2].rate = 50000000, + .config_nodes[3].clk_node = CLK_NODE(g_ckgen_ip_enet1_phy_ref), + .config_nodes[3].rate = 125000000, + .config_nodes[4].clk_node = CLK_NODE(g_ckgen_ip_enet1_timer_sec), + .config_nodes[4].rate = 125000000, + .config_nodes[5].clk_node = CLK_NODE(g_ckgen_ip_can), + .config_nodes[5].rate = 40000000, + .config_nodes[6].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_7_to_12), + .config_nodes[6].rate = 83000000, +}; +#endif /* end ((defined CONFIG_E3210) || (defined CONFIG_E3110)) */ + + +const sdrv_ckgen_config_t g_clock_config = { + .pre_bus_config = &g_pre_bus_config, + .pll_config = &g_pll_config, + .bus_config = &g_bus_config, + .core_config = NULL, + .ip_config = &g_ip_config, + .gating_config = NULL, +}; diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/clock_cfg.h b/boards/e3_176_ref/driver_demo/gpio/configs/clock_cfg.h new file mode 100644 index 0000000..8297846 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/clock_cfg.h @@ -0,0 +1,9 @@ +#ifndef SDRV_CLOCK_CFG_H_ +#define SDRV_CLOCK_CFG_H_ + +#include +#include + +extern sdrv_ckgen_config_t g_clock_config; + +#endif /* SDRV_CLOCK_CFG_H_ */ \ No newline at end of file diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/config.h b/boards/e3_176_ref/driver_demo/gpio/configs/config.h new file mode 100644 index 0000000..df8d842 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/config.h @@ -0,0 +1,153 @@ +/** + * @file config.h + * @brief SSDK configuration header file. + * + * @copyright Copyright (c) 2022 Semidrive Semiconductor. + * All rights reserved. + */ + +/** + * @brief Enable ARM I-Cache and D-Cache operations. + * + * If CONFIG_ARCH_WITH_CACHE is defined, ARM I-Cache and D-Cache + * operations are enabled and you can call functions defiend in cache.h to + * manage caches. + */ +#define CONFIG_ARCH_WITH_CACHE 1 + +/** + * @brief ARM cache line size in bytes. + * + * Cortex R5 cache line length is 8 words (256 bits). + */ +#define CONFIG_ARCH_CACHE_LINE 32 + +/** + * @brief Enable I-Cache on power up. + * + * If CONFIG_ARCH_EARLY_ENABLE_ICACHE is defined, ARM I-Cache is + * enabled on power up. + */ +#define CONFIG_ARCH_EARLY_ENABLE_ICACHE 1 + +/** + * @brief Enable D-Cache on power up. + * + * If CONFIG_ARCH_EARLY_ENABLE_DCACHE is defined, ARM D-Cache is enabled on + * power up. + */ +#define CONFIG_ARCH_EARLY_ENABLE_DCACHE 1 + +/** + * @brief Enable ARM FPU. + * + * If CONFIG_ARCH_WITH_FPU is defined, ARM floating processing unit (FPU) is + * enabled. + */ +#define CONFIG_ARCH_WITH_FPU 1 + +/** + * @brief SemiDrive E3 product macro. + */ +#define CONFIG_ARCH_CHIP_E3 1 + +/** + * @brief Enable ARM TCM. + * + * If CONFIG_ARCH_WITH_TCM is defined, ARM tightly coupled memory + * (TCM) driver is enabed. + */ +#define CONFIG_ARM_WITH_TCM 1 + +/** + * @brief Enable ARM CP 15 operations. + * + * If CONFIG_ARCH_WITH_CP15 is defined, ARM CP15 coprocessor + * instructions are used. + */ +#define CONFIG_ARM_WITH_CP15 1 + +/** + * @brief Enable ARM PMU operations. + * + * If CONFIG_ARCH_WITH_PMU is defined, ARM performance monitor + * unit (PMU) functions can be used to manage PMU. + */ +#define CONFIG_ARM_WITH_PMU 1 + +/** + * @brief Enable Cortex R5 TCM A area. + */ +#define CONFIG_ARMV7R_USE_TCMA 1 + +/** + * @brief Cortex R5 TCM A base address. + * + * TCM A base address is configured on power up, by setting CP15. Note that + * this address could be different from TCMx_BASE address defined in + * regs_base.h, which is the bus address used by other AXI masters to access + * TCMA from outside the Cortex R5 core. + */ +#define CONFIG_ARMV7R_TCMA_BASE 0x10000 + +/** + * @brief Enable Cortex R5 TCM B area. + */ +#define CONFIG_ARMV7R_USE_TCMB 1 + +/** + * @brief Cortex R5 TCM B base address. + * + * TCM B base address is configured on power up, by setting CP15. Note that + * this address could be different from TCMx_BASE address defined in + * regs_base.h, which is the bus address used by other AXI masters to access + * TCMB from outside the Cortex R5 core. + */ +#define CONFIG_ARMV7R_TCMB_BASE 0x0 + +/** + * @brief Enable VIC driver + */ +#define CONFIG_IRQ 1 + +/** + * @brief Enable vectored IRQ mode. + * + * In vectored IRQ mode if IRQ signal received, R5 acknowledge to + * VIC through dedicated hardware channel and get interrupt address + * from VIC directly. + * + * If not configured, interupt address is always 0x18, and interrupt routing + * will read VICADDRESS register to acknowledge to VIC and get interrupt + * nubmer, and branch to user ISR. + */ +#define CONFIG_VIC_IRQ_INTERRUPT_MODE 1 + +/** + * @brief Enable Ethernet controller driver, and LWIP stacks. + */ +#define CONFIG_ETH 1 + +/** + * @brief Enable debug logs and asserts. + * + * Define CONFIG_DEBUG if you want ssdk_printf() logs, as well as PANIC() + * and ASSERT() dumps. + */ +#define CONFIG_DEBUG 1 + +/** + * @brief SSDK Log level. + * + * ssdk_printf() logs with "level" no greater than CONFIG_DEBUG_LEVEL are + * shown, while other logs are ignored. See log levels defined in debug.h. + */ +#define CONFIG_DEBUG_LEVEL SSDK_DEBUG + +/** + * @brief Enable printf function. + * + * The middleware/printf library provides simple printf function. + * CONFIG_PRINTF_LIB is valid only when CONFIG_DEBUG is defined. + */ +#define CONFIG_PRINTF_LIB 1 diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/eth_cfg.c b/boards/e3_176_ref/driver_demo/gpio/configs/eth_cfg.c new file mode 100644 index 0000000..76d9359 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/eth_cfg.c @@ -0,0 +1,82 @@ +#if CONFIG_ETH + +#include +#include "reg.h" +#include "regs_base.h" +#include "irq_num.h" +#include "scr_hw.h" +#include "sdrv_scr.h" +#include "scr_cfg.h" +#include "eth_cfg.h" +#include "sdrv_pinctrl.h" +#include "sdrv_gpio.h" +#include "sdrv_eth.h" +#include +#include +#include + +#define PHY_INTF_SEL 0x2080 + +struct net_driver_s g_eth1_dev; + +static void set_phyif_mode(uint32_t base, eth_phy_intf_mode_type mode) +{ + uint32_t v; + + /* Config MII interface. */ + if (mode == ETH_PHY_INTF_SEL_MII) + v = 0; + else if (mode == ETH_PHY_INTF_SEL_RMII) { + if (base == APB_ENET1_BASE) { + const scr_signal_t rmii_oe = SCR_SF_SCR_ENET1_CLK_RMII_OE; + scr_set(&g_scr_ctrl, &rmii_oe, 1); + } +#if ((CONFIG_E3210) || (CONFIG_E3110)) + else { + const scr_signal_t rmii_oe = SCR_SF_SCR_ENET2_CLK_RMII_OE; + scr_set(&g_scr_ctrl, &rmii_oe, 1); + } +#endif + v = 4; + } + else + v = 1; + + writel(v, base + PHY_INTF_SEL); +} + +static phy_dev_t g_phy_arr1[] = { + { + .phy_addr = 0, + .duplex_mode = ETH_PHY_DUPLEX_MODE_FULL, + .speed = PHY_SPEED_100, + .auto_negotiation = true + }, + + /* Invalid phy dev to indicate end of array. */ + { + .phy_addr = ~0, + } +}; + +static dwc_eth_config_t g_eth1_cfg = { + .base = APB_ENET1_BASE, + .irq_num = ENET1_SBD_INTR_NUM, + .mtu = 1500, + .dma_bus_width = 64, + .phy_intf_mode = ETH_PHY_INTF_SEL_RMII, + .set_phy_intf = set_phyif_mode, + .ip = {192,168,17,20}, + .mask = {255, 255, 255, 0}, + + .phy = g_phy_arr1 +}; + +void board_eth_init(void) +{ + dwc_eth_probe(&g_eth1_dev, &g_eth1_cfg); + External_wdt_refresh(); + lwip_init(); +} + +#endif diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/eth_cfg.h b/boards/e3_176_ref/driver_demo/gpio/configs/eth_cfg.h new file mode 100644 index 0000000..5add184 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/eth_cfg.h @@ -0,0 +1,12 @@ +#ifndef _ETH_CFG_H_ +#define _ETH_CFG_H_ + +#if CONFIG_ETH + +extern struct net_driver_s g_eth1_dev; + +void board_eth_init(void); + +#endif + +#endif \ No newline at end of file diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/flexcan_cfg.c b/boards/e3_176_ref/driver_demo/gpio/configs/flexcan_cfg.c new file mode 100644 index 0000000..457ea1e --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/flexcan_cfg.c @@ -0,0 +1,174 @@ +#include +#include +#include "IAP_Task.h" + +const flexcan_config_t g_flexcan_config = { + .clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */ + .maxMbNum = 64U, + .enableSelfWakeup = true, + .enableIndividMask = true, + .enableCANFD = false, + BAUDRATE_1M_5M, + .enableLBUFTransmittedFirst = true +}; + +static flexcan_rx_fifo_filter_table_t flexcan_tableID[RX_FIFO_ID_FILTER_NUM] = { + { + MAKE_TYPE_A_FILTER(0x01, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x03, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x103, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x104, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x105, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x106, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x107, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x108, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x109, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x10A, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x10B, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { /* LSB can be 0 or 1 */ + MAKE_TYPE_A_FILTER(0x10C, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FE, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x3e7, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID) + }, + { /* LSB can be 0 or 1 */ + MAKE_TYPE_A_FILTER(0x3f7, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFE, EXTENDED_DATA_ID) + }, + /* remaining elements can only be affected by RXFGMASK. */ + { + MAKE_TYPE_A_FILTER(0x507, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x517, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x527, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x537, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x547, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x557, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x567, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x577, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x587, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FE, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x597, STANDARD_DATA_ID), + MAKE_TYPE_A_FILTER(0x7FE, STANDARD_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x5a7, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x5b7, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x5c7, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x5d7, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x5e7, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x5f7, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x607, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID) + }, + { + MAKE_TYPE_A_FILTER(0x617, EXTENDED_DATA_ID), + MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID) + } +}; + +flexcan_rx_fifo_config_t flexcan_fifo_cfg = { + .priority = FLEXCAN_RxFifoPrioHigh, + .idFilterType = FLEXCAN_RxFifoFilterTypeA, + .idFilterNum = RX_FIFO_ID_FILTER_NUM, + .filter_tab = &flexcan_tableID[0] +}; + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/flexcan_cfg.h b/boards/e3_176_ref/driver_demo/gpio/configs/flexcan_cfg.h new file mode 100644 index 0000000..507a8c6 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/flexcan_cfg.h @@ -0,0 +1,53 @@ +#ifndef SDRV_FLEXCAN_CFG_H_ +#define SDRV_FLEXCAN_CFG_H_ + +#include + +/* for 40MHz. */ +#define BAUDRATE_1M_5M \ + .nominalBitTiming = \ + {/* 1Mbps, sample point 80% */ \ + .preDivider = 1U, \ + .rJumpwidth = 5U, \ + .propSeg = 10U, \ + .phaseSeg1 = 21U, \ + .phaseSeg2 = 8U}, \ + .dataBitTiming = \ + {/* 5Mbps, sample point 75% */ \ + .preDivider = \ + 1U, /* Should be the same as nominalBitTiming.preDivider. */ \ + .rJumpwidth = 1U, \ + .propSeg = 2U, \ + .phaseSeg1 = 3U, \ + .phaseSeg2 = 2U} + +/* for 40MHz. */ +#define BAUDRATE_500K_1M \ + .nominalBitTiming = \ + {/* 500kbps, sample point 75% */ \ + .preDivider = 4U, \ + .rJumpwidth = 2U, \ + .propSeg = 6U, \ + .phaseSeg1 = 8U, \ + .phaseSeg2 = 5U}, \ + .dataBitTiming = \ + {/* 1Mbps, sample point 80% */ \ + .preDivider = \ + 4U, /* Should be the same as nominalBitTiming.preDivider. */ \ + .rJumpwidth = 2U, \ + .propSeg = 3U, \ + .phaseSeg1 = 4U, \ + .phaseSeg2 = 2U} + +#define RX_FIFO_ID_FILTER_NUM 32 +#define USED_MB_FOR_FIFO 14 +#define TX_MAILBOX_NUM 7 + +extern const flexcan_config_t g_flexcan_config; +extern flexcan_rx_fifo_config_t flexcan_fifo_cfg; + +void flexcan_transfer_callback(flexcan_handle_t *handle, + flexcan_status_e status, uint32_t result, + void *userData); + +#endif /* SDRV_FLEXCAN_CFG_H_ */ diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/pinmux_cfg.c b/boards/e3_176_ref/driver_demo/gpio/configs/pinmux_cfg.c new file mode 100644 index 0000000..d27ec2b --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/pinmux_cfg.c @@ -0,0 +1,677 @@ +#include "pinmux_cfg.h" +#include "pinmux_cfg.h" +#include "IAP_Task.h" + +const pin_settings_config_t g_pin_init_config[NUM_OF_CONFIGURED_PINS] = { + /* Pin 23, GPIO_Y6, Mux:UART12.TXD */ + { + .pin_index = GPIO_A8, + .mux = PIN_MUX_ALT4, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 24, GPIO_Y7, Mux:UART12.RXD */ + { + .pin_index = GPIO_A9, + .mux = PIN_MUX_ALT4, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 23, GPIO_E0, Mux:UART2.TXD */ + { + .pin_index = GPIO_E0,// + .mux = PIN_MUX_ALT5, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 24, GPIO_E1, Mux:UART2.RXD */ + { + .pin_index = GPIO_E1,// + .mux = PIN_MUX_ALT5, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 25, GPIO_E2, Mux:UART2.EN */ + { + .pin_index = GPIO_E2, + .mux = PIN_MUX_ALT0, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_HIGH, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 33, GPIO_L4, Mux:CANFD3.RX */ + { + .pin_index = GPIO_L4, + .mux = PIN_MUX_ALT3, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_SLOW, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 34, GPIO_L5, Mux:CANFD3.TX */ + { + .pin_index = GPIO_L5, + .mux = PIN_MUX_ALT3, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_SLOW, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 38, GPIO_H12, Mux:GPIO_SAFETY.IO38 */ + { + .pin_index = GPIO_H12, + .mux = PIN_MUX_ALT0, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_HIGH, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 38, GPIO_F5, Mux:GPIO_SAFETY.IO39 */ + { + .pin_index = GPIO_F5, + .mux = PIN_MUX_ALT0, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_12MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 38, GPIO_H13, Mux:GPIO_SAFETY.IO39 */ + { + .pin_index = GPIO_H13, + .mux = PIN_MUX_ALT0, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_12MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 38, GPIO_B9, Mux:GPIO_SAFETY.IO38 */ + { + .pin_index = GPIO_B9, + .mux = PIN_MUX_ALT0, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + +#if EN_24C02 + /* Pin 23, GPIO_Y2, Mux:I2C.SCL */ + { + .pin_index = GPIO_Y2, + .mux = PIN_MUX_ALT0, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 24, GPIO_Y3, Mux:I2C.SDA */ + { + .pin_index = GPIO_Y3, + .mux = PIN_MUX_ALT0, + .open_drain = PIN_OPEN_DRAIN, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 24, GPIO_Y1, Mux:I2C.WP */ + { + .pin_index = GPIO_Y1, + .mux = PIN_MUX_ALT0, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, +#else + /* PortPinid: 0 - SPI6_SS0 */ + { + .pin_index = GPIO_Y2, + .mux = PIN_MUX_ALT3, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + /* PortPinid: 1 - SPI6_SCLK */ + { + .pin_index = GPIO_Y3, + .mux = PIN_MUX_ALT3, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* PortPinid: 2 - SPI6_MISO */ + { + .pin_index = GPIO_Y4, + .mux = PIN_MUX_ALT3, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* PortPinid: 3 - SPI6_MOSI */ + { + .pin_index = GPIO_Y5, + .mux = PIN_MUX_ALT3, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_HIGH, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, +#endif + + /* Pin 95, GPIO_H6, Mux:CANFD6.RX */ + { + .pin_index = GPIO_H6, + .mux = PIN_MUX_ALT2, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_SLOW, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 96, GPIO_H7, Mux:CANFD6.TX */ + { + .pin_index = GPIO_H7, + .mux = PIN_MUX_ALT2, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_SLOW, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 5, GPIO_X0, Mux:XSPI1.PA_DQS */ + { + .pin_index = GPIO_X0, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 6, GPIO_X1, Mux:XSPI1.PA_SCLK */ + { + .pin_index = GPIO_X1, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 7, GPIO_X2, Mux:XSPI1.PA_SS0 */ + { + .pin_index = GPIO_X2, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 8, GPIO_X3, Mux:XSPI1.PA_DATA0 */ + { + .pin_index = GPIO_X3, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 9, GPIO_X4, Mux:XSPI1.PA_DATA1 */ + { + .pin_index = GPIO_X4, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 10, GPIO_X5, Mux:XSPI1.PA_DATA2 */ + { + .pin_index = GPIO_X5, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 11, GPIO_X6, Mux:XSPI1.PA_DATA3 */ + { + .pin_index = GPIO_X6, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 12, GPIO_X7, Mux:XSPI1.PA_DATA4 */ + { + .pin_index = GPIO_X7, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 13, GPIO_X8, Mux:XSPI1.PA_DATA5 */ + { + .pin_index = GPIO_X8, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 14, GPIO_X9, Mux:XSPI1.PA_DATA6 */ + { + .pin_index = GPIO_X9, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 15, GPIO_X10, Mux:XSPI1.PA_DATA7 */ + { + .pin_index = GPIO_X10, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_NOPULL, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + /* Pin 16, GPIO_X11, Mux:XSPI1.PA_SS1 */ + { + .pin_index = GPIO_X11, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_UP, + .drive_strength = PIN_DS_2MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 78, GPIO_G1, Mux:ETHERNET1.TXD0 */ + { + .pin_index = GPIO_G1, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 79, GPIO_G2, Mux:ETHERNET1.TXD1 */ + { + .pin_index = GPIO_G2, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 80, GPIO_G3, Mux:ETHERNET1.MDIO */ + { + .pin_index = GPIO_G3, + .mux = PIN_MUX_ALT2, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 81, GPIO_G4, Mux:ETHERNET1.MDC */ + { + .pin_index = GPIO_G4, + .mux = PIN_MUX_ALT2, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 82, GPIO_G5, Mux:ETHERNET1.TXEN */ + { + .pin_index = GPIO_G5, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 84, GPIO_G7, Mux:ETHERNET1.RXD0 */ + { + .pin_index = GPIO_G7, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 85, GPIO_G8, Mux:ETHERNET1.RXD1 */ + { + .pin_index = GPIO_G8, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 86, GPIO_G9, Mux:ETHERNET1.RMII_REF_CLK */ + { + .pin_index = GPIO_G9, + .mux = PIN_MUX_ALT2, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_ENABLE, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 87, GPIO_G10, Mux:ETHERNET1.RX_ER */ + { + .pin_index = GPIO_G10, + .mux = PIN_MUX_ALT2, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, + + /* Pin 88, GPIO_G11, Mux:ETHERNET1.RXDV */ + { + .pin_index = GPIO_G11, + .mux = PIN_MUX_ALT1, + .open_drain = PIN_PUSH_PULL, + .pull_config = PIN_PULL_DOWN, + .drive_strength = PIN_DS_8MA, + .slew_rate = PIN_SR_FAST, + .input_select = PIN_IS_CMOS_SCHMITT, + .data_direction = PIN_OUTPUT_DIRECTION, + .interrupt_config = PIN_INTERRUPT_DISABLED, + .initial_value = PIN_LEVEL_LOW, + .force_input = PIN_FORCE_INPUT_NORMAL, + .mode_select = PIN_MODE_DIGITAL, + }, +}; diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/pinmux_cfg.h b/boards/e3_176_ref/driver_demo/gpio/configs/pinmux_cfg.h new file mode 100644 index 0000000..a694b4f --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/pinmux_cfg.h @@ -0,0 +1,11 @@ +#ifndef SDRV_PINMUX_CFG_H_ +#define SDRV_PINMUX_CFG_H_ + +#include + +#define NUM_OF_CONFIGURED_PINS 39 + +extern const pin_settings_config_t g_pin_init_config[NUM_OF_CONFIGURED_PINS]; + + +#endif /* SDRV_PINMUX_CFG_H_ */ diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/reset_cfg.c b/boards/e3_176_ref/driver_demo/gpio/configs/reset_cfg.c new file mode 100644 index 0000000..08d22f6 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/reset_cfg.c @@ -0,0 +1,12 @@ +#include +#include "reset_cfg.h" + +sdrv_rstgen_sig_t *board_reset_array[NUM_OF_RSTGEN_SIGS] = { + &rstsig_canfd3, + &rstsig_vic1, + &rstsig_xspi1a, + &rstsig_xspi1b, + &rstsig_canfd6, + &rstsig_enet1, + +}; diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/reset_cfg.h b/boards/e3_176_ref/driver_demo/gpio/configs/reset_cfg.h new file mode 100644 index 0000000..5edeec3 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/reset_cfg.h @@ -0,0 +1,11 @@ +#ifndef SDRV_RESET_CFG_H_ +#define SDRV_RESET_CFG_H_ + +#include +#include + +#define NUM_OF_RSTGEN_SIGS 6 + +extern sdrv_rstgen_sig_t *board_reset_array[NUM_OF_RSTGEN_SIGS]; + +#endif /* SDRV_RESET_CFG_H_ */ \ No newline at end of file diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/scr_cfg.c b/boards/e3_176_ref/driver_demo/gpio/configs/scr_cfg.c new file mode 100644 index 0000000..1e8f937 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/scr_cfg.c @@ -0,0 +1,7 @@ +#include +#include + +/*scr structures*/ +sdrv_scr_t g_scr_ctrl = { + .base = APB_SCR_SF_BASE, +}; \ No newline at end of file diff --git a/boards/e3_176_ref/driver_demo/gpio/configs/scr_cfg.h b/boards/e3_176_ref/driver_demo/gpio/configs/scr_cfg.h new file mode 100644 index 0000000..b24c1a4 --- /dev/null +++ b/boards/e3_176_ref/driver_demo/gpio/configs/scr_cfg.h @@ -0,0 +1,4 @@ +#include + +/*exported scr*/ +extern sdrv_scr_t g_scr_ctrl; \ No newline at end of file