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<div class="headertitle"><div class="title">sdrv_power.h File Reference</div></div>
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<div class="textblock"><code>#include &lt;<a class="el" href="sdrv__common_8h_source.html">sdrv_common.h</a>&gt;</code><br />
<code>#include &lt;types.h&gt;</code><br />
<code>#include &lt;regs_base.h&gt;</code><br />
<code>#include &lt;part.h&gt;</code><br />
<code>#include &quot;<a class="el" href="sdrv__smc_8h_source.html">sdrv_smc.h</a>&quot;</code><br />
<code>#include &quot;<a class="el" href="sdrv__pmu_8h_source.html">sdrv_pmu.h</a>&quot;</code><br />
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<p><a href="sdrv__power_8h_source.html">Go to the source code of this file.</a></p>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__power__analog.html">sdrv_power_analog</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__sleep__mode__config.html">sdrv_sleep_mode_config</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__hibernate__mode__config.html">sdrv_hibernate_mode_config</a></td></tr>
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Functions</h2></td></tr>
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<tr class="memitem:a0c857d41dc400a0a2701304aaff213fc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__power_8h.html#a0c857d41dc400a0a2701304aaff213fc">sdrv_power_clock_set_mode</a> (<a class="el" href="sdrv__power_8h.html#a49ff3e0810ec5a5b7843595d9b432156">sdrv_clock_mode_e</a> mode)</td></tr>
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<tr class="memitem:a51e5041480c8922d452237e7dfae1e22"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__power_8h.html#a51e5041480c8922d452237e7dfae1e22">sdrv_power_usb_power_down</a> (void)</td></tr>
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<tr class="memitem:a6aad576d30ee1ac9c40b7517a396f752"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__power_8h.html#a6aad576d30ee1ac9c40b7517a396f752">sdrv_power_dcdc_config</a> (paddr_t dcdc_base, <a class="el" href="sdrv__power_8h.html#a6e56b1dd4a20b012ac734938ba8e42cb">sdrv_power_dcdc_mode_e</a> mode, <a class="el" href="sdrv__power_8h.html#a85076c534240cfea5dc6ee3058f3b01d">sdrv_power_dcdc_reg_e</a> dcdc_reg, uint8_t cfg_val)</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><dl class="section copyright"><dt>Copyright</dt><dd>Copyright (c) 2022 Semidrive Semiconductor. All rights reserved. </dd></dl>
</div><h2 class="groupheader">Macro Definition Documentation</h2>
<a id="a68de5ecc26716ab768dd8a558e78a738" name="a68de5ecc26716ab768dd8a558e78a738"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a68de5ecc26716ab768dd8a558e78a738">&#9670;&nbsp;</a></span>SDRV_AP_DISP_PD_MASK</h2>
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<td class="memname">#define SDRV_AP_DISP_PD_MASK&#160;&#160;&#160;(0x10UL)</td>
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<a id="aa100e75861e06d4bdc72639dce2dfaab" name="aa100e75861e06d4bdc72639dce2dfaab"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa100e75861e06d4bdc72639dce2dfaab">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_CSI_MASK</h2>
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<td class="memname">#define SDRV_AP_MODULE_CSI_MASK&#160;&#160;&#160;(0x1UL)</td>
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<a id="af2cb64cda909f81e1311ff3fe98468c8" name="af2cb64cda909f81e1311ff3fe98468c8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af2cb64cda909f81e1311ff3fe98468c8">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_DC_MASK</h2>
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<td class="memname">#define SDRV_AP_MODULE_DC_MASK&#160;&#160;&#160;(0x2UL)</td>
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<a id="ab90ab71a8ff2d874ec4cb8b198d92d3f" name="ab90ab71a8ff2d874ec4cb8b198d92d3f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab90ab71a8ff2d874ec4cb8b198d92d3f">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_DMA_MASK</h2>
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<td class="memname">#define SDRV_AP_MODULE_DMA_MASK&#160;&#160;&#160;(0x40UL)</td>
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<a id="a3b0985ec072be88f876d631910798714" name="a3b0985ec072be88f876d631910798714"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3b0985ec072be88f876d631910798714">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_G2D_MASK</h2>
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<td class="memname">#define SDRV_AP_MODULE_G2D_MASK&#160;&#160;&#160;(0x4UL)</td>
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</div><div class="memdoc">
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<a id="a74775d0f29b3574597acaccb5c2d3b74" name="a74775d0f29b3574597acaccb5c2d3b74"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a74775d0f29b3574597acaccb5c2d3b74">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_LVDS_MASK</h2>
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<td class="memname">#define SDRV_AP_MODULE_LVDS_MASK&#160;&#160;&#160;(0x800UL)</td>
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<a id="a28d331e633932a14e24377cb757a610c" name="a28d331e633932a14e24377cb757a610c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a28d331e633932a14e24377cb757a610c">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_SACI1_MASK</h2>
<div class="memitem">
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<td class="memname">#define SDRV_AP_MODULE_SACI1_MASK&#160;&#160;&#160;(0x10UL)</td>
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</div><div class="memdoc">
</div>
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<a id="a0f348861b1aac50b2c089388c4c0e83a" name="a0f348861b1aac50b2c089388c4c0e83a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0f348861b1aac50b2c089388c4c0e83a">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_SACI2_MASK</h2>
<div class="memitem">
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<td class="memname">#define SDRV_AP_MODULE_SACI2_MASK&#160;&#160;&#160;(0x20UL)</td>
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</div><div class="memdoc">
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<a id="a7913fa0f8d4041457666cce69a6d4278" name="a7913fa0f8d4041457666cce69a6d4278"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7913fa0f8d4041457666cce69a6d4278">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_SDRAMC_MASK</h2>
<div class="memitem">
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<td class="memname">#define SDRV_AP_MODULE_SDRAMC_MASK&#160;&#160;&#160;(0x8UL)</td>
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<a id="a5e63b1fe28e9022f19432a5254b739cd" name="a5e63b1fe28e9022f19432a5254b739cd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5e63b1fe28e9022f19432a5254b739cd">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_SEHC1_MASK</h2>
<div class="memitem">
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<td class="memname">#define SDRV_AP_MODULE_SEHC1_MASK&#160;&#160;&#160;(0x80UL)</td>
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</div><div class="memdoc">
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<a id="ad59d237d8693e79e0b0e8240362255c1" name="ad59d237d8693e79e0b0e8240362255c1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad59d237d8693e79e0b0e8240362255c1">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_SEHC2_MASK</h2>
<div class="memitem">
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<td class="memname">#define SDRV_AP_MODULE_SEHC2_MASK&#160;&#160;&#160;(0x100UL)</td>
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<a id="a21f05fc4177f31060d1190b6b75c9d07" name="a21f05fc4177f31060d1190b6b75c9d07"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a21f05fc4177f31060d1190b6b75c9d07">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_SEIP_MASK</h2>
<div class="memitem">
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<td class="memname">#define SDRV_AP_MODULE_SEIP_MASK&#160;&#160;&#160;(0x400UL)</td>
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<a id="a7cf2ac95b5ce1f9806995e701704f25e" name="a7cf2ac95b5ce1f9806995e701704f25e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7cf2ac95b5ce1f9806995e701704f25e">&#9670;&nbsp;</a></span>SDRV_AP_MODULE_USB_MASK</h2>
<div class="memitem">
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<td class="memname">#define SDRV_AP_MODULE_USB_MASK&#160;&#160;&#160;(0x200UL)</td>
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<a id="aa7589ba1b1e6724259e488af546a1de3" name="aa7589ba1b1e6724259e488af546a1de3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa7589ba1b1e6724259e488af546a1de3">&#9670;&nbsp;</a></span>SDRV_GAMA1_PD_MASK</h2>
<div class="memitem">
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<td class="memname">#define SDRV_GAMA1_PD_MASK&#160;&#160;&#160;(0x8UL)</td>
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<a id="aaf26bea82027a315d168288a30d3291c" name="aaf26bea82027a315d168288a30d3291c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aaf26bea82027a315d168288a30d3291c">&#9670;&nbsp;</a></span>SDRV_IRAM1_PD_MASK</h2>
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<td class="memname">#define SDRV_IRAM1_PD_MASK&#160;&#160;&#160;(0x1UL)</td>
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<a id="a79a9e1d098470552729e1ae27de54a54" name="a79a9e1d098470552729e1ae27de54a54"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a79a9e1d098470552729e1ae27de54a54">&#9670;&nbsp;</a></span>SDRV_IRAM2_PD_MASK</h2>
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<td class="memname">#define SDRV_IRAM2_PD_MASK&#160;&#160;&#160;(0x2UL)</td>
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<a id="af998bdf39d4f76d244bddca092c2930c" name="af998bdf39d4f76d244bddca092c2930c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af998bdf39d4f76d244bddca092c2930c">&#9670;&nbsp;</a></span>SDRV_IRAM3_PD_MASK</h2>
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<td class="memname">#define SDRV_IRAM3_PD_MASK&#160;&#160;&#160;(0x4UL)</td>
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<a id="ac626e49f9b134c46dad07ebf7f88b536" name="ac626e49f9b134c46dad07ebf7f88b536"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac626e49f9b134c46dad07ebf7f88b536">&#9670;&nbsp;</a></span>SDRV_IRAM4_PD_MASK</h2>
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<td class="memname">#define SDRV_IRAM4_PD_MASK&#160;&#160;&#160;(0x8UL)</td>
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<a id="af9d8e6ff79c33b241d87a472c6d7a469" name="af9d8e6ff79c33b241d87a472c6d7a469"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af9d8e6ff79c33b241d87a472c6d7a469">&#9670;&nbsp;</a></span>SDRV_PLL1_PD_MASK</h2>
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<td class="memname">#define SDRV_PLL1_PD_MASK&#160;&#160;&#160;(0x1UL)</td>
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<a id="acfb1a50af3d0a2e6af1e4da2cbf468d5" name="acfb1a50af3d0a2e6af1e4da2cbf468d5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acfb1a50af3d0a2e6af1e4da2cbf468d5">&#9670;&nbsp;</a></span>SDRV_PLL2_PD_MASK</h2>
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<td class="memname">#define SDRV_PLL2_PD_MASK&#160;&#160;&#160;(0x2UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a8b4bd8d9524a2c66007f0267cbe0b104">&#9670;&nbsp;</a></span>SDRV_PLL3_PD_MASK</h2>
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<td class="memname">#define SDRV_PLL3_PD_MASK&#160;&#160;&#160;(0x4UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#adfa67eb528c649908766f8405fba7c1c">&#9670;&nbsp;</a></span>SDRV_PLL4_PD_MASK</h2>
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<td class="memname">#define SDRV_PLL4_PD_MASK&#160;&#160;&#160;(0x8UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ac9bea77f6394d20b6afdd868edde344a">&#9670;&nbsp;</a></span>SDRV_PLL5_PD_MASK</h2>
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<td class="memname">#define SDRV_PLL5_PD_MASK&#160;&#160;&#160;(0x10UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a8fa1d5e1072c3dffcee32daa9bf7d260">&#9670;&nbsp;</a></span>SDRV_PLL_LVDS_PD_MASK</h2>
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<td class="memname">#define SDRV_PLL_LVDS_PD_MASK&#160;&#160;&#160;(0x20UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ae04f2e49bc2cea03534eb5e09ef54f3c">&#9670;&nbsp;</a></span>SDRV_PWR_CTRL0_PD_MASK</h2>
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<td class="memname">#define SDRV_PWR_CTRL0_PD_MASK&#160;&#160;&#160;(0x1UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a219fab72569bd7ffb91902d755478825">&#9670;&nbsp;</a></span>SDRV_PWR_CTRL1_PD_MASK</h2>
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<td class="memname">#define SDRV_PWR_CTRL1_PD_MASK&#160;&#160;&#160;(0x2UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#aa5d39d66b3b731cab99011708cf587d8">&#9670;&nbsp;</a></span>SDRV_PWR_CTRL2_PD_MASK</h2>
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<td class="memname">#define SDRV_PWR_CTRL2_PD_MASK&#160;&#160;&#160;(0x4UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#af1fb37ed84462feaeb6dea6b26ef69c2">&#9670;&nbsp;</a></span>SDRV_PWR_CTRL3_PD_MASK</h2>
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<td class="memname">#define SDRV_PWR_CTRL3_PD_MASK&#160;&#160;&#160;(0x8UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a89aa3a04db129cc71c31dbe7b4a38b3c">&#9670;&nbsp;</a></span>SDRV_PWR_ON0_PD_MASK</h2>
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<td class="memname">#define SDRV_PWR_ON0_PD_MASK&#160;&#160;&#160;(0x10UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a41766ba3c810a818045b60c25414137e">&#9670;&nbsp;</a></span>SDRV_PWR_ON1_PD_MASK</h2>
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<td class="memname">#define SDRV_PWR_ON1_PD_MASK&#160;&#160;&#160;(0x20UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ae220a280f5ff8ddee6c3599df542d000">&#9670;&nbsp;</a></span>SDRV_PWR_ON2_PD_MASK</h2>
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<td class="memname">#define SDRV_PWR_ON2_PD_MASK&#160;&#160;&#160;(0x40UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a1fafbb523056f38510294f3a58d18a05">&#9670;&nbsp;</a></span>SDRV_PWR_ON3_PD_MASK</h2>
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<td class="memname">#define SDRV_PWR_ON3_PD_MASK&#160;&#160;&#160;(0x80UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ad53def9c99cb1d1b53c73544384dac13">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_CANFD17_24_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_CANFD17_24_MASK&#160;&#160;&#160;(0x20UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a9a851322386f6bf2a6198269cb4caf83">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_CANFD1_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_CANFD1_MASK&#160;&#160;&#160;(0x1UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#aba9c837c0f6d24f17ef552a864123b1c">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_CANFD2_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_CANFD2_MASK&#160;&#160;&#160;(0x2UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a6987b0650e2d0bbf17b93d7adda5d9b6">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_CANFD3_4_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_CANFD3_4_MASK&#160;&#160;&#160;(0x4UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ac5ca2b74ed62b084ae44bf6827879d05">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_CANFD5_8_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_CANFD5_8_MASK&#160;&#160;&#160;(0x8UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a2d57a4ac9036276ed5bd00e1c19ff379">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_CANFD9_16_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_CANFD9_16_MASK&#160;&#160;&#160;(0x10UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a6d44201c1703d3a46c87037ce281a381">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_DMA_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_DMA_MASK&#160;&#160;&#160;(0x400UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ac06065da50dac123e246ed51a98564e2">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_ENET1_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_ENET1_MASK&#160;&#160;&#160;(0x2000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a56cc553c7f31d3b998e13927b683ed99">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_ENET2_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_ENET2_MASK&#160;&#160;&#160;(0x4000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a9d660ab404bf07125c48a45da1b85d13">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_GAMA1_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_GAMA1_MASK&#160;&#160;&#160;(0x800UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a5ad25198c779a861a1301520696aa121">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_GAMA2_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_GAMA2_MASK&#160;&#160;&#160;(0x1000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ab21ae00807076402d7053c86159c3210">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_MB_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_MB_MASK&#160;&#160;&#160;(0x200000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a11e99a481664cf719a84f860b951da16">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_VIC1_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_VIC1_MASK&#160;&#160;&#160;(0x8000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ad5f3fbd4a3055656ebb7a756da64ade0">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_VIC2A_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_VIC2A_MASK&#160;&#160;&#160;(0x10000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a35cca821ab1bd6e6a00951b22c04ee6a">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_VIC2B_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_VIC2B_MASK&#160;&#160;&#160;(0x20000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#af3adbae730c92a3e5880ff0ffc9a0bf8">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_VIC3A_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_VIC3A_MASK&#160;&#160;&#160;(0x40000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ab22dbb26217db0e02ac6ae4180f31853">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_VIC3B_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_VIC3B_MASK&#160;&#160;&#160;(0x80000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#aaf041fae77404b91dda0fc0423221e20">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_XSPI1A_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_XSPI1A_MASK&#160;&#160;&#160;(0x40UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ad9ca1d0f8707e608558b5e12896dc899">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_XSPI1B_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_XSPI1B_MASK&#160;&#160;&#160;(0x80UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ae24be428614ea60090098a46768d4d2c">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_XSPI2A_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_XSPI2A_MASK&#160;&#160;&#160;(0x100UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a9e65f53b247fca3ce0576fdeb5249571">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_XSPI2B_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_XSPI2B_MASK&#160;&#160;&#160;(0x200UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a4e7ad57eb735418c345e7e12215124e1">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_XSPI_SLV_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_XSPI_SLV_MASK&#160;&#160;&#160;(0x100000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a0537c2f2069999c63ec2079d7c794aaf">&#9670;&nbsp;</a></span>SDRV_SF_MODULE_XTRG_MASK</h2>
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<td class="memname">#define SDRV_SF_MODULE_XTRG_MASK&#160;&#160;&#160;(0x400000UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#af76d811aa8a9489a3871e044a26c5b8d">&#9670;&nbsp;</a></span>SDRV_SF_PD_MASK</h2>
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<td class="memname">#define SDRV_SF_PD_MASK&#160;&#160;&#160;(0x1UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a4225c8586b67f8726fcf99ce2df7dde2">&#9670;&nbsp;</a></span>SDRV_SP_PD_MASK</h2>
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<td class="memname">#define SDRV_SP_PD_MASK&#160;&#160;&#160;(0x2UL)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ada0f6c265d2af0b4956e3dd0269fe365">&#9670;&nbsp;</a></span>SDRV_SX_PD_MASK</h2>
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<td class="memname">#define SDRV_SX_PD_MASK&#160;&#160;&#160;(0x4UL)</td>
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<h2 class="groupheader">Typedef Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a347a970f837446e1f542d38f6e489dce">&#9670;&nbsp;</a></span>mcu_power_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__power_8h.html#af2fa3158e1c31c574fb522da81994679">mcu_power</a> <a class="el" href="sdrv__power_8h.html#a347a970f837446e1f542d38f6e489dce">mcu_power_e</a></td>
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<p>Definition for MCU power switch and IRAMC power. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a49ff3e0810ec5a5b7843595d9b432156">&#9670;&nbsp;</a></span>sdrv_clock_mode_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__power_8h.html#a8bd9d9eb30711fd8a3e3a14f4d1c932d">sdrv_clock_mode</a> <a class="el" href="sdrv__power_8h.html#a49ff3e0810ec5a5b7843595d9b432156">sdrv_clock_mode_e</a></td>
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<p>Definition for core clock mode. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a559ed0afa4db7fea6f92a28209e414d5">&#9670;&nbsp;</a></span>sdrv_hibernate_mode_config_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__hibernate__mode__config.html">sdrv_hibernate_mode_config</a> <a class="el" href="sdrv__power_8h.html#a559ed0afa4db7fea6f92a28209e414d5">sdrv_hibernate_mode_config_t</a></td>
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<p>Definition for hibernate mode config. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a14d3509c43f311009db34db9417e5e23">&#9670;&nbsp;</a></span>sdrv_iram_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__power_8h.html#a6bde4cc9e3dab178a3465febf4e78e88">sdrv_iram</a> <a class="el" href="sdrv__power_8h.html#a14d3509c43f311009db34db9417e5e23">sdrv_iram_e</a></td>
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<p>Definition for iram. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a280de6ff096a4c4e7e73912e363b7c25">&#9670;&nbsp;</a></span>sdrv_power_analog_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__power__analog.html">sdrv_power_analog</a> <a class="el" href="sdrv__power_8h.html#a280de6ff096a4c4e7e73912e363b7c25">sdrv_power_analog_t</a></td>
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<p>Definition for soc internal analog part power control. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a6e56b1dd4a20b012ac734938ba8e42cb">&#9670;&nbsp;</a></span>sdrv_power_dcdc_mode_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__power_8h.html#a6350275795a6fa297721f7babe666764">sdrv_power_dcdc_mode</a> <a class="el" href="sdrv__power_8h.html#a6e56b1dd4a20b012ac734938ba8e42cb">sdrv_power_dcdc_mode_e</a></td>
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<p>Definition for DCDC work mode. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a85076c534240cfea5dc6ee3058f3b01d">&#9670;&nbsp;</a></span>sdrv_power_dcdc_reg_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__power_8h.html#a6dd7c7ad0a3325c29049b6cb7ca391a7">sdrv_power_dcdc_reg</a> <a class="el" href="sdrv__power_8h.html#a85076c534240cfea5dc6ee3058f3b01d">sdrv_power_dcdc_reg_e</a></td>
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<p>DCDC reg config, each reg has 8bit. REG0,7,8 are common config. REG1~6 are separate config for HP_MODE and LP_MODE. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ac0b2128649c400d2c0a2057df8af89ee">&#9670;&nbsp;</a></span>sdrv_power_mode_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__power_8h.html#a8e9c3b3e099048f3b5f3ff089a64b079">sdrv_power_mode</a> <a class="el" href="sdrv__power_8h.html#ac0b2128649c400d2c0a2057df8af89ee">sdrv_power_mode_e</a></td>
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<p>Definition for system work mode. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a5b16251209442c7c3c8cd86147d05149">&#9670;&nbsp;</a></span>sdrv_sleep_mode_config_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__sleep__mode__config.html">sdrv_sleep_mode_config</a> <a class="el" href="sdrv__power_8h.html#a5b16251209442c7c3c8cd86147d05149">sdrv_sleep_mode_config_t</a></td>
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<p>Definition for sleep mode config. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a11c9b25081fb533bbddf19456db70579">&#9670;&nbsp;</a></span>sdrv_wakeup_src_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__power_8h.html#a440adcfe353324250caa17c5e202cfcd">sdrv_wakeup_src</a> <a class="el" href="sdrv__power_8h.html#a11c9b25081fb533bbddf19456db70579">sdrv_wakeup_src_e</a></td>
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<p>Definition for wakeup source. </p>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#af2fa3158e1c31c574fb522da81994679">&#9670;&nbsp;</a></span>mcu_power</h2>
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<td class="memname">enum <a class="el" href="sdrv__power_8h.html#af2fa3158e1c31c574fb522da81994679">mcu_power</a></td>
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<p>Definition for MCU power switch and IRAMC power. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679a414cf2359d240310b8f539a7cf85674d" name="af2fa3158e1c31c574fb522da81994679a414cf2359d240310b8f539a7cf85674d"></a>MCU_POWER_SF&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679a87167666a377792fa33ff26f54a78bfe" name="af2fa3158e1c31c574fb522da81994679a87167666a377792fa33ff26f54a78bfe"></a>MCU_POWER_SP&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679ad5ddf36c644138bd2386d0327d8d2d6d" name="af2fa3158e1c31c574fb522da81994679ad5ddf36c644138bd2386d0327d8d2d6d"></a>MCU_POWER_SX&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679acb214b71ee5784d4c9136f340d323aa5" name="af2fa3158e1c31c574fb522da81994679acb214b71ee5784d4c9136f340d323aa5"></a>MCU_POWER_GAMA&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679a6c7f6ebcc567a920c0b45fc052426afc" name="af2fa3158e1c31c574fb522da81994679a6c7f6ebcc567a920c0b45fc052426afc"></a>MCU_POWER_IRAM1&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679ab964c4c9ee97a3557d00d6c3683d2b70" name="af2fa3158e1c31c574fb522da81994679ab964c4c9ee97a3557d00d6c3683d2b70"></a>MCU_POWER_IRAM2&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679a33cabaf64c2c1d44f8007eedc2d3061d" name="af2fa3158e1c31c574fb522da81994679a33cabaf64c2c1d44f8007eedc2d3061d"></a>MCU_POWER_IRAM3&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679a01e4c38d388a60ef238dad970dd1a749" name="af2fa3158e1c31c574fb522da81994679a01e4c38d388a60ef238dad970dd1a749"></a>MCU_POWER_IRAM4&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679a799e835ee677813cae2502a18567ae95" name="af2fa3158e1c31c574fb522da81994679a799e835ee677813cae2502a18567ae95"></a>MCU_POWER_ACMP1&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679af7e829f8613f86f90ea60fa922d397a9" name="af2fa3158e1c31c574fb522da81994679af7e829f8613f86f90ea60fa922d397a9"></a>MCU_POWER_ACMP2&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679a7ff33b9c137b22c45e223f806c144ad7" name="af2fa3158e1c31c574fb522da81994679a7ff33b9c137b22c45e223f806c144ad7"></a>MCU_POWER_ACMP3&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679ab120e78fc2364212760493804534ade4" name="af2fa3158e1c31c574fb522da81994679ab120e78fc2364212760493804534ade4"></a>MCU_POWER_ACMP4&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af2fa3158e1c31c574fb522da81994679a70aba6f0f4635a69507dc2608783094d" name="af2fa3158e1c31c574fb522da81994679a70aba6f0f4635a69507dc2608783094d"></a>MCU_POWER_END&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a8bd9d9eb30711fd8a3e3a14f4d1c932d">&#9670;&nbsp;</a></span>sdrv_clock_mode</h2>
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<td class="memname">enum <a class="el" href="sdrv__power_8h.html#a8bd9d9eb30711fd8a3e3a14f4d1c932d">sdrv_clock_mode</a></td>
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<p>Definition for core clock mode. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a8bd9d9eb30711fd8a3e3a14f4d1c932da29abeedfc771a5dddb19547d46b572bb" name="a8bd9d9eb30711fd8a3e3a14f4d1c932da29abeedfc771a5dddb19547d46b572bb"></a>SDRV_CLOCK_NORMAL&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a8bd9d9eb30711fd8a3e3a14f4d1c932da6062eb7e12e461b6f1b06c748f76e367" name="a8bd9d9eb30711fd8a3e3a14f4d1c932da6062eb7e12e461b6f1b06c748f76e367"></a>SDRV_CLOCK_MEDIUM&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a8bd9d9eb30711fd8a3e3a14f4d1c932da43991d6e360145dd7373cc0879cf0693" name="a8bd9d9eb30711fd8a3e3a14f4d1c932da43991d6e360145dd7373cc0879cf0693"></a>SDRV_CLOCK_LOW&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a6bde4cc9e3dab178a3465febf4e78e88">&#9670;&nbsp;</a></span>sdrv_iram</h2>
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<td class="memname">enum <a class="el" href="sdrv__power_8h.html#a6bde4cc9e3dab178a3465febf4e78e88">sdrv_iram</a></td>
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<p>Definition for iram. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a6bde4cc9e3dab178a3465febf4e78e88a53f28aab12849f31e6e85faff6bfa764" name="a6bde4cc9e3dab178a3465febf4e78e88a53f28aab12849f31e6e85faff6bfa764"></a>SDRV_IRAM1&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6bde4cc9e3dab178a3465febf4e78e88acf74873aba88e025e69b19c80e2e417a" name="a6bde4cc9e3dab178a3465febf4e78e88acf74873aba88e025e69b19c80e2e417a"></a>SDRV_IRAM2&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6bde4cc9e3dab178a3465febf4e78e88aae5945d73feb9296f97f7d759d9f6ddb" name="a6bde4cc9e3dab178a3465febf4e78e88aae5945d73feb9296f97f7d759d9f6ddb"></a>SDRV_IRAM3&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6bde4cc9e3dab178a3465febf4e78e88aa3b2134a37d15d044d2c3ced56dec20b" name="a6bde4cc9e3dab178a3465febf4e78e88aa3b2134a37d15d044d2c3ced56dec20b"></a>SDRV_IRAM4&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a6350275795a6fa297721f7babe666764">&#9670;&nbsp;</a></span>sdrv_power_dcdc_mode</h2>
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<td class="memname">enum <a class="el" href="sdrv__power_8h.html#a6350275795a6fa297721f7babe666764">sdrv_power_dcdc_mode</a></td>
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<p>Definition for DCDC work mode. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a6350275795a6fa297721f7babe666764abc701340ce68117e36a42ee104dbb1da" name="a6350275795a6fa297721f7babe666764abc701340ce68117e36a42ee104dbb1da"></a>DCDC_HP_MODE&#160;</td><td class="fielddoc"><p >High performance mode </p>
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<tr><td class="fieldname"><a id="a6350275795a6fa297721f7babe666764adbf44b19b3cf44813b077762e90ab5b5" name="a6350275795a6fa297721f7babe666764adbf44b19b3cf44813b077762e90ab5b5"></a>DCDC_LP_MODE&#160;</td><td class="fielddoc"><p >Low performance mode </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a6dd7c7ad0a3325c29049b6cb7ca391a7">&#9670;&nbsp;</a></span>sdrv_power_dcdc_reg</h2>
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<td class="memname">enum <a class="el" href="sdrv__power_8h.html#a6dd7c7ad0a3325c29049b6cb7ca391a7">sdrv_power_dcdc_reg</a></td>
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<p>DCDC reg config, each reg has 8bit. REG0,7,8 are common config. REG1~6 are separate config for HP_MODE and LP_MODE. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a6dd7c7ad0a3325c29049b6cb7ca391a7a4e96f77973ebab828a03133df539846b" name="a6dd7c7ad0a3325c29049b6cb7ca391a7a4e96f77973ebab828a03133df539846b"></a>DCDC_REG_0&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6dd7c7ad0a3325c29049b6cb7ca391a7ad275088a228e15aad24b69fc426d2f42" name="a6dd7c7ad0a3325c29049b6cb7ca391a7ad275088a228e15aad24b69fc426d2f42"></a>DCDC_REG_1&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6dd7c7ad0a3325c29049b6cb7ca391a7aae2838f38f1b9ed9df39a869724ac3e3" name="a6dd7c7ad0a3325c29049b6cb7ca391a7aae2838f38f1b9ed9df39a869724ac3e3"></a>DCDC_REG_2&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6dd7c7ad0a3325c29049b6cb7ca391a7a2dde17ee2d95bfca1b20608190ed9577" name="a6dd7c7ad0a3325c29049b6cb7ca391a7a2dde17ee2d95bfca1b20608190ed9577"></a>DCDC_REG_3&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6dd7c7ad0a3325c29049b6cb7ca391a7ae2d496c280483f3ea58aa49ad728caaa" name="a6dd7c7ad0a3325c29049b6cb7ca391a7ae2d496c280483f3ea58aa49ad728caaa"></a>DCDC_REG_4&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6dd7c7ad0a3325c29049b6cb7ca391a7ade756a740832f8a90bf982423e4ed8e4" name="a6dd7c7ad0a3325c29049b6cb7ca391a7ade756a740832f8a90bf982423e4ed8e4"></a>DCDC_REG_5&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6dd7c7ad0a3325c29049b6cb7ca391a7a8b5a418f26d72db712ab755f665296dc" name="a6dd7c7ad0a3325c29049b6cb7ca391a7a8b5a418f26d72db712ab755f665296dc"></a>DCDC_REG_6&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6dd7c7ad0a3325c29049b6cb7ca391a7a68c511a718b639cdf503b44ab918a97f" name="a6dd7c7ad0a3325c29049b6cb7ca391a7a68c511a718b639cdf503b44ab918a97f"></a>DCDC_REG_7&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a6dd7c7ad0a3325c29049b6cb7ca391a7a081b8f0c63b9da9a01accb478ae996ba" name="a6dd7c7ad0a3325c29049b6cb7ca391a7a081b8f0c63b9da9a01accb478ae996ba"></a>DCDC_REG_8&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#aa4bf2d1e7622257b7fa40ac02842e34c">&#9670;&nbsp;</a></span>sdrv_power_error</h2>
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<td class="memname">enum <a class="el" href="sdrv__power_8h.html#aa4bf2d1e7622257b7fa40ac02842e34c">sdrv_power_error</a></td>
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<p>Power status error code. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="aa4bf2d1e7622257b7fa40ac02842e34ca3efd7f7a59d5ed8dcf6d926c882ced9e" name="aa4bf2d1e7622257b7fa40ac02842e34ca3efd7f7a59d5ed8dcf6d926c882ced9e"></a>SDRV_POWER_CONFIG_PARAMETER_WRONG&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="aa4bf2d1e7622257b7fa40ac02842e34ca76939a052d910d084512650994c313a8" name="aa4bf2d1e7622257b7fa40ac02842e34ca76939a052d910d084512650994c313a8"></a>SDRV_POWER_MODE_SET_WRONG&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="aa4bf2d1e7622257b7fa40ac02842e34cab848728ea3b42ffaf03649792decd2e9" name="aa4bf2d1e7622257b7fa40ac02842e34cab848728ea3b42ffaf03649792decd2e9"></a>SDRV_POWER_WAKEUP_STATUS_ERROR&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="aa4bf2d1e7622257b7fa40ac02842e34caf9096af1ec175b7d35cc59bae578a95d" name="aa4bf2d1e7622257b7fa40ac02842e34caf9096af1ec175b7d35cc59bae578a95d"></a>SDRV_POWER_IRAM_REINIT_TIMEOUT&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="aa4bf2d1e7622257b7fa40ac02842e34ca183554d18e6fa722cf62d02ad72b3ca8" name="aa4bf2d1e7622257b7fa40ac02842e34ca183554d18e6fa722cf62d02ad72b3ca8"></a>SDRV_POWER_CLOCK_SET_FAILED&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="aa4bf2d1e7622257b7fa40ac02842e34caa22277409534504296c453d2270513e4" name="aa4bf2d1e7622257b7fa40ac02842e34caa22277409534504296c453d2270513e4"></a>SDRV_POWER_AP_STATUS_ERROR&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="aa4bf2d1e7622257b7fa40ac02842e34ca67650cfc15fdf9ad297fd4ec3b62721a" name="aa4bf2d1e7622257b7fa40ac02842e34ca67650cfc15fdf9ad297fd4ec3b62721a"></a>SDRV_POWER_PMU_STATUS_ERROR&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="aa4bf2d1e7622257b7fa40ac02842e34ca7c06e7441f51f99e5469ad239442730a" name="aa4bf2d1e7622257b7fa40ac02842e34ca7c06e7441f51f99e5469ad239442730a"></a>SDRV_POWER_SMC_STATUS_ERROR&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a8e9c3b3e099048f3b5f3ff089a64b079">&#9670;&nbsp;</a></span>sdrv_power_mode</h2>
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<td class="memname">enum <a class="el" href="sdrv__power_8h.html#a8e9c3b3e099048f3b5f3ff089a64b079">sdrv_power_mode</a></td>
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<p>Definition for system work mode. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a8e9c3b3e099048f3b5f3ff089a64b079a6b2c96c735e2435f4748c7ef1af77943" name="a8e9c3b3e099048f3b5f3ff089a64b079a6b2c96c735e2435f4748c7ef1af77943"></a>SDRV_RUN_MODE&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a8e9c3b3e099048f3b5f3ff089a64b079a546ba50996d4d18139364ead3a9f9265" name="a8e9c3b3e099048f3b5f3ff089a64b079a546ba50996d4d18139364ead3a9f9265"></a>SDRV_SLEEP_MODE&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a8e9c3b3e099048f3b5f3ff089a64b079a1c5fa3d2193486499853cb0111f80e51" name="a8e9c3b3e099048f3b5f3ff089a64b079a1c5fa3d2193486499853cb0111f80e51"></a>SDRV_HIBERNATE_MODE&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a8e9c3b3e099048f3b5f3ff089a64b079aac1ae1de2f33693cc3a1f13280796125" name="a8e9c3b3e099048f3b5f3ff089a64b079aac1ae1de2f33693cc3a1f13280796125"></a>SDRV_RTC_MODE&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a440adcfe353324250caa17c5e202cfcd">&#9670;&nbsp;</a></span>sdrv_wakeup_src</h2>
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<td class="memname">enum <a class="el" href="sdrv__power_8h.html#a440adcfe353324250caa17c5e202cfcd">sdrv_wakeup_src</a></td>
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<p>Definition for wakeup source. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcdaf0217d886fe8492c40bf0ba6950d8158" name="a440adcfe353324250caa17c5e202cfcdaf0217d886fe8492c40bf0ba6950d8158"></a>SDRV_WAKEUP_GPIO_SF&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcdaaf5697ffc5db2de9f2612755102fde78" name="a440adcfe353324250caa17c5e202cfcdaaf5697ffc5db2de9f2612755102fde78"></a>SDRV_WAKEUP_GPIO_AP&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcda9f3c56cda232390bec601c3528c36230" name="a440adcfe353324250caa17c5e202cfcda9f3c56cda232390bec601c3528c36230"></a>SDRV_WAKEUP_RTC1&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcda6d06d4ffb29b1eda972fe2eec50d572a" name="a440adcfe353324250caa17c5e202cfcda6d06d4ffb29b1eda972fe2eec50d572a"></a>SDRV_WAKEUP_RTC2&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcda7826cc36f0e8fca5f26b3e855d6764e2" name="a440adcfe353324250caa17c5e202cfcda7826cc36f0e8fca5f26b3e855d6764e2"></a>SDRV_WAKEUP_UART1&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcdac6c40f5edc2b3205907e368e8a0b0507" name="a440adcfe353324250caa17c5e202cfcdac6c40f5edc2b3205907e368e8a0b0507"></a>SDRV_WAKEUP_UART2&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcda5ff99ff051dae0fb81cb3f6220e2e70c" name="a440adcfe353324250caa17c5e202cfcda5ff99ff051dae0fb81cb3f6220e2e70c"></a>SDRV_WAKEUP_UART3&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcda51e569c5642ab667e9286a3647c8af76" name="a440adcfe353324250caa17c5e202cfcda51e569c5642ab667e9286a3647c8af76"></a>SDRV_WAKEUP_UART4&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcda9f2ec49442245c09a4106d08fd806f65" name="a440adcfe353324250caa17c5e202cfcda9f2ec49442245c09a4106d08fd806f65"></a>SDRV_WAKEUP_UART5&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcda90d6153bc94a578ba13a8e154fc64f4a" name="a440adcfe353324250caa17c5e202cfcda90d6153bc94a578ba13a8e154fc64f4a"></a>SDRV_WAKEUP_UART6&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcda82b05fb891ba89f7be7187a8177264f9" name="a440adcfe353324250caa17c5e202cfcda82b05fb891ba89f7be7187a8177264f9"></a>SDRV_WAKEUP_UART7&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcdaddf1b8ccc0c5f190d5f7125bcdfff5a7" name="a440adcfe353324250caa17c5e202cfcdaddf1b8ccc0c5f190d5f7125bcdfff5a7"></a>SDRV_WAKEUP_UART8&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a440adcfe353324250caa17c5e202cfcdaccf14a068bf31de6c80937340877448c" name="a440adcfe353324250caa17c5e202cfcdaccf14a068bf31de6c80937340877448c"></a>SDRV_WAKEUP_END&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="groupheader">Function Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a0c857d41dc400a0a2701304aaff213fc">&#9670;&nbsp;</a></span>sdrv_power_clock_set_mode()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_power_clock_set_mode </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__power_8h.html#a49ff3e0810ec5a5b7843595d9b432156">sdrv_clock_mode_e</a>&#160;</td>
<td class="paramname"><em>mode</em></td><td>)</td>
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<p>Set clock mode for core and bus. </p>
<p >This function config clock mode for core and bus. Normal mode use default clock settings, medium mode reduce core and bus frequency to half, low mode set core and bus frequency to 24MHz.</p>
<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>clock mode defined in sdrv_clock_mode_e. </td></tr>
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</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a6aad576d30ee1ac9c40b7517a396f752">&#9670;&nbsp;</a></span>sdrv_power_dcdc_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_power_dcdc_config </td>
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<td class="paramtype">paddr_t&#160;</td>
<td class="paramname"><em>dcdc_base</em>, </td>
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<td class="paramtype"><a class="el" href="sdrv__power_8h.html#a6e56b1dd4a20b012ac734938ba8e42cb">sdrv_power_dcdc_mode_e</a>&#160;</td>
<td class="paramname"><em>mode</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype"><a class="el" href="sdrv__power_8h.html#a85076c534240cfea5dc6ee3058f3b01d">sdrv_power_dcdc_reg_e</a>&#160;</td>
<td class="paramname"><em>dcdc_reg</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint8_t&#160;</td>
<td class="paramname"><em>cfg_val</em>&#160;</td>
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<td></td>
<td>)</td>
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<p>Config DCDC REG0~8. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">dcdc_base</td><td>DCDC controller base. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>high or low performance mode. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">dcdc_reg</td><td>DCDC_REG_0 - DCDC_REG_8. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">cfg_val</td><td>config value. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a616fcde3b5fdddb55ad684e4a3974074">&#9670;&nbsp;</a></span>sdrv_power_init()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_power_init </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__power_8h.html#a5b16251209442c7c3c8cd86147d05149">sdrv_sleep_mode_config_t</a> *&#160;</td>
<td class="paramname"><em>sleep_cfg</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__power_8h.html#a559ed0afa4db7fea6f92a28209e414d5">sdrv_hibernate_mode_config_t</a> *&#160;</td>
<td class="paramname"><em>hib_cfg</em>&#160;</td>
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<p>Initialize clock/reset/power config under sleep and hibernate mode. </p>
<p >This function will mask all interrupts and gate all xcg clock expect for wakeup modules. It will reset all modules expect that need wakeup and user defined not reset in low power mode. According to user configration, config smc sleep/hibernate mode core power switch and pmu pwr ctrl/pwr on status.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">sleep_cfg</td><td>config for sleep mode </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">hib_cfg</td><td>config for hibernate mode </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ada14cd36e53d5c4f51f97c342592b19d">&#9670;&nbsp;</a></span>sdrv_power_iram_reinit()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_power_iram_reinit </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__power_8h.html#a14d3509c43f311009db34db9417e5e23">sdrv_iram_e</a>&#160;</td>
<td class="paramname"><em>iram</em></td><td>)</td>
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<p>Reinit specific iram. </p>
<p >This function reinit specific iram. If iram is power down in hibernate, after wakeup, you need call this function before use it.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">iram</td><td>iram defined in sdrv_iram_e. </td></tr>
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</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ac05307cdb7ace3430c2a22e018181531">&#9670;&nbsp;</a></span>sdrv_power_rom_disable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_power_rom_disable </td>
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<p>Set rom disable. </p>
<p >When set rom disable, ROM code read and register access are disable until POR reset.</p>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a21501e3bfa172f651cc22b3066999ef0">&#9670;&nbsp;</a></span>sdrv_power_set_mode()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_power_set_mode </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__power_8h.html#ac0b2128649c400d2c0a2057df8af89ee">sdrv_power_mode_e</a>&#160;</td>
<td class="paramname"><em>mode</em></td><td>)</td>
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<p>Set soc to specific power mode. </p>
<p >This function config SMC enable wfi detect and excute wfi instrcut. After all core enter wfi, it will start hardware operation. Before enter sleep, software config all iram to retention mode. Before enter hibernate, software power down iram as pre-defined, and power down analog part. Then use SVC interrupt to save all core registers. After wakeup from sleep/hibernate, it will return from this call. Iram and analog will be powered again. If call to enter RTC mode, it will power down at once.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>mode defined in sdrv_power_mode_e. </td></tr>
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</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a51e5041480c8922d452237e7dfae1e22">&#9670;&nbsp;</a></span>sdrv_power_usb_power_down()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_power_usb_power_down </td>
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<p>USB phy power down. </p>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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