483 lines
10 KiB
C
483 lines
10 KiB
C
//*****************************************************************************
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//
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// WARNING: Automatically generated file, don't modify anymore!!!
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//
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// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
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// Software License Agreement
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//
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//*****************************************************************************
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#include <types.h>
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#include <regs_base.h>
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#include <reset_ip.h>
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#include <compiler.h>
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#include <reg.h>
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#include <sdrv_scr.h>
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#include <scr_hw.h>
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#include "udelay/udelay.h"
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/**
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* @brief E3L SAF reset signal id.
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*/
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typedef enum e3l_reset_signal_safety {
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E3L_RSTSIG_SAF_CR5_SAF = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_CORE, 0),
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E3L_RSTSIG_SAF_LATENT = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_LATENT, 0),
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E3L_RSTSIG_SAF_MISSION0 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 0),
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E3L_RSTSIG_SAF_MISSION1 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 1),
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E3L_RSTSIG_SAF_MISSION2 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 2),
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E3L_RSTSIG_SAF_MISSION3 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 3),
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E3L_RSTSIG_SAF_MISSION4 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 4),
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E3L_RSTSIG_SAF_MISSION5 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 5),
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E3L_RSTSIG_SAF_CANFD16 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 0),
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E3L_RSTSIG_SAF_CANFD21,
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E3L_RSTSIG_SAF_CANFD3,
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E3L_RSTSIG_SAF_CANFD4,
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E3L_RSTSIG_SAF_CANFD5,
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E3L_RSTSIG_SAF_CANFD6 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 5),
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E3L_RSTSIG_SAF_CANFD7,
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E3L_RSTSIG_SAF_CANFD23,
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E3L_RSTSIG_SAF_XSPI1A,
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E3L_RSTSIG_SAF_XSPI1B,
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E3L_RSTSIG_SAF_DMA_RST0 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 10),
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E3L_RSTSIG_SAF_DMA_RST1,
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E3L_RSTSIG_SAF_ENET1,
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E3L_RSTSIG_SAF_VIC1,
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E3L_RSTSIG_SAF_XSPI_SLV,
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E3L_RSTSIG_SAF_XTRG = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 15),
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E3L_RSTSIG_SAF_SACI2,
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E3L_RSTSIG_SAF_SEHC1,
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E3L_RSTSIG_SAF_USB,
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E3L_RSTSIG_SAF_SEIP,
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E3L_RSTSIG_SAF_CSLITE = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 20),
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} e3l_reset_signal_safety_e;
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/* SAF rstgen controller */
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sdrv_rstgen_t g_rstgen_saf = {
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.base = APB_RSTGEN_SF_BASE,
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};
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/* global reset */
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sdrv_rstgen_glb_t rstctl_glb = {
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.rst_sf_ctl = &g_rstgen_saf,
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};
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/* SAF core */
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sdrv_rstgen_sig_t rstsig_cr5_saf = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CR5_SAF,
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};
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/**
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* @brief reset latent
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*
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* latent signals will reset automatically after power on.
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*
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* signals in latent:
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* AHB2APB1
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* AHB2APB2
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* AHB2APB3
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* AHB2APB4
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* APBMUX2
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* APBMUX3
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* IROMC
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* IOMUXC_SF_COMP
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* MAC
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* SCR_SF
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* WDT1
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* SEM1
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* SEM2
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* VD_SF_DIG
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* IOC
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* EIC_SF
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* FUSE_LSP_CMP
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* FAB_SF
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* UART1
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* UART2
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* UART3
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* UART4
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* UART5
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* UART6
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* UART7
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* UART8
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* UART9
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* UART10
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* UART11
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* UART12
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* SPI1
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* SPI2
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* SPI3
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* SPI4
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* SPI5
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* SPI6
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* I2C1
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* I2C2
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* I2C3
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* I2C4
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* I2C5
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* I2C6
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* ETMR1
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* ETMR2
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* EPWM1
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* EPWM2
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* MPC_XSPI1A
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* MPC_XSPI1B
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* AAPB_MPC_XSPI1A
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* AAPB_MPC_XSPI1B
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* AAPB_MPC_SEIP
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* WDT8
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* PPC_APBMUX2
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* PPC_APBMUX3
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* PPC_APBMUX4
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* PPC_APBMUX1
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* MPC_ROMC
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* XB_SF
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* MPC_IRAMC1
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* MPC_CR5_SF
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* POR_SF_DIG
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* PT_SNS_SF_DIG
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* MPC_VIC1
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* BTM1
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* BTM2
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* BTM3
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* BTM4
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* AAPB_XSPI1A
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* AAPB_XSPI1B
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* MPC_SEIP
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* APB_APBMUX1_SLV
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* APB_PMUX2_DEC_SLV
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* AAPB_APBMUX3
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* APB_DCDC1_SLV
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* APB_APBMUX4_SLV
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* AAXI_APSF_MST
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*/
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sdrv_rstgen_sig_t rstsig_latent = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_LATENT,
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};
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/*
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* @brief reset mission
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*
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* reset mission signals will reset automatically after power on.
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*
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*/
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/**
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* @brief reset mission 0
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*
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* signals in mission 0:
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* GPIO_SF
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* IOMUXC_SF
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* SMC
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* PMU_CORE
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* APB_APBMUX1_MST
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* APB_PMUX2_DEC_MST
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* APB_SEIP_NVM_MST
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*/
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sdrv_rstgen_sig_t rstsig_mission0 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_MISSION0,
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};
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/**
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* @brief reset mission 1
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*
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* signals in mission 1:
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* PLL1
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* PLL2
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* Pll3
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*/
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sdrv_rstgen_sig_t rstsig_mission1 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_MISSION1,
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};
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/**
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* @brief reset mission 2
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*
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* signals in mission 2:
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* ANA_SF_SADC1
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* ANA_SF_SADC2
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* ANA_SF_SADC3
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* ANA_SF_SACMP1
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* ANA_SF_SACMP2
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*/
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sdrv_rstgen_sig_t rstsig_mission2 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_MISSION2,
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};
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/**
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* @brief reset mission 3
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*
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* signals in mission 3:
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* IRAM1
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*/
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sdrv_rstgen_sig_t rstsig_mission3 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_MISSION3,
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};
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/**
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* @brief reset mission 4
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*
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* signals in mission 4:
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* DCDC1
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* APB_DCDC1_MST
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*/
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sdrv_rstgen_sig_t rstsig_mission4 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_MISSION4,
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};
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/**
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* @brief reset mission 5
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*
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* signals in mission 5:
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* APBMUX4
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* PTB
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* AHBDEC_SEIP
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* APB_SEC_STORAGE1_SLV
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* APB_SEIP_NVM_SLV
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* APB_APBMUX4_MST
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* AAXI_APSF_SLV
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*/
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sdrv_rstgen_sig_t rstsig_mission5 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_MISSION5,
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};
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/* reset module */
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sdrv_rstgen_sig_t rstsig_canfd16 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CANFD16,
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};
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sdrv_rstgen_sig_t rstsig_canfd21 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CANFD21,
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};
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sdrv_rstgen_sig_t rstsig_canfd3 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CANFD3,
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};
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sdrv_rstgen_sig_t rstsig_canfd4 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CANFD4,
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};
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sdrv_rstgen_sig_t rstsig_canfd5 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CANFD5,
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};
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sdrv_rstgen_sig_t rstsig_canfd6 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CANFD6,
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};
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sdrv_rstgen_sig_t rstsig_canfd7 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CANFD7,
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};
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sdrv_rstgen_sig_t rstsig_canfd23 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CANFD23,
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};
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typedef enum reset_xspi_port_id {
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RST_XSPI_1A = 0U,
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RST_XSPI_1B = 1U,
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RST_XSPI_NUM = 2U,
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} reset_xspi_port_id_e;
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static sdrv_scr_t scr_ctrl = {
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.base = APB_SCR_SF_BASE,
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};
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static uint32_t xspi_base[RST_XSPI_NUM] = {
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APB_XSPI1PORTA_BASE,
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APB_XSPI1PORTB_BASE,
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};
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static scr_signal_t sig_xspi_scr[RST_XSPI_NUM][4] = {
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{
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SCR_SF_AAPB_XSPI1A_SRC_IRQ_ENB,
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SCR_SF_AAPB_XSPI1A_SRC_UNCERR_CLR,
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SCR_SF_AAPB_XSPI1A_DST_IRQ_ENB,
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SCR_SF_AAPB_XSPI1A_DST_UNCERR_CLR,
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},
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{
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SCR_SF_AAPB_XSPI1B_SRC_IRQ_ENB,
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SCR_SF_AAPB_XSPI1B_SRC_UNCERR_CLR,
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SCR_SF_AAPB_XSPI1B_DST_IRQ_ENB,
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SCR_SF_AAPB_XSPI1B_DST_UNCERR_CLR,
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},
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};
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/* clear XSPI sem error */
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static void rstsig_xspi_pre_handler(uint32_t rstgen_sig_id)
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{
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uint32_t xspi_id = RST_XSPI_1A;
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if (rstgen_sig_id == E3L_RSTSIG_SAF_XSPI1A) {
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xspi_id = RST_XSPI_1A;
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}
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else if (rstgen_sig_id == E3L_RSTSIG_SAF_XSPI1B) {
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xspi_id = RST_XSPI_1B;
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}
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else {
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return;
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}
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][0], 0U);
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][2], 0U);
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(void)readl(xspi_base[xspi_id]);
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};
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static void rstsig_xspi_post_handler(uint32_t rstgen_sig_id)
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{
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uint32_t xspi_id = RST_XSPI_1A;
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if (rstgen_sig_id == E3L_RSTSIG_SAF_XSPI1A) {
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xspi_id = RST_XSPI_1A;
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}
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else if (rstgen_sig_id == E3L_RSTSIG_SAF_XSPI1B) {
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xspi_id = RST_XSPI_1B;
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}
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else {
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return;
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}
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udelay(10);
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(void)readl(xspi_base[xspi_id]);
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][1], 1U);
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][1], 0U);
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][3], 1U);
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][3], 0U);
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][0], 1U);
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][2], 1U);
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}
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sdrv_rstgen_sig_t rstsig_xspi1a = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_XSPI1A,
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.pre_handler = rstsig_xspi_pre_handler,
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.post_handler = rstsig_xspi_post_handler,
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};
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sdrv_rstgen_sig_t rstsig_xspi1b = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_XSPI1B,
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.pre_handler = rstsig_xspi_pre_handler,
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.post_handler = rstsig_xspi_post_handler,
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};
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sdrv_rstgen_sig_t rstsig_dma_rst0 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_DMA_RST0,
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};
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sdrv_rstgen_sig_t rstsig_dma_rst1 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_DMA_RST1,
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};
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sdrv_rstgen_sig_t rstsig_enet1 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_ENET1,
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};
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sdrv_rstgen_sig_t rstsig_vic1 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_VIC1,
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};
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sdrv_rstgen_sig_t rstsig_xspi_slv = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_XSPI_SLV,
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};
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sdrv_rstgen_sig_t rstsig_xtrg = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_XTRG,
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};
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sdrv_rstgen_sig_t rstsig_saci2 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_SACI2,
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};
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sdrv_rstgen_sig_t rstsig_sehc1 = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_SEHC1,
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};
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sdrv_rstgen_sig_t rstsig_usb = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_USB,
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};
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sdrv_rstgen_sig_t rstsig_seip = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_SEIP,
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.need_clr_rst = true,
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};
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sdrv_rstgen_sig_t rstsig_cslite = {
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.rst_ctl = &g_rstgen_saf,
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.id = E3L_RSTSIG_SAF_CSLITE,
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};
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/* general register */
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sdrv_rstgen_general_reg_t reset_general_reg_sf_remap = {
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.rst_ctl = &g_rstgen_saf,
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.id = 1,
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};
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sdrv_rstgen_general_reg_t reset_general_reg_sf_boot = {
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.rst_ctl = &g_rstgen_saf,
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.id = 7,
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};
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sdrv_rstgen_general_reg_t reset_general_reg_rom_ctrl = {
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.rst_ctl = &g_rstgen_saf,
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.id = 0,
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};
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/* recovery module */
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__WEAK sdrv_recovery_btm_t recovery_btm_list = {
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.btm_num = 4,
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.btm_base = {
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APB_BTM1_BASE,
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APB_BTM2_BASE,
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APB_BTM3_BASE,
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APB_BTM4_BASE,
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},
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};
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__WEAK sdrv_recovery_etimer_t recovery_etimer_list = {
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.etimer_num = 2,
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.etimer_base = {
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APB_ETMR1_BASE,
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APB_ETMR2_BASE,
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},
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};
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__WEAK sdrv_recovery_epwm_t recovery_epwm_list = {
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.epwm_num = 2,
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.epwm_base = {
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APB_EPWM1_BASE,
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APB_EPWM2_BASE,
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|
},
|
|
};
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|
|
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__WEAK sdrv_recovery_module_t recovery_module_array = {
|
|
.btm_list = &recovery_btm_list,
|
|
.etimer_list = &recovery_etimer_list,
|
|
.epwm_list = &recovery_epwm_list,
|
|
};
|