78 lines
2.4 KiB
C
78 lines
2.4 KiB
C
/*
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* arm.h
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*
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* Copyright (c) 2020 Semidrive Semiconductor.
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* All rights reserved.
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*
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* Description: ARMV7R common register interface.
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*
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* Revision History:
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* -----------------
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*/
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#ifndef ARMV7R_ARM_H
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#define ARMV7R_ARM_H
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#define MODE_USR 0x10
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#define MODE_FIQ 0x11
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#define MODE_IRQ 0x12
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#define MODE_SVC 0x13
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#define MODE_ABT 0x17
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#define MODE_UND 0x1B
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#define MODE_SYS 0x1F
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#define MODE_MASK 0x1F
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/* SCTLR */
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#define SCTLR_M (1 << 0)
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#define SCTLR_A (1 << 1)
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#define SCTLR_C (1 << 2)
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#define SCTLR_CCP15BEN (1 << 5)
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#define SCTLR_B (1 << 7)
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#define SCTLR_SW (1 << 10)
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#define SCTLR_Z (1 << 11)
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#define SCTLR_I (1 << 12)
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#define SCTLR_V (1 << 13)
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#define SCTLR_RR (1 << 14)
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#define SCTLR_BR (1 << 17)
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#define SCTLR_DZ (1 << 19)
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#define SCTLR_FI (1 << 21)
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#define SCTLR_U (1 << 22)
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#define SCTLR_VE (1 << 24)
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#define SCTLR_EE (1 << 25)
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#define SCTLR_NMFI (1 << 27)
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#define SCTLR_TE (1 << 30)
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#define SCTLR_IE (1 << 31)
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/* PSR */
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#define PSR_MODE_SHIFT (0)
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#define PSR_MODE_MASK (0x1f << PSR_MODE_SHIFT)
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#define PSR_MODE_USR (MODE_USR << PSR_MODE_SHIFT)
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#define PSR_MODE_FIQ (MODE_FIQ << PSR_MODE_SHIFT)
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#define PSR_MODE_IRQ (MODE_IRQ << PSR_MODE_SHIFT)
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#define PSR_MODE_SVC (MODE_SVC << PSR_MODE_SHIFT)
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#define PSR_MODE_ABT (MODE_ABT << PSR_MODE_SHIFT)
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#define PSR_MODE_UND (MODE_UND << PSR_MODE_SHIFT)
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#define PSR_MODE_SYS (MODE_SYS << PSR_MODE_SHIFT)
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#define PSR_T_BIT (1 << 5)
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#define PSR_F_BIT (1 << 6)
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#define PSR_I_BIT (1 << 7)
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#define PSR_A_BIT (1 << 8)
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#define PSR_E_BIT (1 << 9)
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#define PSR_IT27_SHIFT (10)
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#define PSR_IT27_MASK (0x3f << PSR_IT27_SHIFT)
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#define PSR_GE_SHIFT (16)
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#define PSR_GE_MASK (15 << PSR_GE_SHIFT)
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#define PSR_J_BIT (1 << 24)
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#define PSR_IT01_SHIFT (25)
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#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT)
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#define PSR_Q_BIT (1 << 27)
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#define PSR_V_BIT (1 << 28)
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#define PSR_C_BIT (1 << 29)
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#define PSR_Z_BIT (1 << 30)
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#define PSR_N_BIT (1 << 31)
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#endif
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