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<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_ee023d43c33bfccc31aa50a48a76892b.html">include</a></li> </ul>
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<div class="headertitle"><div class="title">sdrv_dma.h File Reference</div></div>
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<div class="textblock"><code>#include &lt;part.h&gt;</code><br />
<code>#include &quot;common.h&quot;</code><br />
<code>#include &quot;../source/dma/sdrv_dma_regdef.h&quot;</code><br />
<code>#include &quot;compiler.h&quot;</code><br />
<code>#include &quot;regs_base.h&quot;</code><br />
<code>#include &quot;<a class="el" href="sdrv__common_8h_source.html">sdrv_common.h</a>&quot;</code><br />
</div>
<p><a href="sdrv__dma_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__dma__mux__param__t.html">sdrv_dma_mux_param_t</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__dma__linklist__descriptor__t.html">sdrv_dma_linklist_descriptor_t</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__dma.html">sdrv_dma</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__dma__channel__config__t.html">sdrv_dma_channel_config_t</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:a274159adbb399be5ca569555c1b39aab"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a274159adbb399be5ca569555c1b39aab">sdrv_dma_bus_width_e</a> { <a class="el" href="sdrv__dma_8h.html#a274159adbb399be5ca569555c1b39aaba64edfb6c20d4c1dd369b8cccf5f762ae">SDRV_DMA_BUSWIDTH_1_BYTE</a> = 1
, <a class="el" href="sdrv__dma_8h.html#a274159adbb399be5ca569555c1b39aababbea627f8f03a6081436f5e3c93357db">SDRV_DMA_BUSWIDTH_2_BYTES</a> = 2
, <a class="el" href="sdrv__dma_8h.html#a274159adbb399be5ca569555c1b39aaba61a990c895acfe0d73a0ce6201a6842d">SDRV_DMA_BUSWIDTH_4_BYTES</a> = 4
, <a class="el" href="sdrv__dma_8h.html#a274159adbb399be5ca569555c1b39aaba124c119c33bdb51dcc0fc9b6e6f577a8">SDRV_DMA_BUSWIDTH_8_BYTES</a> = 8
}</td></tr>
<tr class="separator:a274159adbb399be5ca569555c1b39aab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ce59be117b706c31d9a07dbb9e88839"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839">sdrv_dma_burst_len_e</a> { <br />
&#160;&#160;<a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a7b89b41973b790926f7cafd71875d033">SDRV_DMA_BURST_LEN_1</a> = 0
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a97a6342a884f90746227d0f67cc26e8b">SDRV_DMA_BURST_LEN_2</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a59ccacaf17ca77444636b785bee8ca15">SDRV_DMA_BURST_LEN_3</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a94386d5df4088c3568e630ef7d3f77a1">SDRV_DMA_BURST_LEN_4</a>
, <br />
&#160;&#160;<a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839ae51f7c8805d36cb72a8bcebbf322e63f">SDRV_DMA_BURST_LEN_5</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a357710059f2a94e4bcb2e2e6b957a431">SDRV_DMA_BURST_LEN_6</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a09b39a5dc7c9ae6f5050c4402719bf6c">SDRV_DMA_BURST_LEN_7</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a6c02d47a25bee28570205a1fbda8f936">SDRV_DMA_BURST_LEN_8</a>
, <br />
&#160;&#160;<a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a79b507f0dd447063530baeb28bffb90a">SDRV_DMA_BURST_LEN_9</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839ab4d1bc8ba573ac61664435bce1f30efc">SDRV_DMA_BURST_LEN_10</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839afc8199130fb10a9a0d6d0ec2b5da4f92">SDRV_DMA_BURST_LEN_11</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a7e6ddc568b2d8d0bb6be9c22dd093389">SDRV_DMA_BURST_LEN_12</a>
, <br />
&#160;&#160;<a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a3495a52eaf56c1f24acf2dd761245150">SDRV_DMA_BURST_LEN_13</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a5ec646f7fe03293f9f519e1939290adc">SDRV_DMA_BURST_LEN_14</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839afd771903388b3894dd2e194b9c4cbc8a">SDRV_DMA_BURST_LEN_15</a>
, <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839ac915d715fbf35b6a06ee325c50f99e49">SDRV_DMA_BURST_LEN_16</a>
, <br />
&#160;&#160;<a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839a89db44b757f4ecf2119a13e6dbc19010">SDRV_DMA_BURST_LEN_UNDEFINED</a>
<br />
}</td></tr>
<tr class="separator:a7ce59be117b706c31d9a07dbb9e88839"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d0cf1f599920228c33c952a30d92c01"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a9d0cf1f599920228c33c952a30d92c01">sdrv_dma_port_sel_e</a> { <a class="el" href="sdrv__dma_8h.html#a9d0cf1f599920228c33c952a30d92c01a07fecbf4286bda882f876004cc1f2dce">SDRV_DMA_PORT_AXI64</a> = 0
, <a class="el" href="sdrv__dma_8h.html#a9d0cf1f599920228c33c952a30d92c01ac78883ce5096aebaf45f0c7197590655">SDRV_DMA_PORT_AHB32</a>
, <a class="el" href="sdrv__dma_8h.html#a9d0cf1f599920228c33c952a30d92c01a51e182952da125efd9855a9cfebefc43">SDRV_DMA_PROT_NOT_DEFINED</a>
}</td></tr>
<tr class="separator:a9d0cf1f599920228c33c952a30d92c01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af223f52b0b99738e3384a3c1f7a3d526"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#af223f52b0b99738e3384a3c1f7a3d526">sdrv_dma_buffer_mode_e</a> { <a class="el" href="sdrv__dma_8h.html#af223f52b0b99738e3384a3c1f7a3d526a155c233259f836182437726b0c3ba3ce">SDRV_DMA_SINGLE_BUFFER</a> = 0
, <a class="el" href="sdrv__dma_8h.html#af223f52b0b99738e3384a3c1f7a3d526aafb62d240365677f9b33ccfacdf1b63d">SDRV_DMA_DOUBLE_BUFFER</a>
, <a class="el" href="sdrv__dma_8h.html#af223f52b0b99738e3384a3c1f7a3d526a54d0d041c6399e93a1fb7d3b998bfc3a">SDRV_DMA_CIRCULAR_BUFFER</a>
, <a class="el" href="sdrv__dma_8h.html#af223f52b0b99738e3384a3c1f7a3d526aaf53df30ad90b12870a79be85a3a4c40">SDRV_DMA_2D_BUFFER</a>
, <a class="el" href="sdrv__dma_8h.html#af223f52b0b99738e3384a3c1f7a3d526a2a7d052b57d12079c62100a55de4415e">SDRV_DMA_BUFFER_NOT_DEFINED</a>
}</td></tr>
<tr class="separator:af223f52b0b99738e3384a3c1f7a3d526"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3a1413e4588936959d4c1b1efcd4a03c"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a3a1413e4588936959d4c1b1efcd4a03c">sdrv_dma_switch_event_ctrl_e</a> { <a class="el" href="sdrv__dma_8h.html#a3a1413e4588936959d4c1b1efcd4a03ca57d713a7292a5aaf98193e8d26d5c31f">SDRV_DMA_SWT_EVT_CTL_STOP_WTH_INT</a> = 0
, <a class="el" href="sdrv__dma_8h.html#a3a1413e4588936959d4c1b1efcd4a03cab97bebc42e8599c7b00683ac19d15d71">SDRV_DMA_SWT_EVT_CTL_SUSPEND_WTH_INT</a>
, <a class="el" href="sdrv__dma_8h.html#a3a1413e4588936959d4c1b1efcd4a03cad09478efd78a174c8e12b858a691f515">SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTH_INT</a>
, <a class="el" href="sdrv__dma_8h.html#a3a1413e4588936959d4c1b1efcd4a03ca3fbe4cc1bcd67e9330473cb40ba785d9">SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTHOUT_INT</a>
, <a class="el" href="sdrv__dma_8h.html#a3a1413e4588936959d4c1b1efcd4a03ca2112366764c560933380e5b933cfcca3">SDRV_DMA_SWT_EVT_CTL_UNDEFINED</a>
}</td></tr>
<tr class="separator:a3a1413e4588936959d4c1b1efcd4a03c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a95f065bec1af860620ef897fec9f868d"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a95f065bec1af860620ef897fec9f868d">sdrv_dma_trigger_mode_e</a> { <a class="el" href="sdrv__dma_8h.html#a95f065bec1af860620ef897fec9f868da242ce90cb31c1fad854a24b06f648612">SDRV_DMA_TRIGGER_BY_HARDWARE</a> = 0
, <a class="el" href="sdrv__dma_8h.html#a95f065bec1af860620ef897fec9f868dac6740297a4301133c77407f34879ec6d">SDRV_DMA_TRIGGER_BY_SOFTWARE</a>
, <a class="el" href="sdrv__dma_8h.html#a95f065bec1af860620ef897fec9f868da3835132e4e38c7804fd08d5132179611">SDRV_DMA_TRIGGER_BY_GTIMER</a>
, <a class="el" href="sdrv__dma_8h.html#a95f065bec1af860620ef897fec9f868da33fb2e286ec68f703f1add3cd90d019f">SDRV_DMA_TRIGGER_BY_INTERNAL_EVENT</a>
, <a class="el" href="sdrv__dma_8h.html#a95f065bec1af860620ef897fec9f868dab346bf001ffd8826bb5a998eefbe0deb">SDRV_DMA_TRIGGER_MODE_NOT_DEFINED</a>
}</td></tr>
<tr class="separator:a95f065bec1af860620ef897fec9f868d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3cf1f3daf3f457f629ecdfc46e090308"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a3cf1f3daf3f457f629ecdfc46e090308">sdrv_dma_loop_mode_e</a> { <a class="el" href="sdrv__dma_8h.html#a3cf1f3daf3f457f629ecdfc46e090308a61706395389492b31c66270ea78cede5">SDRV_DMA_LOOP_MODE_0</a> = 0
, <a class="el" href="sdrv__dma_8h.html#a3cf1f3daf3f457f629ecdfc46e090308ab24bf6651a23d78e19d7868ac7759937">SDRV_DMA_LOOP_MODE_1</a>
, <a class="el" href="sdrv__dma_8h.html#a3cf1f3daf3f457f629ecdfc46e090308a203865882173284915f7e80cdd468829">SDRV_DMA_LOOP_MODE_2</a>
, <a class="el" href="sdrv__dma_8h.html#a3cf1f3daf3f457f629ecdfc46e090308aaff8eb75785ea214b214cbc810138962">SDRV_DMA_LOOP_MODE_UNDEFINED</a>
}</td></tr>
<tr class="separator:a3cf1f3daf3f457f629ecdfc46e090308"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:a0769b2cf8a46624d5ff08de34260c3e5"><td class="memItemLeft" align="right" valign="top">static sdrv_dma_channel_ctrl_t *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a0769b2cf8a46624d5ff08de34260c3e5">sdrv_dma_get_channel_ctrl_base</a> (sdrv_dma_ctrl_t *dma_base, <a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a> channel)</td></tr>
<tr class="separator:a0769b2cf8a46624d5ff08de34260c3e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab413862cd6d6458fd6e69224046a764c"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#ab413862cd6d6458fd6e69224046a764c">sdrv_dma_set_channel_sw_handshake</a> (sdrv_dma_channel_ctrl_t *channel_base)</td></tr>
<tr class="separator:ab413862cd6d6458fd6e69224046a764c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6811b8a5b31e4739ad1a873f8b9d8905"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a6811b8a5b31e4739ad1a873f8b9d8905">sdrv_dma_set_channel_muxid</a> (sdrv_dma_ctrl_t *dma_base, <a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a> channel, uint32_t mux_id)</td></tr>
<tr class="separator:a6811b8a5b31e4739ad1a873f8b9d8905"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a33ab3ea9936f909332aa5bd978144c68"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a33ab3ea9936f909332aa5bd978144c68">sdrv_dma_set_channel_rd_outstanding</a> (sdrv_dma_ctrl_t *dma_base, <a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a> channel, uint8_t value)</td></tr>
<tr class="separator:a33ab3ea9936f909332aa5bd978144c68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1782ff45df981ebedd5d19992ce28877"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a1782ff45df981ebedd5d19992ce28877">sdrv_dma_set_channel_wr_outstanding</a> (sdrv_dma_ctrl_t *dma_base, <a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a> channel, uint8_t value)</td></tr>
<tr class="separator:a1782ff45df981ebedd5d19992ce28877"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acbc275d6a1aca65b02f3fbaa7203a3a5"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#acbc275d6a1aca65b02f3fbaa7203a3a5">sdrv_dma_set_channel_interrupt</a> (sdrv_dma_ctrl_t *dma_base, <a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a> channel, uint32_t int_type)</td></tr>
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<tr class="memitem:aaef77aa516fa3f6943fa0f6b53780328"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#aaef77aa516fa3f6943fa0f6b53780328">sdrv_dma_reset_core_int_status</a> (sdrv_dma_ctrl_t *dma_base)</td></tr>
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<tr class="memitem:a9bc1511949ac434e7fdf0e8ea9b5d64a"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a9bc1511949ac434e7fdf0e8ea9b5d64a">sdrv_dma_reset_fifo</a> (sdrv_dma_ctrl_t *dma_base)</td></tr>
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<tr class="memitem:a8d33970d5cfb77c4f3245f5079d4c3d6"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a8d33970d5cfb77c4f3245f5079d4c3d6">sdrv_dma_set_channel_status</a> (sdrv_dma_channel_ctrl_t *channel_base, <a class="el" href="sdrv__dma_8h.html#a5ddef98910f9d3c31eb47b9412ecacad">sdrv_dma_channel_status_e</a> status)</td></tr>
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<tr class="memitem:a642196ea4807fd0796de61e7462fd4d8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a642196ea4807fd0796de61e7462fd4d8">sdrv_dma_init_dmac</a> (paddr_t base)</td></tr>
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<tr class="memitem:a53415ae94875eb7a9cfe6a539af15d13"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a53415ae94875eb7a9cfe6a539af15d13">sdrv_dma_create_instance</a> (<a class="el" href="sdrv__dma_8h.html#a8398793befd907d68bc1b103b1ea1080">sdrv_dma_t</a> *dma_instance, paddr_t base)</td></tr>
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<tr class="memitem:a76b0a9d46747a4c58e2d6a4ac19ada6a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a76b0a9d46747a4c58e2d6a4ac19ada6a">sdrv_dma_init_channel_config</a> (<a class="el" href="structsdrv__dma__channel__config__t.html">sdrv_dma_channel_config_t</a> *config, <a class="el" href="sdrv__dma_8h.html#a8398793befd907d68bc1b103b1ea1080">sdrv_dma_t</a> *instance)</td></tr>
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<tr class="memitem:a8a5b09a2f169ee6f98e473b1c9c9cf9d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a8a5b09a2f169ee6f98e473b1c9c9cf9d">sdrv_dma_start_channel_xfer</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel)</td></tr>
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<tr class="memitem:a664d4c43d2a51621fbf6827be1062b1a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a664d4c43d2a51621fbf6827be1062b1a">sdrv_dma_stop_channel_xfer</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel)</td></tr>
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<tr class="memitem:a79fb8756fe873971ff572f3581d63379"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a79fb8756fe873971ff572f3581d63379">sdrv_dma_deinit_channel</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel)</td></tr>
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<tr class="memitem:aa74d7fc7a132808a8b38f2a488ec4c37"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#aa74d7fc7a132808a8b38f2a488ec4c37">sdrv_dma_init_linklist_entry</a> (<a class="el" href="structsdrv__dma__linklist__descriptor__t.html">sdrv_dma_linklist_descriptor_t</a> *desc, const <a class="el" href="structsdrv__dma__channel__config__t.html">sdrv_dma_channel_config_t</a> *config)</td></tr>
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<tr class="memitem:af952d929924cbc31db48a7e206b92c12"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#af952d929924cbc31db48a7e206b92c12">sdrv_dma_set_channel_source_address</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel, paddr_t addr)</td></tr>
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<tr class="memitem:a65c810929e6c7bf83c4e26e477d0258e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a65c810929e6c7bf83c4e26e477d0258e">sdrv_dma_set_channel_buffer_size</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel, <a class="el" href="sdrv__dma_8h.html#a3cf1f3daf3f457f629ecdfc46e090308">sdrv_dma_loop_mode_e</a> loop_mode, uint32_t total_size, uint32_t loop_size)</td></tr>
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<tr class="memitem:a5fb1b55ece25615724899d39565af6fa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a5fb1b55ece25615724899d39565af6fa">sdrv_dma_set_channel_destination_address</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel, paddr_t addr)</td></tr>
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<tr class="memitem:aa129ff50ec15717672116fcddab70f0d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#aa129ff50ec15717672116fcddab70f0d">sdrv_dma_set_channel_xfer_bytes</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel, uint32_t xfer_bytes)</td></tr>
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<tr class="memitem:a5ca69e4d9b16835f3b8369735829ca85"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a5ca69e4d9b16835f3b8369735829ca85">sdrv_dma_get_channel_xfer_bytes</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel)</td></tr>
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<tr class="memitem:a2e6749b66c137ff539d2d57c5f77eb19"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a2e6749b66c137ff539d2d57c5f77eb19">sdrv_dma_clear_channel_xfer_bytes</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel)</td></tr>
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<tr class="memitem:ad20111dc252dd711bdd54dfb7637cd47"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#ad20111dc252dd711bdd54dfb7637cd47">sdrv_dma_get_channel_xfer_status</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel)</td></tr>
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<tr class="memitem:a1ad1ffa7c9f117d0200822d1679f88b8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__dma_8h.html#a1ad1ffa7c9f117d0200822d1679f88b8">sdrv_dma_clear_channel_xfer_status</a> (<a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *channel, uint32_t status)</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><dl class="section copyright"><dt>Copyright</dt><dd>Copyright (c) 2022 Semidrive Semiconductor. All rights reserved. </dd></dl>
</div><h2 class="groupheader">Macro Definition Documentation</h2>
<a id="a04db1df3e488ae54403a856ec87f49f8" name="a04db1df3e488ae54403a856ec87f49f8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a04db1df3e488ae54403a856ec87f49f8">&#9670;&nbsp;</a></span>SDRV_DMA_LIMIT_TIMES</h2>
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<td class="memname">#define SDRV_DMA_LIMIT_TIMES&#160;&#160;&#160;5</td>
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<a id="ad50ead6d76663286f1f4f4409057664a" name="ad50ead6d76663286f1f4f4409057664a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad50ead6d76663286f1f4f4409057664a">&#9670;&nbsp;</a></span>SDRV_DMA_LP0_LPSIZE_MAX</h2>
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<td class="memname">#define SDRV_DMA_LP0_LPSIZE_MAX&#160;&#160;&#160;(0x00FFFFFF)</td>
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<a id="a45a0cb3f4621fce1db786e2a14073f62" name="a45a0cb3f4621fce1db786e2a14073f62"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a45a0cb3f4621fce1db786e2a14073f62">&#9670;&nbsp;</a></span>SDRV_DMA_LP1_LP_COUNT_MAX</h2>
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<td class="memname">#define SDRV_DMA_LP1_LP_COUNT_MAX&#160;&#160;&#160;(0X00000FFF)</td>
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<a id="a106e91e6eb4d40c8e3bc86c47d003271" name="a106e91e6eb4d40c8e3bc86c47d003271"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a106e91e6eb4d40c8e3bc86c47d003271">&#9670;&nbsp;</a></span>SDRV_DMA_LP1_LPSIZE_MAX</h2>
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<td class="memname">#define SDRV_DMA_LP1_LPSIZE_MAX&#160;&#160;&#160;(0X00000FFF)</td>
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<a id="a35fc8605113b3eaf681e0ef34d2157ae" name="a35fc8605113b3eaf681e0ef34d2157ae"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a35fc8605113b3eaf681e0ef34d2157ae">&#9670;&nbsp;</a></span>SDRV_DMA_LP2_LPSIZE</h2>
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<td class="memname">#define SDRV_DMA_LP2_LPSIZE</td>
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<td class="paramname">n</td><td>)</td>
<td>&#160;&#160;&#160;((__builtin_ffs(n) - 1) &amp; 0xf)</td>
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<a id="a4803d96ddba9bf13bef8ecfbd56b956c" name="a4803d96ddba9bf13bef8ecfbd56b956c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4803d96ddba9bf13bef8ecfbd56b956c">&#9670;&nbsp;</a></span>SDRV_DMA_LP2_LPSIZE_MAX</h2>
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<td class="memname">#define SDRV_DMA_LP2_LPSIZE_MAX&#160;&#160;&#160;(0x000FFFFF)</td>
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<a id="a0e2556f402bf76e52ccbf77bb0032884" name="a0e2556f402bf76e52ccbf77bb0032884"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0e2556f402bf76e52ccbf77bb0032884">&#9670;&nbsp;</a></span>SDRV_DMA_LP2_TT</h2>
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<td class="memname">#define SDRV_DMA_LP2_TT</td>
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<td>&#160;&#160;&#160;((((n)-1) &lt;&lt; 4) &amp; 0xfffff0)</td>
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<a id="a1485cc7acb50cb6ec3031ac3a48bc983" name="a1485cc7acb50cb6ec3031ac3a48bc983"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1485cc7acb50cb6ec3031ac3a48bc983">&#9670;&nbsp;</a></span>SDRV_DMA_MAD_CRC_REGISTERS</h2>
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<td class="memname">#define SDRV_DMA_MAD_CRC_REGISTERS&#160;&#160;&#160;(7)</td>
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<h2 class="groupheader">Typedef Documentation</h2>
<a id="a5ba1acf987c7f47c922ec6cf8e203ee3" name="a5ba1acf987c7f47c922ec6cf8e203ee3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5ba1acf987c7f47c922ec6cf8e203ee3">&#9670;&nbsp;</a></span>sdrv_dma_irq_handler</h2>
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<td class="memname">typedef void(* sdrv_dma_irq_handler) (uint32_t status, uint32_t param, void *context)</td>
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<p>DMA channel interrupt callback type. </p>
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<a id="a8398793befd907d68bc1b103b1ea1080" name="a8398793befd907d68bc1b103b1ea1080"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8398793befd907d68bc1b103b1ea1080">&#9670;&nbsp;</a></span>sdrv_dma_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__dma.html">sdrv_dma</a> <a class="el" href="sdrv__dma_8h.html#a8398793befd907d68bc1b103b1ea1080">sdrv_dma_t</a></td>
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<p>DMA controller structure. </p>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
<a id="a7ff5f2dff38e7639981794c43dc9167b" name="a7ff5f2dff38e7639981794c43dc9167b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7ff5f2dff38e7639981794c43dc9167b">&#9670;&nbsp;</a></span>anonymous enum</h2>
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<td class="memname">anonymous enum</td>
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<p>DMA status return code. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a7ff5f2dff38e7639981794c43dc9167ba0e9b34db72ae60462ae79f54054a0504" name="a7ff5f2dff38e7639981794c43dc9167ba0e9b34db72ae60462ae79f54054a0504"></a>SDRV_DMA_INVALID_CHANNEL_ID&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a7ff5f2dff38e7639981794c43dc9167ba65b714d8fe9970fc610f75d9afdcaee6" name="a7ff5f2dff38e7639981794c43dc9167ba65b714d8fe9970fc610f75d9afdcaee6"></a>SDRV_DMA_UNSUPPORT_CONFIG&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a7ff5f2dff38e7639981794c43dc9167ba9e5c273955437cce7541196f72647fe4" name="a7ff5f2dff38e7639981794c43dc9167ba9e5c273955437cce7541196f72647fe4"></a>SDRV_DMA_INVALID_MUXID&#160;</td><td class="fielddoc"></td></tr>
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<a id="a6389d60619bc0fbbb010f89c29036927" name="a6389d60619bc0fbbb010f89c29036927"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6389d60619bc0fbbb010f89c29036927">&#9670;&nbsp;</a></span>sdrv_dma_addr_inc_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a6389d60619bc0fbbb010f89c29036927">sdrv_dma_addr_inc_e</a></td>
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<p>DMA channel transfer address increase mode. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a6389d60619bc0fbbb010f89c29036927a3d3e3b2e316859db827b5ea90bc2d7d3" name="a6389d60619bc0fbbb010f89c29036927a3d3e3b2e316859db827b5ea90bc2d7d3"></a>SDRV_DMA_ADDR_INC&#160;</td><td class="fielddoc"><p >Automatically increase DMA source or target address after each transaction, usually for memory buffers. Do not increase DMA source or target address after each transaction, usually for device registers. </p>
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<tr><td class="fieldname"><a id="a6389d60619bc0fbbb010f89c29036927ad9d93331d2cc81b0b55347f9c5855a08" name="a6389d60619bc0fbbb010f89c29036927ad9d93331d2cc81b0b55347f9c5855a08"></a>SDRV_DMA_ADDR_NO_INC&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#af223f52b0b99738e3384a3c1f7a3d526">&#9670;&nbsp;</a></span>sdrv_dma_buffer_mode_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#af223f52b0b99738e3384a3c1f7a3d526">sdrv_dma_buffer_mode_e</a></td>
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<p>The buffer mode used by different application scenarios. </p>
<p >MAD (Memory access description) - one transaction configuration include source address, target address,transfer mode,transfer length,link address,etc..</p>
<p >Buffer mode is related to transfer mode and loop mode (For details see sdrv_dma_loop_mode_e), when Single Mode selected,buffer mode should be set to SINGLE_BUFFER or 2D_BUFFER. when Continuous Mode selected,buffer mode should be set to DOUBLE_BUFFER or CIRCULAR_BUFFER. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="af223f52b0b99738e3384a3c1f7a3d526a155c233259f836182437726b0c3ba3ce" name="af223f52b0b99738e3384a3c1f7a3d526a155c233259f836182437726b0c3ba3ce"></a>SDRV_DMA_SINGLE_BUFFER&#160;</td><td class="fielddoc"><p >single buffer should be used with Single Mode. When the entire length data is transferred, DMA is terminated. double buffer should be used with Continuous Mode. DMA need two memory areas (IRAM, SDRAM), one memory address is filled in source address of MAD and the another is filled in link address of MAD. When one memory area is transferred,the another continues to be transferred.</p>
<p >Set STATUS_ABORT or STATUS_STOP if you want to terminate DMA transfer. </p>
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<tr><td class="fieldname"><a id="af223f52b0b99738e3384a3c1f7a3d526aafb62d240365677f9b33ccfacdf1b63d" name="af223f52b0b99738e3384a3c1f7a3d526aafb62d240365677f9b33ccfacdf1b63d"></a>SDRV_DMA_DOUBLE_BUFFER&#160;</td><td class="fielddoc"><p >circular buffer should be used with Continuous Mode. When the entire length data is transferred, DMA will continue to transfer from source address of MAD.</p>
<p >Set STATUS_ABORT or STATUS_STOP if you want to terminate DMA transfer. </p>
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<tr><td class="fieldname"><a id="af223f52b0b99738e3384a3c1f7a3d526a54d0d041c6399e93a1fb7d3b998bfc3a" name="af223f52b0b99738e3384a3c1f7a3d526a54d0d041c6399e93a1fb7d3b998bfc3a"></a>SDRV_DMA_CIRCULAR_BUFFER&#160;</td><td class="fielddoc"><p >2d buffer is similar to single buffer. The difference is that the entire length data can be transmitted at one handshake request regardless of LOOP_MODE_x. (For details see sdrv_dma_loop_mode_e) </p>
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<tr><td class="fieldname"><a id="af223f52b0b99738e3384a3c1f7a3d526aaf53df30ad90b12870a79be85a3a4c40" name="af223f52b0b99738e3384a3c1f7a3d526aaf53df30ad90b12870a79be85a3a4c40"></a>SDRV_DMA_2D_BUFFER&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="af223f52b0b99738e3384a3c1f7a3d526a2a7d052b57d12079c62100a55de4415e" name="af223f52b0b99738e3384a3c1f7a3d526a2a7d052b57d12079c62100a55de4415e"></a>SDRV_DMA_BUFFER_NOT_DEFINED&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a7ce59be117b706c31d9a07dbb9e88839">&#9670;&nbsp;</a></span>sdrv_dma_burst_len_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a7ce59be117b706c31d9a07dbb9e88839">sdrv_dma_burst_len_e</a></td>
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<p>DMA channel burst length for each transaction. </p>
<p >This is actually the burst length, i.e. AXI AWLEN and ARLEN,for DMA burst transactions. for peripheral transactions,you should set burst length according to peripheral FIFO LEVEL. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a7b89b41973b790926f7cafd71875d033" name="a7ce59be117b706c31d9a07dbb9e88839a7b89b41973b790926f7cafd71875d033"></a>SDRV_DMA_BURST_LEN_1&#160;</td><td class="fielddoc"><p >1 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a97a6342a884f90746227d0f67cc26e8b" name="a7ce59be117b706c31d9a07dbb9e88839a97a6342a884f90746227d0f67cc26e8b"></a>SDRV_DMA_BURST_LEN_2&#160;</td><td class="fielddoc"><p >2 x bus_width per transaction </p>
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<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a59ccacaf17ca77444636b785bee8ca15" name="a7ce59be117b706c31d9a07dbb9e88839a59ccacaf17ca77444636b785bee8ca15"></a>SDRV_DMA_BURST_LEN_3&#160;</td><td class="fielddoc"><p >3 x bus_width per transaction </p>
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<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a94386d5df4088c3568e630ef7d3f77a1" name="a7ce59be117b706c31d9a07dbb9e88839a94386d5df4088c3568e630ef7d3f77a1"></a>SDRV_DMA_BURST_LEN_4&#160;</td><td class="fielddoc"><p >4 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839ae51f7c8805d36cb72a8bcebbf322e63f" name="a7ce59be117b706c31d9a07dbb9e88839ae51f7c8805d36cb72a8bcebbf322e63f"></a>SDRV_DMA_BURST_LEN_5&#160;</td><td class="fielddoc"><p >5 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a357710059f2a94e4bcb2e2e6b957a431" name="a7ce59be117b706c31d9a07dbb9e88839a357710059f2a94e4bcb2e2e6b957a431"></a>SDRV_DMA_BURST_LEN_6&#160;</td><td class="fielddoc"><p >6 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a09b39a5dc7c9ae6f5050c4402719bf6c" name="a7ce59be117b706c31d9a07dbb9e88839a09b39a5dc7c9ae6f5050c4402719bf6c"></a>SDRV_DMA_BURST_LEN_7&#160;</td><td class="fielddoc"><p >7 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a6c02d47a25bee28570205a1fbda8f936" name="a7ce59be117b706c31d9a07dbb9e88839a6c02d47a25bee28570205a1fbda8f936"></a>SDRV_DMA_BURST_LEN_8&#160;</td><td class="fielddoc"><p >8 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a79b507f0dd447063530baeb28bffb90a" name="a7ce59be117b706c31d9a07dbb9e88839a79b507f0dd447063530baeb28bffb90a"></a>SDRV_DMA_BURST_LEN_9&#160;</td><td class="fielddoc"><p >9 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839ab4d1bc8ba573ac61664435bce1f30efc" name="a7ce59be117b706c31d9a07dbb9e88839ab4d1bc8ba573ac61664435bce1f30efc"></a>SDRV_DMA_BURST_LEN_10&#160;</td><td class="fielddoc"><p >10 x bus_width per transaction </p>
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<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839afc8199130fb10a9a0d6d0ec2b5da4f92" name="a7ce59be117b706c31d9a07dbb9e88839afc8199130fb10a9a0d6d0ec2b5da4f92"></a>SDRV_DMA_BURST_LEN_11&#160;</td><td class="fielddoc"><p >11 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a7e6ddc568b2d8d0bb6be9c22dd093389" name="a7ce59be117b706c31d9a07dbb9e88839a7e6ddc568b2d8d0bb6be9c22dd093389"></a>SDRV_DMA_BURST_LEN_12&#160;</td><td class="fielddoc"><p >12 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a3495a52eaf56c1f24acf2dd761245150" name="a7ce59be117b706c31d9a07dbb9e88839a3495a52eaf56c1f24acf2dd761245150"></a>SDRV_DMA_BURST_LEN_13&#160;</td><td class="fielddoc"><p >13 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a5ec646f7fe03293f9f519e1939290adc" name="a7ce59be117b706c31d9a07dbb9e88839a5ec646f7fe03293f9f519e1939290adc"></a>SDRV_DMA_BURST_LEN_14&#160;</td><td class="fielddoc"><p >14 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839afd771903388b3894dd2e194b9c4cbc8a" name="a7ce59be117b706c31d9a07dbb9e88839afd771903388b3894dd2e194b9c4cbc8a"></a>SDRV_DMA_BURST_LEN_15&#160;</td><td class="fielddoc"><p >15 x bus_width per transaction </p>
</td></tr>
<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839ac915d715fbf35b6a06ee325c50f99e49" name="a7ce59be117b706c31d9a07dbb9e88839ac915d715fbf35b6a06ee325c50f99e49"></a>SDRV_DMA_BURST_LEN_16&#160;</td><td class="fielddoc"><p >16 x bus_width per transaction </p>
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<tr><td class="fieldname"><a id="a7ce59be117b706c31d9a07dbb9e88839a89db44b757f4ecf2119a13e6dbc19010" name="a7ce59be117b706c31d9a07dbb9e88839a89db44b757f4ecf2119a13e6dbc19010"></a>SDRV_DMA_BURST_LEN_UNDEFINED&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a274159adbb399be5ca569555c1b39aab">&#9670;&nbsp;</a></span>sdrv_dma_bus_width_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a274159adbb399be5ca569555c1b39aab">sdrv_dma_bus_width_e</a></td>
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<p>DMA channel data width for each transaction. </p>
<p >This is actually the burst size, i.e., AXI AWSIZE and ARSIZE, for DMA transactions. For memory to memory transactions, use 8 bytes width to get better throughput. However for peripheral transactions, you should set bus width according to hardware register data width. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a274159adbb399be5ca569555c1b39aaba64edfb6c20d4c1dd369b8cccf5f762ae" name="a274159adbb399be5ca569555c1b39aaba64edfb6c20d4c1dd369b8cccf5f762ae"></a>SDRV_DMA_BUSWIDTH_1_BYTE&#160;</td><td class="fielddoc"><p >1 byte per transaction </p>
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<tr><td class="fieldname"><a id="a274159adbb399be5ca569555c1b39aababbea627f8f03a6081436f5e3c93357db" name="a274159adbb399be5ca569555c1b39aababbea627f8f03a6081436f5e3c93357db"></a>SDRV_DMA_BUSWIDTH_2_BYTES&#160;</td><td class="fielddoc"><p >2 bytes per transaction </p>
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<tr><td class="fieldname"><a id="a274159adbb399be5ca569555c1b39aaba61a990c895acfe0d73a0ce6201a6842d" name="a274159adbb399be5ca569555c1b39aaba61a990c895acfe0d73a0ce6201a6842d"></a>SDRV_DMA_BUSWIDTH_4_BYTES&#160;</td><td class="fielddoc"><p >4 bytes per transaction </p>
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<tr><td class="fieldname"><a id="a274159adbb399be5ca569555c1b39aaba124c119c33bdb51dcc0fc9b6e6f577a8" name="a274159adbb399be5ca569555c1b39aaba124c119c33bdb51dcc0fc9b6e6f577a8"></a>SDRV_DMA_BUSWIDTH_8_BYTES&#160;</td><td class="fielddoc"><p >8 bytes per transaction </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a2fce8b449dfda53bb26afae8dea00c9f">&#9670;&nbsp;</a></span>sdrv_dma_channel_id_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a></td>
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<p>DMA Channel ID. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9facba77036c540f238fb431e40ad01324b" name="a2fce8b449dfda53bb26afae8dea00c9facba77036c540f238fb431e40ad01324b"></a>SDRV_DMA_CHANNEL_INVALID&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa315f948a01daa968be8cc27a70d984fe" name="a2fce8b449dfda53bb26afae8dea00c9fa315f948a01daa968be8cc27a70d984fe"></a>SDRV_DMA_CHANNEL_0&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fad3d70129d5540bc93c3b4292232af17e" name="a2fce8b449dfda53bb26afae8dea00c9fad3d70129d5540bc93c3b4292232af17e"></a>SDRV_DMA_CHANNEL_1&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9faf7e7ed724ae3e91f6252743ced39b7fd" name="a2fce8b449dfda53bb26afae8dea00c9faf7e7ed724ae3e91f6252743ced39b7fd"></a>SDRV_DMA_CHANNEL_2&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9facd2e9f59b3e70fba4d2eb094a15fc8f9" name="a2fce8b449dfda53bb26afae8dea00c9facd2e9f59b3e70fba4d2eb094a15fc8f9"></a>SDRV_DMA_CHANNEL_3&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa9282886c11108fa42af2495e0f292f73" name="a2fce8b449dfda53bb26afae8dea00c9fa9282886c11108fa42af2495e0f292f73"></a>SDRV_DMA_CHANNEL_4&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa51d18e98fc85a815c8007eafcae215cc" name="a2fce8b449dfda53bb26afae8dea00c9fa51d18e98fc85a815c8007eafcae215cc"></a>SDRV_DMA_CHANNEL_5&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa7fdd13052192fbb777f57669604e92b2" name="a2fce8b449dfda53bb26afae8dea00c9fa7fdd13052192fbb777f57669604e92b2"></a>SDRV_DMA_CHANNEL_6&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa18f360d584bd38c658a70f3250f0625c" name="a2fce8b449dfda53bb26afae8dea00c9fa18f360d584bd38c658a70f3250f0625c"></a>SDRV_DMA_CHANNEL_7&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fae73fcfac5d39c8fc467205805e4cc52e" name="a2fce8b449dfda53bb26afae8dea00c9fae73fcfac5d39c8fc467205805e4cc52e"></a>SDRV_DMA_CHANNEL_8&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa0bb084f01b21c6f0c45699e6b7fe2e14" name="a2fce8b449dfda53bb26afae8dea00c9fa0bb084f01b21c6f0c45699e6b7fe2e14"></a>SDRV_DMA_CHANNEL_9&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fac279163937e0588408b4371eae79269f" name="a2fce8b449dfda53bb26afae8dea00c9fac279163937e0588408b4371eae79269f"></a>SDRV_DMA_CHANNEL_10&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9faf57c3300d58834c8e9795579de786f1f" name="a2fce8b449dfda53bb26afae8dea00c9faf57c3300d58834c8e9795579de786f1f"></a>SDRV_DMA_CHANNEL_11&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa7721384621f73ebc20665d5a114bfa9a" name="a2fce8b449dfda53bb26afae8dea00c9fa7721384621f73ebc20665d5a114bfa9a"></a>SDRV_DMA_CHANNEL_12&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fad14585544383b47f237034b1751fd288" name="a2fce8b449dfda53bb26afae8dea00c9fad14585544383b47f237034b1751fd288"></a>SDRV_DMA_CHANNEL_13&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa8e6f58358b70257cb10e9a38912df0ba" name="a2fce8b449dfda53bb26afae8dea00c9fa8e6f58358b70257cb10e9a38912df0ba"></a>SDRV_DMA_CHANNEL_14&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa5100c5794a6a967d457070f30418a544" name="a2fce8b449dfda53bb26afae8dea00c9fa5100c5794a6a967d457070f30418a544"></a>SDRV_DMA_CHANNEL_15&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa5335d3b85db9d9393a9bf1c8d051a2db" name="a2fce8b449dfda53bb26afae8dea00c9fa5335d3b85db9d9393a9bf1c8d051a2db"></a>SDRV_DMA_CHANNEL_16&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa99c0855ed705fe7cd733bf5e3f419279" name="a2fce8b449dfda53bb26afae8dea00c9fa99c0855ed705fe7cd733bf5e3f419279"></a>SDRV_DMA_CHANNEL_17&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa7f98d466d5e932ae19706d3d3451f923" name="a2fce8b449dfda53bb26afae8dea00c9fa7f98d466d5e932ae19706d3d3451f923"></a>SDRV_DMA_CHANNEL_18&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fada8b1a8996a2d79889b9cacfa93e53e8" name="a2fce8b449dfda53bb26afae8dea00c9fada8b1a8996a2d79889b9cacfa93e53e8"></a>SDRV_DMA_CHANNEL_19&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fad5ad56d6d2e6e17fe9a0b3e30631da50" name="a2fce8b449dfda53bb26afae8dea00c9fad5ad56d6d2e6e17fe9a0b3e30631da50"></a>SDRV_DMA_CHANNEL_20&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa6f9bf72d73b397074fda203c0df41621" name="a2fce8b449dfda53bb26afae8dea00c9fa6f9bf72d73b397074fda203c0df41621"></a>SDRV_DMA_CHANNEL_21&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa248e83d2cdd9ad0b58b146791de7a308" name="a2fce8b449dfda53bb26afae8dea00c9fa248e83d2cdd9ad0b58b146791de7a308"></a>SDRV_DMA_CHANNEL_22&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a2fce8b449dfda53bb26afae8dea00c9fa519e0f498b248717ce0649aedd2ddf3f" name="a2fce8b449dfda53bb26afae8dea00c9fa519e0f498b248717ce0649aedd2ddf3f"></a>SDRV_DMA_CHANNEL_23&#160;</td><td class="fielddoc"></td></tr>
</table>
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<h2 class="memtitle"><span class="permalink"><a href="#a5ddef98910f9d3c31eb47b9412ecacad">&#9670;&nbsp;</a></span>sdrv_dma_channel_status_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a5ddef98910f9d3c31eb47b9412ecacad">sdrv_dma_channel_status_e</a></td>
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<p>DMA channel current status. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a5ddef98910f9d3c31eb47b9412ecacadac30bbd3ee811ae53844b6ed3f7faa9bf" name="a5ddef98910f9d3c31eb47b9412ecacadac30bbd3ee811ae53844b6ed3f7faa9bf"></a>SDRV_DMA_CH_STATUS_STOP&#160;</td><td class="fielddoc"><p >transfer stopped </p>
</td></tr>
<tr><td class="fieldname"><a id="a5ddef98910f9d3c31eb47b9412ecacadacebffaad5c71b547cd6af59d59df8c29" name="a5ddef98910f9d3c31eb47b9412ecacadacebffaad5c71b547cd6af59d59df8c29"></a>SDRV_DMA_CH_STATUS_FLUSH&#160;</td><td class="fielddoc"><p >next MAD config executed directly </p>
</td></tr>
<tr><td class="fieldname"><a id="a5ddef98910f9d3c31eb47b9412ecacada99d0aa63f56745c66916731c10285de7" name="a5ddef98910f9d3c31eb47b9412ecacada99d0aa63f56745c66916731c10285de7"></a>SDRV_DMA_CH_STATUS_REQ_FLUSH&#160;</td><td class="fielddoc"><p >periphal handshake request cleared </p>
</td></tr>
<tr><td class="fieldname"><a id="a5ddef98910f9d3c31eb47b9412ecacada9e86a22a0a56193ffb0c70cf344e0ca7" name="a5ddef98910f9d3c31eb47b9412ecacada9e86a22a0a56193ffb0c70cf344e0ca7"></a>SDRV_DMA_CH_STATUS_HALT&#160;</td><td class="fielddoc"><p >transfer halted </p>
</td></tr>
<tr><td class="fieldname"><a id="a5ddef98910f9d3c31eb47b9412ecacada8e84d2a1af8d004906b6ceea95a2f190" name="a5ddef98910f9d3c31eb47b9412ecacada8e84d2a1af8d004906b6ceea95a2f190"></a>SDRV_DMA_CH_STATUS_ENABLE&#160;</td><td class="fielddoc"><p >transfer enabled </p>
</td></tr>
<tr><td class="fieldname"><a id="a5ddef98910f9d3c31eb47b9412ecacadaaabf85ef153ec93f8b901c5bcb1e163b" name="a5ddef98910f9d3c31eb47b9412ecacadaaabf85ef153ec93f8b901c5bcb1e163b"></a>SDRV_DMA_CH_STATUS_RESUME&#160;</td><td class="fielddoc"><p >transfer resumed </p>
</td></tr>
<tr><td class="fieldname"><a id="a5ddef98910f9d3c31eb47b9412ecacada28764c9c8e56e5ac91360d338b001e8a" name="a5ddef98910f9d3c31eb47b9412ecacada28764c9c8e56e5ac91360d338b001e8a"></a>SDRV_DMA_CH_STATUS_ABORT&#160;</td><td class="fielddoc"><p >transfer aborted </p>
</td></tr>
</table>
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<h2 class="memtitle"><span class="permalink"><a href="#a5e6c428b85fecb624b8d7aa49cff5673">&#9670;&nbsp;</a></span>sdrv_dma_channle_ctrl_fsm_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a5e6c428b85fecb624b8d7aa49cff5673">sdrv_dma_channle_ctrl_fsm_e</a></td>
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<p>DMA channel control state machine status. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a5e6c428b85fecb624b8d7aa49cff5673aa6c49055fbd9acc442cf23c8fbbb5398" name="a5e6c428b85fecb624b8d7aa49cff5673aa6c49055fbd9acc442cf23c8fbbb5398"></a>SDRV_DMA_CH_FSM_IDLE&#160;</td><td class="fielddoc"><p >DMA channel idle state </p>
</td></tr>
<tr><td class="fieldname"><a id="a5e6c428b85fecb624b8d7aa49cff5673acd0f5b4adf1589352ac99e906c262100" name="a5e6c428b85fecb624b8d7aa49cff5673acd0f5b4adf1589352ac99e906c262100"></a>SDRV_DMA_CH_FSM_MAD_CHECK&#160;</td><td class="fielddoc"><p >DMA channel mad check state </p>
</td></tr>
<tr><td class="fieldname"><a id="a5e6c428b85fecb624b8d7aa49cff5673ad5a2e1671b4c4279f21847afa1acf0ec" name="a5e6c428b85fecb624b8d7aa49cff5673ad5a2e1671b4c4279f21847afa1acf0ec"></a>SDRV_DMA_CH_FSM_POLL_OPD2&#160;</td><td class="fielddoc"><p >DMA channel poll opd2 state </p>
</td></tr>
<tr><td class="fieldname"><a id="a5e6c428b85fecb624b8d7aa49cff5673a6db1e25f36c7cac1bd35dbe55f11da19" name="a5e6c428b85fecb624b8d7aa49cff5673a6db1e25f36c7cac1bd35dbe55f11da19"></a>SDRV_DMA_CH_FSM_DATA_TRANSFER&#160;</td><td class="fielddoc"><p >DMA channel data_transfer state </p>
</td></tr>
<tr><td class="fieldname"><a id="a5e6c428b85fecb624b8d7aa49cff5673aff72b3b2644a8b59d8f6d17ac4c76099" name="a5e6c428b85fecb624b8d7aa49cff5673aff72b3b2644a8b59d8f6d17ac4c76099"></a>SDRV_DMA_CH_FSM_STOP&#160;</td><td class="fielddoc"><p >DMA channel stop state </p>
</td></tr>
<tr><td class="fieldname"><a id="a5e6c428b85fecb624b8d7aa49cff5673a102f915ceadddb2760ede0f26bf594ff" name="a5e6c428b85fecb624b8d7aa49cff5673a102f915ceadddb2760ede0f26bf594ff"></a>SDRV_DMA_CH_FSM_HALT&#160;</td><td class="fielddoc"><p >DMA channel halt state </p>
</td></tr>
<tr><td class="fieldname"><a id="a5e6c428b85fecb624b8d7aa49cff5673a9e348bdf14ef7dcd2eea1c398dcc6774" name="a5e6c428b85fecb624b8d7aa49cff5673a9e348bdf14ef7dcd2eea1c398dcc6774"></a>SDRV_DMA_CH_FSM_DONE&#160;</td><td class="fielddoc"><p >DMA channel done state </p>
</td></tr>
</table>
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<h2 class="memtitle"><span class="permalink"><a href="#a5d5575a82a6c15f0fbe010542041ff93">&#9670;&nbsp;</a></span>sdrv_dma_data_crc_mode_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a5d5575a82a6c15f0fbe010542041ff93">sdrv_dma_data_crc_mode_e</a></td>
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<p>DMA Data CRC. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a5d5575a82a6c15f0fbe010542041ff93a2446fe68fbec7034cde28afa7c1a71eb" name="a5d5575a82a6c15f0fbe010542041ff93a2446fe68fbec7034cde28afa7c1a71eb"></a>SDRV_DMA_NO_DATA_CRC&#160;</td><td class="fielddoc"><p >DMA Data crc disable </p>
</td></tr>
<tr><td class="fieldname"><a id="a5d5575a82a6c15f0fbe010542041ff93a8f302e8b05dbb08392ca984b2f0facdf" name="a5d5575a82a6c15f0fbe010542041ff93a8f302e8b05dbb08392ca984b2f0facdf"></a>SDRV_DMA_DATA_CRC_SENSE&#160;</td><td class="fielddoc"><p >DMA Data crc calculated CRC value is stored in OPD </p>
</td></tr>
<tr><td class="fieldname"><a id="a5d5575a82a6c15f0fbe010542041ff93a9fac210c48b405a4b7a61ba324b5735d" name="a5d5575a82a6c15f0fbe010542041ff93a9fac210c48b405a4b7a61ba324b5735d"></a>SDRV_DMA_DATA_CRC_VERIFY_WITH_OPD&#160;</td><td class="fielddoc"><p >DMA Data crc verification with OPD, mismatch CRC verification error interupt is generated </p>
</td></tr>
<tr><td class="fieldname"><a id="a5d5575a82a6c15f0fbe010542041ff93a79bb30b4f8a9e53446f7c694f264711f" name="a5d5575a82a6c15f0fbe010542041ff93a79bb30b4f8a9e53446f7c694f264711f"></a>SDRV_DMA_DATA_CRC_VERIFY_BETWEEN_WR_RD&#160;</td><td class="fielddoc"><p >DMA Data crc verification between writing data and reading data, mismatch CRC verification error interupt is generated </p>
</td></tr>
</table>
</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a0a2c840114bacc40ca37a5c47ae70e32">&#9670;&nbsp;</a></span>sdrv_dma_data_crc_sel_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a0a2c840114bacc40ca37a5c47ae70e32">sdrv_dma_data_crc_sel_e</a></td>
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<p>DMA Data CRC Sel. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a0a2c840114bacc40ca37a5c47ae70e32a0c55dd3333afe59e6ad5478fbfb9954f" name="a0a2c840114bacc40ca37a5c47ae70e32a0c55dd3333afe59e6ad5478fbfb9954f"></a>CRC32_802P3&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a0a2c840114bacc40ca37a5c47ae70e32acdf0c4de024efc53edd374ad22c6da30" name="a0a2c840114bacc40ca37a5c47ae70e32acdf0c4de024efc53edd374ad22c6da30"></a>CRC16_CCITT&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a0a2c840114bacc40ca37a5c47ae70e32ae00c2275c0a5ac47b64c221feadfc3eb" name="a0a2c840114bacc40ca37a5c47ae70e32ae00c2275c0a5ac47b64c221feadfc3eb"></a>CRC8_CCITT&#160;</td><td class="fielddoc"></td></tr>
</table>
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<h2 class="memtitle"><span class="permalink"><a href="#a4fcdf07322430d23f81d47d16e2583db">&#9670;&nbsp;</a></span>sdrv_dma_interrupt_type_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a4fcdf07322430d23f81d47d16e2583db">sdrv_dma_interrupt_type_e</a></td>
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<p>DMA channel interrupt types. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba94ec489a5c7ab5b80161ad6625ea2b1f" name="a4fcdf07322430d23f81d47d16e2583dba94ec489a5c7ab5b80161ad6625ea2b1f"></a>SDRV_DMA_HANDSHAKE_E2E_COR_ERR&#160;</td><td class="fielddoc"><p >DMA Handshake e2e check correctable error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba98518dd24f4bc144436ff485240b9a20" name="a4fcdf07322430d23f81d47d16e2583dba98518dd24f4bc144436ff485240b9a20"></a>SDRV_DMA_HANDSHAKE_E2E_UNCOR_ERR&#160;</td><td class="fielddoc"><p >DMA Handshake e2e check uncorrectable error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba2c78623e887f7e7295f6756169eac21a" name="a4fcdf07322430d23f81d47d16e2583dba2c78623e887f7e7295f6756169eac21a"></a>SDRV_DMA_CHANNEL_FIFO_ECC_COR_ERR&#160;</td><td class="fielddoc"><p >Channel FIFO data ecc check correctable error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba53010e9b28ab72d035f34c4f5c1f2773" name="a4fcdf07322430d23f81d47d16e2583dba53010e9b28ab72d035f34c4f5c1f2773"></a>SDRV_DMA_CHANNEL_FIFO_ECC_UNCOR_ERR&#160;</td><td class="fielddoc"><p >Channel FIFO data ecc check uncorrectable error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dbaba9325a8feb611d3dfa14a2290c7885e" name="a4fcdf07322430d23f81d47d16e2583dbaba9325a8feb611d3dfa14a2290c7885e"></a>SDRV_DMA_AHB_READ_ERR&#160;</td><td class="fielddoc"><p >AHB read response error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba697c7f77b652fe0d6ed95ef509ca8a8f" name="a4fcdf07322430d23f81d47d16e2583dba697c7f77b652fe0d6ed95ef509ca8a8f"></a>SDRV_DMA_AHB_WRITE_ERR&#160;</td><td class="fielddoc"><p >AHB write response error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dbac669bc1b1f5d32b6104060e566d5bf1f" name="a4fcdf07322430d23f81d47d16e2583dbac669bc1b1f5d32b6104060e566d5bf1f"></a>SDRV_DMA_AXI_READ_ERR&#160;</td><td class="fielddoc"><p >AXI read response error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba0923601be51000c1aa8dd107d5033695" name="a4fcdf07322430d23f81d47d16e2583dba0923601be51000c1aa8dd107d5033695"></a>SDRV_DMA_AXI_WRITE_ERR&#160;</td><td class="fielddoc"><p >AXI write response error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba6fec42780ba977f2d5fa784a0a7fbc87" name="a4fcdf07322430d23f81d47d16e2583dba6fec42780ba977f2d5fa784a0a7fbc87"></a>SDRV_DMA_CHANNEL_LINK_ERR&#160;</td><td class="fielddoc"><p >Channel link error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba2c0ce7667860fbefb4b106f2d2b4de8a" name="a4fcdf07322430d23f81d47d16e2583dba2c0ce7667860fbefb4b106f2d2b4de8a"></a>SDRV_DMA_MAD_CRC_ERR&#160;</td><td class="fielddoc"><p >MAD crc error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba580845c17f7fff57bac9576a28c78ca5" name="a4fcdf07322430d23f81d47d16e2583dba580845c17f7fff57bac9576a28c78ca5"></a>SDRV_DMA_FIREWALL_RD_ERR&#160;</td><td class="fielddoc"><p >Firewall protection read error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba0ec29700723336ec01d86e9871a4bacd" name="a4fcdf07322430d23f81d47d16e2583dba0ec29700723336ec01d86e9871a4bacd"></a>SDRV_DMA_FIREWALL_WR_ERR&#160;</td><td class="fielddoc"><p >Firewall protection write error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba8ad4c06352df3b95837a0d139b506d2b" name="a4fcdf07322430d23f81d47d16e2583dba8ad4c06352df3b95837a0d139b506d2b"></a>SDRV_DMA_DATA_CRC_ERR&#160;</td><td class="fielddoc"><p >Data crc error </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba8efc07603d8feda66bc0c454caa41aab" name="a4fcdf07322430d23f81d47d16e2583dba8efc07603d8feda66bc0c454caa41aab"></a>SDRV_DMA_PATTERN_DETECTED&#160;</td><td class="fielddoc"><p >Pattern detected DMA channel all MAD transfer completed </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba22eee2df7977e7625020c8a76bc7acda" name="a4fcdf07322430d23f81d47d16e2583dba22eee2df7977e7625020c8a76bc7acda"></a>SDRV_DMA_LAST_MAD_DONE&#160;</td><td class="fielddoc"><p >DMA channel every MAD transfer completed (actually for Continuous and Liklist mode). </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dbac5e72d83092c26bf282a3d6443e91c86" name="a4fcdf07322430d23f81d47d16e2583dbac5e72d83092c26bf282a3d6443e91c86"></a>SDRV_DMA_EVERY_MAD_DONE&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba39c650254885aaaaf727d213a82341cb" name="a4fcdf07322430d23f81d47d16e2583dba39c650254885aaaaf727d213a82341cb"></a>SDRV_DMA_CH_STOP&#160;</td><td class="fielddoc"><p >DMA channel stop </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba4371e372be8eb61f61eab3dcd39e9037" name="a4fcdf07322430d23f81d47d16e2583dba4371e372be8eb61f61eab3dcd39e9037"></a>SDRV_DMA_CH_FLUSH&#160;</td><td class="fielddoc"><p >DMA channel flush </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba3b615079a816005666a97e57a9ed64bd" name="a4fcdf07322430d23f81d47d16e2583dba3b615079a816005666a97e57a9ed64bd"></a>SDRV_DMA_CH_REQ_FLUSH&#160;</td><td class="fielddoc"><p >DMA channel requst flush DMA channel transfer halted </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dbadc6d1360dbb3da893a304a1cb7525858" name="a4fcdf07322430d23f81d47d16e2583dbadc6d1360dbb3da893a304a1cb7525858"></a>SDRV_DMA_CH_HALT&#160;</td><td class="fielddoc"><p >DMA channel transfer aborted </p>
</td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dbab372a11d91ab61e9586e1239307783f9" name="a4fcdf07322430d23f81d47d16e2583dbab372a11d91ab61e9586e1239307783f9"></a>SDRV_DMA_CH_ABORT&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba30da56f113b0cdf6851c090b6da5bceb" name="a4fcdf07322430d23f81d47d16e2583dba30da56f113b0cdf6851c090b6da5bceb"></a>SDRV_DMA_REQ_TIMEOUT&#160;</td><td class="fielddoc"><p >The handshake request timeout </p>
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<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba1c6412f59ebf7e91038443a7874efe67" name="a4fcdf07322430d23f81d47d16e2583dba1c6412f59ebf7e91038443a7874efe67"></a>SDRV_DMA_SWITCH_EVENT&#160;</td><td class="fielddoc"><p >In the loop mode enable with total size unfixed DMA channel handshake request completed </p>
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<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dbaadbe423a53173ec9f6b53d1cbd9cd9ae" name="a4fcdf07322430d23f81d47d16e2583dbaadbe423a53173ec9f6b53d1cbd9cd9ae"></a>SDRV_DMA_HS_COMP&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba6e94746ec81445e291650abc0b4b0225" name="a4fcdf07322430d23f81d47d16e2583dba6e94746ec81445e291650abc0b4b0225"></a>SDRV_DMA_PATTERN_POLL_MISMACTCH&#160;</td><td class="fielddoc"><p >In the pattern mode with 3'b101 or 3'b110, The pattern status for pattern poll mismatch </p>
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<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dbac70048b2992a65fc943b1304813c3f2c" name="a4fcdf07322430d23f81d47d16e2583dbac70048b2992a65fc943b1304813c3f2c"></a>SDRV_DMA_AXI_OUTSTANDING_UTID_ERR&#160;</td><td class="fielddoc"><p >AXI read or write outstanding UTID error </p>
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<tr><td class="fieldname"><a id="a4fcdf07322430d23f81d47d16e2583dba427886aa00a034ccadb5ff904c3c9ed1" name="a4fcdf07322430d23f81d47d16e2583dba427886aa00a034ccadb5ff904c3c9ed1"></a>SDRV_DMA_PROGRAMING_SEQUENCE_ERR&#160;</td><td class="fielddoc"><p >DMA programing sequence error </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ad007163ad39d5ef99e8dd4f85f390a07">&#9670;&nbsp;</a></span>sdrv_dma_linklist_type_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#ad007163ad39d5ef99e8dd4f85f390a07">sdrv_dma_linklist_type_e</a></td>
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<p>DMA channel linklist mad types. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ad007163ad39d5ef99e8dd4f85f390a07ad9540a3d044f46d901a9e9e1ad1e600d" name="ad007163ad39d5ef99e8dd4f85f390a07ad9540a3d044f46d901a9e9e1ad1e600d"></a>SDRV_DMA_LINKLIST_NORMAL_MAD&#160;</td><td class="fielddoc"><p >DMA channel middle MAD DMA channel first MAD </p>
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<tr><td class="fieldname"><a id="ad007163ad39d5ef99e8dd4f85f390a07a0d538c8d10a3b16834058cf3ce716606" name="ad007163ad39d5ef99e8dd4f85f390a07a0d538c8d10a3b16834058cf3ce716606"></a>SDRV_DMA_LINKLIST_FIRST_MAD&#160;</td><td class="fielddoc"><p >DMA channel last MAD </p>
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<tr><td class="fieldname"><a id="ad007163ad39d5ef99e8dd4f85f390a07a1f5061586f32cf0fb88e1153febb6a0a" name="ad007163ad39d5ef99e8dd4f85f390a07a1f5061586f32cf0fb88e1153febb6a0a"></a>SDRV_DMA_LINKLIST_LAST_MAD&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a3cf1f3daf3f457f629ecdfc46e090308">&#9670;&nbsp;</a></span>sdrv_dma_loop_mode_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a3cf1f3daf3f457f629ecdfc46e090308">sdrv_dma_loop_mode_e</a></td>
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<p>DMA channel transfer data mode in one handshake. </p>
<p >LOOP_MODE_0: when one handshake request, DMA transfers the entire length data then terminated according to MAD. LOOP_MODE_1: DMA transfers the specified length (burst length x bus_width) data through one handshake request. LOOP_MODE_2: DMA transfers the specified length (power of 2) data through one handshake request. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a3cf1f3daf3f457f629ecdfc46e090308a61706395389492b31c66270ea78cede5" name="a3cf1f3daf3f457f629ecdfc46e090308a61706395389492b31c66270ea78cede5"></a>SDRV_DMA_LOOP_MODE_0&#160;</td><td class="fielddoc"><p >entire length data transaction </p>
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<tr><td class="fieldname"><a id="a3cf1f3daf3f457f629ecdfc46e090308ab24bf6651a23d78e19d7868ac7759937" name="a3cf1f3daf3f457f629ecdfc46e090308ab24bf6651a23d78e19d7868ac7759937"></a>SDRV_DMA_LOOP_MODE_1&#160;</td><td class="fielddoc"><p >burst length data transaction </p>
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<tr><td class="fieldname"><a id="a3cf1f3daf3f457f629ecdfc46e090308a203865882173284915f7e80cdd468829" name="a3cf1f3daf3f457f629ecdfc46e090308a203865882173284915f7e80cdd468829"></a>SDRV_DMA_LOOP_MODE_2&#160;</td><td class="fielddoc"><p >power of 2 length data transaction </p>
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<tr><td class="fieldname"><a id="a3cf1f3daf3f457f629ecdfc46e090308aaff8eb75785ea214b214cbc810138962" name="a3cf1f3daf3f457f629ecdfc46e090308aaff8eb75785ea214b214cbc810138962"></a>SDRV_DMA_LOOP_MODE_UNDEFINED&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a7e5e385f109e1f40f780b40245d5df29">&#9670;&nbsp;</a></span>sdrv_dma_mad_crc_mode_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a7e5e385f109e1f40f780b40245d5df29">sdrv_dma_mad_crc_mode_e</a></td>
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<p>DMA MAD CRC. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a7e5e385f109e1f40f780b40245d5df29a07bd41ac23497361f6ff8bfd22ddbc70" name="a7e5e385f109e1f40f780b40245d5df29a07bd41ac23497361f6ff8bfd22ddbc70"></a>SDRV_DMA_NO_MAD_CRC&#160;</td><td class="fielddoc"><p >DMA MAD CRC Disable </p>
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<tr><td class="fieldname"><a id="a7e5e385f109e1f40f780b40245d5df29ae65c316abe76b93d9050ac2e8bed67d9" name="a7e5e385f109e1f40f780b40245d5df29ae65c316abe76b93d9050ac2e8bed67d9"></a>SDRV_DMA_CHECK_CURR_MAD&#160;</td><td class="fielddoc"><p >DMA MAD CRC Check current mad </p>
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<tr><td class="fieldname"><a id="a7e5e385f109e1f40f780b40245d5df29a91d25c784350c2838297e03eb219379b" name="a7e5e385f109e1f40f780b40245d5df29a91d25c784350c2838297e03eb219379b"></a>SDRV_DMA_CHECK_CURR_MAD_AND_PREVIOUS&#160;</td><td class="fielddoc"><p >DMA MAD CRC check LADR of previous MAD and current MAD(Except
LADR of current MAD) </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ad51b2ae201e5ece6bed36d8c4bea6d36">&#9670;&nbsp;</a></span>sdrv_dma_mux_direction_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#ad51b2ae201e5ece6bed36d8c4bea6d36">sdrv_dma_mux_direction_e</a></td>
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<p>DMA channel mux direction. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ad51b2ae201e5ece6bed36d8c4bea6d36abd98205f4021289a6af7f19059ce525f" name="ad51b2ae201e5ece6bed36d8c4bea6d36abd98205f4021289a6af7f19059ce525f"></a>SDRV_DMA_MUX_RD&#160;</td><td class="fielddoc"><p >only peripheral to memory </p>
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<tr><td class="fieldname"><a id="ad51b2ae201e5ece6bed36d8c4bea6d36a7ebd6000464389549084fb826352f723" name="ad51b2ae201e5ece6bed36d8c4bea6d36a7ebd6000464389549084fb826352f723"></a>SDRV_DMA_MUX_WR&#160;</td><td class="fielddoc"><p >only memory to peripheral both peripheral to memory and memory to peripheral </p>
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<tr><td class="fieldname"><a id="ad51b2ae201e5ece6bed36d8c4bea6d36a87679bdc33da3a49749fcc2eccc62009" name="ad51b2ae201e5ece6bed36d8c4bea6d36a87679bdc33da3a49749fcc2eccc62009"></a>SDRV_DMA_MUX_BOTH&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a9d0cf1f599920228c33c952a30d92c01">&#9670;&nbsp;</a></span>sdrv_dma_port_sel_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a9d0cf1f599920228c33c952a30d92c01">sdrv_dma_port_sel_e</a></td>
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<p>The master port used by DMA source and target ports. </p>
<p >The DMA controller as a bus master, has both AXI64 port (for memory access) and AHB32 master port (for device register access). You can configure DMA channels to use different ports for different source and target addresses. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a9d0cf1f599920228c33c952a30d92c01a07fecbf4286bda882f876004cc1f2dce" name="a9d0cf1f599920228c33c952a30d92c01a07fecbf4286bda882f876004cc1f2dce"></a>SDRV_DMA_PORT_AXI64&#160;</td><td class="fielddoc"><p >The AXI64 port, used when the source or target buffer is in normal memory (IRAM, SDRAM). The AHB32 port, used when the source or target buffer is peripheral register. </p>
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<tr><td class="fieldname"><a id="a9d0cf1f599920228c33c952a30d92c01ac78883ce5096aebaf45f0c7197590655" name="a9d0cf1f599920228c33c952a30d92c01ac78883ce5096aebaf45f0c7197590655"></a>SDRV_DMA_PORT_AHB32&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a9d0cf1f599920228c33c952a30d92c01a51e182952da125efd9855a9cfebefc43" name="a9d0cf1f599920228c33c952a30d92c01a51e182952da125efd9855a9cfebefc43"></a>SDRV_DMA_PROT_NOT_DEFINED&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a20e725c7167a1e8583c7449ace841bd6">&#9670;&nbsp;</a></span>sdrv_dma_status_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a20e725c7167a1e8583c7449ace841bd6">sdrv_dma_status_e</a></td>
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<p>DMA channel transfer status. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a20e725c7167a1e8583c7449ace841bd6a4d1c155c6d38424928d32a6da4a78eb5" name="a20e725c7167a1e8583c7449ace841bd6a4d1c155c6d38424928d32a6da4a78eb5"></a>SDRV_DMA_COMPLETED&#160;</td><td class="fielddoc"><p >DMA channel will not accept requests </p>
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<tr><td class="fieldname"><a id="a20e725c7167a1e8583c7449ace841bd6a9d005921e15e93491689647d2cbfc904" name="a20e725c7167a1e8583c7449ace841bd6a9d005921e15e93491689647d2cbfc904"></a>SDRV_DMA_BLOCK_DONE&#160;</td><td class="fielddoc"><p >DMA channel transfer every block done </p>
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<tr><td class="fieldname"><a id="a20e725c7167a1e8583c7449ace841bd6aaa4f41e25622dee53b899a6031d728c1" name="a20e725c7167a1e8583c7449ace841bd6aaa4f41e25622dee53b899a6031d728c1"></a>SDRV_DMA_IN_PROGRESS&#160;</td><td class="fielddoc"><p >DMA channel in transmission </p>
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<tr><td class="fieldname"><a id="a20e725c7167a1e8583c7449ace841bd6aa4e6991915bdab79d0aca304fa1a7854" name="a20e725c7167a1e8583c7449ace841bd6aa4e6991915bdab79d0aca304fa1a7854"></a>SDRV_DMA_PAUSED&#160;</td><td class="fielddoc"><p >DMA channel transfer paused </p>
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<tr><td class="fieldname"><a id="a20e725c7167a1e8583c7449ace841bd6a1ba6e35af6961bb054e0d330e88ee0f8" name="a20e725c7167a1e8583c7449ace841bd6a1ba6e35af6961bb054e0d330e88ee0f8"></a>SDRV_DMA_ERR&#160;</td><td class="fielddoc"><p >DMA channel transfer error </p>
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<tr><td class="fieldname"><a id="a20e725c7167a1e8583c7449ace841bd6a7ebe40cf9567c7ab0a589e178b947d19" name="a20e725c7167a1e8583c7449ace841bd6a7ebe40cf9567c7ab0a589e178b947d19"></a>SDRV_DMA_PENDING&#160;</td><td class="fielddoc"><p >DMA channel transfer pending </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a3a1413e4588936959d4c1b1efcd4a03c">&#9670;&nbsp;</a></span>sdrv_dma_switch_event_ctrl_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a3a1413e4588936959d4c1b1efcd4a03c">sdrv_dma_switch_event_ctrl_e</a></td>
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<p>Hardware control after MAD completed just for LOOP_MODE_1. </p>
<p >When one transaction is completed according to MAD, DMA will trigger different control. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a3a1413e4588936959d4c1b1efcd4a03ca57d713a7292a5aaf98193e8d26d5c31f" name="a3a1413e4588936959d4c1b1efcd4a03ca57d713a7292a5aaf98193e8d26d5c31f"></a>SDRV_DMA_SWT_EVT_CTL_STOP_WTH_INT&#160;</td><td class="fielddoc"><p >DMA will be stopped and trigger interrupt when MAD done. DMA will be halted and trigger interrupt when MAD done. If you need to continue to use it, you need to configure the resume register. </p>
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<tr><td class="fieldname"><a id="a3a1413e4588936959d4c1b1efcd4a03cab97bebc42e8599c7b00683ac19d15d71" name="a3a1413e4588936959d4c1b1efcd4a03cab97bebc42e8599c7b00683ac19d15d71"></a>SDRV_DMA_SWT_EVT_CTL_SUSPEND_WTH_INT&#160;</td><td class="fielddoc"><p >DMA will be continued and trigger interrupt when MAD done. Such as linklist mode. </p>
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<tr><td class="fieldname"><a id="a3a1413e4588936959d4c1b1efcd4a03cad09478efd78a174c8e12b858a691f515" name="a3a1413e4588936959d4c1b1efcd4a03cad09478efd78a174c8e12b858a691f515"></a>SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTH_INT&#160;</td><td class="fielddoc"><p >DMA will be continued and not trigger interrupt when MAD done. Such as linklist mode. </p>
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<tr><td class="fieldname"><a id="a3a1413e4588936959d4c1b1efcd4a03ca3fbe4cc1bcd67e9330473cb40ba785d9" name="a3a1413e4588936959d4c1b1efcd4a03ca3fbe4cc1bcd67e9330473cb40ba785d9"></a>SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTHOUT_INT&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a3a1413e4588936959d4c1b1efcd4a03ca2112366764c560933380e5b933cfcca3" name="a3a1413e4588936959d4c1b1efcd4a03ca2112366764c560933380e5b933cfcca3"></a>SDRV_DMA_SWT_EVT_CTL_UNDEFINED&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a95f065bec1af860620ef897fec9f868d">&#9670;&nbsp;</a></span>sdrv_dma_trigger_mode_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a95f065bec1af860620ef897fec9f868d">sdrv_dma_trigger_mode_e</a></td>
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<p>DMA channel transfer triggered by which mode. </p>
<p >Select appropriate trigger mode according to transfer type and transfer mode. Hardware trigger actually for peripheral transactions, Software trigger actually for memory transactions,Gtimer trigger actually use DMA internal timer for period transactions, Internal event trigger actually for linklist transactions. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a95f065bec1af860620ef897fec9f868da242ce90cb31c1fad854a24b06f648612" name="a95f065bec1af860620ef897fec9f868da242ce90cb31c1fad854a24b06f648612"></a>SDRV_DMA_TRIGGER_BY_HARDWARE&#160;</td><td class="fielddoc"><p >for peripheral transaction </p>
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<tr><td class="fieldname"><a id="a95f065bec1af860620ef897fec9f868dac6740297a4301133c77407f34879ec6d" name="a95f065bec1af860620ef897fec9f868dac6740297a4301133c77407f34879ec6d"></a>SDRV_DMA_TRIGGER_BY_SOFTWARE&#160;</td><td class="fielddoc"><p >for memory transaction </p>
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<tr><td class="fieldname"><a id="a95f065bec1af860620ef897fec9f868da3835132e4e38c7804fd08d5132179611" name="a95f065bec1af860620ef897fec9f868da3835132e4e38c7804fd08d5132179611"></a>SDRV_DMA_TRIGGER_BY_GTIMER&#160;</td><td class="fielddoc"><p >for period transaction </p>
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<tr><td class="fieldname"><a id="a95f065bec1af860620ef897fec9f868da33fb2e286ec68f703f1add3cd90d019f" name="a95f065bec1af860620ef897fec9f868da33fb2e286ec68f703f1add3cd90d019f"></a>SDRV_DMA_TRIGGER_BY_INTERNAL_EVENT&#160;</td><td class="fielddoc"><p >for linklist transaction </p>
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<tr><td class="fieldname"><a id="a95f065bec1af860620ef897fec9f868dab346bf001ffd8826bb5a998eefbe0deb" name="a95f065bec1af860620ef897fec9f868dab346bf001ffd8826bb5a998eefbe0deb"></a>SDRV_DMA_TRIGGER_MODE_NOT_DEFINED&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a7516e48738a553c409c0d7f7f3b302bb">&#9670;&nbsp;</a></span>sdrv_dma_xfer_mode_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a7516e48738a553c409c0d7f7f3b302bb">sdrv_dma_xfer_mode_e</a></td>
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<p>DMA channel transfer mode. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a7516e48738a553c409c0d7f7f3b302bba0b4a9a246072137a07eaca344104eed1" name="a7516e48738a553c409c0d7f7f3b302bba0b4a9a246072137a07eaca344104eed1"></a>SDRV_DMA_TRANSFER_MODE_SINGLE&#160;</td><td class="fielddoc"><p >Single mode. Continuous mode. </p>
</td></tr>
<tr><td class="fieldname"><a id="a7516e48738a553c409c0d7f7f3b302bba0372b96e46c1707019045b96e6340abf" name="a7516e48738a553c409c0d7f7f3b302bba0372b96e46c1707019045b96e6340abf"></a>SDRV_DMA_TRANSFER_MODE_CONTINUOUS&#160;</td><td class="fielddoc"><p >Link list mode. </p>
</td></tr>
<tr><td class="fieldname"><a id="a7516e48738a553c409c0d7f7f3b302bba34c87e10e3352fa56150642b5105742d" name="a7516e48738a553c409c0d7f7f3b302bba34c87e10e3352fa56150642b5105742d"></a>SDRV_DMA_TRANSFER_MODE_LINKLIST&#160;</td><td class="fielddoc"><p >Channel link mode. </p>
</td></tr>
<tr><td class="fieldname"><a id="a7516e48738a553c409c0d7f7f3b302bba8496ab464a6699e801eea0f5ed43f4e5" name="a7516e48738a553c409c0d7f7f3b302bba8496ab464a6699e801eea0f5ed43f4e5"></a>SDRV_DMA_TRANSFER_MODE_CHAN_LINK&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="a7516e48738a553c409c0d7f7f3b302bba359d7b745adf624f8cf79db250ce9119" name="a7516e48738a553c409c0d7f7f3b302bba359d7b745adf624f8cf79db250ce9119"></a>SDRV_DMA_TRANSFER_MODE_NOT_DEFINED&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a4b2f1e33ab3153f5b47ff3d1d305a53e">&#9670;&nbsp;</a></span>sdrv_dma_xfer_type_e</h2>
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<td class="memname">enum <a class="el" href="sdrv__dma_8h.html#a4b2f1e33ab3153f5b47ff3d1d305a53e">sdrv_dma_xfer_type_e</a></td>
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<p>DMA channel transfer types. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a4b2f1e33ab3153f5b47ff3d1d305a53ea14855d0371e9930f4a1c33048f1d0cb7" name="a4b2f1e33ab3153f5b47ff3d1d305a53ea14855d0371e9930f4a1c33048f1d0cb7"></a>SDRV_DMA_DIR_MEM2MEM&#160;</td><td class="fielddoc"><p >memory to memory </p>
</td></tr>
<tr><td class="fieldname"><a id="a4b2f1e33ab3153f5b47ff3d1d305a53ea31a8368612dd982d21e80e12382c847d" name="a4b2f1e33ab3153f5b47ff3d1d305a53ea31a8368612dd982d21e80e12382c847d"></a>SDRV_DMA_DIR_MEM2DEV&#160;</td><td class="fielddoc"><p >memory to device </p>
</td></tr>
<tr><td class="fieldname"><a id="a4b2f1e33ab3153f5b47ff3d1d305a53ea747e6ad988999c7b2f51b58969cbfd9a" name="a4b2f1e33ab3153f5b47ff3d1d305a53ea747e6ad988999c7b2f51b58969cbfd9a"></a>SDRV_DMA_DIR_DEV2MEM&#160;</td><td class="fielddoc"><p >device to memory </p>
</td></tr>
<tr><td class="fieldname"><a id="a4b2f1e33ab3153f5b47ff3d1d305a53eaf01702ded9945b6be7ad4f568a7d8377" name="a4b2f1e33ab3153f5b47ff3d1d305a53eaf01702ded9945b6be7ad4f568a7d8377"></a>SDRV_DMA_DIR_DEV2DEV&#160;</td><td class="fielddoc"><p >device to device </p>
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<tr><td class="fieldname"><a id="a4b2f1e33ab3153f5b47ff3d1d305a53ea9af5771824fe732353300d613e8bc562" name="a4b2f1e33ab3153f5b47ff3d1d305a53ea9af5771824fe732353300d613e8bc562"></a>SDRV_DMA_DIR_REG2MEM&#160;</td><td class="fielddoc"><p >register to memory </p>
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<tr><td class="fieldname"><a id="a4b2f1e33ab3153f5b47ff3d1d305a53eadfa44dabbe82971cee3551b894d39789" name="a4b2f1e33ab3153f5b47ff3d1d305a53eadfa44dabbe82971cee3551b894d39789"></a>SDRV_DMA_DIR_REG2DEV&#160;</td><td class="fielddoc"><p >register to device </p>
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<tr><td class="fieldname"><a id="a4b2f1e33ab3153f5b47ff3d1d305a53eaa4e723f46746cf30fd7f38e73606071c" name="a4b2f1e33ab3153f5b47ff3d1d305a53eaa4e723f46746cf30fd7f38e73606071c"></a>SDRV_DMA_DIR_MEM2REG&#160;</td><td class="fielddoc"><p >memory to register </p>
</td></tr>
<tr><td class="fieldname"><a id="a4b2f1e33ab3153f5b47ff3d1d305a53eab2bac8a753e7c51186df856c5747c393" name="a4b2f1e33ab3153f5b47ff3d1d305a53eab2bac8a753e7c51186df856c5747c393"></a>SDRV_DMA_DIR_DEV2REG&#160;</td><td class="fielddoc"><p >device to register </p>
</td></tr>
<tr><td class="fieldname"><a id="a4b2f1e33ab3153f5b47ff3d1d305a53ea3ed1fa0481536573c3c8db7573f62e59" name="a4b2f1e33ab3153f5b47ff3d1d305a53ea3ed1fa0481536573c3c8db7573f62e59"></a>SDRV_DMA_DIR_NOT_DEFINED&#160;</td><td class="fielddoc"></td></tr>
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<h2 class="groupheader">Function Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a2e6749b66c137ff539d2d57c5f77eb19">&#9670;&nbsp;</a></span>sdrv_dma_clear_channel_xfer_bytes()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_clear_channel_xfer_bytes </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em></td><td>)</td>
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<p>Clear DMA channel transfered bytes counter. </p>
<p >This function clear transfered bytes counter.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>DMA channel. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a1ad1ffa7c9f117d0200822d1679f88b8">&#9670;&nbsp;</a></span>sdrv_dma_clear_channel_xfer_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_clear_channel_xfer_status </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em>, </td>
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<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>status</em>&#160;</td>
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<p>Clear DMA channel status. </p>
<p >This function clear channel current status.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>DMA channel. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">status</td><td>Channel status bitmask. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a53415ae94875eb7a9cfe6a539af15d13">&#9670;&nbsp;</a></span>sdrv_dma_create_instance()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_create_instance </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__dma_8h.html#a8398793befd907d68bc1b103b1ea1080">sdrv_dma_t</a> *&#160;</td>
<td class="paramname"><em>dma_instance</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">paddr_t&#160;</td>
<td class="paramname"><em>base</em>&#160;</td>
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<p>Create DMA controller instance. </p>
<p >This function create instance by dma controller base address.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">dma_instance</td><td>Pointer to DMA instance structure. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">base</td><td>DMA controller base address. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a79fb8756fe873971ff572f3581d63379">&#9670;&nbsp;</a></span>sdrv_dma_deinit_channel()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_deinit_channel </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em></td><td>)</td>
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<p>De-initialize the DMA channel. </p>
<p >This function reset channel registers to default value.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>The DMA channel to de-initialize. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a0769b2cf8a46624d5ff08de34260c3e5">&#9670;&nbsp;</a></span>sdrv_dma_get_channel_ctrl_base()</h2>
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<td class="memname">static sdrv_dma_channel_ctrl_t * sdrv_dma_get_channel_ctrl_base </td>
<td>(</td>
<td class="paramtype">sdrv_dma_ctrl_t *&#160;</td>
<td class="paramname"><em>dma_base</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype"><a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a>&#160;</td>
<td class="paramname"><em>channel</em>&#160;</td>
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<td></td>
<td>)</td>
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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<p>get dma channel controller base address. </p>
<p >This function get dma channel base address by dma controller base address and channel id.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">dma_base</td><td>dma controller base address. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>dma channel id. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname">channel</td><td>controller base address. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a5ca69e4d9b16835f3b8369735829ca85">&#9670;&nbsp;</a></span>sdrv_dma_get_channel_xfer_bytes()</h2>
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<td class="memname">uint32_t sdrv_dma_get_channel_xfer_bytes </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em></td><td>)</td>
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<p>Get number of transfered bytes for the channel. </p>
<p >This function get transfered length in bytes.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>DMA channel. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Number of transfered bytes. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ad20111dc252dd711bdd54dfb7637cd47">&#9670;&nbsp;</a></span>sdrv_dma_get_channel_xfer_status()</h2>
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<td class="memname">uint32_t sdrv_dma_get_channel_xfer_status </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em></td><td>)</td>
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<p>Get DMA channel status. </p>
<p >This function get channel current status.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>DMA channel. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>channel status. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#afb2e3e19ce05d0f2d35fbfb6bd5f5274">&#9670;&nbsp;</a></span>sdrv_dma_init_channel()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_init_channel </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em>, </td>
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<td></td>
<td class="paramtype">const <a class="el" href="structsdrv__dma__channel__config__t.html">sdrv_dma_channel_config_t</a> *&#160;</td>
<td class="paramname"><em>config</em>&#160;</td>
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<p>Initialize DMA channel. </p>
<p >This function set configuration to channel.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>The channel to initialize. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>DMA channel configuration. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>True if the DMA channel is initialized successfully. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a76b0a9d46747a4c58e2d6a4ac19ada6a">&#9670;&nbsp;</a></span>sdrv_dma_init_channel_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_init_channel_config </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__config__t.html">sdrv_dma_channel_config_t</a> *&#160;</td>
<td class="paramname"><em>config</em>, </td>
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<td class="paramtype"><a class="el" href="sdrv__dma_8h.html#a8398793befd907d68bc1b103b1ea1080">sdrv_dma_t</a> *&#160;</td>
<td class="paramname"><em>instance</em>&#160;</td>
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<p>Initialize default configuration for DMA channel. </p>
<p >This function get channel default configuration.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>DMA channel configuration to initialize. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">dma_instance</td><td>DMA controller instance. </td></tr>
</table>
</dd>
</dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a642196ea4807fd0796de61e7462fd4d8">&#9670;&nbsp;</a></span>sdrv_dma_init_dmac()</h2>
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<td class="memname">void sdrv_dma_init_dmac </td>
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<td class="paramname"><em>base</em></td><td>)</td>
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<p>Initialize the DMA controller. </p>
<p >This function initialize dma controller with reset status and fifo.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">base</td><td>DMA controller base address. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#aa74d7fc7a132808a8b38f2a488ec4c37">&#9670;&nbsp;</a></span>sdrv_dma_init_linklist_entry()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_init_linklist_entry </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__linklist__descriptor__t.html">sdrv_dma_linklist_descriptor_t</a> *&#160;</td>
<td class="paramname"><em>desc</em>, </td>
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<td class="paramtype">const <a class="el" href="structsdrv__dma__channel__config__t.html">sdrv_dma_channel_config_t</a> *&#160;</td>
<td class="paramname"><em>config</em>&#160;</td>
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<p>Initialize DMA link list descriptor. </p>
<p >This function initializes a DMA link list descriptor, using specified channel configuration.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">desc</td><td>Link list descriptor. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>DMA channel config. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#aaef77aa516fa3f6943fa0f6b53780328">&#9670;&nbsp;</a></span>sdrv_dma_reset_core_int_status()</h2>
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<td class="memname">static void sdrv_dma_reset_core_int_status </td>
<td>(</td>
<td class="paramtype">sdrv_dma_ctrl_t *&#160;</td>
<td class="paramname"><em>dma_base</em></td><td>)</td>
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<p>reset dma interrupt type. </p>
<p >This function reset dma controller interrupt status.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">dma_base</td><td>dma controller base address. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a9bc1511949ac434e7fdf0e8ea9b5d64a">&#9670;&nbsp;</a></span>sdrv_dma_reset_fifo()</h2>
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<td class="memname">static void sdrv_dma_reset_fifo </td>
<td>(</td>
<td class="paramtype">sdrv_dma_ctrl_t *&#160;</td>
<td class="paramname"><em>dma_base</em></td><td>)</td>
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<p>reset dma fifo. </p>
<p >This function reset dma controller fifo.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">dma_base</td><td>dma controller base address. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a65c810929e6c7bf83c4e26e477d0258e">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_buffer_size()</h2>
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<td class="memname">void sdrv_dma_set_channel_buffer_size </td>
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<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em>, </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__dma_8h.html#a3cf1f3daf3f457f629ecdfc46e090308">sdrv_dma_loop_mode_e</a>&#160;</td>
<td class="paramname"><em>loop_mode</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>total_size</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>loop_size</em>&#160;</td>
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<td></td>
<td>)</td>
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<p>set dma channel single transmit buffer size </p>
<p >This is an unsafe interface. The parameters filled in need to be calculated by yourself, and there is no verification inside the function.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">channel</td><td>dma channel ptr </td></tr>
<tr><td class="paramname">loop_mode</td><td>loop mode </td></tr>
<tr><td class="paramname">total_size</td><td>total bytes </td></tr>
<tr><td class="paramname">loop_size</td><td>every handshake transmic bytes(The loop mode 0 does not take
effect)</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a5fb1b55ece25615724899d39565af6fa">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_destination_address()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_set_channel_destination_address </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">paddr_t&#160;</td>
<td class="paramname"><em>addr</em>&#160;</td>
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<td></td>
<td>)</td>
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<p>Set DMA channel target address. </p>
<p >This function set target address to channel.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>DMA channel. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>target address. </td></tr>
</table>
</dd>
</dl>
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<h2 class="memtitle"><span class="permalink"><a href="#acbc275d6a1aca65b02f3fbaa7203a3a5">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_interrupt()</h2>
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<td class="memname">static void sdrv_dma_set_channel_interrupt </td>
<td>(</td>
<td class="paramtype">sdrv_dma_ctrl_t *&#160;</td>
<td class="paramname"><em>dma_base</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a>&#160;</td>
<td class="paramname"><em>channel</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>int_type</em>&#160;</td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
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<p>set dma channel interrupt type. </p>
<p >This function set dma channel interrupt type.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">dma_base</td><td>dma controller base address. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>dma channel id. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">int_type</td><td>interrupt type. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a6811b8a5b31e4739ad1a873f8b9d8905">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_muxid()</h2>
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<td class="memname">static void sdrv_dma_set_channel_muxid </td>
<td>(</td>
<td class="paramtype">sdrv_dma_ctrl_t *&#160;</td>
<td class="paramname"><em>dma_base</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a>&#160;</td>
<td class="paramname"><em>channel</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>mux_id</em>&#160;</td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
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</table>
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<p>set dma channel mux id. </p>
<p >This function set mux id for periphal transactions.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">dma_base</td><td>dma controller base address. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>dma channel id. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">mux_id</td><td>dma channel mux id. </td></tr>
</table>
</dd>
</dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a33ab3ea9936f909332aa5bd978144c68">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_rd_outstanding()</h2>
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<td class="memname">static void sdrv_dma_set_channel_rd_outstanding </td>
<td>(</td>
<td class="paramtype">sdrv_dma_ctrl_t *&#160;</td>
<td class="paramname"><em>dma_base</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a>&#160;</td>
<td class="paramname"><em>channel</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint8_t&#160;</td>
<td class="paramname"><em>value</em>&#160;</td>
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<tr>
<td></td>
<td>)</td>
<td></td><td></td>
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</table>
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<p>set dma channel read outstanding. </p>
<p >This function set read outstanding for memory transactions to get better performance.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">dma_base</td><td>dma controller base address. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>dma channel id. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>read outstanding value. </td></tr>
</table>
</dd>
</dl>
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<h2 class="memtitle"><span class="permalink"><a href="#af952d929924cbc31db48a7e206b92c12">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_source_address()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_set_channel_source_address </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em>, </td>
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<td class="paramname"><em>addr</em>&#160;</td>
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<p>Set DMA channel source address. </p>
<p >This function set source address to channel.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>DMA channel. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>source address. </td></tr>
</table>
</dd>
</dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a8d33970d5cfb77c4f3245f5079d4c3d6">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_status()</h2>
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<td class="memname">static void sdrv_dma_set_channel_status </td>
<td>(</td>
<td class="paramtype">sdrv_dma_channel_ctrl_t *&#160;</td>
<td class="paramname"><em>channel_base</em>, </td>
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<td></td>
<td class="paramtype"><a class="el" href="sdrv__dma_8h.html#a5ddef98910f9d3c31eb47b9412ecacad">sdrv_dma_channel_status_e</a>&#160;</td>
<td class="paramname"><em>status</em>&#160;</td>
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<td>)</td>
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<p>set dma channel status. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel_base</td><td>dma channel controller base address. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">status</td><td>dma channel status. </td></tr>
</table>
</dd>
</dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ab413862cd6d6458fd6e69224046a764c">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_sw_handshake()</h2>
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<td class="memname">static void sdrv_dma_set_channel_sw_handshake </td>
<td>(</td>
<td class="paramtype">sdrv_dma_channel_ctrl_t *&#160;</td>
<td class="paramname"><em>channel_base</em></td><td>)</td>
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<p>set dma channel software handshake. </p>
<p >This function set software handshake for memory transactions.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel_base</td><td>dma channel controller base address. </td></tr>
</table>
</dd>
</dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a1782ff45df981ebedd5d19992ce28877">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_wr_outstanding()</h2>
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<td class="memname">static void sdrv_dma_set_channel_wr_outstanding </td>
<td>(</td>
<td class="paramtype">sdrv_dma_ctrl_t *&#160;</td>
<td class="paramname"><em>dma_base</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__dma_8h.html#a2fce8b449dfda53bb26afae8dea00c9f">sdrv_dma_channel_id_e</a>&#160;</td>
<td class="paramname"><em>channel</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint8_t&#160;</td>
<td class="paramname"><em>value</em>&#160;</td>
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<td></td>
<td>)</td>
<td></td><td></td>
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</table>
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<p>set dma channel write outstanding. </p>
<p >This function set write outstanding for memory transactions to get better performance.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">dma_base</td><td>dma controller base address. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>dma channel id. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>write outstanding value. </td></tr>
</table>
</dd>
</dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#aa129ff50ec15717672116fcddab70f0d">&#9670;&nbsp;</a></span>sdrv_dma_set_channel_xfer_bytes()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_set_channel_xfer_bytes </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em>, </td>
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<td></td>
<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>xfer_bytes</em>&#160;</td>
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<td>)</td>
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<p>Set transfer length in bytes for the channel. </p>
<p >This function set transfer length in one transaction.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>DMA channel. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">xfer_bytes</td><td>transfer bytes. </td></tr>
</table>
</dd>
</dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a8a5b09a2f169ee6f98e473b1c9c9cf9d">&#9670;&nbsp;</a></span>sdrv_dma_start_channel_xfer()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_start_channel_xfer </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em></td><td>)</td>
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<p>Start DMA transaction. </p>
<p >This function start transfer.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>The DMA channel to start. </td></tr>
</table>
</dd>
</dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a664d4c43d2a51621fbf6827be1062b1a">&#9670;&nbsp;</a></span>sdrv_dma_stop_channel_xfer()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_dma_stop_channel_xfer </td>
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<td class="paramtype"><a class="el" href="structsdrv__dma__channel__t.html">sdrv_dma_channel_t</a> *&#160;</td>
<td class="paramname"><em>channel</em></td><td>)</td>
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<p>Stop DMA transaction. </p>
<p >This function stop transfer.</p>
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<tr><td class="paramdir">[in]</td><td class="paramname">channel</td><td>The DMA channel to stop. </td></tr>
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