200 lines
4.1 KiB
ArmAsm
200 lines
4.1 KiB
ArmAsm
/*
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* sd_vic_baremetal.S
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*
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* Copyright (c) 2020 Semidrive Semiconductor.
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* All rights reserved.
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*
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* Description: SemiDrive VIC interrupt handlers for baremetal.
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*
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* Revision History:
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* -----------------
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*/
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#if __ICCARM__
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extern get_vic_data_base
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extern sdrv_vic_lld_get_priority
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extern sdrv_vic_lld_ack_slow_path
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extern g_vic_user_isr
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extern int_nest_errata_enabled
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extern sdrv_vic_lld_mask_low_priority
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#endif
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#if __GNUC__
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.macro save_fpu_context
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#elif __ICCARM__
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save_fpu_context macro
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#endif
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vmrs r1, fpexc
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tst r1, #(1 << 30)
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beq save_exit
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/* Save callee corrupted fpu registers */
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vpush {d0-d7}
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/* Save fpscr and fpexc */
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vmrs r1, fpscr
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push {r1}
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vmrs r1, fpexc
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save_exit:
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push {r1}
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#if __GNUC__
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.endm
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#elif __ICCARM__
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endm
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#endif
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#if __GNUC__
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.macro restore_fpu_context
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#elif __ICCARM__
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restore_fpu_context macro
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#endif
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pop {r1}
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vmsr fpexc, r1
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tst r1, #(1 << 30)
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beq restore_exit
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pop {r1}
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vmsr fpscr, r1
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vpop {d0-d7}
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restore_exit:
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#if __GNUC__
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.endm
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#elif __ICCARM__
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endm
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#endif
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#if __GNUC__
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.macro vectored_irq_handler vector_num
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.globl vectored_irq\vector_num\()_handler
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vectored_irq\vector_num\()_handler:
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sub lr, lr, #4
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srsdb sp!, #SVC_MODE
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cps #SVC_MODE
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/* Save callee and common_irq_handler corrupted registers */
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push {r0-r5, r12}
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mov r0, #\vector_num
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b .Lcommon_irq_handler
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.endm
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#elif __ICCARM__
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vectored_irq_handler macro vector_num
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public vectored_irq\1_handler
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vectored_irq\1_handler:
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sub lr, lr, #4
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srsdb sp!, #SVC_MODE
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cps #SVC_MODE
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/* Save callee and common_irq_handler corrupted registers */
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push {r0-r5, r12}
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mov r0, #vector_num
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b .Lcommon_irq_handler
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endm
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#endif
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.Lcommon_irq_handler:
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/* Save fpu context, will corrupt r1 */
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save_fpu_context
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/* Force sp to align to 8 bytes */
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mov r1, sp
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bic sp, sp, #7
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/* Save old sp and supervisor lr */
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push {r1, lr}
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/* Save vector number into callee-saved register */
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mov r4, r0
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/* Save old running priority */
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blx get_vic_data_base
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add r1, r0, #8 /* r1 now holds address of {struct vic_data}.cur_rp */
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ldr r2, [r1]
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push {r1, r2}
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/* Update current running priority */
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mov r0, r4
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blx sdrv_vic_lld_get_priority
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ldr r1, [sp]
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str r0, [r1]
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/* Get previous masked priority */
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ldr r1, [r1, #8]
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push {r0, r1}
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blx int_nest_errata_enabled
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/* Save errata enabled flag into callee-saved r5 */
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movs r5, r0
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beq .Lno_errata
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ldr r1, [sp]
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blx sdrv_vic_lld_ack_slow_path
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.Lno_errata:
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pop {r0, r1}
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/* Make sure only unmasked interrupt can be taken. */
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cmp r0, r1
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bge .Lirq_out
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/* Increment interrupt nesting counter */
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ldr r1, [sp]
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ldr r2, [r1, #4]! /* r1 now holds address of {struct vic_data}.irq_nest_cnt */
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add r0, r2, #1
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str r0, [r1]
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push {r1, r2}
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#if CONFIG_VIC_INT_NEST_AUTO_ENABLE
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cmp r0, #CONFIG_VIC_INT_NEST_MAX_CNT
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bge .Lskip_reenable_irq
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cpsie i
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.Lskip_reenable_irq:
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#endif
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/* Call user ISR */
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mov r0, r4
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ldr r1, =g_vic_user_isr
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ldr r1, [r1]
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blx r1
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cpsid i
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/* Decrement interrupt nesting counter */
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pop {r1, r2}
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str r2, [r1]
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.Lirq_out:
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/* Restore current running priority */
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pop {r1, r2}
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str r2, [r1]
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cmp r5, #INT_NEST_ERRATA_TYPE_0
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beq .Lerrata_skip_wr_isr
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ldr r1, [r1, #-8]
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add r1, r1, #0xF00
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/* Perform a dummy write to VICADDRESS register to clear hwmask */
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str r4, [r1]
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.Lerrata_skip_wr_isr:
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cmp r5, #NO_INT_NEST_ERRATA
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beq .Lrestore_context
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/* Unmask priority to previous state. */
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mov r0, r2
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mov r1, #0
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blx sdrv_vic_lld_mask_low_priority
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.Lrestore_context:
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/* Restore sp and supervisor lr */
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pop {r1, lr}
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mov sp, r1
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restore_fpu_context
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/* Restore context */
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pop {r0-r5, r12}
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rfeia sp!
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#if __GNUC__
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.ltorg
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#elif __ICCARM__
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ltorg
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#endif
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