253 lines
8.6 KiB
C
253 lines
8.6 KiB
C
/**
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* @file sdrv_i2c_reg.h
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* @i2c register head file.
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*
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* @Copyright (c) 2022 Semidrive Semiconductor.
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* @All rights reserved.
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*
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**/
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#ifndef SDRV_I2C_REG_H_
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#define SDRV_I2C_REG_H_
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#include <math.h>
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#include <types.h>
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/* register address */
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#define I2C_MCR0 (0x00)
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#define I2C_PRDATAINJ (0x04)
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#define I2C_MCR2 (0x08)
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#define I2C_MCR3 (0x0C)
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#define I2C_MCR4 (0x10)
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#define I2C_MSR0 (0x18)
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#define I2C_MSR1 (0x1c)
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#define I2C_INTR0 (0x20)
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#define I2C_INTR1 (0x24)
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#define I2C_INTR2 (0x28)
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#define I2C_INTR3 (0x2C)
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#define I2C_INTEN0 (0x30)
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#define I2C_INTEN1 (0x34)
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#define I2C_INTEN2 (0x38)
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#define I2C_INTEN3 (0x3C)
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#define I2C_CMDCSR0 (0x40)
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#define I2C_CMDCSR1 (0x44)
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#define I2C_CMDCSR2 (0x48)
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#define I2C_CMDCSR3 (0x4C)
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#define I2C_FCR (0x50)
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#define I2C_FSR (0x60)
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#define I2C_DMACR (0x70)
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#define I2C_DMASR (0x74)
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#define I2C_PCR0 (0x80)
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#define I2C_PCR1 (0x84)
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#define I2C_PCR2 (0x88)
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#define I2C_PCR3 (0x8C)
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#define I2C_PCR4 (0x90)
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#define I2C_PCR5 (0x94)
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#define I2C_PCR6 (0x98)
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#define I2C_PCR7 (0x9C)
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#define I2C_PCR8 (0xA0)
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#define I2C_PCR9 (0xA4)
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#define I2C_PCR10 (0xA8)
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#define I2C_PCR11 (0xAC)
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#define I2C_PCR12 (0xB0)
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#define I2C_PCR13 (0xB4)
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#define I2C_PCR14 (0xB8)
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#define I2C_PCR15 (0xBC)
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#define I2C_PSR0 (0x100)
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#define I2C_PSR1 (0x104)
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#define I2C_PSR2 (0x108)
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#define I2C_PSR3 (0x10c)
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#define I2C_TXFIFO (0x200)
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#define I2C_RXFIFO (0x300)
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#define I2C_PARITY_ERR_INT_STAT (0xE0)
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#define I2C_PARITY_ERR_INT_STAT_EN (0xE4)
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#define I2C_PARITY_ERR_INT_SIG_EN (0xE8)
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/* adapter opmode bitmask */
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#define SDRV_I2C_SLAVE (0x0)
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#define SDRV_SM_SLAVE (0x1)
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#define SDRV_PM_SLAVE (0x2)
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#define SDRV_I2C_MASTER (0x8)
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/* adapter speedmode bitmask */
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#define SDRV_I2C_NSPEED (0x0)
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#define SDRV_I2C_HSPEED (0x3)
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#define SDRV_I2C_USPEED (0x4)
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/* fifo watermark level */
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#define SDRV_I2C_RX_WML (0x1f)
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#define SDRV_I2C_TX_WML (0x1f)
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#define SDRV_I2C_RXTX_WML (SDRV_I2C_TX_WML | SDRV_I2C_RX_WML << 8)
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/* int0 bitmask */
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#define SDRV_I2C_INT0_TXFWE (1 << 0)
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#define SDRV_I2C_INT0_RXFWF (1 << 1)
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#define SDRV_I2C_INT0_TXFUDF (1 << 2)
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#define SDRV_I2C_INT0_RXFUDF (1 << 3)
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#define SDRV_I2C_INT0_TXFOVF (1 << 4)
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#define SDRV_I2C_INT0_RXFOVF (1 << 5)
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#define SDRV_I2C_INT0_TXFABT (1 << 6)
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#define SDRV_I2C_INT0_RXFABT (1 << 7)
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#define SDRV_I2C_INT0_SCLSTUCKLOW (1 << 8)
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#define SDRV_I2C_INT0_SDASTUCKLOW (1 << 9)
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#define SDRV_I2C_INT0_BUSCLRPASS (1 << 10)
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#define SDRV_I2C_INT0_BUSCLRERR (1 << 11)
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#define SDRV_I2C_INT0_APBCMDDONE (1 << 12)
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#define SDRV_I2C_INT0_APBCMDABORT (1 << 13)
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#define SDRV_I2C_INT0_SLVWRTRANSDONE (1 << 14)
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#define SDRV_I2C_INT0_SLVRDTRANSDONE (1 << 15)
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#define SDRV_I2C_INT0_SLVWRTRANSABORT (1 << 16)
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#define SDRV_I2C_INT0_SLVRDTRANSABORT (1 << 17)
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#define SDRV_I2C_INT0_SCLHLDTX (1 << 18)
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#define SDRV_I2C_INT0_SCLHLDRX (1 << 19)
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#define SDRV_I2C_INT0_BUSCLRDET (1 << 20)
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#define SDRV_I2C_INT0_DEFAULT_MASK \
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(SDRV_I2C_INT0_TXFUDF |\
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SDRV_I2C_INT0_RXFUDF |\
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SDRV_I2C_INT0_TXFOVF |\
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SDRV_I2C_INT0_RXFOVF |\
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SDRV_I2C_INT0_TXFABT |\
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SDRV_I2C_INT0_RXFABT |\
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SDRV_I2C_INT0_SCLSTUCKLOW |\
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SDRV_I2C_INT0_SDASTUCKLOW |\
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SDRV_I2C_INT0_APBCMDDONE |\
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SDRV_I2C_INT0_APBCMDABORT)
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#define SDRV_I2C_INT0_ERR_STAT \
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(SDRV_I2C_INT0_TXFUDF |\
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SDRV_I2C_INT0_RXFUDF |\
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SDRV_I2C_INT0_TXFOVF |\
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SDRV_I2C_INT0_RXFOVF |\
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SDRV_I2C_INT0_TXFABT |\
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SDRV_I2C_INT0_RXFABT |\
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SDRV_I2C_INT0_SCLSTUCKLOW |\
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SDRV_I2C_INT0_SDASTUCKLOW |\
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SDRV_I2C_INT0_APBCMDABORT |\
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SDRV_I2C_INT0_SLVWRTRANSABORT |\
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SDRV_I2C_INT0_SLVRDTRANSABORT)
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#define SDRV_I2C_INT0_SLV_DEFAULT_MASK \
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(SDRV_I2C_INT0_TXFUDF |\
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SDRV_I2C_INT0_RXFUDF |\
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SDRV_I2C_INT0_TXFOVF |\
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SDRV_I2C_INT0_RXFOVF |\
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SDRV_I2C_INT0_TXFABT |\
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SDRV_I2C_INT0_RXFABT |\
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SDRV_I2C_INT0_SCLSTUCKLOW |\
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SDRV_I2C_INT0_SDASTUCKLOW |\
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SDRV_I2C_INT0_APBCMDABORT |\
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SDRV_I2C_INT0_SLVWRTRANSDONE |\
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SDRV_I2C_INT0_SLVRDTRANSDONE |\
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SDRV_I2C_INT0_SLVWRTRANSABORT|\
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SDRV_I2C_INT0_SLVRDTRANSABORT)
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#define SDRV_I2C_INT0_SLV_ERR_STAT \
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(SDRV_I2C_INT0_TXFUDF |\
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SDRV_I2C_INT0_RXFUDF |\
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SDRV_I2C_INT0_TXFOVF |\
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SDRV_I2C_INT0_RXFOVF |\
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SDRV_I2C_INT0_TXFABT |\
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SDRV_I2C_INT0_RXFABT |\
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SDRV_I2C_INT0_SCLSTUCKLOW |\
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SDRV_I2C_INT0_SDASTUCKLOW |\
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SDRV_I2C_INT0_APBCMDABORT)
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/* int2 bitmask */
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#define SDRV_I2C_INT2_STARTDET (1 << 0)
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#define SDRV_I2C_INT2_RESTARTDET (1 << 1)
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#define SDRV_I2C_INT2_STOPDET (1 << 2)
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#define SDRV_I2C_INT2_SLVRDREQDET (1 << 18)
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#define SDRV_I2C_INT2_SLVWRREQDET (1 << 19)
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#define SDRV_I2C_INT2_CTLBYTEDET (1 << 28)
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#define SDRV_I2C_INT2_SLV_MASK \
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(SDRV_I2C_INT2_SLVRDREQDET | SDRV_I2C_INT2_SLVWRREQDET)
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/* int3 bitmask */
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#define SDRV_I2C_INT3_DMAEOBAERR (1 << 0)
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#define SDRV_I2C_INT3_DMAEOBCERR (1 << 1)
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#define SDRV_I2C_INT3_DMABWUNCERR (1 << 2)
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#define SDRV_I2C_INT3_DMABWCORERR (1 << 3)
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#define SDRV_I2C_INT3_DMABWFATALERR (1 << 4)
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#define SDRV_I2C_INT3_PCTL0UNCERR (1 << 16)
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#define SDRV_I2C_INT3_PCTL1UNCERR (1 << 17)
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#define SDRV_I2C_INT3_PUSERUNCERR (1 << 18)
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#define SDRV_I2C_INT3_PADDRUNCERR (1 << 19)
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#define SDRV_I2C_INT3_PWDATACORERR (1 << 20)
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#define SDRV_I2C_INT3_PWDATAUNCERR (1 << 21)
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#define SDRV_I2C_INT3_PWDATAFATALERR (1 << 22)
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#define SDRV_I2C_INT3_SELFTESTMODERR (1 << 25)
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#define SDRV_I2C_INT3_REGPAREJENERR (1 << 26)
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#define SDRV_I2C_INT3_MASK \
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(SDRV_I2C_INT3_DMAEOBAERR |\
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SDRV_I2C_INT3_DMAEOBCERR |\
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SDRV_I2C_INT3_DMABWUNCERR |\
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SDRV_I2C_INT3_DMABWFATALERR |\
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SDRV_I2C_INT3_PCTL0UNCERR |\
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SDRV_I2C_INT3_PCTL1UNCERR |\
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SDRV_I2C_INT3_PUSERUNCERR |\
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SDRV_I2C_INT3_PADDRUNCERR |\
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SDRV_I2C_INT3_PWDATAUNCERR |\
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SDRV_I2C_INT3_PWDATAFATALERR)
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/* slave mode cmdcsr bitmask */
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#define SDRV_I2C_CMD0_SLV_MASK (0x0)
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#define SDRV_I2C_CMD1_SLV_MASK (0x0)
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#define SDRV_I2C_CMD2_SLV_MASK (0xffff0000)
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#define SDRV_I2C_CMD3_SLV_MASK (0xffff0000)
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/* i2c timing calculate model */
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#define CAL_BASE(value, clk_khz) (value * clk_khz / 1000000)
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#define CAL_SCLL(value, clk_khz) (CAL_BASE(value, clk_khz))
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#define CAL_TA(value, clk_khz) (CAL_BASE(value, clk_khz))
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#define CAL_DVDAT(value, clk_khz) (CAL_BASE(value, clk_khz) / 2 - 1)
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#define CAL_UNIT(value) (value)
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#define CAL_MEXT(value, clk_khz) (CAL_BASE(value, clk_khz))
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#define CAL_SEXT(value, clk_khz) (CAL_BASE(value, clk_khz))
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#define CAL_STUCK(value, clk_khz) (value * clk_khz / 65536)
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#define CAL_SDARXHLD(value, clk_khz) (CAL_BASE(value, clk_khz))
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#define CAL_DATSPL(value) (value)
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#define CAL_BUF(value, clk_khz) ((uint32_t)(log2(CAL_BASE(value, clk_khz) / 4)))
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#define CAL_IDLE(value, clk_khz) (CAL_BASE(value, clk_khz))
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uint8_t sdrv_i2c_recv_data(paddr_t base);
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void sdrv_i2c_send_data(paddr_t base, uint8_t data);
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uint32_t sdrv_i2c_get_psr_stat(paddr_t base, uint32_t psr_reg);
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uint32_t sdrv_i2c_get_wspace(paddr_t base);
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uint32_t sdrv_i2c_get_rspace(paddr_t base);
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uint32_t sdrv_i2c_get_fifo_empty_stat(paddr_t base);
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void sdrv_i2c_set_watermark(paddr_t base, uint32_t wml);
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void sdrv_i2c_clear_fifo(paddr_t base);
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void sdrv_i2c_set_cmdcsr(paddr_t base, uint32_t cmdcsr_reg,
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uint32_t val);
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uint32_t sdrv_i2c_get_cmdcsr(paddr_t base, uint32_t cmdcsr_reg);
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void sdrv_i2c_clear_int(paddr_t base);
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void sdrv_i2c_clear_int_bits(paddr_t base, uint32_t intr_reg, uint32_t bits);
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void sdrv_i2c_disable_int(paddr_t base);
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uint32_t sdrv_i2c_get_int_stat(paddr_t base, uint32_t intr_reg);
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void sdrv_i2c_unmask_int(paddr_t base, uint32_t inten_reg, uint32_t int_flag);
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void sdrv_i2c_set_IO(paddr_t base, uint32_t io_reg, uint32_t val);
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void sdrv_i2c_set_speed(paddr_t base, uint32_t clk, uint32_t speed_mode);
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void sdrv_i2c_set_nack(paddr_t base);
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void sdrv_i2c_set_slvaddr(paddr_t base, uint8_t addr);
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void sdrv_i2c_set_opmode(paddr_t base, uint32_t opmode);
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uint32_t sdrv_i2c_get_parity_stat(paddr_t base);
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void sdrv_i2c_set_parity_stat(paddr_t base, bool enable);
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void sdrv_i2c_set_parity_sig(paddr_t base, bool enable);
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void sdrv_i2c_set_timing(paddr_t base, uint32_t clk, int idx);
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void sdrv_i2c_disable(paddr_t base);
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void sdrv_i2c_enable(paddr_t base);
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int sdrv_i2c_reset(paddr_t base);
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void sdrv_i2c_dump_reg(paddr_t base, uint32_t *reg_val);
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void sdrv_i2c_write_reg(paddr_t base, uint32_t reg, uint32_t val);
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void sdrv_i2c_read_reg(paddr_t base, uint32_t reg, uint32_t *val);
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#endif
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