366 lines
12 KiB
C
366 lines
12 KiB
C
/**
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* @file sdrv_rstgen.h
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* @brief SemiDrive Reset driver header file.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_RSTGEN_H_
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#define SDRV_RSTGEN_H_
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#include <types.h>
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#include <sdrv_common.h>
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/* Define the type of rstgen */
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#define SDRV_RSTGEN_CORE 1
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#define SDRV_RSTGEN_LATENT 2
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#define SDRV_RSTGEN_MISSION 3
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#define SDRV_RSTGEN_MODULE 4
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#define SDRV_RSTGEN_IST 5
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#define SDRV_RSTGEN_DEBUG 6
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#define SDRV_RSTGEN_TYPE_SHIFT 24
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#define SDRV_RSTGEN_SIG_ID(type, idx) \
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((uint32_t)((((uint32_t)(type)) << ((uint32_t)SDRV_RSTGEN_TYPE_SHIFT)) | ((uint32_t)(idx))))
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#define SDRV_RSTGEN_TYPE(id) ((uint32_t)(((uint32_t)(id)) >> ((uint32_t)SDRV_RSTGEN_TYPE_SHIFT)))
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#define SDRV_RSTGEN_INDEX(id) ((uint32_t)(((uint32_t)(id)) & BIT_MASK(SDRV_RSTGEN_TYPE_SHIFT)))
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#define SDRV_RSTGEN_GENERAL_REG_NUM 8
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/**
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* @brief RESET status error code.
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*/
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enum sdrv_reset_error
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{
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SDRV_RESET_STATUS_SIGNAL_ASSERT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_RESET, 1), /* RESET singal assert. */
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SDRV_RESET_STATUS_LOCK = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_RESET, 2), /* RESET lock error. */
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SDRV_RESET_STATUS_TIMEOUT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_RESET, 3), /* RESET timeout error. */
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SDRV_RESET_STATUS_WRONG_SIGNAL = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_RESET, 4), /* RESET wrong signal. */
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};
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/* Define lowpower mode */
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enum reset_lowpower_mode {
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RESET_LP_HIB = 0,
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RESET_LP_SLEEP = 1,
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};
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typedef enum reset_wdt_id {
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RESET_WDT1, /* Trigger global reset or SF core reset */
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RESET_WDT2, /* Trigger global reset or SF core reset */
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RESET_WDT3, /* Trigger global reset or SP0/SP1 core reset */
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RESET_WDT4, /* Trigger global reset or SP0/SP1 core reset */
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RESET_WDT5, /* Trigger global reset or SX0/SX1 core reset */
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RESET_WDT6, /* Trigger global reset or SX0/SX1 core reset */
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} reset_wdt_id_e;
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typedef enum reset_core_id {
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RESET_CORE_SF = 1,
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RESET_CORE_SP0,
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RESET_CORE_SP1,
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RESET_CORE_SX0,
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RESET_CORE_SX1,
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} reset_core_id_e;
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/**
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* @brief semidrive reset sig handler.
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*
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* call pre handler before reset/assert signal,
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* and call post handler after reset/deassert signal, if necessary.
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*/
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typedef void (*sdrv_rstgen_sig_handler)(uint32_t rstgen_sig_id);
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/**
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* @brief SDRV rstgen controller.
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*/
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typedef struct sdrv_rstgen {
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paddr_t base;
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} sdrv_rstgen_t;
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/**
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* @brief SDRV rstgen signal.
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*/
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typedef struct sdrv_rstgen_sig {
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sdrv_rstgen_t *rst_ctl;
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uint32_t id;
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bool need_clr_rst;
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sdrv_rstgen_sig_handler pre_handler;
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sdrv_rstgen_sig_handler post_handler;
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} sdrv_rstgen_sig_t;
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/**
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* @brief SDRV rstgen general register.
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*/
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typedef struct sdrv_rstgen_general_reg {
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sdrv_rstgen_t *rst_ctl;
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uint32_t id; /* id 1 ~ 7 */
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} sdrv_rstgen_general_reg_t;
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/**
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* @brief SDRV rstgen global reset controller.
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*/
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typedef struct sdrv_rstgen_glb_ctl {
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sdrv_rstgen_t *rst_sf_ctl;
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sdrv_rstgen_t *rst_ap_ctl;
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} sdrv_rstgen_glb_t;
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/**
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* @brief semidrive recovery device.
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*/
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typedef struct sdrv_recovery_btm {
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uint32_t btm_num; /* btm numbers */
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uint32_t btm_base[]; /* btm base list */
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} sdrv_recovery_btm_t;
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typedef struct sdrv_recovery_etimer {
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uint32_t etimer_num; /* etimer numbers */
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uint32_t etimer_base[]; /* etimer base list */
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} sdrv_recovery_etimer_t;
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typedef struct sdrv_recovery_epwm {
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uint32_t epwm_num; /* epwm numbers */
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uint32_t epwm_base[]; /* epwm base list */
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} sdrv_recovery_epwm_t;
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/* semidrive recovery latent module */
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typedef struct sdrv_recovery_module {
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sdrv_recovery_btm_t const *btm_list;
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sdrv_recovery_etimer_t const *etimer_list;
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sdrv_recovery_epwm_t const *epwm_list;
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} sdrv_recovery_module_t;
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/**
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* @brief Assert a reset signal.
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*
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* The reset singal will stay asserted until reset_deassert() is called.
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*
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* @param[in] rst_sig Reset signal.
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* @return 0 if OK, or a negative error code.
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*/
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status_t sdrv_rstgen_assert(sdrv_rstgen_sig_t *rst_sig);
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/**
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* @brief Deassert a reset signal.
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*
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* Release a reset signal.
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*
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* @param[in] rst_sig Reset signal.
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* @return 0 if OK, or a negative error code.
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*/
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status_t sdrv_rstgen_deassert(sdrv_rstgen_sig_t *rst_sig);
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/**
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* @brief Reset a reset signal.
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*
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* Assert a reset signal, and then deassert it automatically.
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*
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* @param[in] rst_sig Reset signal.
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* @return 0 if OK, or a negative error code.
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*/
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status_t sdrv_rstgen_reset(sdrv_rstgen_sig_t *rst_sig);
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/**
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* @brief Global reset.
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*
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* Global reset SF/AP domain
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*
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* @param[in] rst_glb_ctl Global reset controller.
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* @return 0 if OK, or a negative error code.
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*/
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status_t sdrv_rstgen_global_reset(sdrv_rstgen_glb_t *rst_glb_ctl);
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/**
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* @brief Check reset signal status.
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*
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* @param[in] rst_sig Reset signal.
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* @return 0 if deasserted, or a negative error code.
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*/
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status_t sdrv_rstgen_status(sdrv_rstgen_sig_t *rst_sig);
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/**
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* @brief Check global reset status.
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*
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* Global reset status for all the time,
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* including each global reset status before clear or power off.
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* If multiple reset source comes neatly the same time,
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* only the first one will be recorded.
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*
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* @param[in] rst_glb_ctl Global reset controller.
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* @return SF and AP domain global reset status.
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* bit[31:25] for rstgen AP:
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* bit[31] rstgen ap software global reset
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* bit[30] reserved
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* bit[29] efusec security violation
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* bit[28] system panic(vdc function irq)
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* bit[27] sem1/sem2 error
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* bit[26] reserved
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* bit[25] PT sensor interrupt
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* bit[24:0] for rstgen SF:
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* bit[24] wdt6 int reset request
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* bit[23] wdt6 int reset request
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* bit[22] wdt4 int reset request
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* bit[21] wdt4 int reset request
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* bit[20] wdt2 int reset request
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* bit[19] reserved
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* bit[18] wdt5 int reset request
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* bit[17] wdt5 int reset request
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* bit[16] wdt3 int reset request
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* bit[15] wdt3 int reset request
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* bit[14] wdt1 int reset request
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* bit[13] reserved
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* bit[12] ist done fail
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* bit[11] rstgen sf software global reset
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* bit[10] reserved
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* bit[9] wdt2 int reset request (Only for E3104/E3106/E3205/E3206)
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* bit[8] wdt1 int reset request (Only for E3104/E3106/E3205/E3206)
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* bit[7] ist done fail (Only for E3104/E3106/E3205/E3206)
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* bit[6] rstgen sf software global reset (Only for E3104/E3106/E3205/E3206)
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* bit[5] rstgen ap cold reset request
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* bit[4] efusec security violation
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* bit[3] system panic(vdc function irq)
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* bit[2] sem1/sem2 error
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* bit[1] reserved
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* bit[0] PT sensor interrupt
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* Especially, bit[31:10] are invalid for E3104/E3106/E3205/E3206.
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*/
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uint32_t sdrv_rstgen_global_status(sdrv_rstgen_glb_t *rst_glb_ctl);
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/**
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* @brief clear global reset status.
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*
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* Clear global reset status, otherwise the status will keep until power off.
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*
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* @param[in] rst_glb_ctl Global reset controller.
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*/
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status_t sdrv_rstgen_global_status_clear(sdrv_rstgen_glb_t *rst_glb_ctl);
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/**
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* @brief Check current global reset status.
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*
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* Global reset status only for the last time.
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* If multiple reset source comes neatly the same time,
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* only the first one will be recorded.
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*
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* @param[in] rst_glb_ctl Global reset controller.
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* @return SF and AP domain current global reset status.
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* bit[31:25] for rstgen AP:
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* bit[31] rstgen ap software global reset
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* bit[30] reserved
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* bit[29] efusec security violation
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* bit[28] system panic(vdc function irq)
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* bit[27] sem1/sem2 error
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* bit[26] reserved
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* bit[25] PT sensor interrupt
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* bit[24:0] for rstgen SF:
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* bit[24] wdt6 int reset request
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* bit[23] wdt6 int reset request
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* bit[22] wdt4 int reset request
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* bit[21] wdt4 int reset request
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* bit[20] wdt2 int reset request
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* bit[19] reserved
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* bit[18] wdt5 int reset request
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* bit[17] wdt5 int reset request
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* bit[16] wdt3 int reset request
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* bit[15] wdt3 int reset request
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* bit[14] wdt1 int reset request
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* bit[13] reserved
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* bit[12] ist done fail
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* bit[11] rstgen sf software global reset
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* bit[10] reserved
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* bit[9] wdt2 int reset request (Only for E3104/E3106/E3205/E3206)
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* bit[8] wdt1 int reset request (Only for E3104/E3106/E3205/E3206)
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* bit[7] ist done fail (Only for E3104/E3106/E3205/E3206)
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* bit[6] rstgen sf software global reset (Only for E3104/E3106/E3205/E3206)
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* bit[5] rstgen ap cold reset request
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* bit[4] efusec security violation
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* bit[3] system panic(vdc function irq)
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* bit[2] sem1/sem2 error
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* bit[1] reserved
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* bit[0] PT sensor interrupt
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* Especially, bit[31:10] are invalid for E3104/E3106/E3205/E3206.
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*/
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uint32_t sdrv_rstgen_current_global_status(sdrv_rstgen_glb_t *rst_glb_ctl);
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/**
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* @brief Read reset general reg.
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*
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* The data saved in general regs will be not lost until SOC power down.
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*
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* @param[in] rst_gen_reg reset general reg.
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* @return general reg value.
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*/
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uint32_t sdrv_rstgen_read_general(sdrv_rstgen_general_reg_t *rst_gen_reg);
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/**
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* @brief Write reset general reg.
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*
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* @param[in] rst_gen_reg reset general reg.
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* @param[in] val write value.
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* @return 0 if success,
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* or a negative error code.
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*/
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status_t sdrv_rstgen_write_general(sdrv_rstgen_general_reg_t *rst_gen_reg,
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uint32_t val);
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/**
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* @brief Write reset general reg bit.
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*
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* @param[in] rst_gen_reg reset general reg.
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* @param[in] start write start bit.
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* @param[in] width write bit width.
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* @param[in] val write value.
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* @return 0 if success,
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* or a negative error code.
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*/
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status_t sdrv_rstgen_write_general_bit(sdrv_rstgen_general_reg_t *rst_gen_reg,
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uint8_t start, uint8_t width, uint32_t val);
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/**
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* @brief Config reset signal assert/deassert in lowpower mode.
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*
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* @param[in] rst_sig Reset signal.
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* @param[in] mode lowpower mode
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* @param[in] val 0:assert, 1:deassert
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*
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* @return 0 if OK, or a negative error code.
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*/
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status_t sdrv_rstgen_lowpower_set(sdrv_rstgen_sig_t *rst_sig,
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enum reset_lowpower_mode mode, uint32_t val);
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/**
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* @brief Config wdt cause global reset enable
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*
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* @param [in] wdt wdt id
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* @param [in] enable true/false
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* @return 0 if success, or a negative error code.
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*/
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status_t sdrv_rstgen_wdt_reset_enable(reset_wdt_id_e wdt, bool enable);
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/**
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* @brief Config wdt cause single core reset enable
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*
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* Config watchdog timeout trigger core reset. Each core has two watchdog, WDT1 and WDT2 belongs to SF,
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* WDT3 and WDT4 belongs to SP0/SP1, WDT5 and WDT6 belongs to SX0/SX1. SP1 and SX1 can be reset alone, if
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* SP0 or SX0 be reset, SP1 or SX1 will reset followed.
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*
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* @param [in] wdt wdt id
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* @param [in] core core id
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* @param [in] enable true/false
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* @return 0 if success, or a negative error code.
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*/
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status_t sdrv_rstgen_wdt_core_reset_enable(reset_wdt_id_e wdt, reset_core_id_e core, bool enable);
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/**
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* @brief sdrv recovery latent module.
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*
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* Some latent modules (btm/etimer/epwm etc.) will be not reset when core is reset,
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* so these modules should be recovery when core restart.
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*
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* @param[in] recovery_module recovery latent module list
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* @return 0 if success, or a negative error code.
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*/
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status_t sdrv_recovery_module(sdrv_recovery_module_t* recovery_module);
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#endif /* SDRV_RSTGEN_RSTGEN_H_ */
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