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<div id="projectname">SemiDrive SSDK Appication Program Interface<span id="projectnumber"> PTG3.0</span>
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="headertitle"><div class="title">sdrv_ckgen_config</div></div>
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<div class="contents">
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<p><code>#include <<a class="el" href="sdrv__ckgen_8h_source.html">sdrv_ckgen.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:aa9de51d94c57a5eabd2f31a754689756"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__ckgen_8h.html#a50d53483d761ee11c18de98e90b3b5a6">sdrv_ckgen_bus_config_t</a> const * </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__config.html#aa9de51d94c57a5eabd2f31a754689756">pre_bus_config</a></td></tr>
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<tr class="separator:aa9de51d94c57a5eabd2f31a754689756"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad017f48bfab238a7771caae41e5765aa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__ckgen_8h.html#aac6484f5e4b9746a5e7a3789d3b04825">sdrv_ckgen_rate_config_t</a> const * </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__config.html#ad017f48bfab238a7771caae41e5765aa">pll_config</a></td></tr>
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<tr class="memitem:a3a5a0bb9c58de117ab43800e39b4bd7c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__ckgen_8h.html#a50d53483d761ee11c18de98e90b3b5a6">sdrv_ckgen_bus_config_t</a> const * </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__config.html#a3a5a0bb9c58de117ab43800e39b4bd7c">bus_config</a></td></tr>
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<tr class="separator:a3a5a0bb9c58de117ab43800e39b4bd7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3294419f4b40ac21d76dde122371fc7e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__ckgen_8h.html#aac6484f5e4b9746a5e7a3789d3b04825">sdrv_ckgen_rate_config_t</a> const * </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__config.html#a3294419f4b40ac21d76dde122371fc7e">core_config</a></td></tr>
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<tr class="separator:a3294419f4b40ac21d76dde122371fc7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aefdba55e3963ab083583a490ec5bd456"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__ckgen_8h.html#aac6484f5e4b9746a5e7a3789d3b04825">sdrv_ckgen_rate_config_t</a> const * </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__config.html#aefdba55e3963ab083583a490ec5bd456">ip_config</a></td></tr>
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<tr class="separator:aefdba55e3963ab083583a490ec5bd456"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6cd79e3b0471b42d474cc4dbd4b245ac"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__ckgen_8h.html#a145fadf9ee199e81c211cfd2a367e572">sdrv_ckgen_ip_clock_config_t</a> const * </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__config.html#a6cd79e3b0471b42d474cc4dbd4b245ac">enable_config</a></td></tr>
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<tr class="separator:a6cd79e3b0471b42d474cc4dbd4b245ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a17d9964b969fa39f0d9d4f97c32a2695"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__ckgen_8h.html#a9f94e7e5b8252045ab4e30a38a488f53">sdrv_ckgen_gating_config_t</a> const * </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__config.html#a17d9964b969fa39f0d9d4f97c32a2695">gating_config</a></td></tr>
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</table>
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<h2 class="groupheader">Field Documentation</h2>
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<a id="a3a5a0bb9c58de117ab43800e39b4bd7c" name="a3a5a0bb9c58de117ab43800e39b4bd7c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3a5a0bb9c58de117ab43800e39b4bd7c">◆ </a></span>bus_config</h2>
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<td class="memname"><a class="el" href="sdrv__ckgen_8h.html#a50d53483d761ee11c18de98e90b3b5a6">sdrv_ckgen_bus_config_t</a> const* bus_config</td>
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</div><div class="memdoc">
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<p >System bus rate config, this include SF/SP core rate </p>
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<a id="a3294419f4b40ac21d76dde122371fc7e" name="a3294419f4b40ac21d76dde122371fc7e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3294419f4b40ac21d76dde122371fc7e">◆ </a></span>core_config</h2>
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<td class="memname"><a class="el" href="sdrv__ckgen_8h.html#aac6484f5e4b9746a5e7a3789d3b04825">sdrv_ckgen_rate_config_t</a> const* core_config</td>
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<p >Core rate config, now only config SX rate </p>
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<a id="a6cd79e3b0471b42d474cc4dbd4b245ac" name="a6cd79e3b0471b42d474cc4dbd4b245ac"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a6cd79e3b0471b42d474cc4dbd4b245ac">◆ </a></span>enable_config</h2>
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<td class="memname"><a class="el" href="sdrv__ckgen_8h.html#a145fadf9ee199e81c211cfd2a367e572">sdrv_ckgen_ip_clock_config_t</a> const* enable_config</td>
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<p >IP clock enable or disable config </p>
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<a id="a17d9964b969fa39f0d9d4f97c32a2695" name="a17d9964b969fa39f0d9d4f97c32a2695"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a17d9964b969fa39f0d9d4f97c32a2695">◆ </a></span>gating_config</h2>
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<td class="memname"><a class="el" href="sdrv__ckgen_8h.html#a9f94e7e5b8252045ab4e30a38a488f53">sdrv_ckgen_gating_config_t</a> const* gating_config</td>
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</div><div class="memdoc">
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<p >Clock gate config for each xcg under Run/Sleep/Hibernate mode </p>
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<a id="aefdba55e3963ab083583a490ec5bd456" name="aefdba55e3963ab083583a490ec5bd456"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aefdba55e3963ab083583a490ec5bd456">◆ </a></span>ip_config</h2>
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<td class="memname"><a class="el" href="sdrv__ckgen_8h.html#aac6484f5e4b9746a5e7a3789d3b04825">sdrv_ckgen_rate_config_t</a> const* ip_config</td>
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<p >IP rate config </p>
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<a id="ad017f48bfab238a7771caae41e5765aa" name="ad017f48bfab238a7771caae41e5765aa"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ad017f48bfab238a7771caae41e5765aa">◆ </a></span>pll_config</h2>
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<td class="memname"><a class="el" href="sdrv__ckgen_8h.html#aac6484f5e4b9746a5e7a3789d3b04825">sdrv_ckgen_rate_config_t</a> const* pll_config</td>
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<p >PLL rate config </p>
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<a id="aa9de51d94c57a5eabd2f31a754689756" name="aa9de51d94c57a5eabd2f31a754689756"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa9de51d94c57a5eabd2f31a754689756">◆ </a></span>pre_bus_config</h2>
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<td class="memname"><a class="el" href="sdrv__ckgen_8h.html#a50d53483d761ee11c18de98e90b3b5a6">sdrv_ckgen_bus_config_t</a> const* pre_bus_config</td>
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<p >Before config pll, optional change Core/Bus to FS24M </p>
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</div>
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<hr/>The documentation for this struct was generated from the following file:<ul>
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<li>Z:/01-Code/06-SSDK-DEV-Firewall/ssdk/drivers/include/<a class="el" href="sdrv__ckgen_8h_source.html">sdrv_ckgen.h</a></li>
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Generated by <a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.4
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