1074 lines
58 KiB
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1074 lines
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<div id="projectname">SemiDrive SSDK Appication Program Interface<span id="projectnumber"> PTG3.0</span>
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<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_ee023d43c33bfccc31aa50a48a76892b.html">include</a></li> </ul>
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<div class="headertitle"><div class="title">sdrv_rstgen.h File Reference</div></div>
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<div class="textblock"><code>#include <types.h></code><br />
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<code>#include <<a class="el" href="sdrv__common_8h_source.html">sdrv_common.h</a>></code><br />
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a>
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Data Structures</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__rstgen.html">sdrv_rstgen</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__rstgen__sig.html">sdrv_rstgen_sig</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__rstgen__general__reg.html">sdrv_rstgen_general_reg</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__rstgen__glb__ctl.html">sdrv_rstgen_glb_ctl</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__recovery__btm.html">sdrv_recovery_btm</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__recovery__etimer.html">sdrv_recovery_etimer</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__recovery__epwm.html">sdrv_recovery_epwm</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__recovery__module.html">sdrv_recovery_module</a></td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="typedef-members" name="typedef-members"></a>
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Typedefs</h2></td></tr>
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<tr class="memitem:a81742b8488efdd1527d7b6e4c9fb16ed"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a81742b8488efdd1527d7b6e4c9fb16ed">sdrv_rstgen_sig_handler</a>) (uint32_t rstgen_sig_id)</td></tr>
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<tr class="separator:a81742b8488efdd1527d7b6e4c9fb16ed"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
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Functions</h2></td></tr>
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<tr class="memitem:a90eb1f94509a65eec0ef47e9cab365dc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a90eb1f94509a65eec0ef47e9cab365dc">sdrv_rstgen_assert</a> (<a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> *rst_sig)</td></tr>
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<tr class="memitem:aa6189f234be2939d24c0b9e543ec6442"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#aa6189f234be2939d24c0b9e543ec6442">sdrv_rstgen_deassert</a> (<a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> *rst_sig)</td></tr>
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<tr class="memitem:a7b24afa273fa54f81963c02942e858d8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a7b24afa273fa54f81963c02942e858d8">sdrv_rstgen_reset</a> (<a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> *rst_sig)</td></tr>
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<tr class="separator:a7b24afa273fa54f81963c02942e858d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10dde50d7ec285cde7a052ee221c6713"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a10dde50d7ec285cde7a052ee221c6713">sdrv_rstgen_global_reset</a> (<a class="el" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a> *rst_glb_ctl)</td></tr>
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<tr class="separator:a10dde50d7ec285cde7a052ee221c6713"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0726f32906766eb1b8dfb2ba3d38f1fc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a0726f32906766eb1b8dfb2ba3d38f1fc">sdrv_rstgen_status</a> (<a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> *rst_sig)</td></tr>
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<tr class="separator:a0726f32906766eb1b8dfb2ba3d38f1fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a43254dd94c3b9d923b73c189996299c2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a43254dd94c3b9d923b73c189996299c2">sdrv_rstgen_global_status</a> (<a class="el" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a> *rst_glb_ctl)</td></tr>
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<tr class="separator:a43254dd94c3b9d923b73c189996299c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0432a9bac0e2a616cfe8a6100019c123"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a0432a9bac0e2a616cfe8a6100019c123">sdrv_rstgen_global_status_clear</a> (<a class="el" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a> *rst_glb_ctl)</td></tr>
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<tr class="separator:a0432a9bac0e2a616cfe8a6100019c123"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2cd8666bfe5ca507530dfb003faa1b15"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a2cd8666bfe5ca507530dfb003faa1b15">sdrv_rstgen_current_global_status</a> (<a class="el" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a> *rst_glb_ctl)</td></tr>
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<tr class="separator:a2cd8666bfe5ca507530dfb003faa1b15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a32b88bc068653b8f08eae962b0060a40"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a32b88bc068653b8f08eae962b0060a40">sdrv_rstgen_read_general</a> (<a class="el" href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5">sdrv_rstgen_general_reg_t</a> *rst_gen_reg)</td></tr>
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<tr class="separator:a32b88bc068653b8f08eae962b0060a40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af26011c9b69ad7af846f1b1078a6dbc0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#af26011c9b69ad7af846f1b1078a6dbc0">sdrv_rstgen_write_general</a> (<a class="el" href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5">sdrv_rstgen_general_reg_t</a> *rst_gen_reg, uint32_t val)</td></tr>
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<tr class="separator:af26011c9b69ad7af846f1b1078a6dbc0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4b3c16f1ab217cfe2a912ea001e87cd7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a4b3c16f1ab217cfe2a912ea001e87cd7">sdrv_rstgen_write_general_bit</a> (<a class="el" href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5">sdrv_rstgen_general_reg_t</a> *rst_gen_reg, uint8_t start, uint8_t <a class="el" href="warning__image_8h.html#aca34d28e3d8bcbcadb8edb4e3af24f8c">width</a>, uint32_t val)</td></tr>
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<tr class="memitem:a7cbe2d46015f48d329d35575999ee34e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a7cbe2d46015f48d329d35575999ee34e">sdrv_rstgen_lowpower_set</a> (<a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> *rst_sig, enum <a class="el" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874c">reset_lowpower_mode</a> mode, uint32_t val)</td></tr>
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<tr class="memitem:a9c6285cd7cc8c41956bf7f6c3970b94d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a9c6285cd7cc8c41956bf7f6c3970b94d">sdrv_rstgen_wdt_reset_enable</a> (<a class="el" href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017">reset_wdt_id_e</a> wdt, bool enable)</td></tr>
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<tr class="separator:a9c6285cd7cc8c41956bf7f6c3970b94d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeffb793b19f8ac6c847c56a35ca12933"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#aeffb793b19f8ac6c847c56a35ca12933">sdrv_rstgen_wdt_core_reset_enable</a> (<a class="el" href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017">reset_wdt_id_e</a> wdt, <a class="el" href="sdrv__rstgen_8h.html#a8dffb7fec18fcbb349994c9de703141a">reset_core_id_e</a> core, bool enable)</td></tr>
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<tr class="memitem:a9e0d89b5bf32daf40a926cf71f02ea6d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__rstgen_8h.html#a9e0d89b5bf32daf40a926cf71f02ea6d">sdrv_recovery_module</a> (<a class="el" href="sdrv__rstgen_8h.html#a5b0ade04f5bda906381772e55b4b97ac">sdrv_recovery_module_t</a> *recovery_module)</td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><dl class="section copyright"><dt>Copyright</dt><dd>Copyright (c) 2022 Semidrive Semiconductor. All rights reserved. </dd></dl>
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</div><h2 class="groupheader">Macro Definition Documentation</h2>
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<a id="a8699ca89f6c67b19a8ca21d2d9c2f75b" name="a8699ca89f6c67b19a8ca21d2d9c2f75b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a8699ca89f6c67b19a8ca21d2d9c2f75b">◆ </a></span>SDRV_RSTGEN_CORE</h2>
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<td class="memname">#define SDRV_RSTGEN_CORE   1</td>
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<a id="a57bfcf0c368182438491dd42b8359c81" name="a57bfcf0c368182438491dd42b8359c81"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a57bfcf0c368182438491dd42b8359c81">◆ </a></span>SDRV_RSTGEN_DEBUG</h2>
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<td class="memname">#define SDRV_RSTGEN_DEBUG   6</td>
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<a id="a3202225cb77b8c78c13499a12e7a2e5c" name="a3202225cb77b8c78c13499a12e7a2e5c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3202225cb77b8c78c13499a12e7a2e5c">◆ </a></span>SDRV_RSTGEN_GENERAL_REG_NUM</h2>
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<td class="memname">#define SDRV_RSTGEN_GENERAL_REG_NUM   8</td>
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<h2 class="memtitle"><span class="permalink"><a href="#ae6d9d8fbcc0f0b4077fc784f29a8d4bb">◆ </a></span>SDRV_RSTGEN_INDEX</h2>
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<td class="memname">#define SDRV_RSTGEN_INDEX</td>
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<td>(</td>
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<td class="paramname">id</td><td>)</td>
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<td>   ((uint32_t)(((uint32_t)(id)) & BIT_MASK(<a class="el" href="sdrv__rstgen_8h.html#a82cffc586c07ab9c6ff5722686883f28">SDRV_RSTGEN_TYPE_SHIFT</a>)))</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a1a200b16b0a6f9a83c1467b5e72b5ff9">◆ </a></span>SDRV_RSTGEN_IST</h2>
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<td class="memname">#define SDRV_RSTGEN_IST   5</td>
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<a id="a875382884d3d311f9d29eca8669850cf" name="a875382884d3d311f9d29eca8669850cf"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a875382884d3d311f9d29eca8669850cf">◆ </a></span>SDRV_RSTGEN_LATENT</h2>
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<td class="memname">#define SDRV_RSTGEN_LATENT   2</td>
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<a id="a941370b99bca07a9da90d27b3141bfe5" name="a941370b99bca07a9da90d27b3141bfe5"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a941370b99bca07a9da90d27b3141bfe5">◆ </a></span>SDRV_RSTGEN_MISSION</h2>
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<td class="memname">#define SDRV_RSTGEN_MISSION   3</td>
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<h2 class="memtitle"><span class="permalink"><a href="#af04d09fea7c19e3e59655f9fb0b79566">◆ </a></span>SDRV_RSTGEN_MODULE</h2>
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<td class="memname">#define SDRV_RSTGEN_MODULE   4</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a2700172ef9af08e3bd542075e5bccc6e">◆ </a></span>SDRV_RSTGEN_SIG_ID</h2>
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<td class="memname">#define SDRV_RSTGEN_SIG_ID</td>
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<td>(</td>
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<td class="paramtype"> </td>
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<td class="paramname">type, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"> </td>
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<td class="paramname">idx </td>
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<td></td>
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<td>)</td>
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<td></td><td>    ((uint32_t)((((uint32_t)(type)) << ((uint32_t)<a class="el" href="sdrv__rstgen_8h.html#a82cffc586c07ab9c6ff5722686883f28">SDRV_RSTGEN_TYPE_SHIFT</a>)) | ((uint32_t)(idx))))</td>
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<a id="ac3673063c1af75c7ad4b21a5f04b2647" name="ac3673063c1af75c7ad4b21a5f04b2647"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ac3673063c1af75c7ad4b21a5f04b2647">◆ </a></span>SDRV_RSTGEN_TYPE</h2>
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<td class="memname">#define SDRV_RSTGEN_TYPE</td>
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<td>(</td>
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<td class="paramname">id</td><td>)</td>
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<td>   ((uint32_t)(((uint32_t)(id)) >> ((uint32_t)<a class="el" href="sdrv__rstgen_8h.html#a82cffc586c07ab9c6ff5722686883f28">SDRV_RSTGEN_TYPE_SHIFT</a>)))</td>
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<a id="a82cffc586c07ab9c6ff5722686883f28" name="a82cffc586c07ab9c6ff5722686883f28"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a82cffc586c07ab9c6ff5722686883f28">◆ </a></span>SDRV_RSTGEN_TYPE_SHIFT</h2>
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<td class="memname">#define SDRV_RSTGEN_TYPE_SHIFT   24</td>
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<h2 class="groupheader">Typedef Documentation</h2>
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<a id="a8dffb7fec18fcbb349994c9de703141a" name="a8dffb7fec18fcbb349994c9de703141a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a8dffb7fec18fcbb349994c9de703141a">◆ </a></span>reset_core_id_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6">reset_core_id</a> <a class="el" href="sdrv__rstgen_8h.html#a8dffb7fec18fcbb349994c9de703141a">reset_core_id_e</a></td>
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<a id="a5a6258409dc5b32f5ea190ef6ff1c017" name="a5a6258409dc5b32f5ea190ef6ff1c017"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a5a6258409dc5b32f5ea190ef6ff1c017">◆ </a></span>reset_wdt_id_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4">reset_wdt_id</a> <a class="el" href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017">reset_wdt_id_e</a></td>
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<a id="a42d0646052af858609125621e12e73df" name="a42d0646052af858609125621e12e73df"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a42d0646052af858609125621e12e73df">◆ </a></span>sdrv_recovery_btm_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__recovery__btm.html">sdrv_recovery_btm</a> <a class="el" href="sdrv__rstgen_8h.html#a42d0646052af858609125621e12e73df">sdrv_recovery_btm_t</a></td>
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<p>semidrive recovery device. </p>
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<a id="a21f8bc5eeca047f8cfc64737db5f6233" name="a21f8bc5eeca047f8cfc64737db5f6233"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a21f8bc5eeca047f8cfc64737db5f6233">◆ </a></span>sdrv_recovery_epwm_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__recovery__epwm.html">sdrv_recovery_epwm</a> <a class="el" href="sdrv__rstgen_8h.html#a21f8bc5eeca047f8cfc64737db5f6233">sdrv_recovery_epwm_t</a></td>
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<a id="a1c688c1260c4ac042088825c62e283f6" name="a1c688c1260c4ac042088825c62e283f6"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a1c688c1260c4ac042088825c62e283f6">◆ </a></span>sdrv_recovery_etimer_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__recovery__etimer.html">sdrv_recovery_etimer</a> <a class="el" href="sdrv__rstgen_8h.html#a1c688c1260c4ac042088825c62e283f6">sdrv_recovery_etimer_t</a></td>
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<a id="a5b0ade04f5bda906381772e55b4b97ac" name="a5b0ade04f5bda906381772e55b4b97ac"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a5b0ade04f5bda906381772e55b4b97ac">◆ </a></span>sdrv_recovery_module_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__recovery__module.html">sdrv_recovery_module</a> <a class="el" href="sdrv__rstgen_8h.html#a5b0ade04f5bda906381772e55b4b97ac">sdrv_recovery_module_t</a></td>
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<a id="a92e5731422c69ec1c5fff5495238eab5" name="a92e5731422c69ec1c5fff5495238eab5"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a92e5731422c69ec1c5fff5495238eab5">◆ </a></span>sdrv_rstgen_general_reg_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__rstgen__general__reg.html">sdrv_rstgen_general_reg</a> <a class="el" href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5">sdrv_rstgen_general_reg_t</a></td>
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<p>SDRV rstgen general register. </p>
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<a id="aa1e8467a7125039f34727e96720472bd" name="aa1e8467a7125039f34727e96720472bd"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa1e8467a7125039f34727e96720472bd">◆ </a></span>sdrv_rstgen_glb_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__rstgen__glb__ctl.html">sdrv_rstgen_glb_ctl</a> <a class="el" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a></td>
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<p>SDRV rstgen global reset controller. </p>
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<a id="a81742b8488efdd1527d7b6e4c9fb16ed" name="a81742b8488efdd1527d7b6e4c9fb16ed"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a81742b8488efdd1527d7b6e4c9fb16ed">◆ </a></span>sdrv_rstgen_sig_handler</h2>
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<td class="memname">typedef void(* sdrv_rstgen_sig_handler) (uint32_t rstgen_sig_id)</td>
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<p>semidrive reset sig handler. </p>
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<p >call pre handler before reset/assert signal, and call post handler after reset/deassert signal, if necessary. </p>
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<a id="a41d48b277bbb9e943071ea368e876125" name="a41d48b277bbb9e943071ea368e876125"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a41d48b277bbb9e943071ea368e876125">◆ </a></span>sdrv_rstgen_sig_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__rstgen__sig.html">sdrv_rstgen_sig</a> <a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a></td>
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<p>SDRV rstgen signal. </p>
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<td class="memname">typedef struct <a class="el" href="structsdrv__rstgen.html">sdrv_rstgen</a> <a class="el" href="sdrv__rstgen_8h.html#a7ee8f465807f25ace997be437181cf5d">sdrv_rstgen_t</a></td>
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<p>SDRV rstgen controller. </p>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a338f7ed846d720e8eda0201ecd3e4ce6">◆ </a></span>reset_core_id</h2>
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<td class="memname">enum <a class="el" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6">reset_core_id</a></td>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a338f7ed846d720e8eda0201ecd3e4ce6a5daca59ed51f1e2889d65586a364cf9b" name="a338f7ed846d720e8eda0201ecd3e4ce6a5daca59ed51f1e2889d65586a364cf9b"></a>RESET_CORE_SF </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a338f7ed846d720e8eda0201ecd3e4ce6ad406e35953141f83ad359e3b73c0195c" name="a338f7ed846d720e8eda0201ecd3e4ce6ad406e35953141f83ad359e3b73c0195c"></a>RESET_CORE_SP0 </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a338f7ed846d720e8eda0201ecd3e4ce6a1f4a157eafa37a4aca8805d28e85bcbe" name="a338f7ed846d720e8eda0201ecd3e4ce6a1f4a157eafa37a4aca8805d28e85bcbe"></a>RESET_CORE_SP1 </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a338f7ed846d720e8eda0201ecd3e4ce6ac4f70f8d2f0723899a4cef2f42531a35" name="a338f7ed846d720e8eda0201ecd3e4ce6ac4f70f8d2f0723899a4cef2f42531a35"></a>RESET_CORE_SX0 </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a338f7ed846d720e8eda0201ecd3e4ce6ae0a3422be08c341afe381a47dc4e9230" name="a338f7ed846d720e8eda0201ecd3e4ce6ae0a3422be08c341afe381a47dc4e9230"></a>RESET_CORE_SX1 </td><td class="fielddoc"></td></tr>
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<a id="a6eb9e62ef9966b9f79ac98f479c3874c" name="a6eb9e62ef9966b9f79ac98f479c3874c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a6eb9e62ef9966b9f79ac98f479c3874c">◆ </a></span>reset_lowpower_mode</h2>
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<td class="memname">enum <a class="el" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874c">reset_lowpower_mode</a></td>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a6eb9e62ef9966b9f79ac98f479c3874caee6743bff37e3cf2575abfb45ed46979" name="a6eb9e62ef9966b9f79ac98f479c3874caee6743bff37e3cf2575abfb45ed46979"></a>RESET_LP_HIB </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a6eb9e62ef9966b9f79ac98f479c3874ca55f22e14d5b74467fb22464287185cc3" name="a6eb9e62ef9966b9f79ac98f479c3874ca55f22e14d5b74467fb22464287185cc3"></a>RESET_LP_SLEEP </td><td class="fielddoc"></td></tr>
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<a id="ac3922a71f3ae5643e43aee964112e0e4" name="ac3922a71f3ae5643e43aee964112e0e4"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ac3922a71f3ae5643e43aee964112e0e4">◆ </a></span>reset_wdt_id</h2>
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<td class="memname">enum <a class="el" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4">reset_wdt_id</a></td>
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</div><div class="memdoc">
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ac3922a71f3ae5643e43aee964112e0e4af85f5ea2a79400704796fcf14a74e4e2" name="ac3922a71f3ae5643e43aee964112e0e4af85f5ea2a79400704796fcf14a74e4e2"></a>RESET_WDT1 </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="ac3922a71f3ae5643e43aee964112e0e4ab77c8d24a1cae6d5f89dacf59e737874" name="ac3922a71f3ae5643e43aee964112e0e4ab77c8d24a1cae6d5f89dacf59e737874"></a>RESET_WDT2 </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="ac3922a71f3ae5643e43aee964112e0e4a6cf810cc314bc89d88eefcc864d9e66e" name="ac3922a71f3ae5643e43aee964112e0e4a6cf810cc314bc89d88eefcc864d9e66e"></a>RESET_WDT3 </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="ac3922a71f3ae5643e43aee964112e0e4a5f97dc4aaff0c408ed468d4c0bce8758" name="ac3922a71f3ae5643e43aee964112e0e4a5f97dc4aaff0c408ed468d4c0bce8758"></a>RESET_WDT4 </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="ac3922a71f3ae5643e43aee964112e0e4aba07ff62f906c3b381cadfa40feaf3a0" name="ac3922a71f3ae5643e43aee964112e0e4aba07ff62f906c3b381cadfa40feaf3a0"></a>RESET_WDT5 </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="ac3922a71f3ae5643e43aee964112e0e4a14ad451c2dac6f555dd93ca4bf72b638" name="ac3922a71f3ae5643e43aee964112e0e4a14ad451c2dac6f555dd93ca4bf72b638"></a>RESET_WDT6 </td><td class="fielddoc"></td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a3c844a646e50c274a3d86b965fdbdd8d">◆ </a></span>sdrv_reset_error</h2>
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<td class="memname">enum <a class="el" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8d">sdrv_reset_error</a></td>
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<p>RESET status error code. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a3c844a646e50c274a3d86b965fdbdd8dad1b57de90df5b6f0a24c99a2251fb6a5" name="a3c844a646e50c274a3d86b965fdbdd8dad1b57de90df5b6f0a24c99a2251fb6a5"></a>SDRV_RESET_STATUS_SIGNAL_ASSERT </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a3c844a646e50c274a3d86b965fdbdd8dac6a6e5ddd79dd814b49646d021ab3d83" name="a3c844a646e50c274a3d86b965fdbdd8dac6a6e5ddd79dd814b49646d021ab3d83"></a>SDRV_RESET_STATUS_LOCK </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a3c844a646e50c274a3d86b965fdbdd8da47eaf13d223bf25cc064e593aaedf1a9" name="a3c844a646e50c274a3d86b965fdbdd8da47eaf13d223bf25cc064e593aaedf1a9"></a>SDRV_RESET_STATUS_TIMEOUT </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a3c844a646e50c274a3d86b965fdbdd8da31f84ee6f527370a15698b1a101b054a" name="a3c844a646e50c274a3d86b965fdbdd8da31f84ee6f527370a15698b1a101b054a"></a>SDRV_RESET_STATUS_WRONG_SIGNAL </td><td class="fielddoc"></td></tr>
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</table>
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</div>
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<h2 class="groupheader">Function Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a9e0d89b5bf32daf40a926cf71f02ea6d">◆ </a></span>sdrv_recovery_module()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="el" href="structsdrv__recovery__module.html">sdrv_recovery_module</a> </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a5b0ade04f5bda906381772e55b4b97ac">sdrv_recovery_module_t</a> * </td>
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<td class="paramname"><em>recovery_module</em></td><td>)</td>
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<td></td>
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<p>sdrv recovery latent module. </p>
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<p >Some latent modules (btm/etimer/epwm etc.) will be not reset when core is reset, so these modules should be recovery when core restart.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">recovery_module</td><td>recovery latent module list </td></tr>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>0 if success, or a negative error code. </dd></dl>
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</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a90eb1f94509a65eec0ef47e9cab365dc">◆ </a></span>sdrv_rstgen_assert()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_assert </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> * </td>
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<td class="paramname"><em>rst_sig</em></td><td>)</td>
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<p>Assert a reset signal. </p>
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<p >The reset singal will stay asserted until reset_deassert() is called.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_sig</td><td>Reset signal. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>0 if OK, or a negative error code. </dd></dl>
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</div>
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<a id="a2cd8666bfe5ca507530dfb003faa1b15" name="a2cd8666bfe5ca507530dfb003faa1b15"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a2cd8666bfe5ca507530dfb003faa1b15">◆ </a></span>sdrv_rstgen_current_global_status()</h2>
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<td class="memname">uint32_t sdrv_rstgen_current_global_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a> * </td>
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<td class="paramname"><em>rst_glb_ctl</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>Check current global reset status. </p>
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<p >Global reset status only for the last time. If multiple reset source comes neatly the same time, only the first one will be recorded.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_glb_ctl</td><td>Global reset controller. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SF and AP domain current global reset status. bit[31:25] for rstgen AP: bit[31] rstgen ap software global reset bit[30] reserved bit[29] efusec security violation bit[28] system panic(vdc function irq) bit[27] sem1/sem2 error bit[26] reserved bit[25] PT sensor interrupt bit[24:0] for rstgen SF: bit[24] wdt6 int reset request bit[23] wdt6 int reset request bit[22] wdt4 int reset request bit[21] wdt4 int reset request bit[20] wdt2 int reset request bit[19] reserved bit[18] wdt5 int reset request bit[17] wdt5 int reset request bit[16] wdt3 int reset request bit[15] wdt3 int reset request bit[14] wdt1 int reset request bit[13] reserved bit[12] ist done fail bit[11] rstgen sf software global reset bit[10] reserved bit[9] wdt2 int reset request (Only for E3104/E3106/E3205/E3206) bit[8] wdt1 int reset request (Only for E3104/E3106/E3205/E3206) bit[7] ist done fail (Only for E3104/E3106/E3205/E3206) bit[6] rstgen sf software global reset (Only for E3104/E3106/E3205/E3206) bit[5] rstgen ap cold reset request bit[4] efusec security violation bit[3] system panic(vdc function irq) bit[2] sem1/sem2 error bit[1] reserved bit[0] PT sensor interrupt Especially, bit[31:10] are invalid for E3104/E3106/E3205/E3206. </dd></dl>
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<a id="aa6189f234be2939d24c0b9e543ec6442" name="aa6189f234be2939d24c0b9e543ec6442"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa6189f234be2939d24c0b9e543ec6442">◆ </a></span>sdrv_rstgen_deassert()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_deassert </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> * </td>
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<td class="paramname"><em>rst_sig</em></td><td>)</td>
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<p>Deassert a reset signal. </p>
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<p >Release a reset signal.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_sig</td><td>Reset signal. </td></tr>
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</table>
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</dd>
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<dl class="section return"><dt>Returns</dt><dd>0 if OK, or a negative error code. </dd></dl>
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<a id="a10dde50d7ec285cde7a052ee221c6713" name="a10dde50d7ec285cde7a052ee221c6713"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a10dde50d7ec285cde7a052ee221c6713">◆ </a></span>sdrv_rstgen_global_reset()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_global_reset </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a> * </td>
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<td class="paramname"><em>rst_glb_ctl</em></td><td>)</td>
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<p>Global reset. </p>
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<p >Global reset SF/AP domain</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_glb_ctl</td><td>Global reset controller. </td></tr>
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</table>
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<dl class="section return"><dt>Returns</dt><dd>0 if OK, or a negative error code. </dd></dl>
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<a id="a43254dd94c3b9d923b73c189996299c2" name="a43254dd94c3b9d923b73c189996299c2"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a43254dd94c3b9d923b73c189996299c2">◆ </a></span>sdrv_rstgen_global_status()</h2>
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<td class="memname">uint32_t sdrv_rstgen_global_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a> * </td>
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<td class="paramname"><em>rst_glb_ctl</em></td><td>)</td>
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<td></td>
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<p>Check global reset status. </p>
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<p >Global reset status for all the time, including each global reset status before clear or power off. If multiple reset source comes neatly the same time, only the first one will be recorded.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_glb_ctl</td><td>Global reset controller. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>SF and AP domain global reset status. bit[31:25] for rstgen AP: bit[31] rstgen ap software global reset bit[30] reserved bit[29] efusec security violation bit[28] system panic(vdc function irq) bit[27] sem1/sem2 error bit[26] reserved bit[25] PT sensor interrupt bit[24:0] for rstgen SF: bit[24] wdt6 int reset request bit[23] wdt6 int reset request bit[22] wdt4 int reset request bit[21] wdt4 int reset request bit[20] wdt2 int reset request bit[19] reserved bit[18] wdt5 int reset request bit[17] wdt5 int reset request bit[16] wdt3 int reset request bit[15] wdt3 int reset request bit[14] wdt1 int reset request bit[13] reserved bit[12] ist done fail bit[11] rstgen sf software global reset bit[10] reserved bit[9] wdt2 int reset request (Only for E3104/E3106/E3205/E3206) bit[8] wdt1 int reset request (Only for E3104/E3106/E3205/E3206) bit[7] ist done fail (Only for E3104/E3106/E3205/E3206) bit[6] rstgen sf software global reset (Only for E3104/E3106/E3205/E3206) bit[5] rstgen ap cold reset request bit[4] efusec security violation bit[3] system panic(vdc function irq) bit[2] sem1/sem2 error bit[1] reserved bit[0] PT sensor interrupt Especially, bit[31:10] are invalid for E3104/E3106/E3205/E3206. </dd></dl>
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<a id="a0432a9bac0e2a616cfe8a6100019c123" name="a0432a9bac0e2a616cfe8a6100019c123"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a0432a9bac0e2a616cfe8a6100019c123">◆ </a></span>sdrv_rstgen_global_status_clear()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_global_status_clear </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a> * </td>
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<td class="paramname"><em>rst_glb_ctl</em></td><td>)</td>
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<p>clear global reset status. </p>
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<p >Clear global reset status, otherwise the status will keep until power off.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_glb_ctl</td><td>Global reset controller. </td></tr>
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<h2 class="memtitle"><span class="permalink"><a href="#a7cbe2d46015f48d329d35575999ee34e">◆ </a></span>sdrv_rstgen_lowpower_set()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_lowpower_set </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> * </td>
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<td class="paramname"><em>rst_sig</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">enum <a class="el" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874c">reset_lowpower_mode</a> </td>
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<td class="paramname"><em>mode</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>val</em> </td>
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<tr>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Config reset signal assert/deassert in lowpower mode. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_sig</td><td>Reset signal. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>lowpower mode </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">val</td><td>0:assert, 1:deassert</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>0 if OK, or a negative error code. </dd></dl>
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</div>
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<a id="a32b88bc068653b8f08eae962b0060a40" name="a32b88bc068653b8f08eae962b0060a40"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a32b88bc068653b8f08eae962b0060a40">◆ </a></span>sdrv_rstgen_read_general()</h2>
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<td class="memname">uint32_t sdrv_rstgen_read_general </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5">sdrv_rstgen_general_reg_t</a> * </td>
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<td class="paramname"><em>rst_gen_reg</em></td><td>)</td>
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<p>Read reset general reg. </p>
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<p >The data saved in general regs will be not lost until SOC power down.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_gen_reg</td><td>reset general reg. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>general reg value. </dd></dl>
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</div>
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</div>
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<a id="a7b24afa273fa54f81963c02942e858d8" name="a7b24afa273fa54f81963c02942e858d8"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a7b24afa273fa54f81963c02942e858d8">◆ </a></span>sdrv_rstgen_reset()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_reset </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> * </td>
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<td class="paramname"><em>rst_sig</em></td><td>)</td>
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<td></td>
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<p>Reset a reset signal. </p>
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<p >Assert a reset signal, and then deassert it automatically.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_sig</td><td>Reset signal. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>0 if OK, or a negative error code. </dd></dl>
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</div>
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</div>
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<a id="a0726f32906766eb1b8dfb2ba3d38f1fc" name="a0726f32906766eb1b8dfb2ba3d38f1fc"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a0726f32906766eb1b8dfb2ba3d38f1fc">◆ </a></span>sdrv_rstgen_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a> * </td>
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<td class="paramname"><em>rst_sig</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Check reset signal status. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_sig</td><td>Reset signal. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>0 if deasserted, or a negative error code. </dd></dl>
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</div>
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</div>
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<a id="aeffb793b19f8ac6c847c56a35ca12933" name="aeffb793b19f8ac6c847c56a35ca12933"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aeffb793b19f8ac6c847c56a35ca12933">◆ </a></span>sdrv_rstgen_wdt_core_reset_enable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_wdt_core_reset_enable </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017">reset_wdt_id_e</a> </td>
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<td class="paramname"><em>wdt</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a8dffb7fec18fcbb349994c9de703141a">reset_core_id_e</a> </td>
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<td class="paramname"><em>core</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Config wdt cause single core reset enable. </p>
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<p >Config watchdog timeout trigger core reset. Each core has two watchdog, WDT1 and WDT2 belongs to SF, WDT3 and WDT4 belongs to SP0/SP1, WDT5 and WDT6 belongs to SX0/SX1. SP1 and SX1 can be reset alone, if SP0 or SX0 be reset, SP1 or SX1 will reset followed.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">wdt</td><td>wdt id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">core</td><td>core id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>true/false </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>0 if success, or a negative error code. </dd></dl>
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</div>
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</div>
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<a id="a9c6285cd7cc8c41956bf7f6c3970b94d" name="a9c6285cd7cc8c41956bf7f6c3970b94d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a9c6285cd7cc8c41956bf7f6c3970b94d">◆ </a></span>sdrv_rstgen_wdt_reset_enable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_wdt_reset_enable </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017">reset_wdt_id_e</a> </td>
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<td class="paramname"><em>wdt</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Config wdt cause global reset enable. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">wdt</td><td>wdt id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>true/false </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>0 if success, or a negative error code. </dd></dl>
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</div>
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</div>
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<a id="af26011c9b69ad7af846f1b1078a6dbc0" name="af26011c9b69ad7af846f1b1078a6dbc0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#af26011c9b69ad7af846f1b1078a6dbc0">◆ </a></span>sdrv_rstgen_write_general()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_write_general </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5">sdrv_rstgen_general_reg_t</a> * </td>
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<td class="paramname"><em>rst_gen_reg</em>, </td>
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</tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>val</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Write reset general reg. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_gen_reg</td><td>reset general reg. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">val</td><td>write value. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>0 if success, or a negative error code. </dd></dl>
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</div>
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</div>
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<a id="a4b3c16f1ab217cfe2a912ea001e87cd7" name="a4b3c16f1ab217cfe2a912ea001e87cd7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a4b3c16f1ab217cfe2a912ea001e87cd7">◆ </a></span>sdrv_rstgen_write_general_bit()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_rstgen_write_general_bit </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5">sdrv_rstgen_general_reg_t</a> * </td>
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<td class="paramname"><em>rst_gen_reg</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint8_t </td>
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<td class="paramname"><em>start</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype">uint8_t </td>
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<td class="paramname"><em>width</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>val</em> </td>
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<tr>
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<td></td>
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<td>)</td>
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<p>Write reset general reg bit. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">rst_gen_reg</td><td>reset general reg. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">start</td><td>write start bit. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">width</td><td>write bit width. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">val</td><td>write value. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>0 if success, or a negative error code. </dd></dl>
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