/** ************************************************************************************************
 * SEMIDRIVE Copyright Statement
 * Copyright (c) SEMIDRIVE. All rights reserved
 *
 * This software and all rights therein are owned by SEMIDRIVE, and are
 * protected by copyright law and other relevant laws, regulations and
 * protection. Without SEMIDRIVE's prior written consent and/or related rights,
 * please do not use this software or any potion thereof in any form or by any
 * means. You may not reproduce, modify or distribute this software except in
 * compliance with the License. Unless required by applicable law or agreed to
 * in writing, software distributed under the License is distributed on
 * an 'AS IS' basis, WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 **************************************************************************************************/
/** ************************************************************************************************
 * \file     sdrv_firewall_gpio.c
 * \brief    SSDK Firewall GPIO Driver
 *
 * <table>
 * <tr><th>Date           <th>Version
 * <tr><td>2023/11/29     <td>1.0.0
 * </table>
 **************************************************************************************************/

#ifdef __cplusplus
extern "C" {
#endif

/***************************************************************************************************
 *                                      Include header files
 **************************************************************************************************/
#include <reg.h>
#include "sdrv_firewall_gpio.h"

/***************************************************************************************************
 *                                 Private Macro definition
 **************************************************************************************************/
/** \brief The offset bit of privilege mode permission for domain0. */
#define FIREWALL_GPIO_DOM0_PRIVILEGED_BIT (4U)
/** \brief The offset bit of user mode permission for domain0. */
#define FIREWALL_GPIO_DOM0_USER_BIT       (6U)
/** \brief The offset bit of privilege mode permission for domain1. */
#define FIREWALL_GPIO_DOM1_PRIVILEGED_BIT (12U)
/** \brief The offset bit of user mode permission for domain1. */
#define FIREWALL_GPIO_DOM1_USER_BIT       (14U)
/** \brief The offset bit of privilege mode permission for domain2. */
#define FIREWALL_GPIO_DOM2_PRIVILEGED_BIT (20U)
/** \brief The offset bit of user mode permission for domain2. */
#define FIREWALL_GPIO_DOM2_USER_BIT       (22U)
/** \brief The offset bit of privilege mode permission for domain3. */
#define FIREWALL_GPIO_DOM3_PRIVILEGED_BIT (28U)
/** \brief The offset bit of user mode permission for domain3. */
#define FIREWALL_GPIO_DOM3_USER_BIT       (30U)
/** \brief The offset bit of privilege mode permission for domain4. */
#define FIREWALL_GPIO_DOM4_PRIVILEGED_BIT (4U)
/** \brief The offset bit of user mode permission for domain4. */
#define FIREWALL_GPIO_DOM4_USER_BIT       (6U)
/** \brief The offset bit of privilege mode permission for domain5. */
#define FIREWALL_GPIO_DOM5_PRIVILEGED_BIT (12U)
/** \brief The offset bit of user mode permission for domain5. */
#define FIREWALL_GPIO_DOM5_USER_BIT       (14U)
/** \brief The offset bit of privilege mode permission for domain6. */
#define FIREWALL_GPIO_DOM6_PRIVILEGED_BIT (20U)
/** \brief The offset bit of user mode permission for domain6. */
#define FIREWALL_GPIO_DOM6_USER_BIT       (22U)
/** \brief The offset bit of privilege mode permission for domain7. */
#define FIREWALL_GPIO_DOM7_PRIVILEGED_BIT (28U)
/** \brief The offset bit of user mode permission for domain7. */
#define FIREWALL_GPIO_DOM7_USER_BIT       (30U)

/** \brief The offset address of the gpio permission0 register. */
#define FIREWALL_GPIO_DOM_PER0N_0         ((uint32_t)0x00U)
/** \brief The size of the gpio permission0 register. */
#define FIREWALL_GPIO_DOM_PER0N_SIZE      ((uint32_t)0x0CU)
/** \brief The offset address of the gpio permission0 register for different cores. */
#define FIREWALL_GPIO_DOM_PER0N_ADDR(n)                                        \
    (FIREWALL_GPIO_DOM_PER0N_0 + ((n)*FIREWALL_GPIO_DOM_PER0N_SIZE))

/** \brief The offset address of the gpio permission1 register. */
#define FIREWALL_GPIO_DOM_PER1N_0    ((uint32_t)0x04U)
/** \brief The size of the gpio permission1 register. */
#define FIREWALL_GPIO_DOM_PER1N_SIZE ((uint32_t)0x0CU)
/** \brief The offset address of the gpio permission1 register for different cores. */
#define FIREWALL_GPIO_DOM_PER1N_ADDR(n)                                        \
    (FIREWALL_GPIO_DOM_PER1N_0 + ((n)*FIREWALL_GPIO_DOM_PER1N_SIZE))

/** \brief The offset address of the gpio permission lock register. */
#define FIREWALL_GPIO_DOM_PER_LOCKN_0    ((uint32_t)0x08U)
/** \brief The size of the gpio permission lock register. */
#define FIREWALL_GPIO_DOM_PER_LOCKN_SIZE ((uint32_t)0x0CU)
/** \brief The bit mask of locking the gpio permission. */
#define FIREWALL_GPIO_DOM_PER_LOCK       (0xFFUL)
/** \brief The offset address of the gpio permission lock register for different cores. */
#define FIREWALL_GPIO_DOM_PER_LOCKN_ADDR(n)                                    \
    (FIREWALL_GPIO_DOM_PER_LOCKN_0 + ((n)*FIREWALL_GPIO_DOM_PER_LOCKN_SIZE))

/** \brief The offset address of the gpio core select register. */
#define FIREWALL_GPIO_DGSELN_0      ((uint32_t)0x140U)
/** \brief The size of the gpio core select register. */
#define FIREWALL_GPIO_DGSELN_SIZE   ((uint32_t)0x04U)
/** \brief The offset bit of the gpio core select. */
#define FIREWALL_GPIO_RGN_DGSEL_BIT (1U)
/** \brief The bit mask of enabling the gpio permission control. */
#define FIREWALL_GPIO_RGN_EN        (1UL)
/** \brief The bit mask of locking the gpio permission control. */
#define FIREWALL_GPIO_RGN_LOCK      (1UL << 31U)
/** \brief The offset address of the gpio core select register for different pin channels. */
#define FIREWALL_GPIO_DGSELN_ADDR(n)                                           \
    (FIREWALL_GPIO_DGSELN_0 + ((n)*FIREWALL_GPIO_DGSELN_SIZE))

/***************************************************************************************************
 *                                  Private Function Declarations
 **************************************************************************************************/
static status_t sdrv_firewall_gpio_select_core(
    const sdrv_gpio_channel_cfg_t *gpio_channel_cfg, uint8_t core_id);

static status_t sdrv_firewall_gpio_permission_configure(
    const sdrv_gpio_core_cfg_t *gpio_cfg);

/***************************************************************************************************
 *                                  Global Function Declarations
 **************************************************************************************************/
/**
 * @brief Configure the gpio rule space and perimissions.
 *
 * This function Configure the gpio rule space and perimissions.
 * This function should be called only once.
 *
 * @param[in] io_cfg the configuration of pin permission.
 * @param[in] core_num the number of cores.
 *
 * @return The result of this function.
 * @details - return FIREWALL_E_OK : Configure the gpio rule space and perimissions success.
 *          - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
 *          - return FIREWALL_E_GPIO_CORE_NUM : The number of the core configurations is unvalid.
 */
status_t sdrv_firewall_gpio_rulespace_configure(
    const sdrv_gpio_core_cfg_t *io_cfg, uint8_t core_num)
{
    status_t ret_val = FIREWALL_E_OK;
    uint8_t core_id;

    if (NULL == io_cfg)
    {
        ret_val = FIREWALL_E_NULL_POINTER;
    }
    else if (FIREWALL_GPIO_CORE_MAXNUM < core_num)
    {
        ret_val = FIREWALL_E_GPIO_CORE_NUM;
    }
    else
    {
        /* #20 Configure the rule of gpio pins. */
        for (core_id = 0U; core_id < core_num; ++core_id)
        {
            /* Assign gpio pins to the specified core. */
            ret_val = sdrv_firewall_gpio_select_core(
                &io_cfg[core_id].gpio_channel_cfg,
                io_cfg[core_id].gpio_core_id);
            if (FIREWALL_E_OK == ret_val)
            {
                /* Configure the permissions of gpio pins for the core. */
                ret_val =
                    sdrv_firewall_gpio_permission_configure(&io_cfg[core_id]);
            } /* else not needed */

            if (FIREWALL_E_OK != ret_val)
            {
                break;
            } /* else not needed */
        }
    }

    return ret_val;
}

/**
 * @brief Lock the configurations of the gpio rule space and perimissions.
 *
 * This function locks the configurations of the gpio rule space and perimissions.
 * This function is called by sdrv_firewall_init().
 * This function should be called after sdrv_firewall_gpio_rulespace_configure().
 */
void sdrv_firewall_gpio_rulespace_Lock(void)
{
    uint32_t gpio_base = 0U;
    uint16_t channel_id;
    uint16_t channel_num;
    uint32_t temp_val;
    uint8_t core_id;

    /* #10 Lock the assignment of all gpio pins. */
    for (channel_num = 0U; channel_num < FIREWALL_GPIO_CHANNEL_MAXNUM;
         ++channel_num)
    {
        channel_id = channel_num;
        (void)sdrv_firewall_gpio_get_base_addr(&channel_id, &gpio_base);
        temp_val = readl(gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));
        writel(temp_val | (uint32_t)FIREWALL_GPIO_RGN_LOCK,
               gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));
    }

    /* #20 Lock the permissions of gpio pins for different cores. */
    for (core_id = 0U; core_id < FIREWALL_GPIO_CORE_MAXNUM; ++core_id)
    {
        writel((uint32_t)FIREWALL_GPIO_DOM_PER_LOCK,
               FIREWALL_APB_GPIO_SF_BASE +
                   FIREWALL_GPIO_DOM_PER_LOCKN_ADDR(core_id));
#ifdef FIREWALL_APB_GPIO_AP_BASE
        writel((uint32_t)FIREWALL_GPIO_DOM_PER_LOCK,
               FIREWALL_APB_GPIO_AP_BASE +
                   FIREWALL_GPIO_DOM_PER_LOCKN_ADDR(core_id));
#endif /* #ifdef FIREWALL_APB_GPIO_AP_BASE */
    }
}

/***************************************************************************************************
 *                                  Private Function Declarations
 **************************************************************************************************/
/**
 * @brief Configure the gpio pin rule space.
 *
 * This function is called by sdrv_firewall_gpio_rulespace_configure().
 *
 * @param[in] gpio_channel_cfg The pointer to the gpio pin configurations.
 * @param[in] core_id The id of the core.
 *
 * @return The result of this function.
 * @details - return FIREWALL_E_OK : Configure the gpio rule space success.
 *          - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
 *          - return FIREWALL_E_GPIO_CHANNEL_NUM : The number of the gpio pin channels is unvalid.
 */
static status_t sdrv_firewall_gpio_select_core(
    const sdrv_gpio_channel_cfg_t *gpio_channel_cfg, uint8_t core_id)
{
    status_t ret_val = FIREWALL_E_OK;
    uint32_t gpio_base = 0U;
    uint16_t channel_id;
    uint16_t channel_cfgnum;
    uint16_t channel_num;
    uint32_t temp_val;

    /* #10 Check the parameters. */
    if (NULL == gpio_channel_cfg->gpio_channel_id)
    {
        ret_val = FIREWALL_E_NULL_POINTER;
    }
    else if (FIREWALL_GPIO_CHANNEL_MAXNUM < gpio_channel_cfg->gpio_channel_num)
    {
        ret_val = FIREWALL_E_GPIO_CHANNEL_NUM;
    }
    else
    {
        channel_cfgnum = gpio_channel_cfg->gpio_channel_num;

        /* #20 Assign gpio pins to the specified core. */
        for (channel_num = 0U; channel_num < channel_cfgnum; ++channel_num)
        {
            channel_id = gpio_channel_cfg->gpio_channel_id[channel_num];
            if (!sdrv_firewall_gpio_get_base_addr(&channel_id, &gpio_base))
            {
                ret_val = FIREWALL_E_GPIO_CHANNEL_ID;
            }
            if (FIREWALL_E_OK == ret_val)
            {
                /* Select the assignment of the gpio pin. */
                writel((uint32_t)core_id << FIREWALL_GPIO_RGN_DGSEL_BIT,
                       gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));

                /* Enable the assignment of the gpio pin. */
                temp_val =
                    readl(gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));
                writel(temp_val | (uint32_t)FIREWALL_GPIO_RGN_EN,
                       gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));
            } /* else not needed */
        }
    }

    return ret_val;
}

/**
 * @brief Configure the permissions of the gpio pin for the core.
 *
 * This function is called by sdrv_firewall_gpio_rulespace_configure().
 *
 * @param[in] gpio_cfg The pointer to the gpio pin configurations.
 *
 * @return The result of this function.
 * @details - return FIREWALL_E_OK : Configure the gpio rule space perimissions success.
 *          - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
 *          - return FIREWALL_E_GPIO_CORE_ID : The id of the core is unvalid.
 */
static status_t sdrv_firewall_gpio_permission_configure(
    const sdrv_gpio_core_cfg_t *gpio_cfg)
{
    status_t ret_val = FIREWALL_E_OK;
    uint32_t domain_permission0;
    uint32_t domain_permission1;

    /* #10 Check the parameters. */
    if (NULL == gpio_cfg)
    {
        ret_val = FIREWALL_E_NULL_POINTER;
    }
    else
    {
        /* Config lock/unlock/dma domain permission. */
        domain_permission0 = (uint32_t)FIREWALL_PERMISSION_RW
                             << FIREWALL_GPIO_DOM0_PRIVILEGED_BIT;
        domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_RW
                              << FIREWALL_GPIO_DOM0_USER_BIT;
        domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                              << FIREWALL_GPIO_DOM1_PRIVILEGED_BIT;
        domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                              << FIREWALL_GPIO_DOM1_USER_BIT;
        /* #20 Configure permissions of gpio pins for the specified core. */
        switch (gpio_cfg->gpio_core_id)
        {
#ifdef FIREWALL_GPIO_DGSEL_CORE0
            case FIREWALL_GPIO_DGSEL_CORE0:
                /* Configure permissions of gpio pins for all core domains. */
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM2_USER_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM3_USER_BIT;

                domain_permission1 = (uint32_t)FIREWALL_PERMISSION_NONE
                                     << FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM4_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM5_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_USER_BIT;
                domain_permission1 |=
                    ((uint32_t)gpio_cfg->gpio_privileged_permission)
                    << FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
                domain_permission1 |= ((uint32_t)gpio_cfg->gpio_user_permission)
                                      << FIREWALL_GPIO_DOM7_USER_BIT;
                break;
#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE0 */
#ifdef FIREWALL_GPIO_DGSEL_CORE1
            case FIREWALL_GPIO_DGSEL_CORE1:
                /* Configure permissions of gpio pins for all core domains. */
                domain_permission0 |=
                    ((uint32_t)gpio_cfg->gpio_privileged_permission)
                    << FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
                domain_permission0 |= ((uint32_t)gpio_cfg->gpio_user_permission)
                                      << FIREWALL_GPIO_DOM2_USER_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM3_USER_BIT;

                domain_permission1 = (uint32_t)FIREWALL_PERMISSION_NONE
                                     << FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM4_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM5_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM7_USER_BIT;
                break;
#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE1 */
#ifdef FIREWALL_GPIO_DGSEL_CORE2
            case FIREWALL_GPIO_DGSEL_CORE2:
                /* Configure permissions of gpio pins for all core domains. */
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM2_USER_BIT;
                domain_permission0 |=
                    ((uint32_t)gpio_cfg->gpio_privileged_permission)
                    << FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
                domain_permission0 |= ((uint32_t)gpio_cfg->gpio_user_permission)
                                      << FIREWALL_GPIO_DOM3_USER_BIT;

                domain_permission1 = (uint32_t)FIREWALL_PERMISSION_NONE
                                     << FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM4_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM5_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM7_USER_BIT;
                break;
#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE2 */
#ifdef FIREWALL_GPIO_DGSEL_CORE3
            case FIREWALL_GPIO_DGSEL_CORE3:
                /* Configure permissions of gpio pins for all core domains. */
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM2_USER_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM3_USER_BIT;

                domain_permission1 =
                    ((uint32_t)gpio_cfg->gpio_privileged_permission)
                    << FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
                domain_permission1 |= ((uint32_t)gpio_cfg->gpio_user_permission)
                                      << FIREWALL_GPIO_DOM4_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM5_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM7_USER_BIT;
                break;
#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE3 */
#ifdef FIREWALL_GPIO_DGSEL_CORE4
            case FIREWALL_GPIO_DGSEL_CORE4:
                /* Configure permissions of gpio pins for all core domains. */
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM2_USER_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
                domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM3_USER_BIT;

                domain_permission1 = (uint32_t)FIREWALL_PERMISSION_NONE
                                     << FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM4_USER_BIT;
                domain_permission1 |=
                    ((uint32_t)gpio_cfg->gpio_privileged_permission)
                    << FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
                domain_permission1 |= ((uint32_t)gpio_cfg->gpio_user_permission)
                                      << FIREWALL_GPIO_DOM5_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM6_USER_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
                domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
                                      << FIREWALL_GPIO_DOM7_USER_BIT;
                break;
#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE4 */
            default:
            {
                ret_val = FIREWALL_E_GPIO_CORE_ID;
                break;
            }
        }

        /* Set permission registers. */
        writel(domain_permission0,
               FIREWALL_APB_GPIO_SF_BASE +
                   FIREWALL_GPIO_DOM_PER0N_ADDR(gpio_cfg->gpio_core_id));
        writel(domain_permission1,
               FIREWALL_APB_GPIO_SF_BASE +
                   FIREWALL_GPIO_DOM_PER1N_ADDR(gpio_cfg->gpio_core_id));
#ifdef FIREWALL_APB_GPIO_AP_BASE
        writel(domain_permission0,
               FIREWALL_APB_GPIO_AP_BASE +
                   FIREWALL_GPIO_DOM_PER0N_ADDR(gpio_cfg->gpio_core_id));
        writel(domain_permission1,
               FIREWALL_APB_GPIO_AP_BASE +
                   FIREWALL_GPIO_DOM_PER1N_ADDR(gpio_cfg->gpio_core_id));
#endif /* #ifdef FIREWALL_APB_GPIO_AP_BASE */
    }

    return ret_val;
}

#ifdef __cplusplus
}
#endif

/* End of file */