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liumin
2025-10-21 19:40:27 +08:00
parent 5a84d13ae4
commit 391f81f8fc
8417 changed files with 2995282 additions and 0 deletions
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77
e3_176_ref/arch/include/armv7-r/arm.h Normal file
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/*
* arm.h
*
* Copyright (c) 2020 Semidrive Semiconductor.
* All rights reserved.
*
* Description: ARMV7R common register interface.
*
* Revision History:
* -----------------
*/
#ifndef ARMV7R_ARM_H
#define ARMV7R_ARM_H
#define MODE_USR 0x10
#define MODE_FIQ 0x11
#define MODE_IRQ 0x12
#define MODE_SVC 0x13
#define MODE_ABT 0x17
#define MODE_UND 0x1B
#define MODE_SYS 0x1F
#define MODE_MASK 0x1F
/* SCTLR */
#define SCTLR_M (1 << 0)
#define SCTLR_A (1 << 1)
#define SCTLR_C (1 << 2)
#define SCTLR_CCP15BEN (1 << 5)
#define SCTLR_B (1 << 7)
#define SCTLR_SW (1 << 10)
#define SCTLR_Z (1 << 11)
#define SCTLR_I (1 << 12)
#define SCTLR_V (1 << 13)
#define SCTLR_RR (1 << 14)
#define SCTLR_BR (1 << 17)
#define SCTLR_DZ (1 << 19)
#define SCTLR_FI (1 << 21)
#define SCTLR_U (1 << 22)
#define SCTLR_VE (1 << 24)
#define SCTLR_EE (1 << 25)
#define SCTLR_NMFI (1 << 27)
#define SCTLR_TE (1 << 30)
#define SCTLR_IE (1 << 31)
/* PSR */
#define PSR_MODE_SHIFT (0)
#define PSR_MODE_MASK (0x1f << PSR_MODE_SHIFT)
#define PSR_MODE_USR (MODE_USR << PSR_MODE_SHIFT)
#define PSR_MODE_FIQ (MODE_FIQ << PSR_MODE_SHIFT)
#define PSR_MODE_IRQ (MODE_IRQ << PSR_MODE_SHIFT)
#define PSR_MODE_SVC (MODE_SVC << PSR_MODE_SHIFT)
#define PSR_MODE_ABT (MODE_ABT << PSR_MODE_SHIFT)
#define PSR_MODE_UND (MODE_UND << PSR_MODE_SHIFT)
#define PSR_MODE_SYS (MODE_SYS << PSR_MODE_SHIFT)
#define PSR_T_BIT (1 << 5)
#define PSR_F_BIT (1 << 6)
#define PSR_I_BIT (1 << 7)
#define PSR_A_BIT (1 << 8)
#define PSR_E_BIT (1 << 9)
#define PSR_IT27_SHIFT (10)
#define PSR_IT27_MASK (0x3f << PSR_IT27_SHIFT)
#define PSR_GE_SHIFT (16)
#define PSR_GE_MASK (15 << PSR_GE_SHIFT)
#define PSR_J_BIT (1 << 24)
#define PSR_IT01_SHIFT (25)
#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT)
#define PSR_Q_BIT (1 << 27)
#define PSR_V_BIT (1 << 28)
#define PSR_C_BIT (1 << 29)
#define PSR_Z_BIT (1 << 30)
#define PSR_N_BIT (1 << 31)
#endif

62
e3_176_ref/arch/include/armv7-r/atomic.h Normal file
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/*
* atomic.h
*
* Copyright (c) 2020 Semidrive Semiconductor.
* All rights reserved.
*
* Description: ARM atomic interface.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_ATOMIC_H
#define INCLUDE_ARCH_ATOMIC_H
#ifndef ASSEMBLY
#include <compiler.h>
__BEGIN_CDECLS
/*
* atomic swap.
*
* @ptr address of data A.
* @val value of data B.
* @return old value of data A.
*/
int arch_atomic_swap(int *ptr, int val);
/*
* atomic add.
*
* @ptr address of data A.
* @val value of data B.
* @return old value of data A.
*/
int arch_atomic_add(int *ptr, int val);
/*
* atomic and.
*
* @ptr address of data A.
* @val value of data B.
* @return old value of data A.
*/
int arch_atomic_and(int *ptr, int val);
/*
* atomic or.
*
* @ptr address of data A.
* @val value of data B.
* @return old value of data A.
*/
int arch_atomic_or(int *ptr, int val);
__END_CDECLS
#endif
#endif

22
e3_176_ref/arch/include/armv7-r/barriers.h Normal file
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/*
* barriers.h
*
* Copyright (c) 2020 Semidrive Semiconductor.
* All rights reserved.
*
* Description: ARMV7R barriers interface.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_ARMV7R_BARRIERS_H
#define INCLUDE_ARCH_ARMV7R_BARRIERS_H
#include <compiler.h>
#define DSB __ASM volatile("dsb" ::: "memory")
#define DMB __ASM volatile("dmb" ::: "memory")
#define ISB __ASM volatile("isb" ::: "memory")
#endif

113
e3_176_ref/arch/include/armv7-r/cache.h Normal file
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/*
* cache.h
*
* Copyright (c) 2020 Semidrive Semiconductor.
* All rights reserved.
*
* Description: ARM cache interface.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_CACHE_H
#define INCLUDE_ARCH_CACHE_H
#define ICACHE 1
#define DCACHE 2
#define UCACHE (ICACHE|DCACHE)
#define __CACHE_ALIGN __ALIGNED(CONFIG_ARCH_CACHE_LINE)
#ifndef ASSEMBLY
#include <types.h>
#include <compiler.h>
__BEGIN_CDECLS
/*
* enable caches.
*
* @flags cache type.
*/
#if CONFIG_ARCH_WITH_CACHE
void arch_enable_cache(uint8_t flags);
#else
#define arch_enable_cache(flags)
#endif
/*
* disable caches.
*
* @flags cache type.
*/
#if CONFIG_ARCH_WITH_CACHE
void arch_disable_cache(uint8_t flags);
#else
#define arch_disable_cache(flags)
#endif
/*
* clean dcache.
*
* @start start address.
* @len clean data length.
*/
#if CONFIG_ARCH_WITH_CACHE
void arch_clean_cache_range(addr_t start, size_t len);
#else
#define arch_clean_cache_range(start, len)
#endif
/*
* clean and invalidate dcache.
*
* @start start address.
* @len clean data length.
*/
#if CONFIG_ARCH_WITH_CACHE
void arch_clean_invalidate_cache_range(addr_t start, size_t len);
#else
#define arch_clean_invalidate_cache_range(start, len)
#endif
/*
* clean and invalidate dcache all
*
*/
#if CONFIG_ARCH_WITH_CACHE
void arch_clean_invalidate_dcache_all(void);
#else
#define arch_clean_invalidate_dcache_all()
#endif
/*
* invalidate dcache.
*
* @start start address.
* @len clean data length.
*/
#if CONFIG_ARCH_WITH_CACHE
void arch_invalidate_cache_range(addr_t start, size_t len);
#else
#define arch_invalidate_cache_range(start, len)
#endif
/*
* sync dcache.
*
* @start start address.
* @len clean data length.
*/
#if CONFIG_ARCH_WITH_CACHE
void arch_sync_cache_range(addr_t start, size_t len);
#else
#define arch_sync_cache_range(start, len)
#endif
__END_CDECLS
#endif
#endif

64
e3_176_ref/arch/include/armv7-r/exceptions.h Normal file
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/*
* exceptions.h
*
* Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*
* Description: ARMV7R exceptions interface.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_ARMV7R_EXCEPTIONS_H
#define INCLUDE_ARCH_ARMV7R_EXCEPTIONS_H
struct arm_iframe {
#if CONFIG_ARCH_WITH_FPU
uint32_t fpexc;
#endif
uint32_t usp;
uint32_t ulr;
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r4;
uint32_t r12;
uint32_t lr;
uint32_t pc;
uint32_t spsr;
};
struct arm_fault_frame {
#if CONFIG_ARCH_WITH_FPU
uint32_t fpexc;
#endif
uint32_t usp;
uint32_t ulr;
uint32_t r[13];
uint32_t lr;
uint32_t pc;
uint32_t spsr;
};
struct arm_mode_regs {
uint32_t usr_r13, usr_r14;
uint32_t fiq_r13, fiq_r14;
uint32_t irq_r13, irq_r14;
uint32_t svc_r13, svc_r14;
uint32_t abt_r13, abt_r14;
uint32_t und_r13, und_r14;
uint32_t sys_r13, sys_r14;
};
void arm_save_mode_regs(struct arm_mode_regs *regs);
void Arm_Undefined_Handler(void);
void Arm_Prefetch_Handler(void);
void Arm_Abort_Handler(void);
void Arm_SWI_Handler(void);
void Arm_IRQ_Handler(void);
void Arm_FIQ_Handler(void);
void arm_reserved(void);
#endif

44
e3_176_ref/arch/include/armv7-r/fpu.h Normal file
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/*
* fpu.h
*
* Copyright (c) 2020 Semidrive Semiconductor.
* All rights reserved.
*
* Description: ARM fpu interface.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_FPU_H
#define INCLUDE_ARCH_FPU_H
#ifndef ASSEMBLY
#include <compiler.h>
__BEGIN_CDECLS
/*
* fpu enable.
*/
#if CONFIG_ARCH_WITH_FPU
void arm_fpu_enable(void);
#else
#define arm_fpu_enable()
#endif
/*
* fpu disable.
*/
#if CONFIG_ARCH_WITH_FPU
void arm_fpu_disable(void);
#else
#define arm_fpu_disable()
#endif
__END_CDECLS
#endif
#endif

114
e3_176_ref/arch/include/armv7-r/irq.h Normal file
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/*
* irq.h
*
* Copyright (c) 2020 Semidrive Semiconductor.
* All rights reserved.
*
* Description: ARM irq interface.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_IRQ_H
#define INCLUDE_ARCH_IRQ_H
#ifndef ASSEMBLY
#include <compiler.h>
#include <stdbool.h>
__BEGIN_CDECLS
/*
* irq state type.
*/
typedef unsigned int irq_state_t;
/*
* irq enable.
*/
static inline void arch_irq_enable(void)
{
CF;
__ASM volatile("cpsie i");
}
/*
* irq disable.
*/
static inline void arch_irq_disable(void)
{
__ASM volatile("cpsid i");
CF;
}
/*
* irq save.
*
* @return old irq state.
*/
static inline irq_state_t arch_irq_save(void)
{
unsigned int cpsr;
__ASM volatile
(
"\tmrs %0, cpsr\n"
"\tcpsid i\n"
: "=r" (cpsr)
:
: "memory"
);
return cpsr;
}
/*
* irq restore.
*
* @flags old irq state.
*/
static inline void arch_irq_restore(irq_state_t flags)
{
__ASM volatile
(
"msr cpsr_c, %0"
:
: "r" (flags)
: "memory"
);
}
/*
* is irq masked.
*
* @return masked or not.
*/
bool arch_irq_is_masked(void);
/*
* is irq mode.
*
* @return irq mode or not.
*/
bool arch_in_irq_mode(void);
/**
* @brief Enable vectored interrupt mode.
*/
void arch_vectored_irq_enable(bool en);
/**
* @brief Whether core is in FIQ mode or not
*
* @return true FIQ mode
* @return false otherwise
*/
bool arch_in_fiq_mode(void);
__END_CDECLS
#endif
#endif

106
e3_176_ref/arch/include/armv7-r/mpu.h Normal file
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/*
* mpu.h
*
* Copyright (c) 2019 Semidrive Semiconductor.
* All rights reserved.
*
* Description: Cortex V7R MPU driver.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_ARMV7R_MPU_H
#define INCLUDE_ARCH_ARMV7R_MPU_H
/*
* Memory types supported by the MPU driver.
*/
typedef enum mpu_region_type {
/* Strong ordered
* - non-bufferable, non-cachable, shareable, RW, XN
*/
MPU_REGION_STRONGORDERED,
/* Device memory
* - bufferable, non-cachable, shareable, RW, XN
*/
MPU_REGION_DEVICE,
/* Normal memory
* - bufferable, outer and inner write-back & write allocate,
* shareble, RW, non XN
*/
MPU_REGION_NORMAL,
/* Normal non-cacheable memory
* - bufferable, outer and inner non-cacheable, shareble, RW,
* non XN
*/
MPU_REGION_NORMAL_NONCACHEABLE,
/* Normal ready-only memory
* - bufferable, outer and inner wb, no wa, no shareble, RO,
* non XN
*/
MPU_REGION_NORMAL_RO,
/* Not accessable.
*/
MPU_REGION_NO_ACCESS,
MPU_REGION_MAX,
} mpu_region_type_e;
#ifndef ASSEMBLY
#include <compiler.h>
#include <stdbool.h>
#include <types.h>
typedef struct mpu_config {
addr_t addr;
uint64_t size;
mpu_region_type_e type;
} mpu_config_t;
__BEGIN_CDECLS
#if CONFIG_ARCH_WITH_MPU
void mpu_clear_region(void);
#else
#define mpu_clear_region()
#endif
#if CONFIG_ARCH_WITH_MPU
void mpu_add_region(int region, uint32_t base, uint64_t size,
mpu_region_type_e type);
#else
#define mpu_add_region(region, base, size, type)
#endif
uint32_t mpu_region_index(void);
#if CONFIG_ARCH_WITH_MPU
void mpu_enable(bool enable);
#else
#define mpu_enable(enable)
#endif
#if CONFIG_ARCH_WITH_MPU
bool mpu_is_belong_uncache_region(uint32_t base, uint32_t size);
#else
#define mpu_is_belong_uncache_region(base, size)
#endif
#if CONFIG_ARCH_WITH_MPU
void mpu_region_set_type(uint32_t base, uint64_t size,
mpu_region_type_e type);
#else
#define mpu_region_set_type(base, size, type)
#endif
__END_CDECLS
#endif /* ASSEMBLY */
#endif

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e3_176_ref/arch/include/armv7-r/pmu.h Normal file
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/*
* pmu.h
*
* Copyright (c) 2019 Semidrive Semiconductor.
* All rights reserved.
*
* Description: Cortex V7R Performance Monitor driver.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_PMU_H
#define INCLUDE_ARCH_PMU_H
#include <types.h>
#include <armv7-r/register.h>
typedef enum pmu_evt_cntr {
PMU_EVT_COUNTER1 = 0,
PMU_EVT_COUNTER2 = 1,
PMU_EVT_COUNTER3 = 2,
} pmu_evt_cntr_e;
typedef enum pmu_evt {
PMU_EVT_SOFTWARE_INCREMENT = 0x0,
PMU_EVT_ICACHE_MISS = 0x1,
PMU_EVT_DCACHE_MISS = 0x3,
PMU_EVT_DCACHE_ACCESS = 0x4,
PMU_EVT_DATA_READ = 0x6,
PMU_EVT_DATA_WRITE = 0x7,
PMU_EVT_INSTRUCTION_EXECUTED = 0x8,
PMU_EVT_DUAL_ISSUED_INSTUCTIONS = 0x5e,
PMU_EVT_EXECPTION_TAKEN = 0x9,
PMU_EVT_EXECPTION_RETURN = 0xa,
PMU_EVT_CHANGE_CONTEXT_ID = 0xb,
PMU_EVT_SW_CHANGE_PC = 0xc,
PMU_EVT_BRANCH_IMMEDIATE = 0xd,
PMU_EVT_PROCEDURE_RETURN = 0xe,
PMU_EVT_UNALIGNED_ACCESS = 0xf,
PMU_EVT_BRANCH_NOT_PREDICTED = 0x10,
PMU_EVT_CYCLE_CNT = 0x11,
PMU_EVT_BRANCH_PREDICTED = 0x12,
PMU_EVT_STALL_INSTRUCTION = 0x40,
PMU_EVT_STALL_DATA_DEPENDENCY = 0x41,
PMU_EVT_DCACHE_WRITE_BACK = 0x42,
PMU_EVT_EXT_MEMORY_REQ = 0x43,
PMU_EVT_STALL_LSU_BUSY = 0x44,
PMU_EVT_DRAIN_STORE_BUFFER = 0x45,
PMU_EVT_FIQ_DISABLE_CYCLES = 0x46,
PMU_EVT_IRQ_DISABLE_CYCLES = 0x47,
PMU_EVT_ETMEXTOUTM0 = 0x48,
PMU_EVT_ETMEXTOUTM1 = 0x49,
PMU_EVT_ICACHE_TAG_ECCERR = 0x4a,
PMU_EVT_ICACHE_DATA_ECCERR = 0x4b,
PMU_EVT_DCACHE_TAG_ECCERR = 0x4c,
PMU_EVT_DCACHE_DATA_ECCERR = 0x4d,
PMU_EVT_TCM_ECCERR_PFU = 0x4e,
PMU_EVT_TCM_ECCERR_LSU = 0x4f,
PMU_EVT_STORE_BUFFER_MERGE = 0x50,
PMU_EVT_LSU_STALL_BY_STORE_BUFFER = 0x51,
PMU_EVT_LSU_STALL_BY_STORE_QUEUE = 0x52,
PMU_EVT_INT_DIV = 0x53,
PMU_EVT_STALL_CYCLE_BY_INT_DIV = 0x54,
PMU_EVT_PLD_LINEFILL = 0x55,
PMU_EVT_PLD_NO_LINEFILL = 0x56,
PMU_EVT_NON_CACHEABLE_AXI_ACCESS = 0x57,
PMU_EVT_ICACHE_ACCESS = 0x58,
PMU_EVT_STORE_BUFFER_SLOT_ATTR_CONFLICT = 0x59,
PMU_EVT_DUAL_ISSUE_CASE_A = 0x5a,
PMU_EVT_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5b,
PMU_EVT_DUAL_ISSUE_CASE_OTHER = 0x5c,
PMU_EVT_DOUBLE_PRECISION_FLOAT_EXEC = 0x5d,
PMU_EVT_DCACHE_DATA_FATAL_ECCERR = 0x60,
PMU_EVT_DCACHE_TAG_FATAL_ECCERR = 0x61,
PMU_EVT_PROCESSOR_LIVELOCK = 0x62,
PMU_EVT_ATCM_MB_ECCERR = 0x64,
PMU_EVT_B0TCM_MB_ECCERR = 0x65,
PMU_EVT_B1TCM_MB_ECCERR = 0x66,
PMU_EVT_ATCM_SB_ECCERR = 0x67,
PMU_EVT_B0TCM_SB_ECCERR = 0x68,
PMU_EVT_B1TCM_SB_ECCERR = 0x69,
PMU_EVT_TCM_CORRECTABLE_ECCERR_LSU = 0x6a,
PMU_EVT_TCM_CORRECTABLE_ECCERR_PFU = 0x6b,
PMU_EVT_TCM_FATAL_ECCERR_AXI_SLAVE = 0x6c,
PMU_EVT_TCM_CORRECTABLE_ECCERR_AXI_SLAVE = 0x6d,
PMU_EVT_CORRECTABLE_EVENTS = 0x6e,
PMU_EVT_FATAL_EVENTS = 0x6f,
PMU_EVT_CORRECTABLE_BUS_FAULTS = 0x70,
PMU_EVT_FATAL_BUS_FAULTS = 0x71,
PMU_EVT_ACP_DCACHE_ACCESS = 0x72,
PMU_EVT_ACP_DCACHE_INVALIDATE = 0x73,
} pmu_evt_e;
#define PMCR_E (1 << 0) /* pmu enable */
#define PMCR_P (1 << 1) /* event counter reset */
#define PMCR_C (1 << 2) /* cycle counter reset */
#define PMCR_D (1 << 3) /* count every 64 clock cycles */
#if CONFIG_ARM_WITH_PMU
/* Enable the PMU. All counters are cleared. */
static inline void pmu_enable(void)
{
uint32_t val = arm_read_pmcr();
val |= PMCR_P | PMCR_C | PMCR_E;
arm_write_pmcr(val);
}
/* Diable the PMU. All counters are cleared. */
static inline void pmu_disable(void)
{
uint32_t val = arm_read_pmcr();
val &= ~(PMCR_P | PMCR_C | PMCR_E);
arm_write_pmcr(val);
}
/* Get cycle counter enable status */
static inline bool pmu_cycle_cntr_status(void)
{
uint32_t val = arm_read_pmcntenset();
return !!(val & (1U << 31));
}
/* Start cycle counter. Set div64 = true to count every
* 64 clock cycles.
*/
static inline void pmu_start_cycle_cntr(bool div64)
{
uint32_t val = arm_read_pmcr();
if (div64)
val |= PMCR_D;
else
val &= ~PMCR_D;
arm_write_pmcr(val);
arm_write_pmcntenset(1U << 31);
}
/* Stop cycle counter. */
static inline void pmu_stop_cycle_cntr(void)
{
arm_write_pmcntenclr(1U << 31);
}
/* Stop and clear the cycle counter. */
static inline void pmu_stop_clear_cycle_cntr(void)
{
pmu_stop_cycle_cntr();
arm_write_pmccntr(0);
}
/* Get cycle counter value. */
static inline uint32_t pmu_get_cycle_cntr(void)
{
return arm_read_pmccntr();
}
/* Bind event counter to specific event and start it. */
static inline void pmu_start_evt_cntr(pmu_evt_cntr_e cntr,
pmu_evt_e evt)
{
arm_write_pmselr(cntr);
arm_write_pmxevtyper(evt);
arm_write_pmcntenset(1 << cntr);
}
/* Stop event counter without clearing. */
static inline void pmu_stop_evt_cntr(pmu_evt_cntr_e cntr)
{
arm_write_pmcntenclr(1 << cntr);
}
/* Stop and clear the event counter. */
static inline void pmu_stop_clear_evt_cntr(pmu_evt_cntr_e cntr)
{
pmu_stop_evt_cntr(cntr);
arm_write_pmselr(cntr);
arm_write_pmxevcntr(0);
}
/* Get event counter value. */
static inline uint32_t pmu_get_evt_cntr(pmu_evt_cntr_e cntr)
{
arm_write_pmselr(cntr);
return arm_read_pmxevcntr();
}
#else
#define pmu_enable()
#define pmu_disable()
#define pmu_start_cycle_cntr(div64)
#define pmu_stop_cycle_cntr()
#define pmu_stop_clear_cycle_cntr()
#define pmu_get_cycle_cntr()
#define pmu_start_evt_cntr()
#define pmu_stop_evt_cntr()
#define pmu_stop_clear_evt_cntr()
#define pmu_get_evt_cntr()
#endif
#endif /* ARCH_ARM_PMU_H */

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/*
* register.h
*
* Copyright (c) 2020 Semidrive Semiconductor.
* All rights reserved.
*
* Description: ARM cp register interface.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_REGISTER_H
#define INCLUDE_ARCH_REGISTER_H
#define REG_R0 (0)
#define REG_R1 (1)
#define REG_R2 (2)
#define REG_R3 (3)
#define REG_R4 (4)
#define REG_R5 (5)
#define REG_R6 (6)
#define REG_R7 (7)
#define REG_R8 (8)
#define REG_R9 (9)
#define REG_R10 (10)
#define REG_R11 (11)
#define REG_R12 (12)
#define REG_R13 (13)
#define REG_R14 (14)
#define REG_R15 (15)
#define REG_CPSR (16)
#define ARM_CONTEXT_REGS (17)
/* If the MCU supports a floating point unit, then it will be necessary
* to save the state of the FPU status register and data registers on
* each context switch. These registers are not saved during interrupt
* level processing, however. So, as a consequence, floating point
* operations may NOT be performed in interrupt handlers.
*
* The FPU provides an extension register file containing 32 single-
* precision registers. These can be viewed as:
*
* - Sixteen 64-bit double word registers, D0-D15
* - Thirty-two 32-bit single-word registers, S0-S31
* S<2n> maps to the least significant half of D<n>
* S<2n+1> maps to the most significant half of D<n>.
*/
#if CONFIG_ARCH_WITH_FPU
# define REG_D0 (ARM_CONTEXT_REGS+0) /* D0 */
# define REG_S0 (ARM_CONTEXT_REGS+0) /* S0 */
# define REG_S1 (ARM_CONTEXT_REGS+1) /* S1 */
# define REG_D1 (ARM_CONTEXT_REGS+2) /* D1 */
# define REG_S2 (ARM_CONTEXT_REGS+2) /* S2 */
# define REG_S3 (ARM_CONTEXT_REGS+3) /* S3 */
# define REG_D2 (ARM_CONTEXT_REGS+4) /* D2 */
# define REG_S4 (ARM_CONTEXT_REGS+4) /* S4 */
# define REG_S5 (ARM_CONTEXT_REGS+5) /* S5 */
# define REG_D3 (ARM_CONTEXT_REGS+6) /* D3 */
# define REG_S6 (ARM_CONTEXT_REGS+6) /* S6 */
# define REG_S7 (ARM_CONTEXT_REGS+7) /* S7 */
# define REG_D4 (ARM_CONTEXT_REGS+8) /* D4 */
# define REG_S8 (ARM_CONTEXT_REGS+8) /* S8 */
# define REG_S9 (ARM_CONTEXT_REGS+9) /* S9 */
# define REG_D5 (ARM_CONTEXT_REGS+10) /* D5 */
# define REG_S10 (ARM_CONTEXT_REGS+10) /* S10 */
# define REG_S11 (ARM_CONTEXT_REGS+11) /* S11 */
# define REG_D6 (ARM_CONTEXT_REGS+12) /* D6 */
# define REG_S12 (ARM_CONTEXT_REGS+12) /* S12 */
# define REG_S13 (ARM_CONTEXT_REGS+13) /* S13 */
# define REG_D7 (ARM_CONTEXT_REGS+14) /* D7 */
# define REG_S14 (ARM_CONTEXT_REGS+14) /* S14 */
# define REG_S15 (ARM_CONTEXT_REGS+15) /* S15 */
# define REG_D8 (ARM_CONTEXT_REGS+16) /* D8 */
# define REG_S16 (ARM_CONTEXT_REGS+16) /* S16 */
# define REG_S17 (ARM_CONTEXT_REGS+17) /* S17 */
# define REG_D9 (ARM_CONTEXT_REGS+18) /* D9 */
# define REG_S18 (ARM_CONTEXT_REGS+18) /* S18 */
# define REG_S19 (ARM_CONTEXT_REGS+19) /* S19 */
# define REG_D10 (ARM_CONTEXT_REGS+20) /* D10 */
# define REG_S20 (ARM_CONTEXT_REGS+20) /* S20 */
# define REG_S21 (ARM_CONTEXT_REGS+21) /* S21 */
# define REG_D11 (ARM_CONTEXT_REGS+22) /* D11 */
# define REG_S22 (ARM_CONTEXT_REGS+22) /* S22 */
# define REG_S23 (ARM_CONTEXT_REGS+23) /* S23 */
# define REG_D12 (ARM_CONTEXT_REGS+24) /* D12 */
# define REG_S24 (ARM_CONTEXT_REGS+24) /* S24 */
# define REG_S25 (ARM_CONTEXT_REGS+25) /* S25 */
# define REG_D13 (ARM_CONTEXT_REGS+26) /* D13 */
# define REG_S26 (ARM_CONTEXT_REGS+26) /* S26 */
# define REG_S27 (ARM_CONTEXT_REGS+27) /* S27 */
# define REG_D14 (ARM_CONTEXT_REGS+28) /* D14 */
# define REG_S28 (ARM_CONTEXT_REGS+28) /* S28 */
# define REG_S29 (ARM_CONTEXT_REGS+29) /* S29 */
# define REG_D15 (ARM_CONTEXT_REGS+30) /* D15 */
# define REG_S30 (ARM_CONTEXT_REGS+30) /* S30 */
# define REG_S31 (ARM_CONTEXT_REGS+31) /* S31 */
# define REG_FPSCR (ARM_CONTEXT_REGS+32) /* Floating point status and control */
# define FPU_CONTEXT_REGS (33)
#else
# define FPU_CONTEXT_REGS (0)
#endif
/* The total number of registers saved by software */
#define XCPTCONTEXT_REGS (ARM_CONTEXT_REGS + FPU_CONTEXT_REGS)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
#ifndef ASSEMBLY
#include <types.h>
#include <compiler.h>
#include <armv7-r/barriers.h>
static inline uint32_t read_cpsr(void)
{
uint32_t cpsr;
__ASM volatile("mrs %0, cpsr" : "=r" (cpsr));
return cpsr;
}
#define ARM_CP_REG_FUNCS(cp, reg, op1, c1, c2, op2) \
static inline uint32_t arm_read_##reg(void) { \
uint32_t val; \
__ASM volatile("mrc " #cp ", " #op1 ", %0, " #c1 "," #c2 "," #op2 : "=r" (val)); \
return val; \
} \
\
static inline void arm_write_##reg(uint32_t val) { \
__ASM volatile("mcr " #cp ", " #op1 ", %0, " #c1 "," #c2 "," #op2 :: "r" (val)); \
ISB; \
}
#define ARM_CP15_REG_FUNCS(reg, op1, c1, c2, op2) \
ARM_CP_REG_FUNCS(p15, reg, op1, c1, c2, op2)
#define ARM_CP14_REG_FUNCS(reg, op1, c1, c2, op2) \
ARM_CP_REG_FUNCS(p14, reg, op1, c1, c2, op2)
#define ARM_CP10_REG_FUNCS(reg, op1, c1, c2, op2) \
ARM_CP_REG_FUNCS(p10, reg, op1, c1, c2, op2)
ARM_CP15_REG_FUNCS(sctlr, 0, c1, c0, 0);
ARM_CP15_REG_FUNCS(actlr, 0, c1, c0, 1);
ARM_CP15_REG_FUNCS(cpacr, 0, c1, c0, 2);
ARM_CP15_REG_FUNCS(ttbr, 0, c2, c0, 0);
ARM_CP15_REG_FUNCS(ttbr0, 0, c2, c0, 0);
ARM_CP15_REG_FUNCS(ttbr1, 0, c2, c0, 1);
ARM_CP15_REG_FUNCS(ttbcr, 0, c2, c0, 2);
ARM_CP15_REG_FUNCS(dacr, 0, c3, c0, 0);
ARM_CP15_REG_FUNCS(dfsr, 0, c5, c0, 0);
ARM_CP15_REG_FUNCS(ifsr, 0, c5, c0, 1);
ARM_CP15_REG_FUNCS(dfar, 0, c6, c0, 0);
ARM_CP15_REG_FUNCS(wfar, 0, c6, c0, 1);
ARM_CP15_REG_FUNCS(ifar, 0, c6, c0, 2);
ARM_CP15_REG_FUNCS(fcseidr, 0, c13, c0, 0);
ARM_CP15_REG_FUNCS(contextidr, 0, c13, c0, 1);
ARM_CP15_REG_FUNCS(tpidrurw, 0, c13, c0, 2);
ARM_CP15_REG_FUNCS(tpidruro, 0, c13, c0, 3);
ARM_CP15_REG_FUNCS(tpidrprw, 0, c13, c0, 4);
ARM_CP15_REG_FUNCS(midr, 0, c0, c0, 0);
ARM_CP15_REG_FUNCS(mpidr, 0, c0, c0, 5);
ARM_CP15_REG_FUNCS(vbar, 0, c12, c0, 0);
ARM_CP15_REG_FUNCS(cbar, 4, c15, c0, 0);
ARM_CP15_REG_FUNCS(ats1cpr, 0, c7, c8, 0);
ARM_CP15_REG_FUNCS(ats1cpw, 0, c7, c8, 1);
ARM_CP15_REG_FUNCS(ats1cur, 0, c7, c8, 2);
ARM_CP15_REG_FUNCS(ats1cuw, 0, c7, c8, 3);
ARM_CP15_REG_FUNCS(ats12nsopr, 0, c7, c8, 4);
ARM_CP15_REG_FUNCS(ats12nsopw, 0, c7, c8, 5);
ARM_CP15_REG_FUNCS(ats12nsour, 0, c7, c8, 6);
ARM_CP15_REG_FUNCS(ats12nsouw, 0, c7, c8, 7);
ARM_CP15_REG_FUNCS(par, 0, c7, c4, 0);
/* Branch predictor invalidate */
ARM_CP15_REG_FUNCS(bpiall, 0, c7, c5, 6);
ARM_CP15_REG_FUNCS(bpimva, 0, c7, c5, 7);
ARM_CP15_REG_FUNCS(bpiallis, 0, c7, c1, 6);
/* tlb registers */
ARM_CP15_REG_FUNCS(tlbiallis, 0, c8, c3, 0);
ARM_CP15_REG_FUNCS(tlbimvais, 0, c8, c3, 1);
ARM_CP15_REG_FUNCS(tlbiasidis, 0, c8, c3, 2);
ARM_CP15_REG_FUNCS(tlbimvaais, 0, c8, c3, 3);
ARM_CP15_REG_FUNCS(itlbiall, 0, c8, c5, 0);
ARM_CP15_REG_FUNCS(itlbimva, 0, c8, c5, 1);
ARM_CP15_REG_FUNCS(itlbiasid, 0, c8, c5, 2);
ARM_CP15_REG_FUNCS(dtlbiall, 0, c8, c6, 0);
ARM_CP15_REG_FUNCS(dtlbimva, 0, c8, c6, 1);
ARM_CP15_REG_FUNCS(dtlbiasid, 0, c8, c6, 2);
ARM_CP15_REG_FUNCS(tlbiall, 0, c8, c7, 0);
ARM_CP15_REG_FUNCS(tlbimva, 0, c8, c7, 1);
ARM_CP15_REG_FUNCS(tlbiasid, 0, c8, c7, 2);
ARM_CP15_REG_FUNCS(tlbimvaa, 0, c8, c7, 3);
ARM_CP15_REG_FUNCS(l2ctlr, 1, c9, c0, 2);
ARM_CP15_REG_FUNCS(l2ectlr, 1, c9, c0, 3);
/* mpu registers (using unified memory regions) */
ARM_CP15_REG_FUNCS(mpuir, 0, c0, c0, 4);
ARM_CP15_REG_FUNCS(rbar, 0, c6, c1, 0);
ARM_CP15_REG_FUNCS(rsr, 0, c6, c1, 2);
ARM_CP15_REG_FUNCS(racr, 0, c6, c1, 4);
ARM_CP15_REG_FUNCS(rgnr, 0, c6, c2, 0);
/* performance monitor registers */
ARM_CP15_REG_FUNCS(pmcr, 0, c9, c12, 0);
ARM_CP15_REG_FUNCS(pmcntenset, 0, c9, c12, 1);
ARM_CP15_REG_FUNCS(pmcntenclr, 0, c9, c12, 2);
ARM_CP15_REG_FUNCS(pmovsr, 0, c9, c12, 3);
ARM_CP15_REG_FUNCS(pmswinc, 0, c9, c12, 4);
ARM_CP15_REG_FUNCS(pmselr, 0, c9, c12, 5);
ARM_CP15_REG_FUNCS(pmccntr, 0, c9, c13, 0);
ARM_CP15_REG_FUNCS(pmxevtyper, 0, c9, c13, 1);
ARM_CP15_REG_FUNCS(pmxevcntr, 0, c9, c13, 2);
/* TCM registers */
ARM_CP15_REG_FUNCS(tcmtr, 0, c0, c0, 2);
ARM_CP15_REG_FUNCS(btcmrgn, 0, c9, c1, 0);
ARM_CP15_REG_FUNCS(atcmrgn, 0, c9, c1, 1);
/* debug registers */
ARM_CP14_REG_FUNCS(dbddidr, 0, c0, c0, 0);
ARM_CP14_REG_FUNCS(dbgdrar, 0, c1, c0, 0);
ARM_CP14_REG_FUNCS(dbgdsar, 0, c2, c0, 0);
ARM_CP14_REG_FUNCS(dbgdscr, 0, c0, c1, 0);
ARM_CP14_REG_FUNCS(dbgdtrtxint, 0, c0, c5, 0);
ARM_CP14_REG_FUNCS(dbgdtrrxint, 0, c0, c5, 0);
ARM_CP14_REG_FUNCS(dbgwfar, 0, c0, c6, 0);
ARM_CP14_REG_FUNCS(dbgvcr, 0, c0, c7, 0);
ARM_CP14_REG_FUNCS(dbgecr, 0, c0, c9, 0);
ARM_CP14_REG_FUNCS(dbgdsccr, 0, c0, c10, 0);
ARM_CP14_REG_FUNCS(dbgdsmcr, 0, c0, c11, 0);
ARM_CP14_REG_FUNCS(dbgdtrrxext, 0, c0, c0, 2);
ARM_CP14_REG_FUNCS(dbgdscrext, 0, c0, c2, 2);
ARM_CP14_REG_FUNCS(dbgdtrtxext, 0, c0, c3, 2);
ARM_CP14_REG_FUNCS(dbgdrcr, 0, c0, c4, 2);
ARM_CP14_REG_FUNCS(dbgvr0, 0, c0, c0, 4);
ARM_CP14_REG_FUNCS(dbgvr1, 0, c0, c1, 4);
ARM_CP14_REG_FUNCS(dbgvr2, 0, c0, c2, 4);
ARM_CP14_REG_FUNCS(dbgbcr0, 0, c0, c0, 5);
ARM_CP14_REG_FUNCS(dbgbcr1, 0, c0, c1, 5);
ARM_CP14_REG_FUNCS(dbgbcr2, 0, c0, c2, 5);
ARM_CP14_REG_FUNCS(dbgwvr0, 0, c0, c0, 6);
ARM_CP14_REG_FUNCS(dbgwvr1, 0, c0, c1, 6);
ARM_CP14_REG_FUNCS(dbgwcr0, 0, c0, c0, 7);
ARM_CP14_REG_FUNCS(dbgwcr1, 0, c0, c1, 7);
ARM_CP14_REG_FUNCS(dbgoslar, 0, c1, c0, 4);
ARM_CP14_REG_FUNCS(dbgoslsr, 0, c1, c1, 4);
ARM_CP14_REG_FUNCS(dbgossrr, 0, c1, c2, 4);
ARM_CP14_REG_FUNCS(dbgprcr, 0, c1, c4, 4);
ARM_CP14_REG_FUNCS(dbgprsr, 0, c1, c5, 4);
ARM_CP14_REG_FUNCS(dbgclaimset, 0, c7, c8, 6);
ARM_CP14_REG_FUNCS(dbgclaimclr, 0, c7, c9, 6);
ARM_CP14_REG_FUNCS(dbgauthstatus, 0, c7, c14, 6);
ARM_CP14_REG_FUNCS(dbgdevid, 0, c7, c2, 7);
/* fpu registers */
ARM_CP10_REG_FUNCS(fpexc, 7, c8, c0, 0);
#endif /* ASSEMBLY */
#endif /* INCLUDE_ARCH_REGISTER_H */

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/*
* spinlock.h
*
* Copyright (c) 2020 Semidrive Semiconductor.
* All rights reserved.
*
* Description: ARM spinlock interface.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARM_SPINLOCK_H
#define INCLUDE_ARM_SPINLOCK_H
#include <armv7-r/barriers.h>
#define SPIN_LOCK_INITIAL_VALUE (0)
#ifndef ASSEMBLY
__BEGIN_CDECLS
/* spin lock type */
typedef unsigned long spin_lock_t;
#ifdef CONFIG_MULTI_CORE_SMP
#else
static inline int __arch_spin_lock_testset(spin_lock_t *spinlock, int value)
{
int result = 0;
__ASM volatile
(
"1:\n"
"\tldrex %0, [%1]\n"
"\tcmp %0, %2\n"
"\tbeq 2f\n"
"\tstrex %0, %2, [%1]\n"
"\tcmp %0, %2\n"
"\tbeq 1b\n"
"\tdmb ish\n"
"2:\n"
: "=&r" (result)
: "r" (spinlock), "r" (value)
: "cc", "memory"
);
return result;
}
#endif
/*
* arch spinlock init.
*
* @spinlock spinlock address.
*/
#ifdef CONFIG_MULTI_CORE_SMP
void arch_spin_lock_init(spin_lock_t *spinlock);
#else
static inline void arch_spin_lock_init(spin_lock_t *spinlock)
{
*spinlock = SPIN_LOCK_INITIAL_VALUE;
}
#endif
/*
* arch spin lock.
*
* @spinlock spinlock address.
*/
#ifdef CONFIG_MULTI_CORE_SMP
void arch_spin_lock(spin_lock_t *spinlock);
#else
static inline void arch_spin_lock(spin_lock_t *spinlock)
{
/* spin until lock is acquired */
while (__arch_spin_lock_testset(spinlock, 1)) {
DSB;
};
}
#endif
/*
* arch spin trylock.
*
* @spinlock spinlock address.
*/
#ifdef CONFIG_MULTI_CORE_SMP
int arch_spin_trylock(spin_lock_t *spinlock);
#else
static inline int arch_spin_trylock(spin_lock_t *spinlock)
{
return __arch_spin_lock_testset(spinlock, 1) == 0;
}
#endif
/*
* arch spin unlock.
*
* @spinlock spinlock address.
*/
#ifdef CONFIG_MULTI_CORE_SMP
void arch_spin_unlock(spin_lock_t *spinlock);
#else
static inline void arch_spin_unlock(spin_lock_t *spinlock)
{
DMB;
*spinlock = 0;
DSB;
}
#endif
__END_CDECLS
#endif
#endif

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/*
* svcall.h
*
* Copyright (c) 2022 Semidrive Semiconductor.
* All rights reserved.
*
* Description: SV call header file.
*
* Revision History:
* -----------------
*/
#ifndef ARM_V7R_SVCALL_H_
#define ARM_V7R_SVCALL_H_
/* Cortex-R system calls ************************************************************/
/* SYS call 0:
*
* int arm_saveusercontext(uint32_t *saveregs);
*/
#define SYS_save_context (0)
/* SYS call 1:
*
* void arm_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*/
#define SYS_restore_context (1)
/* SYS call 2:
*
* void arm_switchcontext(void);
*/
#define SYS_switch_context (2)
#endif /* ARM_V7R_SVCALL_H_ */

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/*
* tcm.h
*
* Copyright (c) 2019 Semidrive Semiconductor.
* All rights reserved.
*
* Description: Cortex V7R TCM driver.
*
* Revision History:
* -----------------
*/
#ifndef INCLUDE_ARCH_ARMV7R_TCM_H
#define INCLUDE_ARCH_ARMV7R_TCM_H
#define ATCMPCEN (1ul << 25)
#define B0TCMPCEN (1ul << 26)
#define B1TCMPCEN (1ul << 27)
#ifndef ASSEMBLY
#include <types.h>
#include <compiler.h>
#include <stdbool.h>
__BEGIN_CDECLS
/*
* tcma enable.
*
* @atcm_base tcma base address.
* @enable_ecc enable tcm ecc.
*/
#if CONFIG_ARM_WITH_TCM
void tcma_enable(uint32_t tcm_base, bool enable_ecc);
#else
#define tcma_enable(tcm_base, enable_ecc)
#endif
/*
* tcmb enable.
*
* @atcm_base tcmb base address.
* @enable_ecc enable tcm ecc.
*/
#if CONFIG_ARM_WITH_TCM
void tcmb_enable(uint32_t tcm_base, bool enable_ecc);
#else
#define tcmb_enable(tcm_base, enable_ecc)
#endif
__END_CDECLS
#endif
#endif