107 lines
4.3 KiB
C
107 lines
4.3 KiB
C
/**
|
|
* @file analog_control.h
|
|
* @brief Describe all analog mux of a chip and how to disable ADC/ACMP channels.
|
|
*
|
|
* Before including this header file, describe base addresses of ADC/ACMP and SCR,
|
|
* and include the specific <scr_hw.h>.
|
|
*
|
|
* @copyright Copyright (c) 2025 Semidrive Semiconductor.
|
|
* All rights reserved.
|
|
*/
|
|
|
|
#ifndef ANALOG_CONTROL_H_
|
|
#define ANALOG_CONTROL_H_
|
|
|
|
#include <analog_mux.h>
|
|
#include <reg.h>
|
|
#include <param.h>
|
|
|
|
|
|
#ifndef ACMP3_BASE /* ACMP3 may not exist. */
|
|
#define ACMP3_BASE 0
|
|
#endif
|
|
|
|
#ifndef ACMP4_BASE /* ACMP4 may not exist. */
|
|
#define ACMP4_BASE 0
|
|
#endif
|
|
|
|
|
|
static const struct channel_amux_scr adc1_chnl_scr[] = {
|
|
{ADC_ACMP_NEG_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ADC1_CH5N_CSEL_3},
|
|
{ADC_ACMP_POS_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ADC1_CH5P_CSEL_3},
|
|
};
|
|
|
|
static const struct channel_amux_scr adc2_chnl_scr[] = {
|
|
{ADC_ACMP_NEG_CHNL(4), SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH4N_CSEL_3},
|
|
{ADC_ACMP_POS_CHNL(4), SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH4P_CSEL_3},
|
|
{ADC_ACMP_NEG_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH5N_CSEL_3},
|
|
{ADC_ACMP_POS_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH5P_CSEL_3},
|
|
{ADC_ACMP_NEG_CHNL(6), SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH6N_CSEL_3},
|
|
};
|
|
|
|
static const struct channel_amux_scr adc3_chnl_scr[] = {
|
|
{ADC_ACMP_NEG_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ADC3_CH5N_CSEL_3},
|
|
{ADC_ACMP_POS_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ADC3_CH5P_CSEL_3},
|
|
};
|
|
|
|
static const struct channel_amux_scr acmp1_chnl_scr[] = {
|
|
{ADC_ACMP_NEG_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ACMP1_CH5N_CSEL_3},
|
|
{ADC_ACMP_POS_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ACMP1_CH5P_CSEL_3},
|
|
};
|
|
|
|
static const struct channel_amux_scr acmp2_chnl_scr[] = {
|
|
{ADC_ACMP_NEG_CHNL(6), SCR_SF_ANA_SF_CFG_AMUX_ACMP2_CH6N_CSEL_3},
|
|
{ADC_ACMP_POS_CHNL(6), SCR_SF_ANA_SF_CFG_AMUX_ACMP2_CH6P_CSEL_3},
|
|
};
|
|
|
|
static const struct channel_amux_scr acmp3_chnl_scr[] = {
|
|
{ADC_ACMP_NEG_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ACMP3_CH5N_CSEL_3},
|
|
{ADC_ACMP_POS_CHNL(5), SCR_SF_ANA_SF_CFG_AMUX_ACMP3_CH5P_CSEL_3},
|
|
};
|
|
|
|
static const struct channel_amux_scr acmp4_chnl_scr[] = {
|
|
{ADC_ACMP_NEG_CHNL(6), SCR_SF_ANA_SF_CFG_AMUX_ACMP4_CH6N_CSEL_3},
|
|
{ADC_ACMP_POS_CHNL(6), SCR_SF_ANA_SF_CFG_AMUX_ACMP4_CH6N_CSEL_3},
|
|
};
|
|
|
|
static const struct device_amux_scr adc_acmp_amux_scr[] = {
|
|
{ADC1_BASE, adc1_chnl_scr, ARRAY_SIZE(adc1_chnl_scr)},
|
|
{ADC2_BASE, adc2_chnl_scr, ARRAY_SIZE(adc2_chnl_scr)},
|
|
{ADC3_BASE, adc3_chnl_scr, ARRAY_SIZE(adc3_chnl_scr)},
|
|
{ACMP1_BASE, acmp1_chnl_scr, ARRAY_SIZE(acmp1_chnl_scr)},
|
|
{ACMP2_BASE, acmp2_chnl_scr, ARRAY_SIZE(acmp2_chnl_scr)},
|
|
{ACMP3_BASE, acmp3_chnl_scr, ARRAY_SIZE(acmp3_chnl_scr)},
|
|
{ACMP4_BASE, acmp4_chnl_scr, ARRAY_SIZE(acmp4_chnl_scr)},
|
|
};
|
|
|
|
static struct chip_amux_scr taishan_amux_scr = {
|
|
SCR_BASE, adc_acmp_amux_scr, ARRAY_SIZE(adc_acmp_amux_scr)
|
|
};
|
|
|
|
|
|
#define analog_init_func_def(func_name) \
|
|
void func_name(void) \
|
|
{ \
|
|
sdrv_scr_t scr_ctrl = {SCR_BASE}; \
|
|
scr_signal_t amux7_sig[] = { \
|
|
SCR_SF_ANA_SF_CFG_AMUX_REF_P_CSEL_3_0, \
|
|
SCR_SF_ANA_SF_CFG_AMUX_REF_N_CSEL_3_0 \
|
|
}; \
|
|
\
|
|
analog_chip_amux_init(&taishan_amux_scr); \
|
|
analog_chip_amux_register(&taishan_amux_scr); \
|
|
for (int i = 0; i < ARRAY_SIZE(amux7_sig); i++) { \
|
|
scr_set(&scr_ctrl, &amux7_sig[i], 6); \
|
|
} \
|
|
}
|
|
|
|
#define amux_register_func_def(func_name) \
|
|
void func_name(void) \
|
|
{ \
|
|
analog_chip_amux_register(&taishan_amux_scr); \
|
|
}
|
|
|
|
|
|
#endif /* ANALOG_CONTROL_H_ */
|
|
|