651 lines
16 KiB
C
651 lines
16 KiB
C
//*****************************************************************************
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//
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// WARNING: Automatically generated file, don't modify anymore!!!
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//
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// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
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// Software License Agreement
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//
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//*****************************************************************************
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#ifndef REGS_BASE_H
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#define REGS_BASE_H
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/*------------------------------------------------------
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* Mailbox
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*------------------------------------------------------*/
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/* Mailbox Register */
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#define MB_REG_BASE (0xF4000000ul)
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/* Mailbox Buffer */
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#define MB_MEM_BASE (0x02001000ul)
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/*------------------------------------------------------
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* Interrupt
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*------------------------------------------------------*/
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/* Vectored Interrupt Controller (VIC) 1 Base Address, for SF Core (cluster 0) */
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#define VIC1_BASE (0xF1C00000ul)
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/*------------------------------------------------------
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* Bus Inter-Connect
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*------------------------------------------------------*/
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/* Configuration Register for FAB_DISP Fabric */
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#define APB_GPV_DISP_BASE (0xF34F0000ul)
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/* Configuration Register for FAB_AP Fabric */
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#define APB_GPV_AP_BASE (0xF31B0000ul)
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/* Configuration Register for FAB_SP Fabric */
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#define APB_GPV_SP_BASE (0xF2180000ul)
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/* Configuration Register for FAB_SX Fabric */
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#define APB_GPV_SX_BASE (0xF07A0000ul)
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/* Configuration Register for FAB_XB Fabric */
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#define APB_GPV_XB_BASE (0xF0790000ul)
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/* Configuration Register for FAB_SAFETY Fabric */
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#define APB_GPV_SF_BASE (0xF0780000ul)
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/* Configuration Register for FAB_AP Fabric */
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#define APB_GPV_AAHB_BASE (0xF0770000ul)
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/*------------------------------------------------------
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* Display
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*------------------------------------------------------*/
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/* Display Mux */
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#define APB_DISP_MUX_BASE (0xF34C0000ul)
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/* Graphics Processing Unit */
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#define APB_G2D_BASE (0xF3440000ul)
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/* Display Controller */
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#define APB_DC_BASE (0xF3410000ul)
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/*------------------------------------------------------
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* DMA
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*------------------------------------------------------*/
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/* AP Domain Direct Memory Access (DMA) */
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#define APB_DMA_AP_BASE (0xF3180000ul)
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/* SF Domain Direct Memory Access (DMA) 1 */
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#define APB_DMA_SF1_BASE (0xF0540000ul)
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/* SF Domain Direct Memory Access (DMA) 0 */
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#define APB_DMA_SF0_BASE (0xF0500000ul)
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/*------------------------------------------------------
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* Peripherals
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*------------------------------------------------------*/
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/* AP Domain General Porpose Intput Output (GPIO) */
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#define APB_GPIO_AP_BASE (0xF3120000ul)
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/* SF Domain General Porpose Intput Output (GPIO) */
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#define APB_GPIO_SF_BASE (0xF0740000ul)
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/* CAN with Flexible Data rate (CANFD) 3 */
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#define APB_CANFD3_BASE (0xF05A0000ul)
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/* CAN with Flexible Data rate (CANFD) 4 */
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#define APB_CANFD4_BASE (0xF05B0000ul)
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/* CAN with Flexible Data rate (CANFD) 16 */
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#define APB_CANFD16_BASE (0xF0F00000ul)
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/* CAN with Flexible Data rate (CANFD) 21 */
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#define APB_CANFD21_BASE (0xF0B50000ul)
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/* Universal Asynchronous Receiver/Transmitter (UART) 1 */
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#define APB_UART1_BASE (0xF0930000ul)
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/* Universal Asynchronous Receiver/Transmitter (UART) 2 */
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#define APB_UART2_BASE (0xF0C60000ul)
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/* Universal Asynchronous Receiver/Transmitter (UART) 3 */
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#define APB_UART3_BASE (0xF0940000ul)
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/* Universal Asynchronous Receiver/Transmitter (UART) 4 */
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#define APB_UART4_BASE (0xF0C70000ul)
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/* Universal Asynchronous Receiver/Transmitter (UART) 5 */
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#define APB_UART5_BASE (0xF0950000ul)
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/* Universal Asynchronous Receiver/Transmitter (UART) 6 */
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#define APB_UART6_BASE (0xF0C80000ul)
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/* Universal Asynchronous Receiver/Transmitter (UART) 7 */
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#define APB_UART7_BASE (0xF0960000ul)
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/* Universal Asynchronous Receiver/Transmitter (UART) 8 */
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#define APB_UART8_BASE (0xF0C90000ul)
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/* Ethernet (ENET) 1 */
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#define APB_ENET1_BASE (0xF2010000ul)
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/* Ethernet (ENET) 2 */
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#define APB_ENET2_BASE (0xF2020000ul)
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/* Inter-Integrated Circuit (I2C) 3 */
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#define APB_I2C3_BASE (0xF0A40000ul)
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/* Inter-Integrated Circuit (I2C) 4 */
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#define APB_I2C4_BASE (0xF0DE0000ul)
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/* Inter-Integrated Circuit (I2C) 5 */
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#define APB_I2C5_BASE (0xF0A50000ul)
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/* Inter-Integrated Circuit (I2C) 6 */
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#define APB_I2C6_BASE (0xF0DF0000ul)
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/* Serial Peripheral Interface (SPI) 1 */
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#define APB_SPI1_BASE (0xF09F0000ul)
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/* Serial Peripheral Interface (SPI) 2 */
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#define APB_SPI2_BASE (0xF0D90000ul)
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/* Serial Peripheral Interface (SPI) 3 */
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#define APB_SPI3_BASE (0xF0A00000ul)
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/* Serial Peripheral Interface (SPI) 4 */
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#define APB_SPI4_BASE (0xF0DA0000ul)
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/* Serial Peripheral Interface (SPI) 5 */
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#define APB_SPI5_BASE (0xF0A10000ul)
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/* Serial Peripheral Interface (SPI) 6 */
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#define APB_SPI6_BASE (0xF0DB0000ul)
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/*------------------------------------------------------
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* Security
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*------------------------------------------------------*/
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/* Secure Element Intellectual Property */
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#define APB_SEIP_BASE (0xF3100000ul)
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/* SEIP Kbuf */
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#define APB_KBUF_BASE (0xF21DE000ul)
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/* SEIP APB System Reg */
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#define APB_APBSYSTEMREG_BASE (0xF21DD800ul)
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/* SEIP UART0 */
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#define APB_SEIP_UART0_BASE (0xF21DD000ul)
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/* SEIP Mailbox */
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#define APB_SEIP_MAILBOX_BASE (0xF21D8000ul)
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/* SEIP AHB System Reg */
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#define APB_AHBSYSTEMREG_BASE (0xF21D0000ul)
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/* SEIP HFE */
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#define APB_SEIP_HFE_BASE (0xF21CC000ul)
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/* SEIP HKE */
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#define APB_SEIP_SKE_BASE (0xF21C8000ul)
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/* SEIP TRNG */
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#define APB_SEIP_TRNG_BASE (0xF21C4000ul)
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/* SEIP PKE */
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#define APB_SEIP_PKE_BASE (0xF21C0000ul)
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/* SDIP SRAM1 */
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#define APB_SEIP_SRAM1_BASE (0xF21A0000ul)
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/* SEIP SRAM0 */
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#define APB_SEIP_SRAM0_BASE (0xF2180000ul)
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/* SEIP CPU FIO */
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#define APB_SEIP_CPU_FIO_BASE (0xF2160000ul)
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/* SEIP CPU PLIC */
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#define APB_SEIP_CPU_PLIC_BASE (0xF2150000ul)
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/* SEIP CPU CLINT */
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#define APB_SEIP_CPU_CLINT_BASE (0xF2140000ul)
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/* SEIP DTCM */
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#define APB_SEIP_DTCM_BASE (0xF2120000ul)
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/* SEIP ITCM */
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#define APB_SEIP_ITCM_BASE (0xF2100000ul)
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/* E-Fuse controller */
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#define APB_EFUSEC_BASE (0xF05F0000ul)
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/* Secure Storage */
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#define APB_SEC_STORAGE_BASE (0xF00A0000ul)
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/* Tamper Monitor */
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#define APB_TM_BASE (0xF0080000ul)
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/* SEIP Secured Key Buffer */
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#define SEIP_SEIPSECUREDKEYBUFFER_BASE (0x02200000ul)
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/* SEIP */
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#define SEIP_SEIP_BASE (0x02100000ul)
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/*------------------------------------------------------
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* System Control
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*------------------------------------------------------*/
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/* AP Domain Status and Controller Register (SCR) */
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#define APB_SCR_AP_BASE (0xF30F0000ul)
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/* SF Domain Status and Controller Register (SCR) */
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#define APB_SCR_SF_BASE (0xF0680000ul)
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/*------------------------------------------------------
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* I/O Control
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*------------------------------------------------------*/
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/* AP Domain IO Multiplexing Controller(IOMUXC) */
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#define APB_IOMUXC_AP_BASE (0xF30E0000ul)
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/* SF Domain IO Multiplexing Controller(IOMUXC) */
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#define APB_IOMUXC_SF_BASE (0xF0630000ul)
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/* RTC Domain IO Multiplexing Controller (IOMUXC) */
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#define APB_IOMUXC_RTC_BASE (0xF0070000ul)
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/*------------------------------------------------------
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* Clock & Reset
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*------------------------------------------------------*/
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/* AP Domain Reset Generator (RSTGEN) */
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#define APB_RSTGEN_AP_BASE (0xF30D0000ul)
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/* AP Domain Clock Generator (CKGEN) */
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#define APB_CKGEN_AP_BASE (0xF30C0000ul)
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/* Phase Locked Loop (PLL) LVDS */
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#define APB_PLL_LVDS_BASE (0xF30A0000ul)
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/* Phase Locked Loop (PLL) 5 */
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#define APB_PLL5_BASE (0xF3090000ul)
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/* Phase Locked Loop (PLL) 4 */
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#define APB_PLL4_BASE (0xF3080000ul)
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/* Phase Locked Loop (PLL) 3 */
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#define APB_PLL3_BASE (0xF06D0000ul)
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/* Phase Locked Loop (PLL) 2 */
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#define APB_PLL2_BASE (0xF06C0000ul)
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/* Phase Locked Loop (PLL) 1 */
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#define APB_PLL1_BASE (0xF06B0000ul)
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/* SF Domain Clock Generator (CKGEN) */
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#define APB_CKGEN_SF_BASE (0xF06A0000ul)
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/* SF Domain Reset Generator (RSTGEN) */
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#define APB_RSTGEN_SF_BASE (0xF0690000ul)
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/* 24MHZ generation block with failsafe function(FS24M) */
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#define APB_FS_24M_BASE (0xF0660000ul)
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/* 32KHZ generation block with failsafe function (FS32K) */
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#define APB_FS_32K_BASE (0xF0030000ul)
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/*------------------------------------------------------
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* Power Management
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*------------------------------------------------------*/
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/* Temperature Sensor for AP Domain */
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#define APB_PT_SNS_AP_BASE (0xF3060000ul)
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/* Power on Reset for AP Domain */
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#define APB_POR_AP_BASE (0xF3050000ul)
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/* Voltage Detector for AP Domain */
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#define APB_VD_AP_BASE (0xF3040000ul)
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/* Temperature Sensor for SF Domain */
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#define APB_PT_SNS_SF_BASE (0xF06F0000ul)
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/* Voltage Detector for SF Domain */
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#define APB_VD_SF_BASE (0xF06E0000ul)
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/* Power on Reset for Safety Domain */
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#define APB_POR_SF_BASE (0xF0650000ul)
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/* System Work Mode Controller(SMC) */
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#define APB_SMC_BASE (0xF0640000ul)
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/* Linear Mode Regulator Controller(LDO) */
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#define APB_LDO_DIG_BASE (0xF0610000ul)
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/* Digital controller of bulk mode DC-DC converter(DCDC) */
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#define APB_DCDC1_BASE (0xF0600000ul)
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/* Power Management Unit */
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#define APB_PMU_CORE_BASE (0xF0060000ul)
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/*------------------------------------------------------
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* Debug
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*------------------------------------------------------*/
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/* CoreSight */
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#define APB_CSSYS_BASE (0xF2080000ul)
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/*------------------------------------------------------
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* FuSa
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*------------------------------------------------------*/
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/* Error Injection Controller for SP Domain */
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#define APB_EIC_SP_BASE (0xF2050000ul)
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/* Error Injection Controller for SF Domain */
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#define APB_EIC_SF_BASE (0xF0FE0000ul)
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/* System Error Management 2 */
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#define APB_SEM2_BASE (0xF07D0000ul)
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/* System Error Management 1 */
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#define APB_SEM1_BASE (0xF07C0000ul)
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/* Input/Output Consistency */
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#define APB_IOC_BASE (0xF0750000ul)
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/* Error Injection Controller for Boot */
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#define APB_EIC_BOOT_BASE (0xF0720000ul)
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/*------------------------------------------------------
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* External Memory Interface
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*------------------------------------------------------*/
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/* Extended SPI Slave */
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#define APB_XSPI_SLV_BASE (0xF2040000ul)
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/* Extended SPI1 Port B */
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#define XSPI1_XSPI1PORTB_BASE (0x18000000ul)
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/* Extended SPI1 */
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#define XSPI1_BASE (0x10000000ul)
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/* Extended SPI1 Port A */
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#define XSPI1_XSPI1PORTA_BASE (0x10000000ul)
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/* Extended SPI 1 Port B Control Registers */
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#define APB_XSPI1PORTB_BASE (0xF0710000ul)
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/* Extended SPI 1 Port A Control Registers */
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#define APB_XSPI1PORTA_BASE (0xF0700000ul)
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/* Extended SPI2 Port B */
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#define XSPI2_XSPI2PORTB_BASE (0x28000000ul)
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/* Extended SPI2 */
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#define XSPI2_BASE (0x20000000ul)
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/* Extended SPI2 Port A */
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#define XSPI2_XSPI2PORTA_BASE (0x20000000ul)
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/* Extended SPI 2 Port B Control Registers */
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#define APB_XSPI2PORTB_BASE (0xF0BD0000ul)
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/* Extended SPI 2 Port A Control Registers */
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#define APB_XSPI2PORTA_BASE (0xF0BC0000ul)
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/* SD/EMMC Host Controller 2 */
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#define APB_SEHC2_BASE (0xF3170000ul)
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/* SD/EMMC Host Controller 1 */
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#define APB_SEHC1_BASE (0xF3160000ul)
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/* SDRAM Controller */
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#define APB_SDRAMC_BASE (0xF3130000ul)
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/* DDR Memory */
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#define DRAM_BASE (0x30000000ul)
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/*------------------------------------------------------
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* Access Permission Control
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*------------------------------------------------------*/
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/* Memory Access Controller */
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#define APB_MAC_BASE (0xF07B0000ul)
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/*------------------------------------------------------
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* Internal Memory Configuration
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*------------------------------------------------------*/
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/* Internal ROM Controller */
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#define APB_IROMC_BASE (0xF0670000ul)
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/* IRAM1 RAM Controller */
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#define APB_IRAMC1_BASE (0xF0D20000ul)
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/* IRAM2 RAM Controller */
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#define APB_IRAMC2_BASE (0xF0D30000ul)
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/* IRAM3 RAM Controller */
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#define APB_IRAMC3_BASE (0xF0D40000ul)
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/* IRAM4 RAM Controller */
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#define APB_IRAMC4_BASE (0xF2030000ul)
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/*------------------------------------------------------
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* Misc
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*------------------------------------------------------*/
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/* In System Test Controller */
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#define APB_ISTC_BASE (0xF0620000ul)
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/*------------------------------------------------------
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* Timers
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*------------------------------------------------------*/
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/* Basic Timer Module (BTM) 6 */
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#define APB_BTM6_BASE (0xF0470000ul)
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/* Basic Timer Module (BTM) 5 */
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#define APB_BTM5_BASE (0xF0460000ul)
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/* Basic Timer Module (BTM) 4 */
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#define APB_BTM4_BASE (0xF0450000ul)
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/* Basic Timer Module (BTM) 3 */
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#define APB_BTM3_BASE (0xF0440000ul)
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/* Basic Timer Module (BTM) 2 */
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#define APB_BTM2_BASE (0xF0430000ul)
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/* Basic Timer Module (BTM) 1 */
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#define APB_BTM1_BASE (0xF0420000ul)
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/* Cross Trigger */
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#define APB_XTRG_BASE (0xF0410000ul)
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/* Real Time Clock 2 */
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#define APB_RTC2_BASE (0xF0020000ul)
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/* Real Time Clock 1 */
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#define APB_RTC1_BASE (0xF0010000ul)
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/* Targeting general purpose timer 1 */
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#define APB_ETMR1_BASE (0xF04C0000ul)
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/* Targeting general purpose timer 2 */
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#define APB_ETMR2_BASE (0xF04D0000ul)
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/* Targeting general purpose timer 3 */
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#define APB_ETMR3_BASE (0xF04E0000ul)
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/* Targeting general purpose timer 4 */
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#define APB_ETMR4_BASE (0xF04F0000ul)
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/* Energy Pulse-Width Modulator 1 */
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#define APB_EPWM1_BASE (0xF0480000ul)
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/* Energy Pulse-Width Modulator 2 */
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#define APB_EPWM2_BASE (0xF0490000ul)
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/* Energy Pulse-Width Modulator 3 */
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#define APB_EPWM3_BASE (0xF04A0000ul)
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/* Energy Pulse-Width Modulator 4 */
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#define APB_EPWM4_BASE (0xF04B0000ul)
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/* Watch Dog(WDT) 1 */
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#define APB_WDT1_BASE (0xF07E0000ul)
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/* Watch Dog(WDT) 2 */
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#define APB_WDT2_BASE (0xF07F0000ul)
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/* Watch Dog(WDT) 8 */
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#define APB_WDT8_BASE (0xF31F0000ul)
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/*------------------------------------------------------
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* CPU
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*------------------------------------------------------*/
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/* Cluster 0 D-Cache */
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#define R5_SF_CACHE_R5_SF_DCACHE_BASE (0x01978000ul)
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/* Cluster 0 I-Cache */
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#define R5_SF_CACHE_R5_SF_ICACHE_BASE (0x01970000ul)
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/* Cluster 0 TCM A */
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#define R5_SF_TCM_R5_SF_TCMA_BASE (0x01940000ul)
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/* Cluster 0 TCM B */
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#define R5_SF_TCM_R5_SF_TCMB_BASE (0x01930000ul)
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/*------------------------------------------------------
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* IRAM
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*------------------------------------------------------*/
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/* Internal RAM 1 */
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#define IRAM1_BASE (0x00400000ul)
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/* RAM for IRAM1 ECC. Used as internal RAM when ECC is disabled. */
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#define IRAM1_ECC_BASE (0x00860000ul)
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/* IRAM1_ECC Aliased Address */
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#define IRAM1_ECCALIASED_BASE (0x00B80000ul)
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/* IRAM1 Aliased Address */
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#define IRAM1ALIASED_BASE (0x00C00000ul)
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/* Internal RAM 2 */
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#define IRAM2_BASE (0x00500000ul)
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/* RAM for IRAM2 ECC. Used as internal RAM when ECC is disabled. */
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#define IRAM2_ECC_BASE (0x00840000ul)
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/* IRAM2_ECC Aliased Address */
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#define IRAM2_ECCALIASED_BASE (0x00BA0000ul)
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/* IRAM2 Aliased Address */
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#define IRAM2ALIASED_BASE (0x00D00000ul)
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/* Internal RAM 3 */
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#define IRAM3_BASE (0x00600000ul)
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/* RAM for IRAM3 ECC. Used as internal RAM when ECC is disabled. */
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#define IRAM3_ECC_BASE (0x00820000ul)
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/* IRAM3_ECC Aliased Address */
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#define IRAM3_ECCALIASED_BASE (0x00BC0000ul)
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/* IRAM3 Aliased Address */
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#define IRAM3ALIASED_BASE (0x00E00000ul)
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/* IRAM4 */
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#define IRAM4_BASE (0x00700000ul)
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/* RAM for IRAM4 ECC. Used as internal RAM when ECC is disabled. */
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#define IRAM4_ECC_BASE (0x00800000ul)
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/* IRAM4_ECC Aliased Address */
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#define IRAM4_ECCALIASED_BASE (0x00BE0000ul)
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/* IRAM4 Aliased Address */
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#define IRAM4ALIASED_BASE (0x00F00000ul)
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/*------------------------------------------------------
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|
* USB
|
|
*------------------------------------------------------*/
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/* USB Controller */
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#define APB_USB_BASE (0xF30B0000ul)
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/*------------------------------------------------------
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|
* Audio
|
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*------------------------------------------------------*/
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|
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/* Serial Audio Controller Interface 1 */
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#define APB_SACI1_BASE (0xF3010000ul)
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/* Serial Audio Controller Interface 2 */
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#define APB_SACI2_BASE (0xF3020000ul)
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|
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/*------------------------------------------------------
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* ADC & ACMP
|
|
*------------------------------------------------------*/
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|
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/* Analog Digital Converter 1 */
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#define APB_ADC1_BASE (0xF0F70000ul)
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|
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/* Analog Digital Converter 2 */
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#define APB_ADC2_BASE (0xF0F80000ul)
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|
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/* Analog Digital Converter 3 */
|
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#define APB_ADC3_BASE (0xF0F90000ul)
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|
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/* Analog Compare (ACMP) 1 */
|
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#define APB_ACMP1_BASE (0xF0FA0000ul)
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|
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/* Analog Compare (ACMP) 2 */
|
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#define APB_ACMP2_BASE (0xF0FB0000ul)
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|
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/* Analog Compare (ACMP) 3 */
|
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#define APB_ACMP3_BASE (0xF0FC0000ul)
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|
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/* Analog Compare (ACMP) 4 */
|
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#define APB_ACMP4_BASE (0xF0FD0000ul)
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|
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/*------------------------------------------------------
|
|
* Camera
|
|
*------------------------------------------------------*/
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|
|
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/* CMOS Sensor Interface */
|
|
#define APB_CSI_BASE (0xF3460000ul)
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|
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/*------------------------------------------------------
|
|
* Energy Processing Unit
|
|
*------------------------------------------------------*/
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|
|
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#endif /* REGS_BASE_H */
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