298 lines
20 KiB
C
298 lines
20 KiB
C
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//*****************************************************************************
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//
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// WARNING: Automatically generated file, don't modify anymore!!!
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//
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// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
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// Software License Agreement
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//
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//*****************************************************************************
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#ifndef IRQ_NUM_H
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#define IRQ_NUM_H
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#define MB_MU_MESSAGE_READY_INTR_NUM 0
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#define MB_MU_WAKEUP_INTR_NUM 1
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#define MB_SEMAPHORE_LOCK_FAIL_INTR_NUM 2
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#define MB_SEMAPHORE_LOCK_STATUS_CHANGE_INTR_NUM 3
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#define GPIO_SF_SYNC_DGPIO_INTR_NUM 4
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#define GPIO_SF_ASYNC_DGPIO_INTR_NUM 4
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#define GPIO_SF_SYNC_GRP_0_INTR_NUM 5
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#define GPIO_SF_ASYNC_GRP_0_INTR_NUM 5
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#define GPIO_SF_SYNC_GRP_1_INTR_NUM 6
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#define GPIO_SF_ASYNC_GRP_1_INTR_NUM 6
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#define GPIO_SF_SYNC_GRP_2_INTR_NUM 7
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#define GPIO_SF_ASYNC_GRP_2_INTR_NUM 7
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#define GPIO_SF_SYNC_GRP_3_INTR_NUM 8
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#define GPIO_SF_ASYNC_GRP_3_INTR_NUM 8
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#define GPIO_SF_SYNC_GRP_4_INTR_NUM 9
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#define GPIO_SF_ASYNC_GRP_4_INTR_NUM 9
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#define CR5_SF_NPMUIRQ0_INTR_NUM 10
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#define GPIO_AP_SYNC_DGPIO_INTR_NUM 11
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#define GPIO_AP_ASYNC_DGPIO_INTR_NUM 11
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#define GPIO_AP_SYNC_GRP_0_INTR_NUM 12
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#define GPIO_AP_ASYNC_GRP_0_INTR_NUM 12
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#define GPIO_AP_SYNC_GRP_1_INTR_NUM 13
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#define GPIO_AP_ASYNC_GRP_1_INTR_NUM 13
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#define GPIO_AP_SYNC_GRP_2_INTR_NUM 14
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#define GPIO_AP_ASYNC_GRP_2_INTR_NUM 14
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#define SMC_SMC_WAKEUP_0_INTR_NUM 15
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#define WDT1_WDT_INTR_NUM 16
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#define WDT2_WDT_INTR_NUM 17
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#define WDT8_WDT_INTR_NUM 22
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#define DMA_SF_DMA0_CH_0_INTR_NUM 23
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#define DMA_SF_DMA0_CH_1_INTR_NUM 24
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#define DMA_SF_DMA0_CH_2_INTR_NUM 25
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#define DMA_SF_DMA0_CH_3_INTR_NUM 26
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#define DMA_SF_DMA0_CH_4_INTR_NUM 27
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#define DMA_SF_DMA0_CH_5_INTR_NUM 28
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#define DMA_SF_DMA0_CH_6_INTR_NUM 29
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#define DMA_SF_DMA0_CH_7_INTR_NUM 30
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#define DMA_SF_DMA0_CH_8_INTR_NUM 31
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#define DMA_SF_DMA0_CH_9_INTR_NUM 32
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#define DMA_SF_DMA0_CH_10_INTR_NUM 33
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#define DMA_SF_DMA0_CH_11_INTR_NUM 34
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#define DMA_SF_DMA0_CH_12_INTR_NUM 35
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#define DMA_SF_DMA0_CH_13_INTR_NUM 36
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#define DMA_SF_DMA0_CH_14_INTR_NUM 37
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#define DMA_SF_DMA0_CH_15_INTR_NUM 38
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#define DMA_SF_DMA0_CH_16_INTR_NUM 39
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#define DMA_SF_DMA0_CH_17_INTR_NUM 40
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#define DMA_SF_DMA0_CH_18_INTR_NUM 41
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#define DMA_SF_DMA0_CH_19_INTR_NUM 42
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#define DMA_SF_DMA0_CH_20_INTR_NUM 43
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#define DMA_SF_DMA0_CH_21_INTR_NUM 44
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#define DMA_SF_DMA0_CH_22_INTR_NUM 45
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#define DMA_SF_DMA0_CH_23_INTR_NUM 46
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#define DMA_SF_DMA0_INTR_NUM 47
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#define DMA_SF_DMA1_CH_0_INTR_NUM 48
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#define DMA_SF_DMA1_CH_1_INTR_NUM 49
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#define DMA_SF_DMA1_CH_2_INTR_NUM 50
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#define DMA_SF_DMA1_CH_3_INTR_NUM 51
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#define DMA_SF_DMA1_CH_4_INTR_NUM 52
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#define DMA_SF_DMA1_CH_5_INTR_NUM 53
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#define DMA_SF_DMA1_CH_6_INTR_NUM 54
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#define DMA_SF_DMA1_CH_7_INTR_NUM 55
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#define DMA_SF_DMA1_CH_8_INTR_NUM 56
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#define DMA_SF_DMA1_CH_9_INTR_NUM 57
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#define DMA_SF_DMA1_CH_10_INTR_NUM 58
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#define DMA_SF_DMA1_CH_11_INTR_NUM 59
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#define DMA_SF_DMA1_CH_12_INTR_NUM 60
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#define DMA_SF_DMA1_CH_13_INTR_NUM 61
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#define DMA_SF_DMA1_CH_14_INTR_NUM 62
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#define DMA_SF_DMA1_CH_15_INTR_NUM 63
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#define DMA_SF_DMA1_CH_16_INTR_NUM 64
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#define DMA_SF_DMA1_CH_17_INTR_NUM 65
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#define DMA_SF_DMA1_CH_18_INTR_NUM 66
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#define DMA_SF_DMA1_CH_19_INTR_NUM 67
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#define DMA_SF_DMA1_CH_20_INTR_NUM 68
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#define DMA_SF_DMA1_CH_21_INTR_NUM 69
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#define DMA_SF_DMA1_CH_22_INTR_NUM 70
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#define DMA_SF_DMA1_CH_23_INTR_NUM 71
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#define DMA_SF_DMA1_INTR_NUM 72
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#define DMA_AP_DMA_CH_0_INTR_NUM 73
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#define DMA_AP_DMA_CH_1_INTR_NUM 74
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#define DMA_AP_DMA_CH_2_INTR_NUM 75
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#define DMA_AP_DMA_CH_3_INTR_NUM 76
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#define DMA_AP_DMA_CH_4_INTR_NUM 77
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#define DMA_AP_DMA_CH_5_INTR_NUM 78
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#define DMA_AP_DMA_CH_6_INTR_NUM 79
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#define DMA_AP_DMA_CH_7_INTR_NUM 80
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#define DMA_AP_DMA_INTR_NUM 81
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#define DMA_AP_DMA_AP_UNCERR_INTR_NUM 82
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#define SEM1_O_SEM_CPU_INTR_NUM 84
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#define SEM2_O_SEM_CPU_INTR_NUM 85
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#define UART1_INTR_NUM 86
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#define UART2_INTR_NUM 87
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#define UART3_INTR_NUM 88
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#define UART4_INTR_NUM 89
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#define UART5_INTR_NUM 90
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#define UART6_INTR_NUM 91
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#define UART7_INTR_NUM 92
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#define UART8_INTR_NUM 93
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#define I2C3_INTR_NUM 104
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#define I2C4_INTR_NUM 105
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#define I2C5_INTR_NUM 106
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#define I2C6_INTR_NUM 107
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#define SPI1_SPI_INTR_NUM 110
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#define SPI2_SPI_INTR_NUM 111
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#define SPI3_SPI_INTR_NUM 112
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#define SPI4_SPI_INTR_NUM 113
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#define SPI5_SPI_INTR_NUM 114
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#define SPI6_SPI_INTR_NUM 115
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#define XSPI1_IRQ0_INTR_NUM 118
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#define XSPI1_IRQ1_INTR_NUM 119
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#define XSPI2_IRQ0_INTR_NUM 120
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#define XSPI2_IRQ1_INTR_NUM 121
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#define XSPI_SLV_INTR_NUM 122
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#define SACI1_I2S_INTR_NUM 123
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#define SACI1_PDM_INTR_NUM 124
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#define SACI2_I2S_INTR_NUM 125
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#define SACI2_PDM_INTR_NUM 126
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#define USB_INTR_NUM 127
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#define ENET1_SBD_INTR_NUM 128
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#define ENET1_SBD_PERCH_TX_O0_INTR_NUM 129
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#define ENET1_SBD_PERCH_TX_O1_INTR_NUM 129
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#define ENET1_SBD_PERCH_TX_O2_INTR_NUM 129
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#define ENET1_SBD_PERCH_TX_O3_INTR_NUM 129
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#define ENET1_SBD_PERCH_TX_O4_INTR_NUM 129
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#define ENET1_SBD_PERCH_RX_O0_INTR_NUM 129
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#define ENET1_SBD_PERCH_RX_O1_INTR_NUM 129
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#define ENET1_SBD_PERCH_RX_O2_INTR_NUM 129
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#define ENET1_SBD_PERCH_RX_O3_INTR_NUM 129
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#define ENET1_SBD_PERCH_RX_O4_INTR_NUM 129
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#define ENET1_LPI_INTR_NUM 130
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#define ENET1_PMT_INTR_NUM 130
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#define ENET2_SBD_INTR_NUM 131
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#define ENET2_SBD_PERCH_TX_O0_INTR_NUM 132
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#define ENET2_SBD_PERCH_TX_O1_INTR_NUM 132
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#define ENET2_SBD_PERCH_TX_O2_INTR_NUM 132
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#define ENET2_SBD_PERCH_TX_O3_INTR_NUM 132
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#define ENET2_SBD_PERCH_TX_O4_INTR_NUM 132
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#define ENET2_SBD_PERCH_RX_O0_INTR_NUM 132
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#define ENET2_SBD_PERCH_RX_O1_INTR_NUM 132
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#define ENET2_SBD_PERCH_RX_O2_INTR_NUM 132
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#define ENET2_SBD_PERCH_RX_O3_INTR_NUM 132
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#define ENET2_SBD_PERCH_RX_O4_INTR_NUM 132
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#define ENET2_LPI_INTR_NUM 133
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#define ENET2_PMT_INTR_NUM 133
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#define SEHC1_SEHC_INTR_NUM 136
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#define SEHC1_SEHC_WAKEUP_INTR_NUM 137
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#define SEHC2_SEHC_INTR_NUM 138
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#define SEHC2_SEHC_WAKEUP_INTR_NUM 139
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#define DC_DC_IRQ0_INTR_NUM 140
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#define DC_DC_IRQ1_INTR_NUM 141
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#define CSI_INTR_NUM 142
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#define G2D_G2D_INTR_NUM 143
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#define CANFD3_CANFD_INTR_NUM 146
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#define CANFD4_CANFD_INTR_NUM 147
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#define CANFD16_CANFD_INTR_NUM 159
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#define CANFD21_CANFD_INTR_NUM 164
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#define SEIP_PKE_INTR_NUM 182
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#define SEIP_SKE_INTR_NUM 183
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#define SEIP_HASH_INTR_NUM 184
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#define SEIP_TRNG_INTR_NUM 185
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#define SEIP_KEY_CHK_INTR_NUM 186
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#define SEIP_SOC_INTR_NUM 187
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#define SEIP_UART_INTR_NUM 188
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#define SEIP_SENSOR_INTR_NUM 189
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#define SEIP_O_INTR_SE2SOC_MBOX_INTR_NUM 190
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#define SEIP_SEIP_ERR_INTR_NUM 191
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#define SDRAMC_SDRAMC_INTR_NUM 192
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#define BTM1_O_BTM_INTR_NUM 193
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#define BTM2_O_BTM_INTR_NUM 194
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#define BTM3_O_BTM_INTR_NUM 195
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#define BTM4_O_BTM_INTR_NUM 196
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#define BTM5_O_BTM_INTR_NUM 197
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#define BTM6_O_BTM_INTR_NUM 198
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#define ETMR1_CHN_A_INTR_NUM 199
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#define ETMR1_CHN_B_INTR_NUM 199
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#define ETMR1_CHN_C_INTR_NUM 199
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#define ETMR1_CHN_D_INTR_NUM 199
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#define ETMR1_CNT_OVF_INTR_NUM 200
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#define ETMR2_CHN_A_INTR_NUM 201
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#define ETMR2_CHN_B_INTR_NUM 201
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#define ETMR2_CHN_C_INTR_NUM 201
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#define ETMR2_CHN_D_INTR_NUM 201
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#define ETMR2_CNT_OVF_INTR_NUM 202
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#define ETMR3_CHN_A_INTR_NUM 203
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#define ETMR3_CHN_B_INTR_NUM 203
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#define ETMR3_CHN_C_INTR_NUM 203
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#define ETMR3_CHN_D_INTR_NUM 203
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#define ETMR3_CNT_OVF_INTR_NUM 204
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#define ETMR4_CHN_A_INTR_NUM 205
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#define ETMR4_CHN_B_INTR_NUM 205
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#define ETMR4_CHN_C_INTR_NUM 205
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#define ETMR4_CHN_D_INTR_NUM 205
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#define ETMR4_CNT_OVF_INTR_NUM 206
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#define EPWM1_CHN_A_INTR_NUM 207
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#define EPWM1_CHN_B_INTR_NUM 207
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#define EPWM1_CHN_C_INTR_NUM 207
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#define EPWM1_CHN_D_INTR_NUM 207
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#define EPWM1_CNT_OVF_INTR_NUM 208
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#define EPWM2_CHN_A_INTR_NUM 209
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#define EPWM2_CHN_B_INTR_NUM 209
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#define EPWM2_CHN_C_INTR_NUM 209
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#define EPWM2_CHN_D_INTR_NUM 209
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#define EPWM2_CNT_OVF_INTR_NUM 210
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#define EPWM3_CHN_A_INTR_NUM 211
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#define EPWM3_CHN_B_INTR_NUM 211
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#define EPWM3_CHN_C_INTR_NUM 211
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#define EPWM3_CHN_D_INTR_NUM 211
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#define EPWM3_CNT_OVF_INTR_NUM 212
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#define EPWM4_CHN_A_INTR_NUM 213
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#define EPWM4_CHN_B_INTR_NUM 213
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#define EPWM4_CHN_C_INTR_NUM 213
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#define EPWM4_CHN_D_INTR_NUM 213
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#define EPWM4_CNT_OVF_INTR_NUM 214
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#define XTRG_FUNC_INTR_NUM 215
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#define IOC_GPIO_SYNC_INTR_NUM 216
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#define IOC_GPIO_ASYNC_INTR_NUM 216
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#define RTC1_RTC_WAKEUP_INTR_NUM 217
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#define RTC1_RTC_PERIODICAL_INTR_NUM 218
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#define RTC1_VIOLATION_INTR_NUM 219
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#define RTC2_RTC_WAKEUP_INTR_NUM 220
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#define RTC2_RTC_PERIODICAL_INTR_NUM 221
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#define RTC2_VIOLATION_INTR_NUM 222
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#define TM_VIOLATION_INTR_NUM 223
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#define VD_AP_O_VDC_FUNC_INTR_NUM 224
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#define VD_SF_DIG_O_VDC_FUNC_INTR_NUM 225
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#define PT_SNS_AP_PVT_0_INTR_NUM 226
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#define PT_SNS_AP_PVT_1_INTR_NUM 227
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#define PT_SNS_SF_DIG_PVT_0_INTR_NUM 228
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#define PT_SNS_SF_DIG_PVT_1_INTR_NUM 229
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#define SCR_SF_SCR_APB_PSLVERR_INTR_NUM 230
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#define SCR_AP_SCR_INTR_NUM 231
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#define PMU_CORE_PMU_INTR_NUM 232
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#define RSTGEN_SF_RSTGEN_INTR_NUM 233
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#define U_CKGEN_SF_CKGEN_INTR_NUM 234
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#define RSTGEN_AP_RSTGEN_INTR_NUM 235
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#define U_CKGEN_AP_CKGEN_INTR_NUM 236
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#define SMC_SMC_INTR_NUM 237
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#define SADC1_O_SADC_INTR_NUM 238
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#define SADC2_O_SADC_INTR_NUM 239
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#define SADC3_O_SADC_INTR_NUM 240
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#define ACMP1_O_ACMP_INTR_NUM 241
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#define ACMP2_O_ACMP_INTR_NUM 242
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#define ACMP3_O_ACMP_INTR_NUM 243
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#define ACMP4_O_ACMP_INTR_NUM 244
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#define DCDC1_O_DCDC_FUNC_INTR_NUM 245
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#define LDO_DIG_O_LDO_FUNC_INTR_NUM 246
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#define FS_32K_FS_32K_INTR_NUM 247
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#define ISTC_INTR_NUM 249
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#define MPC_XSPI1A_FUNC_INTR_NUM 250
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#define MPC_XSPI1B_FUNC_INTR_NUM 250
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#define MPC_XSPI2A_FUNC_INTR_NUM 250
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#define MPC_XSPI2B_FUNC_INTR_NUM 250
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#define MPC_R5SX_S0_FUNC_INTR_NUM 250
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#define MPC_R5SX_S1_FUNC_INTR_NUM 250
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#define MPC_VIC3A_FUNC_INTR_NUM 250
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#define MPC_VIC3B_FUNC_INTR_NUM 250
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#define MPC_R5SF_S_FUNC_INTR_NUM 250
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#define MPC_MB_FUNC_INTR_NUM 250
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#define MPC_ROMC_FUNC_INTR_NUM 250
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#define MPC_IRAMC1_FUNC_INTR_NUM 250
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#define MPC_IRAMC2_FUNC_INTR_NUM 250
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#define MPC_IRAMC3_FUNC_INTR_NUM 250
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#define MPC_IRAMC4_FUNC_INTR_NUM 250
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#define MPC_VIC1_FUNC_INTR_NUM 250
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#define MAC_FUNC_INTR_NUM 250
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#define PPC_APBMUX2_FUNC_INTR_NUM 250
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#define PPC_APBMUX3_FUNC_INTR_NUM 250
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#define PPC_APBMUX4_FUNC_INTR_NUM 250
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#define MPC_CR5_SP0_FUNC_INTR_NUM 250
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#define MPC_CR5_SP1_FUNC_INTR_NUM 250
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#define MPC_VIC2A_FUNC_INTR_NUM 250
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#define MPC_VIC2B_FUNC_INTR_NUM 250
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#define PPC_APBMUX5_FUNC_INTR_NUM 250
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#define MPC_SDRAMC_FUNC_INTR_NUM 250
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#define MPC_SEIP_FUNC_INTR_NUM 250
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#define PPC_APBMUX1_FUNC_INTR_NUM 250
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#define PPC_APBMUX6_FUNC_INTR_NUM 250
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#define PPC_APBMUX7_FUNC_INTR_NUM 250
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#define GPIO_SF_SGPIO_INTR_NUM 251
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#define IRQ_MAX_INTR_NUM 252
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#endif /* IRQ_NUM_H */
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