669 lines
39 KiB
C
669 lines
39 KiB
C
/**
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* @file scr_hw.h
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* @brief Status and Controller Register (SCR) signal header file.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef _SCR_HW_H_
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#define _SCR_HW_H_
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#define SCR_SF_EFUSEC_MANU_CFG_87_64 {TYPE_RO, 32, 24}
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#define SCR_SF_EFUSEC_MISC_CFG_7 {TYPE_RO, 56, 1}
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#define SCR_SF_EFUSEC_MANU_CFG_95 {TYPE_RO, 57, 1}
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#define SCR_SF_EFUSEC_FA_CFG_0 {TYPE_RO, 58, 1}
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#define SCR_SF_FAB_SF_M_F_0_I_MAINNOPENDINGTRANS {TYPE_RO, 64, 1}
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#define SCR_SF_FAB_SF_M_F_1_I_MAINNOPENDINGTRANS {TYPE_RO, 65, 1}
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#define SCR_SF_FAB_SF_S_F_8_T_MAINNOPENDINGTRANS {TYPE_RO, 66, 1}
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#define SCR_SF_FAB_SF_M_F_10_I_MAINNOPENDINGTRANS {TYPE_RO, 67, 1}
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#define SCR_SF_FAB_SF_M_F_11_I_MAINNOPENDINGTRANS {TYPE_RO, 68, 1}
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#define SCR_SF_FAB_SF_M_F_12_I_MAINNOPENDINGTRANS {TYPE_RO, 69, 1}
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#define SCR_SF_FAB_SF_M_F_13_I_MAINNOPENDINGTRANS {TYPE_RO, 70, 1}
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#define SCR_SF_FAB_SF_S_F_12_T_MAINNOPENDINGTRANS {TYPE_RO, 71, 1}
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#define SCR_SF_FAB_SF_S_F_13_T_MAINNOPENDINGTRANS {TYPE_RO, 72, 1}
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#define SCR_SF_FAB_SF_M_F_2_I_MAINNOPENDINGTRANS {TYPE_RO, 73, 1}
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#define SCR_SF_FAB_SF_M_F_3_I_MAINNOPENDINGTRANS {TYPE_RO, 74, 1}
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#define SCR_SF_FAB_SF_M_F_4_I_MAINNOPENDINGTRANS {TYPE_RO, 75, 1}
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#define SCR_SF_FAB_SF_M_F_5_I_MAINNOPENDINGTRANS {TYPE_RO, 76, 1}
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#define SCR_SF_FAB_SF_M_F_6_I_MAINNOPENDINGTRANS {TYPE_RO, 77, 1}
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#define SCR_SF_FAB_SF_M_F_7_I_MAINNOPENDINGTRANS {TYPE_RO, 78, 1}
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#define SCR_SF_FAB_SF_M_F_8_I_MAINNOPENDINGTRANS {TYPE_RO, 79, 1}
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#define SCR_SF_FAB_SF_S_F_0_T_MAINNOPENDINGTRANS {TYPE_RO, 80, 1}
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#define SCR_SF_FAB_SF_S_F_10_T_MAINNOPENDINGTRANS {TYPE_RO, 81, 1}
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#define SCR_SF_FAB_SF_S_F_11_T_MAINNOPENDINGTRANS {TYPE_RO, 82, 1}
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#define SCR_SF_FAB_SF_S_F_1_T_MAINNOPENDINGTRANS {TYPE_RO, 83, 1}
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#define SCR_SF_FAB_SF_S_F_2_T_MAINNOPENDINGTRANS {TYPE_RO, 84, 1}
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#define SCR_SF_FAB_SF_S_F_3_T_MAINNOPENDINGTRANS {TYPE_RO, 85, 1}
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#define SCR_SF_FAB_SF_S_F_5_T_MAINNOPENDINGTRANS {TYPE_RO, 86, 1}
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#define SCR_SF_FAB_SF_M_F_GPV_I_MAINNOPENDINGTRANS {TYPE_RO, 87, 1}
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#define SCR_SF_FAB_SF_S_F_9_T_MAINNOPENDINGTRANS {TYPE_RO, 88, 1}
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#define SCR_SF_FAB_SF_SVREG_T_MAINNOPENDINGTRANS {TYPE_RO, 89, 1}
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#define SCR_SF_FAB_SF_SVREG_MAINNOPENDINGTRANS {TYPE_RO, 90, 1}
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#define SCR_SF_FAB_SF_S_F_6A_T_MAINNOPENDINGTRANS {TYPE_RO, 91, 1}
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#define SCR_SF_FAB_SF_S_F_6B_T_MAINNOPENDINGTRANS {TYPE_RO, 92, 1}
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#define SCR_SF_FAB_SF_S_F_7A_T_MAINNOPENDINGTRANS {TYPE_RO, 93, 1}
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#define SCR_SF_FAB_SF_S_F_7B_T_MAINNOPENDINGTRANS {TYPE_RO, 94, 1}
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#define SCR_SF_FAB_SX_M_H_0_I_MAINNOPENDINGTRANS {TYPE_RO, 96, 1}
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#define SCR_SF_FAB_SX_M_H_1_I_MAINNOPENDINGTRANS {TYPE_RO, 97, 1}
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#define SCR_SF_FAB_SX_M_H_GPV_I_MAINNOPENDINGTRANS {TYPE_RO, 98, 1}
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#define SCR_SF_FAB_SX_NOC_REG_T_MAINNOPENDINGTRANS {TYPE_RO, 99, 1}
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#define SCR_SF_FAB_SX_NOC_REG_MAINNOPENDINGTRANS {TYPE_RO, 100, 1}
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#define SCR_SF_FAB_SX_S_H_0_T_MAINNOPENDINGTRANS {TYPE_RO, 101, 1}
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#define SCR_SF_FAB_SP_M_P_0_I_MAINNOPENDINGTRANS {TYPE_RO, 128, 1}
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#define SCR_SF_FAB_SP_M_P_1_I_MAINNOPENDINGTRANS {TYPE_RO, 129, 1}
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#define SCR_SF_FAB_SP_M_P_2_I_MAINNOPENDINGTRANS {TYPE_RO, 130, 1}
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#define SCR_SF_FAB_SP_M_P_3_I_MAINNOPENDINGTRANS {TYPE_RO, 131, 1}
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#define SCR_SF_FAB_SP_S_P_0_T_MAINNOPENDINGTRANS {TYPE_RO, 132, 1}
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#define SCR_SF_FAB_SP_S_P_1_T_MAINNOPENDINGTRANS {TYPE_RO, 133, 1}
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#define SCR_SF_FAB_SP_M_P_10_I_MAINNOPENDINGTRANS {TYPE_RO, 134, 1}
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#define SCR_SF_FAB_SP_M_P_5_I_MAINNOPENDINGTRANS {TYPE_RO, 135, 1}
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#define SCR_SF_FAB_SP_M_P_6_I_MAINNOPENDINGTRANS {TYPE_RO, 136, 1}
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#define SCR_SF_FAB_SP_M_P_7_I_MAINNOPENDINGTRANS {TYPE_RO, 137, 1}
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#define SCR_SF_FAB_SP_S_P_10_T_MAINNOPENDINGTRANS {TYPE_RO, 138, 1}
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#define SCR_SF_FAB_SP_S_P_2_T_MAINNOPENDINGTRANS {TYPE_RO, 139, 1}
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#define SCR_SF_FAB_SP_S_P_3_T_MAINNOPENDINGTRANS {TYPE_RO, 140, 1}
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#define SCR_SF_FAB_SP_S_P_5_T_MAINNOPENDINGTRANS {TYPE_RO, 141, 1}
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#define SCR_SF_FAB_SP_S_P_7_T_MAINNOPENDINGTRANS {TYPE_RO, 142, 1}
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#define SCR_SF_FAB_SP_S_P_8_T_MAINNOPENDINGTRANS {TYPE_RO, 143, 1}
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#define SCR_SF_FAB_SP_M_P_GPV_I_MAINNOPENDINGTRANS {TYPE_RO, 144, 1}
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#define SCR_SF_FAB_SP_S_P_4_T_MAINNOPENDINGTRANS {TYPE_RO, 145, 1}
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#define SCR_SF_FAB_SP_SVREG_T_MAINNOPENDINGTRANS {TYPE_RO, 146, 1}
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#define SCR_SF_FAB_SP_SVREG_MAINNOPENDINGTRANS {TYPE_RO, 147, 1}
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#define SCR_SF_FAB_SP_M_P_4_I_MAINNOPENDINGTRANS {TYPE_RO, 148, 1}
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#define SCR_SF_FAB_SP_M_P_9_I_MAINNOPENDINGTRANS {TYPE_RO, 149, 1}
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#define SCR_SF_FAB_SP_S_P_6_T_MAINNOPENDINGTRANS {TYPE_RO, 150, 1}
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#define SCR_SF_EFUSEC_FUSE_READY {TYPE_RO, 160, 1}
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#define SCR_SF_EFUSEC_FUSE_LATCHED_PARTIAL {TYPE_RO, 161, 1}
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#define SCR_SF_ANA_SF_AMUX_REF_P_CSEL_OUT_3_0 {TYPE_RO, 192, 4}
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#define SCR_SF_ANA_SF_AMUX_REF_N_CSEL_OUT_3_0 {TYPE_RO, 196, 4}
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#define SCR_SF_CR5_SF_FPIXC0 {TYPE_RO, 224, 1}
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#define SCR_SF_CR5_SF_FPOFC0 {TYPE_RO, 225, 1}
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#define SCR_SF_CR5_SF_FPUFC0 {TYPE_RO, 226, 1}
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#define SCR_SF_CR5_SF_FPIOC0 {TYPE_RO, 227, 1}
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#define SCR_SF_CR5_SF_FPDZC0 {TYPE_RO, 228, 1}
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#define SCR_SF_CR5_SF_FPIDC0 {TYPE_RO, 229, 1}
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#define SCR_SF_CR5_SP_FPIXC0 {TYPE_RO, 256, 1}
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#define SCR_SF_CR5_SP_FPOFC0 {TYPE_RO, 257, 1}
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#define SCR_SF_CR5_SP_FPUFC0 {TYPE_RO, 258, 1}
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#define SCR_SF_CR5_SP_FPIOC0 {TYPE_RO, 259, 1}
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#define SCR_SF_CR5_SP_FPDZC0 {TYPE_RO, 260, 1}
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#define SCR_SF_CR5_SP_FPIDC0 {TYPE_RO, 261, 1}
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#define SCR_SF_CR5_SP_FPIXC1 {TYPE_RO, 262, 1}
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#define SCR_SF_CR5_SP_FPOFC1 {TYPE_RO, 263, 1}
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#define SCR_SF_CR5_SP_FPUFC1 {TYPE_RO, 264, 1}
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#define SCR_SF_CR5_SP_FPIOC1 {TYPE_RO, 265, 1}
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#define SCR_SF_CR5_SP_FPDZC1 {TYPE_RO, 266, 1}
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#define SCR_SF_CR5_SP_FPIDC1 {TYPE_RO, 267, 1}
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#define SCR_SF_CR5_SX_FPIXC0 {TYPE_RO, 288, 1}
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#define SCR_SF_CR5_SX_FPOFC0 {TYPE_RO, 289, 1}
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#define SCR_SF_CR5_SX_FPUFC0 {TYPE_RO, 290, 1}
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#define SCR_SF_CR5_SX_FPIOC0 {TYPE_RO, 291, 1}
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#define SCR_SF_CR5_SX_FPDZC0 {TYPE_RO, 292, 1}
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#define SCR_SF_CR5_SX_FPIDC0 {TYPE_RO, 293, 1}
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#define SCR_SF_CR5_SX_FPIXC1 {TYPE_RO, 294, 1}
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#define SCR_SF_CR5_SX_FPOFC1 {TYPE_RO, 295, 1}
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#define SCR_SF_CR5_SX_FPUFC1 {TYPE_RO, 296, 1}
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#define SCR_SF_CR5_SX_FPIOC1 {TYPE_RO, 297, 1}
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#define SCR_SF_CR5_SX_FPDZC1 {TYPE_RO, 298, 1}
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#define SCR_SF_CR5_SX_FPIDC1 {TYPE_RO, 299, 1}
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#define SCR_SF_HV_DCDC_TGO2SAF_O_BUF_0 {TYPE_RO, 300, 1}
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#define SCR_SF_HV_DCDC_TGO2SAF_O_BUF_1 {TYPE_RO, 301, 1}
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#define SCR_SF_DMA_SF_MEM_AR_CMD_FIFO0_MEM_EMA_6_0 {TYPE_RO, 320, 7}
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#define SCR_SF_DMA_SF_MEM_AW_CMD_FIFO0_MEM_EMA_6_0 {TYPE_RO, 327, 7}
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#define SCR_SF_DMA_SF_MEM_AR_CMD_FIFO1_MEM_EMA_6_0 {TYPE_RO, 334, 7}
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#define SCR_SF_DMA_SF_MEM_AW_CMD_FIFO1_MEM_EMA_6_0 {TYPE_RO, 341, 7}
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#define SCR_SF_SCR_IRAM1_ECC_DISABLE {TYPE_L16, 0, 1}
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#define SCR_SF_SCR_IRAM2_ECC_DISABLE {TYPE_L16, 1, 1}
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#define SCR_SF_SCR_IRAM3_ECC_DISABLE {TYPE_L16, 2, 1}
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#define SCR_SF_SCR_IRAM4_ECC_DISABLE {TYPE_L16, 3, 1}
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#define SCR_SF_REMAP_CR5_SF_AW_ADDR_OFFSET_19_0 {TYPE_L31, 0, 20}
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#define SCR_SF_SCR_REMAP_CR5_SF_REMAP_EN {TYPE_L31, 20, 1}
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#define SCR_SF_REMAP_CR5_SF_AR_ADDR_OFFSET_19_0 {TYPE_L31, 0, 20}
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#define SCR_SF_REMAP_CR5_SF_AR_REMAP_EN {TYPE_L31, 20, 1}
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#define SCR_SF_REMAP_CR5_SX_AW0_ADDR_OFFSET_19_0 {TYPE_L31, 32, 20}
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#define SCR_SF_REMAP_CR5_SX_AW0_REMAP_EN {TYPE_L31, 52, 1}
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#define SCR_SF_REMAP_CR5_SX_AR0_ADDR_OFFSET_19_0 {TYPE_L31, 32, 20}
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#define SCR_SF_REMAP_CR5_SX_AR0_REMAP_EN {TYPE_L31, 52, 1}
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#define SCR_SF_REMAP_CR5_SX_AW1_ADDR_OFFSET_19_0 {TYPE_L31, 64, 20}
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#define SCR_SF_REMAP_CR5_SX_AW1_REMAP_EN {TYPE_L31, 84, 1}
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#define SCR_SF_REMAP_CR5_SX_AR1_ADDR_OFFSET_19_0 {TYPE_L31, 64, 20}
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#define SCR_SF_REMAP_CR5_SX_AR1_REMAP_EN {TYPE_L31, 84, 1}
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#define SCR_SF_REMAP_CR5_SP_AW0_ADDR_OFFSET_19_0 {TYPE_L31, 96, 20}
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#define SCR_SF_REMAP_CR5_SP_AW0_REMAP_EN {TYPE_L31, 116, 1}
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#define SCR_SF_REMAP_CR5_SP_AR0_ADDR_OFFSET_19_0 {TYPE_L31, 96, 20}
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#define SCR_SF_REMAP_CR5_SP_AR0_REMAP_EN {TYPE_L31, 116, 1}
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#define SCR_SF_REMAP_CR5_SP_AW1_ADDR_OFFSET_19_0 {TYPE_L31, 128, 20}
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#define SCR_SF_REMAP_CR5_SP_AW1_REMAP_EN {TYPE_L31, 148, 1}
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#define SCR_SF_REMAP_CR5_SP_AR1_ADDR_OFFSET_19_0 {TYPE_L31, 128, 20}
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#define SCR_SF_REMAP_CR5_SP_AR1_REMAP_EN {TYPE_L31, 148, 1}
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#define SCR_SF_SCR_CR5_SF_DBGEN0 {TYPE_L31, 160, 1}
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#define SCR_SF_SCR_CR5_SF_NIDEN0 {TYPE_L31, 161, 1}
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#define SCR_SF_SCR_CR5_SP_DBGEN0 {TYPE_L31, 192, 1}
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#define SCR_SF_SCR_CR5_SP_NIDEN0 {TYPE_L31, 193, 1}
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#define SCR_SF_SCR_CR5_SP_DBGEN1 {TYPE_L31, 194, 1}
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#define SCR_SF_SCR_CR5_SP_NIDEN1 {TYPE_L31, 195, 1}
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#define SCR_SF_SCR_CR5_SX_DBGEN0 {TYPE_L31, 224, 1}
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#define SCR_SF_SCR_CR5_SX_NIDEN0 {TYPE_L31, 225, 1}
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#define SCR_SF_SCR_CR5_SX_DBGEN1 {TYPE_L31, 226, 1}
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#define SCR_SF_SCR_CR5_SX_NIDEN1 {TYPE_L31, 227, 1}
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#define SCR_SF_XSPI1_SRC_CFG_SWAP {TYPE_L31, 256, 1}
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#define SCR_SF_XSPI1_SRC_CFG_PARALLEL_MODE {TYPE_L31, 257, 1}
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#define SCR_SF_XSPI1_SRC_CFG_LOCKSTEP_MODE_P {TYPE_L31, 258, 1}
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#define SCR_SF_XSPI1_SRC_CFG_LOCKSTEP_MODE_N {TYPE_L31, 258, 1}
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#define SCR_SF_XSPI2_SRC_CFG_SWAP {TYPE_L31, 288, 1}
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#define SCR_SF_XSPI2_SRC_CFG_PARALLEL_MODE {TYPE_L31, 289, 1}
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#define SCR_SF_XSPI2_SRC_CFG_LOCKSTEP_MODE_P {TYPE_L31, 290, 1}
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#define SCR_SF_XSPI2_SRC_CFG_LOCKSTEP_MODE_N {TYPE_L31, 290, 1}
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#define SCR_SF_DMA_SF_LOCK_STEP_EN_P {TYPE_L31, 320, 1}
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#define SCR_SF_DMA_SF_LOCK_STEP_EN_N {TYPE_L31, 320, 1}
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#define SCR_SF_VIC2_IS_LOCKSTEP_MODE_P {TYPE_L31, 352, 1}
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#define SCR_SF_VIC2_IS_LOCKSTEP_MODE_N {TYPE_L31, 352, 1}
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#define SCR_SF_VIC3_IS_LOCKSTEP_MODE_P {TYPE_L31, 384, 1}
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#define SCR_SF_VIC3_IS_LOCKSTEP_MODE_N {TYPE_L31, 384, 1}
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#define SCR_SF_SCR_CR5_SP_LS_DISABLE {TYPE_L31, 416, 1}
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#define SCR_SF_SCR_CR5_SP_SLCLAMP_DISABLE {TYPE_L31, 417, 1}
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#define SCR_SF_SCR_CR5_SX_LS_DISABLE {TYPE_L31, 448, 1}
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#define SCR_SF_SCR_CR5_SX_SLCLAMP_DISABLE {TYPE_L31, 449, 1}
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#define SCR_SF_SCR_FAB_SF_FIREWALL_APISO {TYPE_L31, 480, 1}
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#define SCR_SF_REMAP_CR5_SF_AW_IRQ_EN {TYPE_RW, 0, 1}
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#define SCR_SF_REMAP_CR5_SF_AR_IRQ_EN {TYPE_RW, 1, 1}
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#define SCR_SF_REMAP_CR5_SF_AW_UNCOR_IRQ_CLR {TYPE_RW, 2, 1}
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#define SCR_SF_REMAP_CR5_SF_AR_UNCOR_IRQ_CLR {TYPE_RW, 3, 1}
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#define SCR_SF_REMAP_CR5_SX_AW0_IRQ_EN {TYPE_RW, 32, 1}
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#define SCR_SF_REMAP_CR5_SX_AR0_IRQ_EN {TYPE_RW, 33, 1}
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#define SCR_SF_REMAP_CR5_SX_AW1_IRQ_EN {TYPE_RW, 34, 1}
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#define SCR_SF_REMAP_CR5_SX_AR1_IRQ_EN {TYPE_RW, 35, 1}
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#define SCR_SF_REMAP_CR5_SX_AW0_UNCOR_IRQ_CLR {TYPE_RW, 36, 1}
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#define SCR_SF_REMAP_CR5_SX_AR0_UNCOR_IRQ_CLR {TYPE_RW, 37, 1}
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#define SCR_SF_REMAP_CR5_SX_AW1_UNCOR_IRQ_CLR {TYPE_RW, 38, 1}
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#define SCR_SF_REMAP_CR5_SX_AR1_UNCOR_IRQ_CLR {TYPE_RW, 39, 1}
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#define SCR_SF_REMAP_CR5_SP_AW0_IRQ_EN {TYPE_RW, 64, 1}
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#define SCR_SF_REMAP_CR5_SP_AR0_IRQ_EN {TYPE_RW, 65, 1}
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#define SCR_SF_REMAP_CR5_SP_AW1_IRQ_EN {TYPE_RW, 66, 1}
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#define SCR_SF_REMAP_CR5_SP_AR1_IRQ_EN {TYPE_RW, 67, 1}
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#define SCR_SF_REMAP_CR5_SP_AW0_UNCOR_IRQ_CLR {TYPE_RW, 68, 1}
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#define SCR_SF_REMAP_CR5_SP_AR0_UNCOR_IRQ_CLR {TYPE_RW, 69, 1}
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#define SCR_SF_REMAP_CR5_SP_AW1_UNCOR_IRQ_CLR {TYPE_RW, 70, 1}
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#define SCR_SF_REMAP_CR5_SP_AR1_UNCOR_IRQ_CLR {TYPE_RW, 71, 1}
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#define SCR_SF_ETMR1_LP_MODE {TYPE_RW, 96, 1}
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#define SCR_SF_ETMR1_MUX_CPT_EN {TYPE_RW, 97, 1}
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#define SCR_SF_ETMR2_LP_MODE {TYPE_RW, 128, 1}
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#define SCR_SF_ETMR2_MUX_CPT_EN {TYPE_RW, 129, 1}
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#define SCR_SF_ETMR3_LP_MODE {TYPE_RW, 160, 1}
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#define SCR_SF_ETMR4_LP_MODE {TYPE_RW, 192, 1}
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#define SCR_SF_IRAM_MUX_UNC_IRQ_EN {TYPE_RW, 224, 1}
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#define SCR_SF_IRAM_MUX_UNC_IRQ_CLR {TYPE_RW, 225, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC1_CH5N_CSEL_3 {TYPE_RW, 256, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC1_CH5P_CSEL_3 {TYPE_RW, 257, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH4N_CSEL_3 {TYPE_RW, 258, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH4P_CSEL_3 {TYPE_RW, 259, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH5N_CSEL_3 {TYPE_RW, 260, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH5P_CSEL_3 {TYPE_RW, 261, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH6N_CSEL_3 {TYPE_RW, 262, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC3_CH5N_CSEL_3 {TYPE_RW, 263, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC3_CH5P_CSEL_3 {TYPE_RW, 264, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP1_CH5N_CSEL_3 {TYPE_RW, 265, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP1_CH5P_CSEL_3 {TYPE_RW, 266, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP2_CH6N_CSEL_3 {TYPE_RW, 267, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP2_CH6P_CSEL_3 {TYPE_RW, 268, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP3_CH5N_CSEL_3 {TYPE_RW, 269, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP3_CH5P_CSEL_3 {TYPE_RW, 270, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP4_CH6N_CSEL_3 {TYPE_RW, 271, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP4_CH6P_CSEL_3 {TYPE_RW, 272, 1}
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#define SCR_SF_AHB2APB1_COR_IRQ_EN {TYPE_RW, 288, 1}
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#define SCR_SF_AHB2APB1_UNCOR_IRQ_EN {TYPE_RW, 289, 1}
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#define SCR_SF_AHB2APB1_COR_IRQ_CLR {TYPE_RW, 290, 1}
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#define SCR_SF_AHB2APB1_UNCOR_IRQ_CLR {TYPE_RW, 291, 1}
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#define SCR_SF_AHB2APB2_COR_IRQ_EN {TYPE_RW, 292, 1}
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#define SCR_SF_AHB2APB2_UNCOR_IRQ_EN {TYPE_RW, 293, 1}
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#define SCR_SF_AHB2APB2_COR_IRQ_CLR {TYPE_RW, 294, 1}
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#define SCR_SF_AHB2APB2_UNCOR_IRQ_CLR {TYPE_RW, 295, 1}
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#define SCR_SF_AHB2APB3_COR_IRQ_EN {TYPE_RW, 296, 1}
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#define SCR_SF_AHB2APB3_UNCOR_IRQ_EN {TYPE_RW, 297, 1}
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#define SCR_SF_AHB2APB3_COR_IRQ_CLR {TYPE_RW, 298, 1}
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#define SCR_SF_AHB2APB3_UNCOR_IRQ_CLR {TYPE_RW, 299, 1}
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#define SCR_SF_AHB2APB4_COR_IRQ_EN {TYPE_RW, 300, 1}
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#define SCR_SF_AHB2APB4_UNCOR_IRQ_EN {TYPE_RW, 301, 1}
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#define SCR_SF_AHB2APB4_COR_IRQ_CLR {TYPE_RW, 302, 1}
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#define SCR_SF_AHB2APB4_UNCOR_IRQ_CLR {TYPE_RW, 303, 1}
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#define SCR_SF_APB_APBMUX1_MST_DST_IRQ_ENB {TYPE_RW, 320, 1}
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#define SCR_SF_APB_APBMUX1_MST_DST_UNCERR_CLR {TYPE_RW, 321, 1}
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#define SCR_SF_APB_APBMUX1_SLV_SRC_IRQ_ENB {TYPE_RW, 322, 1}
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#define SCR_SF_APB_APBMUX1_SLV_SRC_UNCERR_CLR {TYPE_RW, 323, 1}
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#define SCR_SF_APB_MAC_SP_MST_DST_IRQ_ENB {TYPE_RW, 324, 1}
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#define SCR_SF_APB_MAC_SP_MST_DST_UNCERR_CLR {TYPE_RW, 325, 1}
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#define SCR_SF_APB_MAC_SP_SLV_SRC_IRQ_ENB {TYPE_RW, 326, 1}
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#define SCR_SF_APB_MAC_SP_SLV_SRC_UNCERR_CLR {TYPE_RW, 327, 1}
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#define SCR_SF_AAPB_MAC_SRC_IRQ_ENB {TYPE_RW, 328, 1}
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#define SCR_SF_AAPB_MAC_SRC_UNCERR_CLR {TYPE_RW, 329, 1}
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#define SCR_SF_AAPB_MAC_DST_IRQ_ENB {TYPE_RW, 330, 1}
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#define SCR_SF_AAPB_MAC_DST_UNCERR_CLR {TYPE_RW, 331, 1}
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#define SCR_SF_APB_LDO_DIG_MST_DST_IRQ_ENB {TYPE_RW, 332, 1}
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#define SCR_SF_APB_LDO_DIG_MST_DST_UNCERR_CLR {TYPE_RW, 333, 1}
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#define SCR_SF_APB_LDO_DIG_SLV_SRC_IRQ_ENB {TYPE_RW, 334, 1}
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#define SCR_SF_APB_LDO_DIG_SLV_SRC_UNCERR_CLR {TYPE_RW, 335, 1}
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#define SCR_SF_APB_DCDC1_MST_DST_IRQ_ENB {TYPE_RW, 336, 1}
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#define SCR_SF_APB_DCDC1_MST_DST_UNCERR_CLR {TYPE_RW, 337, 1}
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#define SCR_SF_APB_DCDC1_SLV_SRC_IRQ_ENB {TYPE_RW, 338, 1}
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#define SCR_SF_APB_DCDC1_SLV_SRC_UNCERR_CLR {TYPE_RW, 339, 1}
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#define SCR_SF_APB_SEC_STORAGE1_MST_DST_IRQ_ENB {TYPE_RW, 340, 1}
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#define SCR_SF_APB_SEC_STORAGE1_MST_DST_UNCERR_CLR {TYPE_RW, 341, 1}
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#define SCR_SF_APB_SEC_STORAGE1_SLV_SRC_IRQ_ENB {TYPE_RW, 342, 1}
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#define SCR_SF_APB_SEC_STORAGE1_SLV_SRC_UNCERR_CLR {TYPE_RW, 343, 1}
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#define SCR_SF_AAPB_XSPI1A_SRC_IRQ_ENB {TYPE_RW, 352, 1}
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#define SCR_SF_AAPB_XSPI1A_SRC_UNCERR_CLR {TYPE_RW, 353, 1}
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#define SCR_SF_AAPB_XSPI1A_DST_IRQ_ENB {TYPE_RW, 354, 1}
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#define SCR_SF_AAPB_XSPI1A_DST_UNCERR_CLR {TYPE_RW, 355, 1}
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#define SCR_SF_AAPB_XSPI1B_SRC_IRQ_ENB {TYPE_RW, 356, 1}
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#define SCR_SF_AAPB_XSPI1B_SRC_UNCERR_CLR {TYPE_RW, 357, 1}
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#define SCR_SF_AAPB_XSPI1B_DST_IRQ_ENB {TYPE_RW, 358, 1}
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#define SCR_SF_AAPB_XSPI1B_DST_UNCERR_CLR {TYPE_RW, 359, 1}
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#define SCR_SF_AAPB_XSPI2A_SRC_IRQ_ENB {TYPE_RW, 360, 1}
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#define SCR_SF_AAPB_XSPI2A_SRC_UNCERR_CLR {TYPE_RW, 361, 1}
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#define SCR_SF_AAPB_XSPI2A_DST_IRQ_ENB {TYPE_RW, 362, 1}
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#define SCR_SF_AAPB_XSPI2A_DST_UNCERR_CLR {TYPE_RW, 363, 1}
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#define SCR_SF_AAPB_XSPI2B_SRC_IRQ_ENB {TYPE_RW, 364, 1}
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#define SCR_SF_AAPB_XSPI2B_SRC_UNCERR_CLR {TYPE_RW, 365, 1}
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#define SCR_SF_AAPB_XSPI2B_DST_IRQ_ENB {TYPE_RW, 366, 1}
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#define SCR_SF_AAPB_XSPI2B_DST_UNCERR_CLR {TYPE_RW, 367, 1}
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#define SCR_SF_AAPB_FLEXRAY1_SRC_IRQ_ENB {TYPE_RW, 368, 1}
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#define SCR_SF_AAPB_FLEXRAY1_SRC_UNCERR_CLR {TYPE_RW, 369, 1}
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#define SCR_SF_AAPB_FLEXRAY1_DST_IRQ_ENB {TYPE_RW, 370, 1}
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#define SCR_SF_AAPB_FLEXRAY1_DST_UNCERR_CLR {TYPE_RW, 371, 1}
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#define SCR_SF_AAPB_FLEXRAY2_SRC_IRQ_ENB {TYPE_RW, 372, 1}
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#define SCR_SF_AAPB_FLEXRAY2_SRC_UNCERR_CLR {TYPE_RW, 373, 1}
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#define SCR_SF_AAPB_FLEXRAY2_DST_IRQ_ENB {TYPE_RW, 374, 1}
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#define SCR_SF_AAPB_FLEXRAY2_DST_UNCERR_CLR {TYPE_RW, 375, 1}
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#define SCR_SF_APB_APBMUX3_SLV_SRC_IRQ_ENB {TYPE_RW, 376, 1}
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#define SCR_SF_APB_APBMUX3_SLV_SRC_UNCERR_CLR {TYPE_RW, 377, 1}
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#define SCR_SF_APB_APBMUX3_MST_DST_IRQ_ENB {TYPE_RW, 378, 1}
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#define SCR_SF_APB_APBMUX3_MST_DST_UNCERR_CLR {TYPE_RW, 379, 1}
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#define SCR_SF_APB_APBMUX4_SLV_SRC_IRQ_ENB {TYPE_RW, 380, 1}
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#define SCR_SF_APB_APBMUX4_SLV_SRC_UNCERR_CLR {TYPE_RW, 381, 1}
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#define SCR_SF_APB_APBMUX4_MST_DST_IRQ_ENB {TYPE_RW, 382, 1}
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#define SCR_SF_APB_APBMUX4_MST_DST_UNCERR_CLR {TYPE_RW, 383, 1}
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#define SCR_SF_MPC_XSPI1A_SRC_IRQ_ENB {TYPE_RW, 384, 1}
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#define SCR_SF_MPC_XSPI1A_SRC_UNCERR_CLR {TYPE_RW, 385, 1}
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#define SCR_SF_MPC_XSPI1A_DST_IRQ_ENB {TYPE_RW, 386, 1}
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#define SCR_SF_MPC_XSPI1A_DST_UNCERR_CLR {TYPE_RW, 387, 1}
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#define SCR_SF_MPC_XSPI1B_SRC_IRQ_ENB {TYPE_RW, 388, 1}
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#define SCR_SF_MPC_XSPI1B_SRC_UNCERR_CLR {TYPE_RW, 389, 1}
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#define SCR_SF_MPC_XSPI1B_DST_IRQ_ENB {TYPE_RW, 390, 1}
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#define SCR_SF_MPC_XSPI1B_DST_UNCERR_CLR {TYPE_RW, 391, 1}
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#define SCR_SF_MPC_XSPI2A_SRC_IRQ_ENB {TYPE_RW, 392, 1}
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#define SCR_SF_MPC_XSPI2A_SRC_UNCERR_CLR {TYPE_RW, 393, 1}
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#define SCR_SF_MPC_XSPI2A_DST_IRQ_ENB {TYPE_RW, 394, 1}
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#define SCR_SF_MPC_XSPI2A_DST_UNCERR_CLR {TYPE_RW, 395, 1}
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#define SCR_SF_MPC_XSPI2B_SRC_IRQ_ENB {TYPE_RW, 396, 1}
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#define SCR_SF_MPC_XSPI2B_SRC_UNCERR_CLR {TYPE_RW, 397, 1}
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#define SCR_SF_MPC_XSPI2B_DST_IRQ_ENB {TYPE_RW, 398, 1}
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#define SCR_SF_MPC_XSPI2B_DST_UNCERR_CLR {TYPE_RW, 399, 1}
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#define SCR_SF_MPC_CR5_SF_SRC_IRQ_ENB {TYPE_RW, 416, 1}
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#define SCR_SF_MPC_CR5_SF_SRC_UNCERR_CLR {TYPE_RW, 417, 1}
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#define SCR_SF_MPC_CR5_SF_DST_IRQ_ENB {TYPE_RW, 418, 1}
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#define SCR_SF_MPC_CR5_SF_DST_UNCERR_CLR {TYPE_RW, 419, 1}
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#define SCR_SF_MPC_CR5_SX0_SRC_IRQ_ENB {TYPE_RW, 420, 1}
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#define SCR_SF_MPC_CR5_SX0_SRC_UNCERR_CLR {TYPE_RW, 421, 1}
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#define SCR_SF_MPC_CR5_SX0_DST_IRQ_ENB {TYPE_RW, 422, 1}
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#define SCR_SF_MPC_CR5_SX0_DST_UNCERR_CLR {TYPE_RW, 423, 1}
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#define SCR_SF_MPC_CR5_SX1_SRC_IRQ_ENB {TYPE_RW, 424, 1}
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#define SCR_SF_MPC_CR5_SX1_SRC_UNCERR_CLR {TYPE_RW, 425, 1}
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#define SCR_SF_MPC_CR5_SX1_DST_IRQ_ENB {TYPE_RW, 426, 1}
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#define SCR_SF_MPC_CR5_SX1_DST_UNCERR_CLR {TYPE_RW, 427, 1}
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#define SCR_SF_MPC_CR5_SP0_SRC_IRQ_ENB {TYPE_RW, 428, 1}
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#define SCR_SF_MPC_CR5_SP0_SRC_UNCERR_CLR {TYPE_RW, 429, 1}
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#define SCR_SF_MPC_CR5_SP0_DST_IRQ_ENB {TYPE_RW, 430, 1}
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#define SCR_SF_MPC_CR5_SP0_DST_UNCERR_CLR {TYPE_RW, 431, 1}
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#define SCR_SF_MPC_CR5_SP1_SRC_IRQ_ENB {TYPE_RW, 432, 1}
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#define SCR_SF_MPC_CR5_SP1_SRC_UNCERR_CLR {TYPE_RW, 433, 1}
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#define SCR_SF_MPC_CR5_SP1_DST_IRQ_ENB {TYPE_RW, 434, 1}
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#define SCR_SF_MPC_CR5_SP1_DST_UNCERR_CLR {TYPE_RW, 435, 1}
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#define SCR_SF_APB_PMUX2_DEC_MST_DST_IRQ_ENB {TYPE_RW, 436, 1}
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#define SCR_SF_APB_PMUX2_DEC_MST_DST_UNCERR_CLR {TYPE_RW, 437, 1}
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#define SCR_SF_APB_PMUX2_DEC_SLV_SRC_IRQ_ENB {TYPE_RW, 438, 1}
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#define SCR_SF_APB_PMUX2_DEC_SLV_SRC_UNCERR_CLR {TYPE_RW, 439, 1}
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#define SCR_SF_ANA_SF_CFG_VREF1_VTRIM_4_0 {TYPE_RW, 448, 5}
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#define SCR_SF_SCR_VREF1_PDREF {TYPE_RW, 453, 1}
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#define SCR_SF_ANA_SF_CFG_VREF2_VTRIM_4_0 {TYPE_RW, 454, 5}
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#define SCR_SF_SCR_VREF2_PDREF {TYPE_RW, 459, 1}
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#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF1_D0_10_8 {TYPE_RW, 480, 3}
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#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF1_D0_7_0 {TYPE_RW, 483, 8}
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#define SCR_SF_SCR_BGR_ANA_SF1_TRIM_SEL {TYPE_RW, 491, 1}
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#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF2_D0_10_8 {TYPE_RW, 512, 3}
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#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF2_D0_7_0 {TYPE_RW, 515, 8}
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#define SCR_SF_SCR_BGR_ANA_SF2_TRIM_SEL {TYPE_RW, 523, 1}
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#define SCR_SF_SCAN_SAFMUX_BGR_SF_D0_10_8 {TYPE_RW, 544, 3}
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#define SCR_SF_SCAN_SAFMUX_BGR_SF_D0_7_0 {TYPE_RW, 547, 8}
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#define SCR_SF_BGR33_SF_SCR_BGR33_SF_TRIM_SEL {TYPE_RW, 555, 1}
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#define SCR_SF_SCAN_SAFMUX_BGR_LDO_TEST_D0_2_0 {TYPE_RW, 576, 3}
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#define SCR_SF_BGR33_LDO_SCR_BGR33_LDO_TRIM_2_0 {TYPE_RW, 579, 3}
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#define SCR_SF_SCAN_SAFMUX_BGR_LDO_REG0_H_D0_4_0 {TYPE_RW, 582, 5}
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#define SCR_SF_BGR33_LDO_SCR_BGR33_LDO_TRIM_SEL {TYPE_RW, 587, 1}
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#define SCR_SF_SCR_CR5_SF_CPUHALT0 {TYPE_RW, 608, 1}
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#define SCR_SF_SCR_CR5_SF_CPUHALT1 {TYPE_RW, 609, 1}
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#define SCR_SF_CR5_SF_SCR_CR5_IRQ_CLR {TYPE_RW, 610, 1}
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#define SCR_SF_CR5_SF_SCR_CR5_VICADDR_DISABLE {TYPE_RW, 611, 1}
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#define SCR_SF_SCR_CR5_SF_DCCMINP_0 {TYPE_RW, 612, 1}
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#define SCR_SF_SCR_CR5_SP_CPUHALT0 {TYPE_RW, 640, 1}
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#define SCR_SF_SCR_CR5_SP_CPUHALT1 {TYPE_RW, 641, 1}
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#define SCR_SF_CR5_SP_SCR_CR5_IRQ_CLR {TYPE_RW, 642, 1}
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#define SCR_SF_CR5_SP_SCR_CR5_VICADDR_DISABLE {TYPE_RW, 643, 1}
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#define SCR_SF_CR5_SP_DCCMINP_0 {TYPE_RW, 644, 1}
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#define SCR_SF_CR5_SP_DCCMINP2_0 {TYPE_RW, 645, 1}
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#define SCR_SF_SCR_CR5_SX_CPUHALT0 {TYPE_RW, 672, 1}
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#define SCR_SF_SCR_CR5_SX_CPUHALT1 {TYPE_RW, 673, 1}
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#define SCR_SF_CR5_SX_SCR_CR5_IRQ_CLR {TYPE_RW, 674, 1}
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#define SCR_SF_CR5_SX_SCR_CR5_VICADDR_DISABLE {TYPE_RW, 675, 1}
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#define SCR_SF_CR5_SX_DCCMINP_0 {TYPE_RW, 676, 1}
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#define SCR_SF_CR5_SX_DCCMINP2_0 {TYPE_RW, 677, 1}
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#define SCR_SF_ANA_SF_CFG_APD_A_A0_CTRL_3_0 {TYPE_RW, 704, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A1_CTRL_3_0 {TYPE_RW, 708, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A2_CTRL_3_0 {TYPE_RW, 712, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A3_CTRL_3_0 {TYPE_RW, 716, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A4_CTRL_3_0 {TYPE_RW, 720, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A5_CTRL_3_0 {TYPE_RW, 724, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A6_CTRL_3_0 {TYPE_RW, 728, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A7_CTRL_3_0 {TYPE_RW, 732, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A8_CTRL_3_0 {TYPE_RW, 736, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A9_CTRL_3_0 {TYPE_RW, 740, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A10_CTRL_3_0 {TYPE_RW, 744, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A11_CTRL_3_0 {TYPE_RW, 748, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A12_CTRL_3_0 {TYPE_RW, 752, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A13_CTRL_3_0 {TYPE_RW, 756, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A14_CTRL_3_0 {TYPE_RW, 760, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A15_CTRL_3_0 {TYPE_RW, 764, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B0_CTRL_3_0 {TYPE_RW, 768, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B1_CTRL_3_0 {TYPE_RW, 772, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B2_CTRL_3_0 {TYPE_RW, 776, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B3_CTRL_3_0 {TYPE_RW, 780, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B4_CTRL_3_0 {TYPE_RW, 784, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B5_CTRL_3_0 {TYPE_RW, 788, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B6_CTRL_3_0 {TYPE_RW, 792, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B7_CTRL_3_0 {TYPE_RW, 796, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B8_CTRL_3_0 {TYPE_RW, 800, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B9_CTRL_3_0 {TYPE_RW, 804, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B10_CTRL_3_0 {TYPE_RW, 808, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B11_CTRL_3_0 {TYPE_RW, 812, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B12_CTRL_3_0 {TYPE_RW, 816, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B13_CTRL_3_0 {TYPE_RW, 820, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B14_CTRL_3_0 {TYPE_RW, 824, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B15_CTRL_3_0 {TYPE_RW, 828, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C0_CTRL_3_0 {TYPE_RW, 832, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C1_CTRL_3_0 {TYPE_RW, 836, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C2_CTRL_3_0 {TYPE_RW, 840, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C3_CTRL_3_0 {TYPE_RW, 844, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C4_CTRL_3_0 {TYPE_RW, 848, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C5_CTRL_3_0 {TYPE_RW, 852, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C6_CTRL_3_0 {TYPE_RW, 856, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C7_CTRL_3_0 {TYPE_RW, 860, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C8_CTRL_3_0 {TYPE_RW, 864, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C9_CTRL_3_0 {TYPE_RW, 868, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C10_CTRL_3_0 {TYPE_RW, 872, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C11_CTRL_3_0 {TYPE_RW, 876, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C12_CTRL_3_0 {TYPE_RW, 880, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C13_CTRL_3_0 {TYPE_RW, 884, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C14_CTRL_3_0 {TYPE_RW, 888, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C15_CTRL_3_0 {TYPE_RW, 892, 4}
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#define SCR_SF_ANA_SF_CFG_AMUX_REF_P_CSEL_3_0 {TYPE_RW, 896, 4}
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#define SCR_SF_ANA_SF_CFG_AMUX_REF_N_CSEL_3_0 {TYPE_RW, 900, 4}
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#define SCR_SF_SCR_SF_DEBUG_MODE {TYPE_RW, 928, 1}
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#define SCR_SF_ENET1_SBD_FLOWCTRL_I_4_0 {TYPE_RW, 960, 5}
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#define SCR_SF_SCR_ENET1_CAP_COMP_0_OE {TYPE_RW, 965, 1}
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#define SCR_SF_SCR_ENET1_CAP_COMP_1_OE {TYPE_RW, 966, 1}
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#define SCR_SF_SCR_ENET1_CAP_COMP_2_OE {TYPE_RW, 967, 1}
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#define SCR_SF_SCR_ENET1_CAP_COMP_3_OE {TYPE_RW, 968, 1}
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#define SCR_SF_SCR_ENET1_CLK_RMII_OE {TYPE_RW, 969, 1}
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#define SCR_SF_ENET2_SBD_FLOWCTRL_I_4_0 {TYPE_RW, 992, 5}
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#define SCR_SF_SCR_ENET2_CAP_COMP_0_OE {TYPE_RW, 997, 1}
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#define SCR_SF_SCR_ENET2_CAP_COMP_1_OE {TYPE_RW, 998, 1}
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#define SCR_SF_SCR_ENET2_CAP_COMP_2_OE {TYPE_RW, 999, 1}
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#define SCR_SF_SCR_ENET2_CAP_COMP_3_OE {TYPE_RW, 1000, 1}
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#define SCR_SF_SCR_ENET2_CLK_RMII_OE {TYPE_RW, 1001, 1}
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#define SCR_SF_SCR_SF_EMA_UPD {TYPE_RW, 1088, 1}
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#define SCR_SF_SCR_AP_EMA_UPD {TYPE_RW, 1120, 1}
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#define SCR_SF_AAPB_PLL1_SRC_IRQ_ENB {TYPE_RW, 1152, 1}
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#define SCR_SF_AAPB_PLL1_SRC_UNCERR_CLR {TYPE_RW, 1153, 1}
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#define SCR_SF_AAPB_PLL1_DST_IRQ_ENB {TYPE_RW, 1154, 1}
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#define SCR_SF_AAPB_PLL1_DST_UNCERR_CLR {TYPE_RW, 1155, 1}
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#define SCR_SF_AAPB_PLL2_SRC_IRQ_ENB {TYPE_RW, 1156, 1}
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#define SCR_SF_AAPB_PLL2_SRC_UNCERR_CLR {TYPE_RW, 1157, 1}
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#define SCR_SF_AAPB_PLL2_DST_IRQ_ENB {TYPE_RW, 1158, 1}
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#define SCR_SF_AAPB_PLL2_DST_UNCERR_CLR {TYPE_RW, 1159, 1}
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#define SCR_SF_AAPB_PLL3_SRC_IRQ_ENB {TYPE_RW, 1160, 1}
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#define SCR_SF_AAPB_PLL3_SRC_UNCERR_CLR {TYPE_RW, 1161, 1}
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#define SCR_SF_AAPB_PLL3_DST_IRQ_ENB {TYPE_RW, 1162, 1}
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#define SCR_SF_AAPB_PLL3_DST_UNCERR_CLR {TYPE_RW, 1163, 1}
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#define SCR_SF_SCR_XSPI1_PA_SS1_SCLKB_SEL {TYPE_RW, 1184, 1}
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#define SCR_SF_SCR_XSPI1_PB_SS1_SCLKB_SEL {TYPE_RW, 1185, 1}
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#define SCR_SF_ETMR1_CMP_A_ZO_EN {TYPE_RW, 1216, 1}
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#define SCR_SF_ETMR1_CMP_B_ZO_EN {TYPE_RW, 1217, 1}
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#define SCR_SF_ETMR1_CMP_C_ZO_EN {TYPE_RW, 1218, 1}
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#define SCR_SF_ETMR1_CMP_D_ZO_EN {TYPE_RW, 1219, 1}
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#define SCR_SF_ETMR1_CMP_A_CBC_EN {TYPE_RW, 1220, 1}
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#define SCR_SF_ETMR1_CMP_B_CBC_EN {TYPE_RW, 1221, 1}
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#define SCR_SF_ETMR1_CMP_C_CBC_EN {TYPE_RW, 1222, 1}
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#define SCR_SF_ETMR1_CMP_D_CBC_EN {TYPE_RW, 1223, 1}
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#define SCR_SF_ETMR2_CMP_A_ZO_EN {TYPE_RW, 1224, 1}
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#define SCR_SF_ETMR2_CMP_B_ZO_EN {TYPE_RW, 1225, 1}
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#define SCR_SF_ETMR2_CMP_C_ZO_EN {TYPE_RW, 1226, 1}
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#define SCR_SF_ETMR2_CMP_D_ZO_EN {TYPE_RW, 1227, 1}
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#define SCR_SF_ETMR2_CMP_A_CBC_EN {TYPE_RW, 1228, 1}
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#define SCR_SF_ETMR2_CMP_B_CBC_EN {TYPE_RW, 1229, 1}
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#define SCR_SF_ETMR2_CMP_C_CBC_EN {TYPE_RW, 1230, 1}
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#define SCR_SF_ETMR2_CMP_D_CBC_EN {TYPE_RW, 1231, 1}
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#define SCR_SF_ETMR3_CMP_A_ZO_EN {TYPE_RW, 1232, 1}
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#define SCR_SF_ETMR3_CMP_B_ZO_EN {TYPE_RW, 1233, 1}
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#define SCR_SF_ETMR3_CMP_C_ZO_EN {TYPE_RW, 1234, 1}
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#define SCR_SF_ETMR3_CMP_D_ZO_EN {TYPE_RW, 1235, 1}
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#define SCR_SF_ETMR3_CMP_A_CBC_EN {TYPE_RW, 1236, 1}
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#define SCR_SF_ETMR3_CMP_B_CBC_EN {TYPE_RW, 1237, 1}
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#define SCR_SF_ETMR3_CMP_C_CBC_EN {TYPE_RW, 1238, 1}
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#define SCR_SF_ETMR3_CMP_D_CBC_EN {TYPE_RW, 1239, 1}
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#define SCR_SF_ETMR4_CMP_A_ZO_EN {TYPE_RW, 1240, 1}
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#define SCR_SF_ETMR4_CMP_B_ZO_EN {TYPE_RW, 1241, 1}
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#define SCR_SF_ETMR4_CMP_C_ZO_EN {TYPE_RW, 1242, 1}
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#define SCR_SF_ETMR4_CMP_D_ZO_EN {TYPE_RW, 1243, 1}
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#define SCR_SF_ETMR4_CMP_A_CBC_EN {TYPE_RW, 1244, 1}
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#define SCR_SF_ETMR4_CMP_B_CBC_EN {TYPE_RW, 1245, 1}
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#define SCR_SF_ETMR4_CMP_C_CBC_EN {TYPE_RW, 1246, 1}
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#define SCR_SF_ETMR4_CMP_D_CBC_EN {TYPE_RW, 1247, 1}
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#define SCR_SF_EPWM1_CMP_A_ZO_EN {TYPE_RW, 1248, 1}
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#define SCR_SF_EPWM1_CMP_B_ZO_EN {TYPE_RW, 1249, 1}
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#define SCR_SF_EPWM1_CMP_C_ZO_EN {TYPE_RW, 1250, 1}
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#define SCR_SF_EPWM1_CMP_D_ZO_EN {TYPE_RW, 1251, 1}
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#define SCR_SF_EPWM1_CMP_A_CBC_EN {TYPE_RW, 1252, 1}
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#define SCR_SF_EPWM1_CMP_B_CBC_EN {TYPE_RW, 1253, 1}
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#define SCR_SF_EPWM1_CMP_C_CBC_EN {TYPE_RW, 1254, 1}
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#define SCR_SF_EPWM1_CMP_D_CBC_EN {TYPE_RW, 1255, 1}
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#define SCR_SF_EPWM2_CMP_A_ZO_EN {TYPE_RW, 1256, 1}
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#define SCR_SF_EPWM2_CMP_B_ZO_EN {TYPE_RW, 1257, 1}
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#define SCR_SF_EPWM2_CMP_C_ZO_EN {TYPE_RW, 1258, 1}
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#define SCR_SF_EPWM2_CMP_D_ZO_EN {TYPE_RW, 1259, 1}
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#define SCR_SF_EPWM2_CMP_A_CBC_EN {TYPE_RW, 1260, 1}
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#define SCR_SF_EPWM2_CMP_B_CBC_EN {TYPE_RW, 1261, 1}
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#define SCR_SF_EPWM2_CMP_C_CBC_EN {TYPE_RW, 1262, 1}
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#define SCR_SF_EPWM2_CMP_D_CBC_EN {TYPE_RW, 1263, 1}
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#define SCR_SF_EPWM3_CMP_A_ZO_EN {TYPE_RW, 1264, 1}
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#define SCR_SF_EPWM3_CMP_B_ZO_EN {TYPE_RW, 1265, 1}
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#define SCR_SF_EPWM3_CMP_C_ZO_EN {TYPE_RW, 1266, 1}
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#define SCR_SF_EPWM3_CMP_D_ZO_EN {TYPE_RW, 1267, 1}
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#define SCR_SF_EPWM3_CMP_A_CBC_EN {TYPE_RW, 1268, 1}
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#define SCR_SF_EPWM3_CMP_B_CBC_EN {TYPE_RW, 1269, 1}
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#define SCR_SF_EPWM3_CMP_C_CBC_EN {TYPE_RW, 1270, 1}
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#define SCR_SF_EPWM3_CMP_D_CBC_EN {TYPE_RW, 1271, 1}
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#define SCR_SF_EPWM4_CMP_A_ZO_EN {TYPE_RW, 1272, 1}
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#define SCR_SF_EPWM4_CMP_B_ZO_EN {TYPE_RW, 1273, 1}
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#define SCR_SF_EPWM4_CMP_C_ZO_EN {TYPE_RW, 1274, 1}
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#define SCR_SF_EPWM4_CMP_D_ZO_EN {TYPE_RW, 1275, 1}
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#define SCR_SF_EPWM4_CMP_A_CBC_EN {TYPE_RW, 1276, 1}
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#define SCR_SF_EPWM4_CMP_B_CBC_EN {TYPE_RW, 1277, 1}
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#define SCR_SF_EPWM4_CMP_C_CBC_EN {TYPE_RW, 1278, 1}
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#define SCR_SF_EPWM4_CMP_D_CBC_EN {TYPE_RW, 1279, 1}
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#define SCR_SF_BTI_SF_M0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 0, 8}
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#define SCR_SF_BTI_SF_M0_BTI_EN {TYPE_R16W16, 8, 1}
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#define SCR_SF_BTI_SF_M0_UNCOR_IRQ_EN {TYPE_R16W16, 9, 1}
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#define SCR_SF_BTI_SF_M0_UNCOR_IRQ_CLR {TYPE_R16W16, 10, 1}
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#define SCR_SF_BTI_SF_P0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 32, 8}
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#define SCR_SF_BTI_SF_P0_BTI_EN {TYPE_R16W16, 40, 1}
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#define SCR_SF_BTI_SF_P0_UNCOR_IRQ_EN {TYPE_R16W16, 41, 1}
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#define SCR_SF_BTI_SF_P0_UNCOR_IRQ_CLR {TYPE_R16W16, 42, 1}
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#define SCR_SF_BTI_SF_AHB_TIMEOUT_DIV_7_0 {TYPE_R16W16, 64, 8}
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#define SCR_SF_BTI_SF_AHB_BTI_EN {TYPE_R16W16, 72, 1}
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#define SCR_SF_BTI_SF_AHB_UNCOR_IRQ_EN {TYPE_R16W16, 73, 1}
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#define SCR_SF_BTI_SF_AHB_UNCOR_IRQ_CLR {TYPE_R16W16, 74, 1}
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#define SCR_SF_BTI_SX_M0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 96, 8}
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#define SCR_SF_BTI_SX_M0_BTI_EN {TYPE_R16W16, 104, 1}
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#define SCR_SF_BTI_SX_M0_UNCOR_IRQ_EN {TYPE_R16W16, 105, 1}
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#define SCR_SF_BTI_SX_M0_UNCOR_IRQ_CLR {TYPE_R16W16, 106, 1}
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#define SCR_SF_BTI_SX_P0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 128, 8}
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#define SCR_SF_BTI_SX_P0_BTI_EN {TYPE_R16W16, 136, 1}
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#define SCR_SF_BTI_SX_P0_UNCOR_IRQ_EN {TYPE_R16W16, 137, 1}
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#define SCR_SF_BTI_SX_P0_UNCOR_IRQ_CLR {TYPE_R16W16, 138, 1}
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#define SCR_SF_BTI_SX_M1_TIMEOUT_DIV_7_0 {TYPE_R16W16, 160, 8}
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#define SCR_SF_BTI_SX_M1_BTI_EN {TYPE_R16W16, 168, 1}
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#define SCR_SF_BTI_SX_M1_UNCOR_IRQ_EN {TYPE_R16W16, 169, 1}
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#define SCR_SF_BTI_SX_M1_UNCOR_IRQ_CLR {TYPE_R16W16, 170, 1}
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#define SCR_SF_BTI_SX_P1_TIMEOUT_DIV_7_0 {TYPE_R16W16, 192, 8}
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#define SCR_SF_BTI_SX_P1_BTI_EN {TYPE_R16W16, 200, 1}
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#define SCR_SF_BTI_SX_P1_UNCOR_IRQ_EN {TYPE_R16W16, 201, 1}
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#define SCR_SF_BTI_SX_P1_UNCOR_IRQ_CLR {TYPE_R16W16, 202, 1}
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#define SCR_SF_BTI_SX_AHB_TIMEOUT_DIV_7_0 {TYPE_R16W16, 224, 8}
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#define SCR_SF_BTI_SX_AHB_BTI_EN {TYPE_R16W16, 232, 1}
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#define SCR_SF_BTI_SX_AHB_UNCOR_IRQ_EN {TYPE_R16W16, 233, 1}
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#define SCR_SF_BTI_SX_AHB_UNCOR_IRQ_CLR {TYPE_R16W16, 234, 1}
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#define SCR_SF_BTI_DISPSF_TIMEOUT_DIV_7_0 {TYPE_R16W16, 256, 8}
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#define SCR_SF_BTI_DISPSF_BTI_EN {TYPE_R16W16, 264, 1}
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#define SCR_SF_BTI_DISPSF_UNCOR_IRQ_EN {TYPE_R16W16, 265, 1}
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#define SCR_SF_BTI_DISPSF_UNCOR_IRQ_CLR {TYPE_R16W16, 266, 1}
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#define SCR_SF_BTI_DISPSF_COR_IRQ_EN {TYPE_R16W16, 267, 1}
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#define SCR_SF_BTI_DISPSF_COR_IRQ_CLR {TYPE_R16W16, 268, 1}
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#define SCR_SF_BTI_APSF_TIMEOUT_DIV_7_0 {TYPE_R16W16, 288, 8}
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#define SCR_SF_BTI_APSF_BTI_EN {TYPE_R16W16, 296, 1}
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#define SCR_SF_BTI_APSF_UNCOR_IRQ_EN {TYPE_R16W16, 297, 1}
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#define SCR_SF_BTI_APSF_UNCOR_IRQ_CLR {TYPE_R16W16, 298, 1}
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#define SCR_SF_BTI_APSF_COR_IRQ_EN {TYPE_R16W16, 299, 1}
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#define SCR_SF_BTI_APSF_COR_IRQ_CLR {TYPE_R16W16, 300, 1}
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#define SCR_SF_BTI_SP_M0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 320, 8}
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#define SCR_SF_BTI_SP_M0_BTI_EN {TYPE_R16W16, 328, 1}
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#define SCR_SF_BTI_SP_M0_UNCOR_IRQ_EN {TYPE_R16W16, 329, 1}
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#define SCR_SF_BTI_SP_M0_UNCOR_IRQ_CLR {TYPE_R16W16, 330, 1}
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#define SCR_SF_BTI_SP_P0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 352, 8}
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#define SCR_SF_BTI_SP_P0_BTI_EN {TYPE_R16W16, 360, 1}
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#define SCR_SF_BTI_SP_P0_UNCOR_IRQ_EN {TYPE_R16W16, 361, 1}
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#define SCR_SF_BTI_SP_P0_UNCOR_IRQ_CLR {TYPE_R16W16, 362, 1}
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#define SCR_SF_BTI_SP0_AHB_TIMEOUT_DIV_7_0 {TYPE_R16W16, 384, 8}
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#define SCR_SF_BTI_SP0_AHB_BTI_EN {TYPE_R16W16, 392, 1}
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#define SCR_SF_BTI_SP0_AHB_UNCOR_IRQ_EN {TYPE_R16W16, 393, 1}
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#define SCR_SF_BTI_SP0_AHB_UNCOR_IRQ_CLR {TYPE_R16W16, 394, 1}
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#define SCR_SF_BTI_SP_M1_TIMEOUT_DIV_7_0 {TYPE_R16W16, 416, 8}
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#define SCR_SF_BTI_SP_M1_BTI_EN {TYPE_R16W16, 424, 1}
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#define SCR_SF_BTI_SP_M1_UNCOR_IRQ_EN {TYPE_R16W16, 425, 1}
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#define SCR_SF_BTI_SP_M1_UNCOR_IRQ_CLR {TYPE_R16W16, 426, 1}
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#define SCR_SF_BTI_SP_P1_TIMEOUT_DIV_7_0 {TYPE_R16W16, 448, 8}
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#define SCR_SF_BTI_SP_P1_BTI_EN {TYPE_R16W16, 456, 1}
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#define SCR_SF_BTI_SP_P1_UNCOR_IRQ_EN {TYPE_R16W16, 457, 1}
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#define SCR_SF_BTI_SP_P1_UNCOR_IRQ_CLR {TYPE_R16W16, 458, 1}
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#define SCR_SF_CANFD1_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 480, 4}
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#define SCR_SF_CANFD1_STOP_DOZE_SEL {TYPE_R16W16, 484, 1}
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#define SCR_SF_CANFD2_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 512, 4}
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#define SCR_SF_CANFD2_STOP_DOZE_SEL {TYPE_R16W16, 516, 1}
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#define SCR_SF_CANFD3_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 544, 4}
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#define SCR_SF_CANFD3_STOP_DOZE_SEL {TYPE_R16W16, 548, 1}
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#define SCR_SF_CANFD4_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 549, 4}
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#define SCR_SF_CANFD4_STOP_DOZE_SEL {TYPE_R16W16, 553, 1}
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#define SCR_SF_CANFD5_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 576, 4}
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#define SCR_SF_CANFD5_STOP_DOZE_SEL {TYPE_R16W16, 580, 1}
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#define SCR_SF_CANFD6_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 581, 4}
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#define SCR_SF_CANFD6_STOP_DOZE_SEL {TYPE_R16W16, 585, 1}
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#define SCR_SF_CANFD7_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 608, 4}
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#define SCR_SF_CANFD7_STOP_DOZE_SEL {TYPE_R16W16, 612, 1}
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#define SCR_SF_CANFD8_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 613, 4}
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#define SCR_SF_CANFD8_STOP_DOZE_SEL {TYPE_R16W16, 617, 1}
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#define SCR_SF_CANFD9_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 640, 4}
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#define SCR_SF_CANFD9_STOP_DOZE_SEL {TYPE_R16W16, 644, 1}
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#define SCR_SF_CANFD10_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 645, 4}
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#define SCR_SF_CANFD10_STOP_DOZE_SEL {TYPE_R16W16, 649, 1}
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#define SCR_SF_CANFD11_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 672, 4}
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#define SCR_SF_CANFD11_STOP_DOZE_SEL {TYPE_R16W16, 676, 1}
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#define SCR_SF_CANFD12_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 677, 4}
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#define SCR_SF_CANFD12_STOP_DOZE_SEL {TYPE_R16W16, 681, 1}
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#define SCR_SF_CANFD13_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 704, 4}
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#define SCR_SF_CANFD13_STOP_DOZE_SEL {TYPE_R16W16, 708, 1}
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#define SCR_SF_CANFD14_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 709, 4}
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#define SCR_SF_CANFD14_STOP_DOZE_SEL {TYPE_R16W16, 713, 1}
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#define SCR_SF_CANFD15_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 736, 4}
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#define SCR_SF_CANFD15_STOP_DOZE_SEL {TYPE_R16W16, 740, 1}
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#define SCR_SF_CANFD16_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 741, 4}
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#define SCR_SF_CANFD16_STOP_DOZE_SEL {TYPE_R16W16, 745, 1}
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#define SCR_SF_CANFD17_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 768, 4}
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#define SCR_SF_CANFD17_STOP_DOZE_SEL {TYPE_R16W16, 772, 1}
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#define SCR_SF_CANFD18_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 773, 4}
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#define SCR_SF_CANFD18_STOP_DOZE_SEL {TYPE_R16W16, 777, 1}
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#define SCR_SF_CANFD19_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 800, 4}
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#define SCR_SF_CANFD19_STOP_DOZE_SEL {TYPE_R16W16, 804, 1}
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#define SCR_SF_CANFD20_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 805, 4}
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#define SCR_SF_CANFD20_STOP_DOZE_SEL {TYPE_R16W16, 809, 1}
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#define SCR_SF_CANFD21_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 832, 4}
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#define SCR_SF_CANFD21_STOP_DOZE_SEL {TYPE_R16W16, 836, 1}
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#define SCR_SF_CANFD22_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 837, 4}
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#define SCR_SF_CANFD22_STOP_DOZE_SEL {TYPE_R16W16, 841, 1}
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#define SCR_SF_CANFD23_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 864, 4}
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#define SCR_SF_CANFD23_STOP_DOZE_SEL {TYPE_R16W16, 868, 1}
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#define SCR_SF_CANFD24_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 869, 4}
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#define SCR_SF_CANFD24_STOP_DOZE_SEL {TYPE_R16W16, 873, 1}
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#define SCR_SF_BTI_SF_M0_CHN_IDLE {TYPE_R16W16, 16, 1}
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#define SCR_SF_BTI_SF_P0_CHN_IDLE {TYPE_R16W16, 48, 1}
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#define SCR_SF_BTI_SF_AHB_CHN_IDLE {TYPE_R16W16, 80, 1}
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#define SCR_SF_BTI_SX_M0_CHN_IDLE {TYPE_R16W16, 112, 1}
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#define SCR_SF_BTI_SX_P0_CHN_IDLE {TYPE_R16W16, 144, 1}
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#define SCR_SF_BTI_SX_M1_CHN_IDLE {TYPE_R16W16, 176, 1}
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#define SCR_SF_BTI_SX_P1_CHN_IDLE {TYPE_R16W16, 208, 1}
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#define SCR_SF_BTI_SX_AHB_CHN_IDLE {TYPE_R16W16, 240, 1}
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#define SCR_SF_BTI_DISPSF_CHN_IDLE {TYPE_R16W16, 272, 1}
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#define SCR_SF_BTI_APSF_CHN_IDLE {TYPE_R16W16, 304, 1}
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#define SCR_SF_BTI_SP_M0_CHN_IDLE {TYPE_R16W16, 336, 1}
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#define SCR_SF_BTI_SP_P0_CHN_IDLE {TYPE_R16W16, 368, 1}
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#define SCR_SF_BTI_SP0_AHB_CHN_IDLE {TYPE_R16W16, 400, 1}
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#define SCR_SF_BTI_SP_M1_CHN_IDLE {TYPE_R16W16, 432, 1}
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#define SCR_SF_BTI_SP_P1_CHN_IDLE {TYPE_R16W16, 464, 1}
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#define SCR_AP_FAB_AP_M_A_12_I_MAINNOPENDINGTRANS {TYPE_RO, 32, 1}
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#define SCR_AP_FAB_AP_M_A_2_I_MAINNOPENDINGTRANS {TYPE_RO, 33, 1}
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#define SCR_AP_FAB_AP_M_A_3_I_MAINNOPENDINGTRANS {TYPE_RO, 34, 1}
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#define SCR_AP_FAB_AP_M_A_5_I_MAINNOPENDINGTRANS {TYPE_RO, 35, 1}
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#define SCR_AP_FAB_AP_M_A_7_I_MAINNOPENDINGTRANS {TYPE_RO, 36, 1}
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#define SCR_AP_FAB_AP_M_A_8_I_MAINNOPENDINGTRANS {TYPE_RO, 37, 1}
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#define SCR_AP_FAB_AP_S_A_5_T_MAINNOPENDINGTRANS {TYPE_RO, 38, 1}
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#define SCR_AP_FAB_AP_M_A_4A_I_MAINNOPENDINGTRANS {TYPE_RO, 39, 1}
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#define SCR_AP_FAB_AP_M_A_4B_I_MAINNOPENDINGTRANS {TYPE_RO, 40, 1}
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#define SCR_AP_FAB_AP_M_A_GPV_I_MAINNOPENDINGTRANS {TYPE_RO, 41, 1}
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#define SCR_AP_FAB_AP_S_A_1_T_MAINNOPENDINGTRANS {TYPE_RO, 42, 1}
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#define SCR_AP_FAB_AP_S_A_2_T_MAINNOPENDINGTRANS {TYPE_RO, 43, 1}
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#define SCR_AP_FAB_AP_SVREG_T_MAINNOPENDINGTRANS {TYPE_RO, 44, 1}
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#define SCR_AP_FAB_AP_SVREG_MAINNOPENDINGTRANS {TYPE_RO, 45, 1}
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#define SCR_AP_FAB_AP_M_A_10_I_MAINNOPENDINGTRANS {TYPE_RO, 46, 1}
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#define SCR_AP_FAB_AP_S_A_7_T_MAINNOPENDINGTRANS {TYPE_RO, 47, 1}
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#define SCR_AP_FAB_AP_M_A_6_I_MAINNOPENDINGTRANS {TYPE_RO, 48, 1}
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#define SCR_AP_FAB_AP_M_A_9_I_MAINNOPENDINGTRANS {TYPE_RO, 49, 1}
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#define SCR_AP_FAB_AP_S_A_0_T_MAINNOPENDINGTRANS {TYPE_RO, 50, 1}
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#define SCR_AP_FAB_DISP_M_D_0_I_MAINNOPENDINGTRANS {TYPE_RO, 64, 1}
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#define SCR_AP_FAB_DISP_M_D_1_I_MAINNOPENDINGTRANS {TYPE_RO, 65, 1}
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#define SCR_AP_FAB_DISP_M_D_2_I_MAINNOPENDINGTRANS {TYPE_RO, 66, 1}
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#define SCR_AP_FAB_DISP_M_D_3_I_MAINNOPENDINGTRANS {TYPE_RO, 67, 1}
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#define SCR_AP_FAB_DISP_S_D_0_T_MAINNOPENDINGTRANS {TYPE_RO, 68, 1}
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#define SCR_AP_FAB_DISP_S_D_1_T_MAINNOPENDINGTRANS {TYPE_RO, 69, 1}
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#define SCR_AP_FAB_DISP_M_D_GPV_I_MAINNOPENDINGTRANS {TYPE_RO, 70, 1}
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#define SCR_AP_FAB_DISP_SVREG_T_MAINNOPENDINGTRANS {TYPE_RO, 71, 1}
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#define SCR_AP_FAB_DISP_SVREG_MAINNOPENDINGTRANS {TYPE_RO, 72, 1}
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#define SCR_AP_SEIP_KEY_SEC_STORAGE_SCR_1_0 {TYPE_L31, 0, 2}
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#define SCR_AP_SCAN_SAFMUX_BGR_AP_D0_10_8 {TYPE_RW, 0, 3}
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#define SCR_AP_SCAN_SAFMUX_BGR_AP_D0_7_0 {TYPE_RW, 3, 8}
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#define SCR_AP_SCR_BGR33_AP_TRIM_SEL {TYPE_RW, 11, 1}
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#define SCR_AP_DISP_MUX_BGR33_FUSE_TRIM_7_3 {TYPE_RW, 32, 5}
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#define SCR_AP_SCR_BGR33_DISP_TRIM_SEL {TYPE_RW, 37, 1}
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#define SCR_AP_USB_I_USB2_WAKE_USER {TYPE_RW, 64, 1}
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#define SCR_AP_SCR_AP_DEBUG_MODE_P {TYPE_RW, 96, 1}
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#define SCR_AP_SCR_XSPI2_PA_SS1_SCLKB_SEL {TYPE_RW, 128, 1}
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#define SCR_AP_SCR_XSPI2_PB_SS1_SCLKB_SEL {TYPE_RW, 129, 1}
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#endif /*_SCR_HW_H_*/ |