751 lines
29 KiB
C
751 lines
29 KiB
C
/**
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* dw_mac_lld.h
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*
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* Copyright (c) 2021 Semidrive Semiconductor.
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* All rights reserved.
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*
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* Description: dw eth mac lld header file
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*
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* Revision History:
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* -----------------
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*/
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#ifndef _DW_MAC_LLD_H_
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#define _DW_MAC_LLD_H_
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#ifndef BIT
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#define BIT(n) (1U << (n))
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#endif
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#ifndef GENMASK
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#define GENMASK(h, l) \
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(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (32 - 1 - (h))))
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#endif
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/* MAC reg */
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#define MAC_CONFIG 0x00000000
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#define MAC_PACKET_FILTER 0x00000008
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#define MAC_HASH_TAB_0_31 0x00000010
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#define MAC_HASH_TAB_32_63 0x00000014
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#define MAC_HASH_TAB_64_95 0x00000018
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#define MAC_HASH_TAB_96_127 0x0000001c
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#define MAC_RX_FLOW_CTRL 0x00000090
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#define MAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
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#define MAC_TXQ_PRTY_MAP0 0x98
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#define MAC_TXQ_PRTY_MAP1 0x9C
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#define MAC_RXQ_CTRL0 0x000000a0
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#define MAC_RXQ_CTRL1 0x000000a4
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#define MAC_RXQ_CTRL2 0x000000a8
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#define MAC_RXQ_CTRL3 0x000000ac
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#define MAC_INT_STATUS 0x000000b0
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#define MAC_INT_EN 0x000000b4
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#define MAC_RX_TX_STATUS 0x000000b8
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#define MAC_PMT_CONTROL_STATUS 0x000000c0
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#define MAC_LPI_CONTROL_STATUS 0x000000d0
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#define MAC_1US_TIC_COUNTER 0x000000dc
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#define MAC_PCS_BASE 0x000000e0
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#define MAC_AN_STATUS 0x000000e4
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#define MAC_PHYIF_CONTROL_STATUS 0x000000f8
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#define MAC_PMT 0x000000c0
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#define MAC_VERSION 0x00000110
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#define MAC_DEBUG 0x00000114
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#define MAC_HW_FEATURE0 0x0000011c
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#define MAC_HW_FEATURE1 0x00000120
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#define MAC_HW_FEATURE2 0x00000124
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#define MAC_HW_FEATURE3 0x00000128
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#define MAC_MDIO_ADDR 0x00000200
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#define MAC_MDIO_DATA 0x00000204
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#define MAC_ADDR_HIGH(reg) (0x300 + reg * 8)
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#define MAC_ADDR_LOW(reg) (0x304 + reg * 8)
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/* Rx Stats */
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#define MAC_PACKETS_RX_CONUT_64 0x000007ac
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#define MAC_PACKETS_RX_CONUT_65_127 0x000007b0
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#define MAC_PACKETS_RX_CONUT_128_255 0x000007b4
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#define MAC_PACKETS_RX_CONUT_256_511 0x000007b8
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#define MAC_PACKETS_RX_CONUT_512_1023 0x000007bc
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#define MAC_PACKETS_RX_CONUT_1024_MAX 0x000007c0
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#define MAC_PACKETS_RX_CONUT_UNICAST 0x000007c4
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#define MAC_PACKETS_RX_CONUT_MULTICAST 0x00000790
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#define MAC_PACKETS_RX_CONUT_BROADCAST 0x0000078c
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#define MAC_PACKETS_RX_CONUT_ALL_BYTES 0x00000784
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#define MAC_PACKETS_RX_CONUT_ALL_PKT 0x00000780
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#define MAC_PACKETS_RX_CONUT_BAD_PKT 0x000007e0
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#define MAC_PACKETS_RX_CONUT_CRC_ERR 0x00000794
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#define MAC_PACKETS_RX_CONUT_FRAG_ERR 0x0000079C
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#define MAC_PACKETS_RX_CONUT_ALIGN_ERR 0x00000798
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#define MAC_PACKETS_RX_CONUT_JABBER_ERR 0x000007a0
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#define MAC_PACKETS_RX_CONUT_UNDER_PKT 0x000007a4
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#define MAC_PACKETS_RX_CONUT_OVER_PKT 0x000007a8
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#define MAC_PACKETS_RX_CONUT_DROP_PKT 0x000007d4
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#define MAC_PACKETS_RX_CONUT_MIIDROP_PKT 0x000007e0
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/* Tx Stats */
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#define MAC_PACKETS_TX_CONUT_ALL_BYTES 0x00000714
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#define MAC_PACKETS_TX_CONUT_UNICAST 0x0000073C
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#define MAC_PACKETS_TX_CONUT_BROADCAST 0x00000744
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#define MAC_PACKETS_TX_CONUT_MULTICAST 0x00000740
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#define MAC_PACKETS_TX_CONUT_SINGL_COLL 0x0000074C
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#define MAC_PACKETS_TX_CONUT_MULT_COLL 0x00000750
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#define MAC_PACKETS_TX_CONUT_DFRD_COLL 0x00000754
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#define MAC_PACKETS_TX_CONUT_LATE_COLL 0x00000758
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#define MAC_PACKETS_TX_CONUT_OVER_PKT 0x00000778
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#define MAC_PACKETS_TX_CONUT_ALL_PKT 0x00000718
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#define MAC_PACKETS_TX_CONUT_GOOD_PKT 0x00000768
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#define MAC_PACKETS_TX_CONUT_DROP_PKT_COLL 0x0000075c
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#define MAC_PACKETS_TX_CONUT_DROP_PKT_CARR 0x00000760
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#define MAC_PACKETS_TX_CONUT_ERR_PKT 0x0000076c
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#define MMC_RX_INTERRUPT_MASK 0x70C
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#define MMC_TX_INTERRUPT_MASK 0x710
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#define MMC_IPC_RX_INTERRUPT_MASK 0x800
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/* RX Queues Routing */
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#define MAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
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#define MAC_RXQCTRL_AVCPQ_SHIFT 0
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#define MAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)
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#define MAC_RXQCTRL_PTPQ_SHIFT 4
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#define MAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
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#define MAC_RXQCTRL_DCBCPQ_SHIFT 8
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#define MAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)
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#define MAC_RXQCTRL_UPQ_SHIFT 12
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#define MAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
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#define MAC_RXQCTRL_MCBCQ_SHIFT 16
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#define MAC_RXQCTRL_MCBCQEN BIT(20)
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#define MAC_RXQCTRL_MCBCQEN_SHIFT 20
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#define MAC_RXQCTRL_TACPQE BIT(21)
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#define MAC_RXQCTRL_TACPQE_SHIFT 21
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/* MAC Packet Filtering */
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#define MAC_PACKET_FILTER_PR BIT(0)
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#define MAC_PACKET_FILTER_HUC BIT(1)
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#define MAC_PACKET_FILTER_HMC BIT(2)
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#define MAC_PACKET_FILTER_DAIF BIT(3)
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#define MAC_PACKET_FILTER_PM BIT(4)
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#define MAC_PACKET_FILTER_DBF BIT(5)
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#define MAC_PACKET_FILTER_MASK GENMASK(7, 6)
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#define MAC_PACKET_FILTER_SHIFT (6)
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#define MAC_PACKET_FILTER_HPF BIT(10)
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#define MAC_PACKET_FILTER_PA BIT(31)
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#define MAC_MAX_PERFECT_ADDRESSES 128
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/* MAC RX Queue Enable */
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#define MAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
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#define MAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
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#define MAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
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/* MAC Flow Control RX */
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#define MAC_RX_FLOW_CTRL_RFE BIT(0)
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/* RX Queues Priorities */
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#define MAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
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#define MAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8)
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/* TX Queues Priorities */
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#define MAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
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#define MAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8)
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/* MAC Flow Control TX */
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#define MAC_TX_FLOW_CTRL_TFE BIT(1)
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#define MAC_TX_FLOW_CTRL_PT_SHIFT 16
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/* MAC Interrupt bitmap*/
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#define MAC_INT_RGSMIIS BIT(0)
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#define MAC_INT_PCS_LINK BIT(1)
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#define MAC_INT_PCS_ANE BIT(2)
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#define MAC_INT_PCS_PHYIS BIT(3)
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#define MAC_INT_PMT_EN BIT(4)
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#define MAC_INT_LPI_EN BIT(5)
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#define MAC_PCS_IRQ_DEFAULT (MAC_INT_RGSMIIS | MAC_INT_PCS_LINK | MAC_INT_PCS_ANE)
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#define MAC_INT_DEFAULT_ENABLE (MAC_INT_PMT_EN | MAC_INT_LPI_EN)
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/* MAC config */
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#define MAC_CONFIG_IPC BIT(27)
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#define MAC_CONFIG_2K BIT(22)
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#define MAC_CONFIG_ACS BIT(20)
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#define MAC_CONFIG_WD BIT(19)
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#define MAC_CONFIG_BE BIT(18)
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#define MAC_CONFIG_JD BIT(17)
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#define MAC_CONFIG_JE BIT(16)
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#define MAC_CONFIG_PS BIT(15)
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#define MAC_CONFIG_FES BIT(14)
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#define MAC_CONFIG_DM BIT(13)
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#define MAC_CONFIG_DCRS BIT(9)
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#define MAC_CONFIG_TE BIT(1)
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#define MAC_CONFIG_RE BIT(0)
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/* MAC HW ADDR regs */
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#define MAC_HI_DCS GENMASK(18, 16)
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#define MAC_HI_DCS_SHIFT 16
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#define MAC_HI_REG_AE BIT(31)
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/* MTL registers */
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#define MTL__OPERATION_MODE 0x00000c00
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#define MTL__OPERATION_SCHALG_MASK GENMASK(6, 5)
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#define MTL__OPERATION_SCHALG_WRR (0x0 << 5)
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#define MTL__OPERATION_SCHALG_WFQ (0x1 << 5)
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#define MTL__OPERATION_SCHALG_DWRR (0x2 << 5)
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#define MTL__OPERATION_SCHALG_SP (0x3 << 5)
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#define MTL__OPERATION_RAA BIT(2)
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#define MTL__OPERATION_RAA_SP (0x0 << 2)
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#define MTL__OPERATION_RAA_WSP (0x1 << 2)
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#define MTL__TX_OPERATION_TSF BIT(2)
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#define MTL__TX_OPERATION_TQ GENMASK(3, 2)
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#define MTL__TX_OPERATION_TQ_EN (0x2 << 2)
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#define MTL__TX_OPERATION_TQ_DIS (0x0 << 2)
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#define MTL__TX_CONFIG_FLAGS_TQ BIT(3)
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#define MTL__INT_STATUS 0x00000c20
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#define MTL__INT_QX(x) BIT(x)
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#define MTL__RXQ_DMA__MAP0 0x00000c30 /* queue 0 to 3 */
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#define MTL__RXQ_DMA__MAP1 0x00000c34 /* queue 4 to 7 */
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#define MTL__RXQ_DMA__Q04MDMACH_MASK GENMASK(3, 0)
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#define MTL__RXQ_DMA__Q04MDMACH(x) ((x) << 0)
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#define MTL__RXQ_DMA__QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
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#define MTL__RXQ_DMA__QXMDMACH(channel, q) ((channel) << (8 * (q)))
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#define MTL__ECC_CTRL 0xcc0
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#define MTL__ECC_DEFAULT_ENABLE 0xf
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#define MTL__DPP_CTRL 0x00000ce0
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#define MTL__DPP_CTRL_DATA_PARITY BIT(0)
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#define MTL__DPP_CTRL_SLAVE_PARITY BIT(2)
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#define MTL__CHAN_BASE_ADDR 0x00000d00
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#define MTL__CHAN_BASE_OFFSET 0x40
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#define MTL__CHANX_BASE_ADDR(x) (MTL__CHAN_BASE_ADDR + \
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(x * MTL__CHAN_BASE_OFFSET))
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#define MTL__CHAN_TX_OP_MODE(x) MTL__CHANX_BASE_ADDR(x)
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#define MTL__CHAN_TX_DEBUG(x) (MTL__CHANX_BASE_ADDR(x) + 0x8)
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#define MTL__CHAN_INT_CTRL(x) (MTL__CHANX_BASE_ADDR(x) + 0x2c)
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#define MTL__CHAN_RX_OP_MODE(x) (MTL__CHANX_BASE_ADDR(x) + 0x30)
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#define MTL__CHAN_RX_DEBUG(x) (MTL__CHANX_BASE_ADDR(x) + 0x38)
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#define MTL__OP_MODE_RSF BIT(5)
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#define MTL__OP_MODE_TXQEN_MASK GENMASK(3, 2)
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#define MTL__OP_MODE_TXQEN_AV BIT(2)
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#define MTL__OP_MODE_TXQEN BIT(3)
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#define MTL__OP_MODE_TSF BIT(1)
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#define MTL__OP_MODE_TQS_MASK GENMASK(24, 16)
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#define MTL__OP_MODE_TQS_SHIFT 16
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#define MTL__OP_MODE_TTC_MASK 0x70
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#define MTL__OP_MODE_TTC_SHIFT 4
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#define MTL__OP_MODE_TTC_32 0
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#define MTL__OP_MODE_TTC_64 (1 << MTL__OP_MODE_TTC_SHIFT)
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#define MTL__OP_MODE_TTC_96 (2 << MTL__OP_MODE_TTC_SHIFT)
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#define MTL__OP_MODE_TTC_128 (3 << MTL__OP_MODE_TTC_SHIFT)
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#define MTL__OP_MODE_TTC_192 (4 << MTL__OP_MODE_TTC_SHIFT)
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#define MTL__OP_MODE_TTC_256 (5 << MTL__OP_MODE_TTC_SHIFT)
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#define MTL__OP_MODE_TTC_384 (6 << MTL__OP_MODE_TTC_SHIFT)
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#define MTL__OP_MODE_TTC_512 (7 << MTL__OP_MODE_TTC_SHIFT)
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#define MTL__OP_MODE_RQS_MASK GENMASK(29, 20)
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#define MTL__OP_MODE_RQS_SHIFT 20
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#define MTL__OP_MODE_RFD_MASK GENMASK(19, 14)
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#define MTL__OP_MODE_RFD_SHIFT 14
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#define MTL__OP_MODE_RFA_MASK GENMASK(13, 8)
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#define MTL__OP_MODE_RFA_SHIFT 8
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#define MTL__OP_MODE_FEP BIT(4)
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#define MTL__OP_MODE_FUP BIT(3)
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#define MTL__OP_MODE_EHFC BIT(7)
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#define MTL__OP_MODE_RTC_MASK 0x18
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#define MTL__OP_MODE_RTC_SHIFT 3
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#define MTL__OP_MODE_RTC_32 (1 << MTL__OP_MODE_RTC_SHIFT)
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#define MTL__OP_MODE_RTC_64 0
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#define MTL__OP_MODE_RTC_96 (2 << MTL__OP_MODE_RTC_SHIFT)
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#define MTL__OP_MODE_RTC_128 (3 << MTL__OP_MODE_RTC_SHIFT)
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/* MTL ETS Control register */
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#define MTL__ETS_CTRL_BASE_ADDR 0x00000d10
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#define MTL__ETS_CTRL_BASE_OFFSET 0x40
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#define MTL__ETSX_CTRL_BASE_ADDR(x) (MTL__ETS_CTRL_BASE_ADDR + \
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((x) * MTL__ETS_CTRL_BASE_OFFSET))
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#define MTL__ETS_CTRL_CC BIT(3)
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#define MTL__ETS_CTRL_AVALG BIT(2)
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/* MTL Queue Quantum Weight */
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#define MTL__TXQ_WEIGHT_BASE_ADDR 0x00000d18
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#define MTL__TXQ_WEIGHT_BASE_OFFSET 0x40
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#define MTL__TXQX_WEIGHT_BASE_ADDR(x) (MTL__TXQ_WEIGHT_BASE_ADDR + \
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((x) * MTL__TXQ_WEIGHT_BASE_OFFSET))
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#define MTL__TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)
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/* MTL sendSlopeCredit register */
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#define MTL__SEND_SLP_CRED_BASE_ADDR 0x00000d1c
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#define MTL__SEND_SLP_CRED_OFFSET 0x40
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#define MTL__SEND_SLP_CREDX_BASE_ADDR(x) (MTL__SEND_SLP_CRED_BASE_ADDR + \
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((x) * MTL__SEND_SLP_CRED_OFFSET))
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#define MTL__SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)
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/* MTL hiCredit register */
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#define MTL__HIGH_CRED_BASE_ADDR 0x00000d20
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#define MTL__HIGH_CRED_OFFSET 0x40
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#define MTL__HIGH_CREDX_BASE_ADDR(x) (MTL__HIGH_CRED_BASE_ADDR + \
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((x) * MTL__HIGH_CRED_OFFSET))
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#define MTL__HIGH_CRED_HC_MASK GENMASK(28, 0)
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/* MTL loCredit register */
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#define MTL__LOW_CRED_BASE_ADDR 0x00000d24
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#define MTL__LOW_CRED_OFFSET 0x40
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#define MTL__LOW_CREDX_BASE_ADDR(x) (MTL__LOW_CRED_BASE_ADDR + \
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((x) * MTL__LOW_CRED_OFFSET))
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#define MTL__HIGH_CRED_LC_MASK GENMASK(28, 0)
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/* MTL interrupt */
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#define MTL__RX_OVERFLOW_INT_EN BIT(24)
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#define MTL__RX_OVERFLOW_INT BIT(16)
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#define MTL__TX_UNDEROVERFLOW_INT BIT(0)
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/* Default operating mode of the MAC */
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#define MAC_CORE_INIT (MAC_CONFIG_JD | MAC_CONFIG_PS | \
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MAC_CONFIG_BE | MAC_CONFIG_DCRS | MAC_CONFIG_DM)
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/* To dump the core regs excluding the Address Registers */
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#define MAC_REG_NUM 0x300
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/* MTL algorithms identifiers */
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#define MTL__TX_ALGORITHM_WRR 0x0
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#define MTL__TX_ALGORITHM_WFQ 0x1
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#define MTL__TX_ALGORITHM_DWRR 0x2
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#define MTL__TX_ALGORITHM_SP 0x3
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#define MTL__RX_ALGORITHM_SP 0x4
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#define MTL__RX_ALGORITHM_WSP 0x5
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/* RX/TX Queue Mode */
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#define MTL__QUEUE_MODE_AVB 0x1
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#define MTL__QUEUE_MODE_DCB 0x2
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#define SF_MODE 1
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#define MAC_FITER_PASS_ALL 0
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#define MAC_FITER_PASS_MULTICAST 1
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#define MAC_FITER_PASS_HASH_MULTICAST 2
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#define MAC_FITER_PASS_UNICAST 3
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#define ERDESC4_MSG_TYPE_MASK GENMASK(11, 8)
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/* TDESC2 (read format) */
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#define TDESC2_BUFFER1_SIZE_MASK GENMASK(13, 0)
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#define TDESC2_VLAN_TAG_MASK GENMASK(15, 14)
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#define TDESC2_BUFFER2_SIZE_MASK GENMASK(29, 16)
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#define TDESC2_BUFFER2_SIZE_MASK_SHIFT 16
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#define TDESC2_TIMESTAMP_ENABLE BIT(30)
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#define TDESC2_INTERRUPT_ON_COMPLETION BIT(31)
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/* TDESC3 (read format) */
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#define TDESC3_PACKET_SIZE_MASK GENMASK(14, 0)
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#define TDESC3_CHECKSUM_INSERTION_MASK GENMASK(17, 16)
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#define TDESC3_CHECKSUM_INSERTION_SHIFT 16
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#define TDESC3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0)
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#define TDESC3_TCP_SEGMENTATION_ENABLE BIT(18)
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#define TDESC3_HDR_LEN_SHIFT 19
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#define TDESC3_SLOT_NUMBER_MASK GENMASK(22, 19)
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#define TDESC3_SA_INSERT_CTRL_MASK GENMASK(25, 23)
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#define TDESC3_CRC_PAD_CTRL_MASK GENMASK(27, 26)
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/* TDESC3 (write back format) */
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#define TDESC3_IP_HDR_ERROR BIT(0)
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#define TDESC3_DEFERRED BIT(1)
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#define TDESC3_UNDERFLOW_ERROR BIT(2)
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#define TDESC3_EXCESSIVE_DEFERRAL BIT(3)
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#define TDESC3_COLLISION_COUNT_MASK GENMASK(7, 4)
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#define TDESC3_COLLISION_COUNT_SHIFT 4
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#define TDESC3_EXCESSIVE_COLLISION BIT(8)
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#define TDESC3_LATE_COLLISION BIT(9)
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#define TDESC3_NO_CARRIER BIT(10)
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#define TDESC3_LOSS_CARRIER BIT(11)
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#define TDESC3_PAYLOAD_ERROR BIT(12)
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#define TDESC3_PACKET_FLUSHED BIT(13)
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#define TDESC3_JABBER_TIMEOUT BIT(14)
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#define TDESC3_ERROR_SUMMARY BIT(15)
|
|
#define TDESC3_TIMESTAMP_STATUS BIT(17)
|
|
#define TDESC3_TIMESTAMP_STATUS_SHIFT 17
|
|
|
|
/* TDESC3 context */
|
|
#define TDESC3_CTXT_TCMSSV BIT(26)
|
|
|
|
/* TDESC3 Common */
|
|
#define TDESC3_RS1V BIT(26)
|
|
#define TDESC3_RS1V_SHIFT 26
|
|
#define TDESC3_LAST_DESCRIPTOR BIT(28)
|
|
#define TDESC3_LAST_DESCRIPTOR_SHIFT 28
|
|
#define TDESC3_FIRST_DESCRIPTOR BIT(29)
|
|
#define TDESC3_CONTEXT_TYPE BIT(30)
|
|
#define TDESC3_CONTEXT_TYPE_SHIFT 30
|
|
|
|
/* TDS3 use for both format (read and write back) */
|
|
#define TDESC3_OWN BIT(31)
|
|
#define TDESC3_OWN_SHIFT 31
|
|
|
|
/* Normal receive descriptor defines (without split feature) */
|
|
|
|
/* RDESC0 (write back format) */
|
|
#define RDESC0_VLAN_TAG_MASK GENMASK(15, 0)
|
|
|
|
/* RDESC1 (write back format) */
|
|
#define RDESC1_IP_PAYLOAD_TYPE_MASK GENMASK(2, 0)
|
|
#define RDESC1_IP_HDR_ERROR BIT(3)
|
|
#define RDESC1_IPV4_HEADER BIT(4)
|
|
#define RDESC1_IPV6_HEADER BIT(5)
|
|
#define RDESC1_IP_CSUM_BYPASSED BIT(6)
|
|
#define RDESC1_IP_CSUM_ERROR BIT(7)
|
|
#define RDESC1_PTP_MSG_TYPE_MASK GENMASK(11, 8)
|
|
#define RDESC1_PTP_PACKET_TYPE BIT(12)
|
|
#define RDESC1_PTP_VER BIT(13)
|
|
#define RDESC1_TIMESTAMP_AVAILABLE BIT(14)
|
|
#define RDESC1_TIMESTAMP_AVAILABLE_SHIFT 14
|
|
#define RDESC1_TIMESTAMP_DROPPED BIT(15)
|
|
#define RDESC1_IP_TYPE1_CSUM_MASK GENMASK(31, 16)
|
|
|
|
/* RDESC2 (write back format) */
|
|
#define RDESC2_L3_L4_HEADER_SIZE_MASK GENMASK(9, 0)
|
|
#define RDESC2_VLAN_FILTER_STATUS BIT(15)
|
|
#define RDESC2_SA_FILTER_FAIL BIT(16)
|
|
#define RDESC2_DA_FILTER_FAIL BIT(17)
|
|
#define RDESC2_HASH_FILTER_STATUS BIT(18)
|
|
#define RDESC2_MAC_ADDR_MATCH_MASK GENMASK(26, 19)
|
|
#define RDESC2_HASH_VALUE_MATCH_MASK GENMASK(26, 19)
|
|
#define RDESC2_L3_FILTER_MATCH BIT(27)
|
|
#define RDESC2_L4_FILTER_MATCH BIT(28)
|
|
#define RDESC2_L3_L4_FILT_NB_MATCH_MASK GENMASK(27, 26)
|
|
#define RDESC2_L3_L4_FILT_NB_MATCH_SHIFT 26
|
|
|
|
/* RDESC3 (write back format) */
|
|
#define RDESC3_PACKET_SIZE_MASK GENMASK(14, 0)
|
|
#define RDESC3_ERROR_SUMMARY BIT(15)
|
|
#define RDESC3_PACKET_LEN_TYPE_MASK GENMASK(18, 16)
|
|
#define RDESC3_DRIBBLE_ERROR BIT(19)
|
|
#define RDESC3_RECEIVE_ERROR BIT(20)
|
|
#define RDESC3_OVERFLOW_ERROR BIT(21)
|
|
#define RDESC3_RECEIVE_WATCHDOG BIT(22)
|
|
#define RDESC3_GIANT_PACKET BIT(23)
|
|
#define RDESC3_CRC_ERROR BIT(24)
|
|
#define RDESC3_RDESC0_VALID BIT(25)
|
|
#define RDESC3_RDESC1_VALID BIT(26)
|
|
#define RDESC3_RDESC2_VALID BIT(27)
|
|
#define RDESC3_LAST_DESCRIPTOR BIT(28)
|
|
#define RDESC3_FIRST_DESCRIPTOR BIT(29)
|
|
#define RDESC3_CONTEXT_DESCRIPTOR BIT(30)
|
|
#define RDESC3_CONTEXT_DESCRIPTOR_SHIFT 30
|
|
|
|
/* RDESC3 (read format) */
|
|
#define RDESC3_BUFFER1_VALID_ADDR BIT(24)
|
|
#define RDESC3_BUFFER2_VALID_ADDR BIT(25)
|
|
#define RDESC3_INT_ON_COMPLETION_EN BIT(30)
|
|
|
|
/* TDS3 use for both format (read and write back) */
|
|
#define RDESC3_OWN BIT(31)
|
|
|
|
/* Extended RDESC4 message type definitions */
|
|
#define RDESC_EXT_NO_PTP 0x0
|
|
#define RDESC_EXT_SYNC 0x1
|
|
#define RDESC_EXT_FOLLOW_UP 0x2
|
|
#define RDESC_EXT_DELAY_REQ 0x3
|
|
#define RDESC_EXT_DELAY_RESP 0x4
|
|
#define RDESC_EXT_PDELAY_REQ 0x5
|
|
#define RDESC_EXT_PDELAY_RESP 0x6
|
|
#define RDESC_EXT_PDELAY_FOLLOW_UP 0x7
|
|
#define RDESC_PTP_ANNOUNCE 0x8
|
|
#define RDESC_PTP_MANAGEMENT 0x9
|
|
#define RDESC_PTP_SIGNALING 0xa
|
|
#define RDESC_PTP_PKT_RESERVED_TYPE 0xf
|
|
|
|
/* Rx IPC status */
|
|
enum rx_frame_status {
|
|
RX_GOOD = 0x0,
|
|
RX_BAD = 0x1,
|
|
RX_DMA__PROCESS = 0x8,
|
|
csum_none = 0x2,
|
|
llc_snap = 0x4,
|
|
rx_not_ls = 0x10,
|
|
};
|
|
|
|
enum tx_frame_status {
|
|
TX_GOOD = 0x0,
|
|
TX_ERROR = 0x1,
|
|
TX_DMA__PROCESS = 0x2,
|
|
TX_NOT_LS = 0x3,
|
|
};
|
|
|
|
/* DMA config */
|
|
#define ETH_MAX_DMA_CHANNEL 1
|
|
|
|
#define DMA__BUS_MODE 0x00001000
|
|
#define DMA__STATUS 0x00001008
|
|
#define DMA__SYS_BUS_MODE 0x00001004
|
|
#define DMA__DEBUG_STATUS_0 0x0000100c
|
|
#define DMA__DEBUG_STATUS_1 0x00001010
|
|
#define DMA__DEBUG_STATUS_2 0x00001014
|
|
#define DMA__AXI_BUS_MODE 0x00001028
|
|
|
|
enum dma_rx_status {
|
|
DMX_RX_STOP = 0,
|
|
DMX_RX_RUN_FRTD,
|
|
DMX_RX_RSVD,
|
|
DMX_RX_WRP,
|
|
DMX_RX_SUSPND,
|
|
DMX_RX_RUN_CRD,
|
|
DMX_RX_TSTMP,
|
|
DMX_RX_TRP
|
|
};
|
|
|
|
/* DMA Bus Mode bitmap */
|
|
#define DMA__BUS_MODE_SFT_RESET BIT(0)
|
|
|
|
/* DMA SYS Bus Mode bitmap */
|
|
#define DMA__BUS_MODE_SPH BIT(24)
|
|
#define DMA__BUS_MODE_PBL BIT(16)
|
|
#define DMA__BUS_MODE_PBL_SHIFT 16
|
|
#define DMA__BUS_MODE_RPBL_SHIFT 16
|
|
#define DMA__BUS_MODE_MB BIT(14)
|
|
#define DMA__BUS_MODE_FB BIT(0)
|
|
|
|
/* DMA Interrupt top status */
|
|
#define DMA__STATUS_MAC BIT(17)
|
|
#define DMA__STATUS_MTL BIT(16)
|
|
#define DMA__STATUS_CHAN7 BIT(7)
|
|
#define DMA__STATUS_CHAN6 BIT(6)
|
|
#define DMA__STATUS_CHAN5 BIT(5)
|
|
#define DMA__STATUS_CHAN4 BIT(4)
|
|
#define DMA__STATUS_CHAN3 BIT(3)
|
|
#define DMA__STATUS_CHAN2 BIT(2)
|
|
#define DMA__STATUS_CHAN1 BIT(1)
|
|
#define DMA__STATUS_CHAN0 BIT(0)
|
|
#define DMA__STATUS_CHAN0_5 GENMASK(4,0)
|
|
|
|
/* DMA debug status bitmap */
|
|
#define DMA__DEBUG_STATUS_TS_MASK 0xf
|
|
#define DMA__DEBUG_STATUS_RS_MASK 0xf
|
|
|
|
/* DMA AXI bitmap */
|
|
#define DMA__AXI_EN_LPI BIT(31)
|
|
#define DMA__AXI_LPI_XIT_FRM BIT(30)
|
|
#define DMA__AXI_WR_OSR_LMT GENMASK(27, 24)
|
|
#define DMA__AXI_WR_OSR_LMT_SHIFT 24
|
|
#define DMA__AXI_RD_OSR_LMT GENMASK(19, 16)
|
|
#define DMA__AXI_RD_OSR_LMT_SHIFT 16
|
|
|
|
#define DMA__AXI_OSR_MAX 0xf
|
|
#define DMA__AXI_MAX_OSR_LIMIT ((DMA__AXI_OSR_MAX << DMA__AXI_WR_OSR_LMT_SHIFT) | \
|
|
(DMA__AXI_OSR_MAX << DMA__AXI_RD_OSR_LMT_SHIFT))
|
|
|
|
#define DMA__SYS_BUS_MB BIT(14)
|
|
#define DMA__AXI_1KBBE BIT(13)
|
|
#define DMA__SYS_BUS_AAL BIT(12)
|
|
#define DMA__SYS_BUS_EAME BIT(11)
|
|
#define DMA__AXI_BLEN256 BIT(7)
|
|
#define DMA__AXI_BLEN128 BIT(6)
|
|
#define DMA__AXI_BLEN64 BIT(5)
|
|
#define DMA__AXI_BLEN32 BIT(4)
|
|
#define DMA__AXI_BLEN16 BIT(3)
|
|
#define DMA__AXI_BLEN8 BIT(2)
|
|
#define DMA__AXI_BLEN4 BIT(1)
|
|
#define DMA__SYS_BUS_FB BIT(0)
|
|
|
|
#define DMA__BURST_LEN_DEFAULT (DMA__AXI_BLEN256 | DMA__AXI_BLEN128 | \
|
|
DMA__AXI_BLEN64 | DMA__AXI_BLEN32 | \
|
|
DMA__AXI_BLEN16 | DMA__AXI_BLEN8 | \
|
|
DMA__AXI_BLEN4)
|
|
|
|
#define DMA__AXI_BURST_LEN_MASK 0x000000FE
|
|
|
|
/* Following DMA defines are chanels oriented */
|
|
#define DMA__CHAN_BASE_ADDR 0x00001100
|
|
#define DMA__CHAN_BASE_OFFSET 0x80
|
|
#define DMA__CHANX_BASE_ADDR(x) (DMA__CHAN_BASE_ADDR + (x * DMA__CHAN_BASE_OFFSET))
|
|
#define DMA__CHAN_REG_NUMBER 17
|
|
|
|
#define DMA__CHAN_CONTROL(x) DMA__CHANX_BASE_ADDR(x)
|
|
#define DMA__CHAN_TX_CONTROL(x) (DMA__CHANX_BASE_ADDR(x) + 0x4)
|
|
#define DMA__CHAN_RX_CONTROL(x) (DMA__CHANX_BASE_ADDR(x) + 0x8)
|
|
#define DMA__CHAN_TX_BASE_ADDR_HI(x) (DMA__CHANX_BASE_ADDR(x) + 0x10)
|
|
#define DMA__CHAN_TX_BASE_ADDR(x) (DMA__CHANX_BASE_ADDR(x) + 0x14)
|
|
#define DMA__CHAN_RX_BASE_ADDR_HI(x) (DMA__CHANX_BASE_ADDR(x) + 0x18)
|
|
#define DMA__CHAN_RX_BASE_ADDR(x) (DMA__CHANX_BASE_ADDR(x) + 0x1c)
|
|
#define DMA__CHAN_TX_END_ADDR(x) (DMA__CHANX_BASE_ADDR(x) + 0x20)
|
|
#define DMA__CHAN_RX_END_ADDR(x) (DMA__CHANX_BASE_ADDR(x) + 0x28)
|
|
#define DMA__CHAN_TX_RING_LEN(x) (DMA__CHANX_BASE_ADDR(x) + 0x2c)
|
|
#define DMA__CHAN_RX_RING_LEN(x) (DMA__CHANX_BASE_ADDR(x) + 0x30)
|
|
#define DMA__CHAN_INTR_ENA(x) (DMA__CHANX_BASE_ADDR(x) + 0x34)
|
|
#define DMA__CHAN_RX_WATCHDOG(x) (DMA__CHANX_BASE_ADDR(x) + 0x38)
|
|
#define DMA__CHAN_SLOT_CTRL_STATUS(x) (DMA__CHANX_BASE_ADDR(x) + 0x3c)
|
|
#define DMA__CHAN_CUR_TX_DESC(x) (DMA__CHANX_BASE_ADDR(x) + 0x44)
|
|
#define DMA__CHAN_CUR_RX_DESC(x) (DMA__CHANX_BASE_ADDR(x) + 0x4c)
|
|
#define DMA__CHAN_CUR_TX_BUF_ADDR(x) (DMA__CHANX_BASE_ADDR(x) + 0x54)
|
|
#define DMA__CHAN_CUR_RX_BUF_ADDR(x) (DMA__CHANX_BASE_ADDR(x) + 0x5c)
|
|
#define DMA__CHAN_STATUS(x) (DMA__CHANX_BASE_ADDR(x) + 0x60)
|
|
|
|
/* DMA Control X */
|
|
#define DMA__CONTROL_MSS_MASK GENMASK(13, 0)
|
|
|
|
/* DMA Tx channel X Control register defines */
|
|
#define DMA__CONTROL_DSL_MASK GENMASK(20, 18)
|
|
#define DMA__CONTROL_DSL_SHIFT 18
|
|
#define DMA__CONTROL_TSE BIT(12)
|
|
#define DMA__CONTROL_OSP BIT(4)
|
|
#define DMA__CONTROL_ST BIT(0)
|
|
#define DMA__CONTROL_TXPBL(x) (((x) << 16) & GENMASK(21, 16))
|
|
|
|
/* DMA Rx channel X Control register defines */
|
|
#define DMA__CONTROL_SR BIT(0)
|
|
#define DMA__RBSZ_MASK GENMASK(14, 1)
|
|
#define DMA__RBSZ_SHIFT 1
|
|
#define DMA__CONTROL_RXPBL(x) (((x) << 16) & GENMASK(21, 16))
|
|
|
|
/* Interrupt status per channel */
|
|
#define DMA__CHAN_STATUS_REB GENMASK(21, 19)
|
|
#define DMA__CHAN_STATUS_REB_SHIFT 19
|
|
#define DMA__CHAN_STATUS_TEB GENMASK(18, 16)
|
|
#define DMA__CHAN_STATUS_TEB_SHIFT 16
|
|
#define DMA__CHAN_STATUS_NIS BIT(15)
|
|
#define DMA__CHAN_STATUS_AIS BIT(14)
|
|
#define DMA__CHAN_STATUS_CDE BIT(13)
|
|
#define DMA__CHAN_STATUS_FBE BIT(12)
|
|
#define DMA__CHAN_STATUS_ERI BIT(11)
|
|
#define DMA__CHAN_STATUS_ETI BIT(10)
|
|
#define DMA__CHAN_STATUS_RWT BIT(9)
|
|
#define DMA__CHAN_STATUS_RPS BIT(8)
|
|
#define DMA__CHAN_STATUS_RBU BIT(7)
|
|
#define DMA__CHAN_STATUS_RI BIT(6)
|
|
#define DMA__CHAN_STATUS_TBU BIT(2)
|
|
#define DMA__CHAN_STATUS_TPS BIT(1)
|
|
#define DMA__CHAN_STATUS_TI BIT(0)
|
|
|
|
/* Interrupt enable bits per channel */
|
|
#define DMA__CHAN_INTR_ENA_NIE BIT(15)
|
|
#define DMA__CHAN_INTR_ENA_AIE BIT(14)
|
|
#define DMA__CHAN_INTR_ENA_CDE BIT(13)
|
|
#define DMA__CHAN_INTR_ENA_FBE BIT(12)
|
|
#define DMA__CHAN_INTR_ENA_ERE BIT(11)
|
|
#define DMA__CHAN_INTR_ENA_ETE BIT(10)
|
|
#define DMA__CHAN_INTR_ENA_RWE BIT(9)
|
|
#define DMA__CHAN_INTR_ENA_RSE BIT(8)
|
|
#define DMA__CHAN_INTR_ENA_RBUE BIT(7)
|
|
#define DMA__CHAN_INTR_ENA_RIE BIT(6)
|
|
#define DMA__CHAN_INTR_ENA_TBUE BIT(2)
|
|
#define DMA__CHAN_INTR_ENA_TSE BIT(1)
|
|
#define DMA__CHAN_INTR_ENA_TIE BIT(0)
|
|
|
|
#define DMA__CHAN_INTR_NORMAL (DMA__CHAN_INTR_ENA_NIE | \
|
|
DMA__CHAN_INTR_ENA_RIE | \
|
|
DMA__CHAN_INTR_ENA_TIE )
|
|
|
|
#define DMA__CHAN_INTR_ABNORMAL (DMA__CHAN_INTR_ENA_AIE | \
|
|
DMA__CHAN_INTR_ENA_FBE)
|
|
/* DMA default interrupt mask for 4.00 */
|
|
#define DMA__CHAN_INTR_DEFAULT_MASK (DMA__CHAN_INTR_NORMAL | \
|
|
DMA__CHAN_INTR_ABNORMAL)
|
|
|
|
#define PHY_CLAUSE_22 0xFF
|
|
|
|
static inline void udelay(uint32_t usecs)
|
|
{
|
|
volatile uint64_t count = usecs * 300;
|
|
|
|
while (count > 0)
|
|
count--;
|
|
}
|
|
|
|
/*
|
|
mode transmit store and forward enable or not
|
|
qmode transmit queue enable or not
|
|
fifo transmit queue size
|
|
*/
|
|
#if defined(DEBUG_ENABLE)
|
|
void dwmac_dump_mac(uint32_t addr);
|
|
void dwmac_dump_mtl(uint32_t regbase, uint32_t queue);
|
|
#endif
|
|
void dwmac_prog_mtl_rx_algorithms(uint32_t regbase, uint32_t rx_alg);
|
|
void dwmac_prog_mtl_tx_algorithms(uint32_t regbase, uint32_t tx_alg);
|
|
void dwmac_map_mtl_dma(uint32_t addr, uint32_t queue, uint32_t channel);
|
|
int32_t dwmac_set_filter(uint32_t regbase, uint32_t mode,
|
|
const uint8_t *mac_addr);
|
|
void dwmac_flow_ctrl(uint32_t regbase, uint32_t duplex, uint32_t fc,
|
|
uint32_t pause_time, uint32_t tx_cnt);
|
|
void dwmac_core_init(uint32_t regbase, uint32_t mtu, uint32_t speed,
|
|
uint8_t *macaddr);
|
|
void dwmac_clr_umac_addr(uint32_t regbase, uint32_t Reg_n);
|
|
void dwmac_set_umac_addr(uint32_t regbase, const uint8_t *addr,
|
|
uint32_t reg_n);
|
|
void dwmac_get_umac_addr(uint32_t regbase, uint8_t *addr, uint32_t reg_n);
|
|
void dwmac_rx_queue_enable(uint32_t addr, uint8_t mode, uint32_t queue);
|
|
int dwmac_irq_mtl_status(uint32_t regbase, uint32_t channel);
|
|
int32_t dwmac_dma_reset(uint32_t regbase);
|
|
bool dwmac_access_test(uint32_t regbase);
|
|
void dwmac_enable_dma_irq(uint32_t regbase, uint32_t channel, bool rx,
|
|
bool tx);
|
|
void dwmac_disable_dma_irq(uint32_t regbase, uint32_t channel);
|
|
void dwmac_dump_dma_regs(uint32_t regbase, int channel);
|
|
void dwmac_dma_start_tx(uint32_t regbase, uint32_t channel);
|
|
void dwmac_dma_stop_tx(uint32_t regbase, uint32_t channel);
|
|
void dwmac_dma_start_rx(uint32_t regbase, uint32_t channel);
|
|
void dwmac_dma_stop_rx(uint32_t regbase, uint32_t channel);
|
|
void dwmac_dma_rx_chan_op_mode(uint32_t regbase, uint32_t channel, int mode,
|
|
int fifosz, uint8_t qmode);
|
|
/*
|
|
mode transmit store and forward enable or not
|
|
qmode transmit queue enable or not
|
|
fifo transmit queue size
|
|
*/
|
|
void dwmac_dma_tx_chan_op_mode(uint32_t regbase, uint32_t channel, int mode,
|
|
int fifosz, uint8_t qmode);
|
|
|
|
void dwmac_set_rx_ring_len(uint32_t regbase, uint32_t len, uint32_t channel);
|
|
void dwmac_set_tx_ring_len(uint32_t regbase, uint32_t len, uint32_t channel);
|
|
void dwmac_set_rx_list_ptr(uint32_t regbase, uint32_t list_ptr,
|
|
uint32_t channel);
|
|
void dwmac_set_tx_list_ptr(uint32_t regbase, uint32_t list_ptr,
|
|
uint32_t channel);
|
|
void dwmac_set_rx_tail_ptr(uint32_t regbase, uint32_t tail_ptr,
|
|
uint32_t channel);
|
|
void dwmac_set_tx_tail_ptr(uint32_t regbase, uint32_t tail_ptr,
|
|
uint32_t channel);
|
|
void dwmac_dma_init_rx_chan(uint32_t regbase, uint32_t base_ptr,
|
|
uint32_t rbsz, uint32_t channel);
|
|
void dwmac_dma_init_tx_chan(uint32_t regbase, uint32_t base_ptr,
|
|
uint32_t channel);
|
|
void dwmac_dma_bus_init(uint32_t regbase, uint32_t flags);
|
|
uint32_t dwmac_dma_rx_state_get(uint32_t regbase, uint32_t channel);
|
|
void dwmac_dma_init_channel(uint32_t regbase, uint32_t flags, \
|
|
uint32_t channel, uint32_t skip);
|
|
|
|
void dwmac_set_bfsize(uint32_t regbase, int bfsize, uint32_t channel);
|
|
int32_t mac_mdio_write(uint32_t regbase, uint8_t phyaddr, uint8_t device,
|
|
uint16_t phyreg, uint16_t phydata);
|
|
int32_t mac_mdio_read(uint32_t regbase, uint8_t phyaddr, uint8_t device,
|
|
uint16_t phyreg);
|
|
void dwmac_rx_trigger(uint32_t regbase, uint32_t channel);
|
|
void dwmac_mac_rx_queue_mcbc_routing(uint32_t regbase, uint8_t channel);
|
|
uint8_t *dwmac_get_default_mac_addr(void);
|
|
void dwmac_enable_dma_rx_int(uint32_t regbase, uint32_t channel, bool enable);
|
|
void dwmac_enable_dma_tx_int(uint32_t regbase, uint32_t channel, bool enable);
|
|
uint32_t dwmac_get_dma_int_status(uint32_t regbase);
|
|
uint32_t dwmac_get_mac_int_status(uint32_t regbase);
|
|
uint32_t dwmac_get_mac_phyif_control_status(uint32_t regbase);
|
|
uint32_t dwmac_get_mac_an_status(uint32_t regbase);
|
|
uint32_t dwmac_get_mac_pmt_control_status(uint32_t regbase);
|
|
uint32_t dwmac_get_mac_lpi_control_status(uint32_t regbase);
|
|
uint32_t dwmac_get_mtl_int_status(uint32_t regbase);
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uint32_t dwmac_get_mtl_q_int_status(uint32_t regbase, uint32_t channel);
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void dwmac_clr_mtl_q_int_status(uint32_t regbase, uint32_t channel, uint32_t val);
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uint32_t dwmac_get_dma_chn_status(uint32_t regbase, uint32_t channel);
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void dwmac_clear_dma_chn_int_status(uint32_t regbase, uint32_t channel);
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#endif
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