475 lines
14 KiB
C
475 lines
14 KiB
C
/**
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* @file sdrv_spi.h
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* @brief SemiDrive SPI driver header file.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_SPI_H
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#define SDRV_SPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <sdrv_ckgen.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "reg.h"
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#include "sdrv_dma.h"
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#include "spi_reg.h"
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#define SPI_PIPE_LINE_SIZE_8B 3U
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#define SPI_PIPE_LINE_SIZE_4B 4U
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#define SPI_PIPE_LINE_SIZE_2B 5U
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#define SPI_PIPE_LINE_SIZE_OB 2U
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// 2 mst_idle 3 mst_start 7 mst_data_wait
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#define SPI_FSM_WAIT_DATA_STA 7U
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#define SPI_FSM_M_STR_STA 3U
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#define SPI_FSM_IDLE_STA 2U
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#define MAX_TIMEOUT_SWRST 2560U
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/**
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* @brief Spi sclk idle mode.
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*/
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enum spi_cpol { SCK_IDLE_LOW, SCK_IDLE_HIGH };
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/**
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* @brief Spi sclk phase mode.
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*/
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enum spi_cpha {
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DATA_CPT_ON_FIRST_SCK_EDGE,
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DATA_CPT_ON_SECOND_SCK_EDGE,
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};
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/**
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* @brief Spi cs mode.
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*/
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enum spi_cs_polarity { CS_ACTIVE_LOW, CS_ACTIVE_HIGH };
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/**
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* @brief Spi hardware cs select .
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*/
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enum spi_cs_select { CS_SEL_SS0 = 0, CS_SEL_SS1, CS_SEL_SS2, CS_SEL_SS3 };
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/**
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* @brief Spi Bus state flags.
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*/
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enum spi_state {
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SPI_STATE_UNINIT = 0x0,
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SPI_STATE_INITED = 0x1,
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SPI_STATE_BUSY_TX = 0x02,
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SPI_STATE_BUSY_RX = 0x04,
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SPI_STATE_IRQ_ACT = 0x08,
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SPI_STATE_DMA_TX = 0x10,
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SPI_STATE_DMA_RX = 0x20,
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SPI_STATE_IRQ_TX = 0x40,
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SPI_STATE_IRQ_RX = 0x80,
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SPI_STATE_IS_SLAVE = 0x100,
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SPI_STATE_CS_ACTIVEED = 0x200,
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SPI_STATE_IS_UNS_EN = 0x400,
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SPI_STATE_IS_RO_END = 0x800,
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SPI_STATE_DMA_TX_RD = 0x1000,
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SPI_STATE_DMA_RX_RD = 0x2000,
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};
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/**
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* @brief Spi fifo state flags.
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*/
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enum fifo_state {
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SPI_RX_FIFO_READ = (0x01 << 0),
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SPI_TX_FIFO_WRITE = (0x01 << 1),
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SPI_TX_FIFO_UDR = (0x01 << 2),
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SPI_RX_FIFO_OVR = (0x01 << 3),
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SPI_TX_DMA_ERR = (0x01 << 4),
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SPI_RX_DMA_ERR = (0x01 << 5),
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SPI_TX_ONLY_DONE = (0x01 << 6),
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};
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/**
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* @brief Spi irq type .
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*/
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enum irq_type {
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SPI_TRASPORT_FINISH = 0x01 << 0,
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SPI_RX_READ_REQ = 0x01 << 1,
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SPI_TX_WRITE_REQ = 0x01 << 2,
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SPI_CS_INVLD_REQ = 0x01 << 3,
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};
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/**
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* @brief Spi bus idle/busy state .
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*/
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enum spi_bus_state { SPI_IDLE = 0, SPI_BUSY };
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/**
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* @brief Spi transmit mode .
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*/
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enum spi_ops_type {
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OP_MODE_SYNC = 0,
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OP_MODE_IRQ,
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OP_MODE_DMA,
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};
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/**
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* @brief Spi async transmit callback type .
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*/
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typedef enum {
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SPI_TRANS_DONE = 0,
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SPI_TRANS_FAIL,
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SPI_TRANS_PASS
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} spi_event_type;
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/**
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* @brief Spi transmit data direction type .
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*/
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enum data_dir { SPI_RX_DIR = 0x01, SPI_TX_DIR = 0x02 };
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/**
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* @brief Spi async transmit callback type .
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*/
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typedef void (*spi_callback_t)(void *spi, spi_event_type Event);
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/**
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* @brief SPI device configuration.
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*/
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struct spi_device_config {
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/* sclk frea in hz */
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uint32_t sclk_freq;
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/* Idle level */
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enum spi_cpol cpol;
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/* Sampling phase */
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enum spi_cpha cpha;
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/* cs active polarity */
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enum spi_cs_polarity cs_pol;
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/* ss0-ss3 or GPIO_xx */
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uint8_t cs_sel;
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/* deivce raw data width 4-32*/
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uint8_t width;
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/* minimum interval between two transmissions in n*sclk */
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uint8_t fream_delay;
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/* cs setup time in n*sclk */
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uint8_t clk2cs_delay;
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/* cs hold time in n*sclk */
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uint8_t clk2cs_end_delay;
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/* lsb or msb */
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bool is_lsb_mode;
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/* Control the cs signal through IO or peripherals */
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bool is_soft_cs;
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/* enable miso sampling delay half sclk on master mode */
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bool is_tx_delay;
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};
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/**
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* @brief Spi controller configuration .
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*/
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struct spi_common_config {
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/* motor rola mode or ti mode */
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bool is_spi_mode;
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/* half mode */
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bool is_half_mode;
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/* master or slave mode */
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bool is_master;
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/* polling mode */
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bool is_polling_mode;
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#if CONFIG_SPI_ENABLE_DMA
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/* rx dma channel id */
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sdrv_dma_channel_id_e rx_ch_id;
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/* tx dma channel id */
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sdrv_dma_channel_id_e tx_ch_id;
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/* dma handler */
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sdrv_dma_t *dma_ins;
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#endif
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/* reg base */
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uint32_t base;
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/* irq num */
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uint32_t irq;
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/* root clk node */
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const sdrv_ckgen_slice_node_t *clk;
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};
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/**
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* @brief Spi transmition data ptr .
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*/
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union spi_data_ptr {
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/* data */
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uint32_t val;
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uint8_t *u8_ptr;
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uint16_t *u16_ptr;
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uint32_t *u32_ptr;
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};
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/**
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* @brief Spi dma context type .
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*/
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struct spi_dma_context {
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enum data_dir dir;
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void *bus;
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bool is_need_handle;
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};
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/**
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* @brief Spi transmit context type .
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*/
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struct spi_transmit_cb {
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/* transmit_sche mode need this*/
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uint32_t len;
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/* tansmit data width type */
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uint8_t width_type;
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/* prxdata */
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union spi_data_ptr prxdata;
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/* ptxdata */
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union spi_data_ptr ptxdata;
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/* prxdata */
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uint32_t rx_cur;
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/* ptxdata */
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uint32_t tx_cur;
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/* remain of this item */
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uint32_t cur_remian;
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/* once except of this item */
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uint32_t expect_len;
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/* vector transmit need */
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struct spi_transmit_cb *next;
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};
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/**
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* @brief Spi bus module handler type .
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*/
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typedef struct sdrv_spi {
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/* get frame static config */
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uint32_t base;
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/* get frame static config */
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uint32_t irq;
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/* Max baudrate when divide by 0 */
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uint32_t max_baudrate;
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/* Max baudrate when divide by 256 */
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uint32_t min_baudrate;
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/* spi preinstance config */
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const struct spi_common_config *com_config;
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/* default Config or slave mode cfg */
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const struct spi_device_config *dev_config;
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/* */
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spi_callback_t callback;
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/* */
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struct spi_transmit_cb transmit_sche;
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/* status */
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uint32_t state;
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/* cur cmd */
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uint32_t cur_cmd;
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#if CONFIG_SPI_ENABLE_DMA
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/* dma rx channel */
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sdrv_dma_channel_t rx_dma_chan;
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/* dma rx channel */
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struct spi_dma_context rx_context;
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/* dma rx channel */
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sdrv_dma_channel_t tx_dma_chan;
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/* dma rx channel */
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struct spi_dma_context tx_context;
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/* dma error */
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uint32_t dma_err;
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#endif
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} sdrv_spi_t;
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#define SPI_POL_VEL_ILLEGAL (~0xFu)
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#define SPI_START_DELAY_MAX 0xFFu
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#define SPI_END_DELAY_MAX 0xFFu
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#define SPI_FRAME_DELAY_MAX 0xFFu
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#define SPI_CLK_PRESSCALE_MAX 0xFFu
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#define SPI_FIFO_LEN 16u
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#define SPI_FRAME_SIZE_MAX 1024U
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#define SPI_SLAVE_IRQ_NICE_ADJUST (-1) /* slave irq nice val */
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/**
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* @brief Spi transmit data width type only for internal .
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*/
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#define SPI_DATA_WIDTH_MIN 4U
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#define SPI_DATA_WIDTH_BYTE 8U
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#define SPI_DATA_WIDTH_HALF_WORD 16U
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#define SPI_DATA_WIDTH_WORD 32U
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#define SPI_DATA_WIDTH_MAX SPI_DATA_WIDTH_WORD
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#define SPI_INTERNAL_DIV_SHIFT (1u)
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#define SPI_CLK_PRESSCALE_MAX_SHIFT (8u)
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#define SPI_TIMMING_CFG(f, s, e) \
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(FV_SPI_TIM_CTRL_START_DLY(s) | FV_SPI_TIM_CTRL_END_DLY(e) | \
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FV_SPI_TIM_CTRL_FRM_DLY(f))
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#define BUS_BUSY_MASK (SPI_STATE_BUSY_TX | SPI_STATE_BUSY_RX)
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#define BUS_BUSY_DMA_MASK (SPI_STATE_DMA_TX | SPI_STATE_DMA_RX)
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#define BUS_BUSY_IRQ_MASK (SPI_STATE_IRQ_TX | SPI_STATE_IRQ_RX)
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#define BUS_FIFO_STATE_MASK (SPI_RX_FIFO_READ | SPI_TX_FIFO_WRITE)
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#define BUS_BUSY_ASYNC_MASK (BUS_BUSY_DMA_MASK | BUS_BUSY_IRQ_MASK)
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#define BUS_BUSY_STATUS_MASK (BUS_BUSY_MASK | BUS_BUSY_ASYNC_MASK)
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#define BUS_FIFO_STATE_ERR_MASK \
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(SPI_TX_FIFO_UDR | SPI_RX_FIFO_OVR | SPI_TX_DMA_ERR | SPI_RX_DMA_ERR)
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#define BUS_FIFO_EMPTYE_TIMEOUT(f_delay, s_delay, e_delay, baudrate) \
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(((f_delay) + (s_delay) + (e_delay) + SPI_DATA_WIDTH_MAX) * 1000000 / \
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(baudrate))
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#define BUS_STATE_TX_MASK \
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(SPI_STATE_DMA_TX | SPI_STATE_BUSY_TX | SPI_STATE_IRQ_TX)
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#define BUS_STATE_RX_MASK \
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(SPI_STATE_DMA_RX | SPI_STATE_BUSY_RX | SPI_STATE_IRQ_RX)
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#define SPI_SATE_EXT_FLAGS \
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(SPI_STATE_IS_UNS_EN | SPI_STATE_IS_RO_END | SPI_STATE_CS_ACTIVEED)
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#define SPI_GET_WIDTH_SHIFT(width_type) \
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(((width_type) == SPI_DATA_WIDTH_WORD \
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? 2 \
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: ((width_type) / SPI_DATA_WIDTH_BYTE) - 1))
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#define SPI_GET_WIDTH_TYPE(width) \
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(((width) > 16U) \
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? (SPI_DATA_WIDTH_WORD) \
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: ((width) > 8U ? SPI_DATA_WIDTH_HALF_WORD : SPI_DATA_WIDTH_BYTE))
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#define SPI_IS_VALID_LEN(bytes, width) \
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(!((bytes) & ((0x1 << SPI_GET_WIDTH_SHIFT(SPI_GET_WIDTH_TYPE(width))) - 1)))
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/* (16 * 32 + 9 * delay * 1000000)/baudrate == us */
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#define SPI_READ_FIFO_TIMEOUT_MAX(f_delay, s_delay, e_delay, baudrate) \
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((((f_delay) + (s_delay) + (e_delay)) * 9 + \
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SPI_DATA_WIDTH_MAX * SPI_FIFO_LEN) * \
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1000000 / (baudrate))
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/**
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* @brief spi status return code
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*/
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enum {
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SDRV_SPI_STATUS_MODE_ERROR = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI, 1), /* Spi configuration mode usage mismatch. */
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SDRV_SPI_STATUS_GCMD_NO_SUPPORT = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI, 2), /* Spi IP version is not supported. */
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SDRV_SPI_STATUS_GCMD_TIMEOUT_WRITE = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI, 3), /* Spi first Write CMD wait timeout. */
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SDRV_SPI_STATUS_GCMD_TIMEOUT_FINISH = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI,
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4), /* Spi first write CMD last transfer ended wait timeout. */
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SDRV_SPI_STATUS_SOFT_CS_TIMEOUT =
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SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_SPI,
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5), /* Spi CLK idle level switching wait timeout. */
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SDRV_SPI_STATUS_UCMD_TIMEOUT_WRITE = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI,
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6), /* Spi Write CMD wait timeout(Not the first time). */
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SDRV_SPI_STATUS_UCMD_TIMEOUT_FINISH = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI,
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7), /* Spi last transfer ended wait timeout.(Not the first time) */
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SDRV_SPI_STATUS_SYNC_TIMEOUT = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI, 8), /* Spi Synchronous transfer timeout. */
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SDRV_SPI_STATUS_SOFT_CS_WAIT_TIMEOUT = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI,
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9), /* Spi Synchronous transfer(Tx only) wait clk ended timeout. */
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SDRV_SPI_STATUS_FAIL_DMA_SETUP = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI, 10), /* Spi dma configuration failed. */
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SDRV_SPI_STATUS_FAIL_IRQ_SETUP = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI, 11), /* Spi irq configuration failed. */
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SDRV_SPI_STATUS_PARAM_ILLEGAL = SDRV_ERROR_STATUS(
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SDRV_STATUS_GROUP_SPI, 12), /* Spi user params error.*/
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};
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/**
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* @brief Initialize the SPI module.
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*
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* @param[in] spi SPI bus
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* @param[in] cfg SPI device configuration.
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*
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* @note SPI device configuration memory must not be recycled during transfer.
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* @return 0 is ok, otherwise bus error occurred.
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*/
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int sdrv_spi_init(struct sdrv_spi *spi, struct spi_common_config *cfg);
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/**
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* @brief Deinitialize the SPI device.
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*
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* @param[in] bus SPI bus
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*
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* @return 0 is ok, otherwise bus error occurred.
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*/
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int sdrv_spi_deinit(struct sdrv_spi *bus);
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/**
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* @brief SPI device configuration.
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*
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* This function select and activate an external device. Data transfers are
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* performed according to this device configuration.
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*
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* @param[in] spi SPI bus
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* @param[in] cfg SPI device configuration.
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*
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* @note SPI device configuration memory must not be recycled during
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* transfer.
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* @return 0 is ok, and other values mean bus is busy.
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*/
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int sdrv_spi_config_device(struct sdrv_spi *spi,
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const struct spi_device_config *cfg);
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/**
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* @brief SPI sync transmit.
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*
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* @param[in] spi SPI bus.
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* @param[in] tx_buf Pointer to data to transmit, which must be aligned with the
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* corresponding data width, otherwise unaligned access will occur and cause an
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* exception.
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* @param[out] rx_buf Pointer to receive data storage, which must be aligned
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* with the corresponding data width, otherwise unaligned access will occur and
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* cause an exception.
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* @param[in] bytes The amount of data in bytes.
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* @param[in] timeout Timeout time >= total transmitted bytes / data-width*2.
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* @return 0 is ok, and other values for error.
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*/
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int sdrv_spi_sync_transmit(struct sdrv_spi *spi, void *tx_buf, void *rx_buf,
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uint32_t bytes, uint32_t timeout);
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/**
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* @brief Setup the async callback handler.
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*
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* @param[in] spi SPI bus
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* @param[in] cb The async callback handler.
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*/
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void sdrv_spi_attach_async_callback(struct sdrv_spi *spi, spi_callback_t cb);
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/**
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* @brief SPI async transmit in IRQ or DMA mode.
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*
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* @param[in] spi SPI bus
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* @param[in] tx_buf Pointer to data to transmit, which must be aligned with the
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* corresponding data width, otherwise unaligned access will occur and cause an
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* exception.
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* @param[out] rx_buf Pointer to receive data storage, which must be aligned
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* with the corresponding data width, otherwise unaligned access will occur and
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* cause an exception.
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* @param[in] bytes The amount of data in bytes.
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* @param[in] type OP_MODE_IRQ for IRQ Mode. OP_MODE_DMA for DMA Mode.
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* @return 0 is ok, and other values for error.
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*/
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int sdrv_spi_async_transmit(struct sdrv_spi *spi, void *tx_buf, void *rx_buf,
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uint32_t bytes, enum spi_ops_type type);
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/**
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* @brief Get SPI bus state
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*
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* @param[in] spi SPI bus
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* @return SPI_BUSY: spi bus is busy. SPI_IDLE: spi bus is idle.
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*/
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enum spi_bus_state sdrv_spi_get_status(struct sdrv_spi *spi);
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/**
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* @brief Get SPI bus polling
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*
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* @param spi SPI bus
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* @return None
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*/
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void sdrv_spi_polling(struct sdrv_spi *bus);
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/**
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* @brief Get slave transmit cnt
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*
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* @param[in] spi SPI bus
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* @return uint32: transmited bytes.
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*/
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uint32_t sdrv_spi_slave_get_transmit_len(struct sdrv_spi *bus);
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#ifdef __cplusplus
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}
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#endif
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#endif
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