226 lines
5.9 KiB
C
226 lines
5.9 KiB
C
/**
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* @file sdrv_eth.h
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* @brief SemiDrive ethernet mac driver header file
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*
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* @copyright Copyright (c) 2021 Semidrive Semiconductor.
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* All rights reserved.
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*
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* Revision History:
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* -----------------
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*/
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#ifndef DWC_ETH_QOS_H
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#define DWC_ETH_QOS_H
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#include <stdint.h>
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#include <stdbool.h>
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#include "sdrv_ckgen.h"
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#include "sdrv_rstgen.h"
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#include "netdev.h"
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#include "../source/eth/sdrv_mac_lld.h"
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#include "../source/eth/phy/phy.h"
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#ifndef CONFIG_ETH_RX_DESCRIPTOR_NUM
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#define CONFIG_ETH_RX_DESCRIPTOR_NUM 32
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#endif
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#ifndef CONFIG_ETH_TX_DESCRIPTOR_NUM
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#define CONFIG_ETH_TX_DESCRIPTOR_NUM 32
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#endif
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/* assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
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#define ARCH_DMA_MINALIGN CONFIG_ARCH_CACHE_LINE /* Should be cache line aligned */
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#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
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#define EQOS_DESCRIPTORS_TX CONFIG_ETH_TX_DESCRIPTOR_NUM
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#define EQOS_DESCRIPTORS_RX CONFIG_ETH_RX_DESCRIPTOR_NUM
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#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
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#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
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#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
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#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
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#define EQOS_TX_BUFFER_SIZE (EQOS_DESCRIPTORS_TX * EQOS_MAX_PACKET_SIZE)
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/* If rx api thread safe is guranteed by driver,
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* the two following macros should be defined.
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*/
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#ifndef EQOS_RX_LOCK
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#define EQOS_RX_LOCK(eqos)
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#endif
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#ifndef EQOS_RX_UNLOCK
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#define EQOS_RX_UNLOCK(eqos)
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#endif
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/* If tx api thread safe is guranteed by driver,
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* the two following macros should be defined.
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*/
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#ifndef EQOS_TX_LOCK
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#define EQOS_TX_LOCK(eqos)
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#endif
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#ifndef EQOS_TX_UNLOCK
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#define EQOS_TX_UNLOCK(eqos)
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#endif
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/* DMA descriptor */
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/* DO NOT align this struct to cache line length,
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* because length of this struct is used to caculate
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* DSL bit value of DMA_CH_CONTROL register.
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* Aligning eqos dma descriptors to cache line length
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* is done when allocating descriptors.
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*/
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struct eqos_desc {
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volatile uint32_t des0;
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volatile uint32_t des1;
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volatile uint32_t des2;
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volatile uint32_t des3;
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};
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#define EQOS_DESC3_OWN BIT(31)
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#define EQOS_DESC3_IOC BIT(30)
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#define EQOS_DESC3_FD BIT(29)
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#define EQOS_DESC3_LD BIT(28)
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#define EQOS_DESC3_BUF1V BIT(24)
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typedef enum {
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ETHERNET1_IDX = 0,
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ETHERNET2_IDX,
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} eth_idx_type;
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typedef enum {
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/* Controller Disable */
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ETH_MODE_DOWN = 0,
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/* Controller Enable */
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ETH_MODE_ACTIVE,
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} eth_mode_type;
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typedef enum {
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/* add the MAC address to the filter, meaning allow reception */
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ETH_ADD_TO_FILTER = 0,
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/* remove the MAC address from the filter, meaning reception is blocked in the lower layer */
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ETH_REMOVE_FROM_FILTER,
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} eth_filter_action_type;
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typedef enum {
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ETH_MAC_LAYER_SPEED_100M = 0,
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ETH_MAC_LAYER_SPEED_10G,
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ETH_MAC_LAYER_SPEED_10M,
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ETH_MAC_LAYER_SPEED_1G
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} eth_mac_layer_speed_type;
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typedef enum {
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/* MAC layer interface (data) bandwith class 1Gbit/s (e.g. GMII, RGMII, SGMII, RvGMII, USGMII)*/
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ETH_MAC_LAYER_TYPE_XGMII = 0,
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/* MAC layer interface (data) bandwith class 100Mbit/s (e.g. RMII, RvMII, SMII, RvMII) */
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ETH_MAC_LAYER_TYPE_XMII,
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/* MAC layer interface (data) bandwith class 10Gbit/s */
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ETH_MAC_LAYER_TYPE_XXGMII,
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} eth_mac_layer_type;
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typedef enum {
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LIGHT = 0,
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REDUCED,
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REVERSED,
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SERIAL,
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STANDARD,
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UNIVERSAL_SERIAL
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} eth_mac_layer_sub_type;
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typedef enum {
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ETH_PHY_INTF_SEL_GMII = 0,
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ETH_PHY_INTF_SEL_RGMII,
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ETH_PHY_INTF_SEL_SGMII,
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ETH_PHY_INTF_SEL_TBI,
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ETH_PHY_INTF_SEL_RMII,
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ETH_PHY_INTF_SEL_RTBI,
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ETH_PHY_INTF_SEL_SMII,
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ETH_PHY_INTF_SEL_REVMII,
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ETH_PHY_INTF_SEL_MII,
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} eth_phy_intf_mode_type;
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typedef struct {
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uint32_t base;
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uint32_t irq_num;
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uint32_t mtu;
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uint8_t *mac_addr;
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/* Bus width, unit: bit. */
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uint8_t dma_bus_width;
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/* clock & reset */
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sdrv_ckgen_node_t *tx_clk;
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sdrv_ckgen_node_t *rmii_clk;
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sdrv_ckgen_node_t *phy_ref_clk;
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sdrv_ckgen_node_t *timer_sec_clk;
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sdrv_rstgen_sig_t *rst;
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/* mii interface config */
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eth_phy_intf_mode_type phy_intf_mode;
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void (*set_phy_intf)(uint32_t base,
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eth_phy_intf_mode_type mode);
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/* ipv4 config */
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uint8_t ip[4];
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uint8_t mask[4];
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/* All PHYs connected to this mac */
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phy_dev_t *phy;
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} dwc_eth_config_t;
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struct eqos_priv {
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void *descs;
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int tx_desc_idx, rx_desc_idx;
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unsigned int desc_size;
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/* Channel control register DSL bits. */
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uint32_t dsl;
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void *tx_dma_buf;
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void *rx_dma_buf;
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bool started;
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};
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typedef void (*dma_rx_int_cb_t)(struct net_driver_s *dev);
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typedef struct dwc_eth_dev {
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bool init;
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dwc_eth_config_t *config;
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struct eqos_priv *eqos;
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dma_rx_int_cb_t rx_cb;
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phy_bus_t phy_bus;
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void *(*to_cpu_addr)(void *slave_addr);
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} dwc_eth_dev_t;
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/**
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* @brief Enable rx interrupt.
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*
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* When receive is completed, callback will be executed.
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*
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* @param [in] dev eth device.
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* @param [in] callback receive complete callback.
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*/
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void dwc_eth_enable_dma_rx_int(struct net_driver_s *dev, dma_rx_int_cb_t callback);
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/**
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* @brief try to read rx packet and send the packet to lwip stack.
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* Should be called in thread context.
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* If enable DMA rx interrupt, i.e. poll is false, this function
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* should be called after DMA rx interrupt triggered. DMA rx
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* interrupt will be disabled in ISR, and re-enabled in this
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* function after reading out all rx packets, this is helpful to
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* avoid too much rx interrupt.
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*
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* @param [in] dev eth device
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* @param [in] poll true for polling read, false for interrupt read
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* @return int total length of rx packets or -1 if rx nothing
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*/
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int dwc_eth_rx(struct net_driver_s *dev, bool pool);
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/**
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* @brief Initializes net driver.
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*
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* @param [in] dev eth device.
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* @param [in] cfg Configuration of ethernet.
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* @return int return ERR_OK if initialization can be completed.
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*/
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int dwc_eth_probe(struct net_driver_s *dev, dwc_eth_config_t *cfg);
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#endif
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