776 lines
16 KiB
C
776 lines
16 KiB
C
//*****************************************************************************
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//
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// WARNING: Automatically generated file, don't modify anymore!!!
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//
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// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
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// Software License Agreement
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//
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//*****************************************************************************
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#include <types.h>
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#include <regs_base.h>
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#include <reset_ip.h>
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#include <compiler.h>
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#include <reg.h>
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#include <sdrv_scr.h>
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#include <scr_hw.h>
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#include "udelay/udelay.h"
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/**
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* @brief SAF reset signal id.
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*/
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typedef enum reset_signal_safety {
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RSTSIG_SAF_RSTGEN_AP = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_CORE, 0),
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RSTSIG_SAF_CR5_SAF,
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RSTSIG_SAF_CR5_SP0,
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RSTSIG_SAF_CR5_SP1,
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RSTSIG_SAF_CR5_SX0,
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RSTSIG_SAF_CR5_SX1,
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RSTSIG_SAF_LATENT = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_LATENT, 0),
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RSTSIG_SAF_MISSION0 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 0),
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RSTSIG_SAF_MISSION1,
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RSTSIG_SAF_MISSION2,
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RSTSIG_SAF_MISSION3,
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RSTSIG_SAF_MISSION4,
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RSTSIG_SAF_MISSION5,
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RSTSIG_SAF_MISSION6 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 6),
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RSTSIG_SAF_MISSION8 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 8),
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RSTSIG_SAF_MISSION9 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 9),
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RSTSIG_SAF_CANFD1 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 0),
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RSTSIG_SAF_CANFD2,
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RSTSIG_SAF_CANFD3_4,
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RSTSIG_SAF_CANFD5_8,
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RSTSIG_SAF_CANFD9_16,
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RSTSIG_SAF_CANFD17_24,
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RSTSIG_SAF_XSPI1A = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 10),
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RSTSIG_SAF_XSPI1B,
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RSTSIG_SAF_XSPI2A,
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RSTSIG_SAF_XSPI2B,
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RSTSIG_SAF_DMA_RST0 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 15),
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RSTSIG_SAF_DMA_RST1,
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RSTSIG_SAF_ENET1,
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RSTSIG_SAF_ENET2,
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RSTSIG_SAF_GAMA1 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 21),
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RSTSIG_SAF_AHB_SYNCUP_GAMA1 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 21),
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RSTSIG_SAF_GAMA2,
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RSTSIG_SAF_AHB_SYNCUP_GAMA2 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 22),
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RSTSIG_SAF_VIC1,
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RSTSIG_SAF_VIC2_PORTA,
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RSTSIG_SAF_VIC2_PORTB,
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RSTSIG_SAF_VIC3_PORTA = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 27),
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RSTSIG_SAF_VIC3_PORTB,
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RSTSIG_SAF_XSPI_SLV,
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RSTSIG_SAF_MB,
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RSTSIG_SAF_XTRG,
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RSTSIG_SAF_DEBUG = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_DEBUG, 0),
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} reset_signal_safety_e;
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/**
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* @brief AP reset signal id.
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*/
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typedef enum reset_signal_ap {
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RSTSIG_AP_MISSION0 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 0),
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RSTSIG_AP_MISSION1 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 1),
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RSTSIG_AP_CSI = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 0),
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RSTSIG_AP_DC,
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RSTSIG_AP_G2D,
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RSTSIG_AP_SDRAMC,
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RSTSIG_AP_SACI1,
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RSTSIG_AP_SACI2,//5
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RSTSIG_AP_DMA_AP,
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RSTSIG_AP_SEHC1,
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RSTSIG_AP_SEHC2,
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RSTSIG_AP_USB,
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RSTSIG_AP_SEIP,//10
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RSTSIG_AP_LVDS_SS = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 12),
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RSTSIG_AP_DEBUG = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_DEBUG, 0),
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} reset_signal_ap_e;
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/* SAF rstgen controller */
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sdrv_rstgen_t g_rstgen_saf = {
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.base = APB_RSTGEN_SF_BASE,
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};
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/* AP rstgen controller */
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sdrv_rstgen_t g_rstgen_ap = {
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.base = APB_RSTGEN_AP_BASE,
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};
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/* global reset */
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sdrv_rstgen_glb_t rstctl_glb = {
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.rst_sf_ctl = &g_rstgen_saf,
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.rst_ap_ctl = &g_rstgen_ap,
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};
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/* SAF core */
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sdrv_rstgen_sig_t rstsig_rstgen_ap = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_RSTGEN_AP,
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};
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sdrv_rstgen_sig_t rstsig_cr5_saf = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_CR5_SAF,
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};
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/**
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* @brief SAF latent
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*
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* latent signals will reset automatically after power on.
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*
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* signals in SAF latent:
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* MAC
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* SCR_BOOT
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* EIC_BOOT
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* FUSE_LSP_CMP
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* AHB2APB1
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* AHB2APB2
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* AHB2APB3
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* AHB2APB4
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* APBMUX2
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* APBMUX3
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* APBMUX4
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* IROMC
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* GPIO_SF
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* IOMUXC_SF
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* WDT1
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* WDT2
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* SEM1
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* SEM2
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* VD_SF_DIG
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* IOC
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* ETMR1
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* ETMR2
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* ETMR3
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* ETMR4
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* EPWM1
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* EPWM2
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* EPWM3
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* EPWM4
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* MPC_XSPI1A
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* MPC_XSPI1B
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* PPC_APBMUX2
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* PPC_APBMUX3
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* PPC_APBMUX4
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* PPC_APBMUX1
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* MPC_ROMC
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* XB_SF
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* POR_SF_DIG
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* PT_SNS_SF_DIG
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* APB_MAC_SP_SLV
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* APB_MAC_AP_SLV
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* APB_APBMUX1_SLV
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* MPC_VIC1
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* BTM1
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* BTM2
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* BTM3
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* BTM4
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* BTM5
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* BTM6
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* AAPB_XSPI1A
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* AAPB_XSPI1B
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*/
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sdrv_rstgen_sig_t rstsig_saf_latent = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_LATENT,
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};
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/*
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* @brief SAF mission
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*
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* SAF mission signals will reset automatically after power on.
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*
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*/
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/**
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* @brief SAF mission 0
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*
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* signals in SAF mission 0:
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* FAB_SF
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* IOMUXC_SF
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* SCR_SF
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* SMC
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* MPC_CR5_SF
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* PMU_CORE
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* APB_APBMUX1_MST
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* APB_PMUX2_DEC_SLV
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* APB_PMUX2_DEC_MST
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*/
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sdrv_rstgen_sig_t rstsig_saf_mission0 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_MISSION0,
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};
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/**
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* @brief SAF mission 1
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*
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* signals in mission 1:
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* PLL1
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* PLL2
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* PLL3
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*/
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sdrv_rstgen_sig_t rstsig_saf_mission1 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_MISSION1,
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};
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/**
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* @brief SAF mission 2
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*
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* signals in SAF mission 2:
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* ANA_SF_SADC1
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* ANA_SF_SADC2
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* ANA_SF_SADC3
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* ANA_SF_ACMP1
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* ANA_SF_ACMP2
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* ANA_SF_ACMP3
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* ANA_SF_ACMP4
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*/
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sdrv_rstgen_sig_t rstsig_saf_mission2 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_MISSION2,
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};
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/**
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* @brief SAF mission 3
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*
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* signals in SAF mission 3:
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* APBMUX3
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* APBMUX4
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* IOMUXC_SF_COMP
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* EIC_SF
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* UART1
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* UART2
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* UART3
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* UART4
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* UART5
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* UART6
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* UART7
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* UART8
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* SPI1
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* SPI2
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* SPI3
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* SPI4
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* SPI5
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* SPI6
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* I2C3
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* I2C4
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* I2C5
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* I2C6
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* MPC_XSPI2A
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* MPC_XSPI2B
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* FLEXRAY1
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* FLEXRAY2
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* WDT5
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* WDT6
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* MPC_MB
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* AAPB_XSPI2A
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* AAPB_XSPI2B
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* APB_APBMUX3_SLV
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* APB_APBMUX3_MST
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* APB_APBMUX4_SLV
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* APB_APBMUX4_MST
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* APB_SEIP_NVM_MST
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* APB_SEIP_NVM_SLV
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* ADB_SFAP_SLV
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* ADB_SFAP_MST
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* ADB_APSF_SLV
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* ADB_APSF_MST
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* ADB_DISPSF_SLV
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* ADB_DISPSF_MST
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* BTI_DISPSF
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* BTI_APSF
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*/
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sdrv_rstgen_sig_t rstsig_saf_mission3 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_MISSION3,
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};
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/**
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* @brief SAF mission 4
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*
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* signals in SAF mission 4:
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* IRAMC1
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* IRAMC2
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* IRAMC3
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* IRAM_MUX
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* MPC_IRAMC1
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* MPC_IRAMC2
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* MPC_IRAMC3
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*/
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sdrv_rstgen_sig_t rstsig_saf_mission4 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_MISSION4,
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};
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/**
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* @brief SAF mission 5
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*
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* signals in SAF mission 5:
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* IRAMC4
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* APBMUX5
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* WDT3
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* WDT4
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* PTB
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* FAB_SP
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* MPC_IRAMC4
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* PPC_APBMUX5
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* EIC_SP
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* CSLITE
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* AAHB_SPSF_SLV
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* AAHB_SPSF_MST
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* APB_MAC_SP_SLV
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* APB_MAC_SP_MST
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* ADB_SPAP_SLV
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* ADB_SPAP_MST
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*/
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sdrv_rstgen_sig_t rstsig_saf_mission5 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_MISSION5,
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};
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/**
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* @brief SAF mission 6
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*
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* signals in SAF mission 6:
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* reserved
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*/
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sdrv_rstgen_sig_t rstsig_saf_mission6 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_MISSION6,
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};
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/**
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* @brief SAF mission 8
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*
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* signals in SAF mission 8:
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* LDO_DIG
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* APB_LDO_DIG_MST
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* APB_LDO_DIG_SLV
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*/
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sdrv_rstgen_sig_t rstsig_saf_mission8 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_MISSION8,
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};
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/**
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* @brief SAF mission 9
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*
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* signals in SAF mission 9:
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* DCDC1
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* APB_DCDC1_MST
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* APB_DCDC1_SLV
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*/
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sdrv_rstgen_sig_t rstsig_saf_mission9 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_MISSION9,
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};
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/* SAF module */
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sdrv_rstgen_sig_t rstsig_canfd3_4 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_CANFD3_4,
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};
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sdrv_rstgen_sig_t rstsig_canfd5_8 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_CANFD5_8,
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};
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sdrv_rstgen_sig_t rstsig_canfd9_16 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_CANFD9_16,
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};
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sdrv_rstgen_sig_t rstsig_canfd17_24 = {
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.rst_ctl = &g_rstgen_saf,
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.id = RSTSIG_SAF_CANFD17_24,
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};
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typedef enum reset_xspi_port_id {
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RST_XSPI_1A = 0U,
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RST_XSPI_1B = 1U,
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RST_XSPI_2A = 2U,
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RST_XSPI_2B = 3U,
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RST_XSPI_NUM = 4U,
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} reset_xspi_port_id_e;
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static sdrv_scr_t scr_ctrl = {
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.base = APB_SCR_SF_BASE,
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};
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static uint32_t xspi_base[RST_XSPI_NUM] = {
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APB_XSPI1PORTA_BASE,
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APB_XSPI1PORTB_BASE,
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APB_XSPI2PORTA_BASE,
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APB_XSPI2PORTB_BASE,
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};
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static scr_signal_t sig_xspi_scr[RST_XSPI_NUM][4] = {
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{
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SCR_SF_AAPB_XSPI1A_SRC_IRQ_ENB,
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SCR_SF_AAPB_XSPI1A_SRC_UNCERR_CLR,
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SCR_SF_AAPB_XSPI1A_DST_IRQ_ENB,
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SCR_SF_AAPB_XSPI1A_DST_UNCERR_CLR,
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},
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{
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SCR_SF_AAPB_XSPI1B_SRC_IRQ_ENB,
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SCR_SF_AAPB_XSPI1B_SRC_UNCERR_CLR,
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SCR_SF_AAPB_XSPI1B_DST_IRQ_ENB,
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SCR_SF_AAPB_XSPI1B_DST_UNCERR_CLR,
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},
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{
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SCR_SF_AAPB_XSPI2A_SRC_IRQ_ENB,
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SCR_SF_AAPB_XSPI2A_SRC_UNCERR_CLR,
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SCR_SF_AAPB_XSPI2A_DST_IRQ_ENB,
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SCR_SF_AAPB_XSPI2A_DST_UNCERR_CLR,
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},
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{
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SCR_SF_AAPB_XSPI2B_SRC_IRQ_ENB,
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SCR_SF_AAPB_XSPI2B_SRC_UNCERR_CLR,
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SCR_SF_AAPB_XSPI2B_DST_IRQ_ENB,
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SCR_SF_AAPB_XSPI2B_DST_UNCERR_CLR,
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},
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};
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/* clear XSPI sem error */
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static void rstsig_xspi_pre_handler(uint32_t rstgen_sig_id)
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{
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uint32_t xspi_id = RST_XSPI_1A;
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if (rstgen_sig_id == RSTSIG_SAF_XSPI1A) {
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xspi_id = RST_XSPI_1A;
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}
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else if (rstgen_sig_id == RSTSIG_SAF_XSPI1B) {
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xspi_id = RST_XSPI_1B;
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}
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else if (rstgen_sig_id == RSTSIG_SAF_XSPI2A) {
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xspi_id = RST_XSPI_2A;
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}
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else if (rstgen_sig_id == RSTSIG_SAF_XSPI2B) {
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xspi_id = RST_XSPI_2B;
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}
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else {
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return;
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}
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][0], 0U);
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scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][2], 0U);
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(void)readl(xspi_base[xspi_id]);
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};
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static void rstsig_xspi_post_handler(uint32_t rstgen_sig_id)
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{
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uint32_t xspi_id = RST_XSPI_1A;
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if (rstgen_sig_id == RSTSIG_SAF_XSPI1A) {
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xspi_id = RST_XSPI_1A;
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}
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else if (rstgen_sig_id == RSTSIG_SAF_XSPI1B) {
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xspi_id = RST_XSPI_1B;
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}
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else if (rstgen_sig_id == RSTSIG_SAF_XSPI2A) {
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xspi_id = RST_XSPI_2A;
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}
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else if (rstgen_sig_id == RSTSIG_SAF_XSPI2B) {
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xspi_id = RST_XSPI_2B;
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}
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else {
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return;
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}
|
|
|
|
udelay(10);
|
|
(void)readl(xspi_base[xspi_id]);
|
|
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][1], 1U);
|
|
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][1], 0U);
|
|
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][3], 1U);
|
|
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][3], 0U);
|
|
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][0], 1U);
|
|
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][2], 1U);
|
|
}
|
|
|
|
sdrv_rstgen_sig_t rstsig_xspi1a = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_XSPI1A,
|
|
.pre_handler = rstsig_xspi_pre_handler,
|
|
.post_handler = rstsig_xspi_post_handler,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_xspi1b = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_XSPI1B,
|
|
.pre_handler = rstsig_xspi_pre_handler,
|
|
.post_handler = rstsig_xspi_post_handler,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_xspi2a = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_XSPI2A,
|
|
.pre_handler = rstsig_xspi_pre_handler,
|
|
.post_handler = rstsig_xspi_post_handler,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_xspi2b = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_XSPI2B,
|
|
.pre_handler = rstsig_xspi_pre_handler,
|
|
.post_handler = rstsig_xspi_post_handler,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_dma_rst0 = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_DMA_RST0,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_dma_rst1 = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_DMA_RST1,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_enet1 = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_ENET1,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_enet2 = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_ENET2,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_vic1 = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_VIC1,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_vic2_porta = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_VIC2_PORTA,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_vic2_portb = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_VIC2_PORTB,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_vic3_porta = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_VIC3_PORTA,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_vic3_portb = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_VIC3_PORTB,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_xspi_slv = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_XSPI_SLV,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_mb = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_MB,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_xtrg = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_XTRG,
|
|
};
|
|
|
|
/*
|
|
* @brief AP mission
|
|
*
|
|
* AP mission signals will reset automatically after power on.
|
|
*
|
|
*/
|
|
|
|
/**
|
|
* @brief AP mision 0
|
|
*
|
|
* signals in AP mission 0:
|
|
* PLL4
|
|
* PLL5
|
|
* PLL_LVDS
|
|
*/
|
|
sdrv_rstgen_sig_t rstsig_ap_mission0 = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_MISSION0,
|
|
};
|
|
|
|
/**
|
|
* @brief AP mision 1
|
|
*
|
|
* signals in AP mission 1:
|
|
* APBMUX7
|
|
* DISP_MUX
|
|
* FAB_AP
|
|
* VD_AP
|
|
* APBMUX6
|
|
* GPIO_AP
|
|
* IOMUXC_AP
|
|
* WDT8
|
|
* MPC_SEIP
|
|
* MPC_SDRAMC
|
|
* PPC_APBMUX6
|
|
* PPC_APBMUX7
|
|
* FAB_DISP
|
|
* AHBDEC_SEIP
|
|
* PT_SNS_AP
|
|
* POR_AP
|
|
* SCR_AP
|
|
* RSTGEN_AP
|
|
* APB_MAC_AP_SLV
|
|
* APB_MAC_AP_MST
|
|
* APB_APBMUX7_SLV
|
|
* APB_APBMUX7_MST
|
|
* APB_SEC_STORAGE1_SLV
|
|
* APB_SEC_STORAGE1_MST
|
|
* APB_SEIP_NVM_MST
|
|
* APB_SEIP_NVM_SLV
|
|
* ADB_SPAP_SLV
|
|
* ADB_SPAP_MST
|
|
* ADB_SFAP_SLV
|
|
* ADB_SFAP_MST
|
|
* ADB_APSF_SLV
|
|
* ADB_APSF_MST
|
|
* ADB_DISPSF_SLV
|
|
* ADB_DISPSF_MST
|
|
* BTI_DISPSF
|
|
* BTI_APSF
|
|
*/
|
|
sdrv_rstgen_sig_t rstsig_ap_mission1 = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_MISSION1,
|
|
};
|
|
|
|
/* AP module */
|
|
sdrv_rstgen_sig_t rstsig_csi = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_CSI,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_dc = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_DC,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_g2d = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_G2D,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_sdramc = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_SDRAMC,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_saci1 = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_SACI1,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_saci2 = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_SACI2,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_dma_ap = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_DMA_AP,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_sehc1 = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_SEHC1,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_sehc2 = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_SEHC2,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_usb = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_USB,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_seip = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_SEIP,
|
|
.need_clr_rst = true,
|
|
};
|
|
|
|
sdrv_rstgen_sig_t rstsig_lvds_ss = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_LVDS_SS,
|
|
};
|
|
|
|
/* SAF debug */
|
|
sdrv_rstgen_sig_t rstsig_saf_debug = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = RSTSIG_SAF_DEBUG,
|
|
};
|
|
|
|
/* AP debug */
|
|
sdrv_rstgen_sig_t rstsig_ap_debug = {
|
|
.rst_ctl = &g_rstgen_ap,
|
|
.id = RSTSIG_AP_DEBUG,
|
|
};
|
|
|
|
/* general register */
|
|
sdrv_rstgen_general_reg_t reset_general_reg_sf_remap = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = 1,
|
|
};
|
|
|
|
sdrv_rstgen_general_reg_t reset_general_reg_sf_boot = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = 7,
|
|
};
|
|
|
|
sdrv_rstgen_general_reg_t reset_general_reg_rom_ctrl = {
|
|
.rst_ctl = &g_rstgen_saf,
|
|
.id = 0,
|
|
};
|
|
|
|
/* recovery module */
|
|
__WEAK sdrv_recovery_btm_t recovery_btm_list = {
|
|
.btm_num = 6,
|
|
.btm_base = {
|
|
APB_BTM1_BASE,
|
|
APB_BTM2_BASE,
|
|
APB_BTM3_BASE,
|
|
APB_BTM4_BASE,
|
|
APB_BTM5_BASE,
|
|
APB_BTM6_BASE,
|
|
},
|
|
};
|
|
|
|
__WEAK sdrv_recovery_etimer_t recovery_etimer_list = {
|
|
.etimer_num = 4,
|
|
.etimer_base = {
|
|
APB_ETMR1_BASE,
|
|
APB_ETMR2_BASE,
|
|
APB_ETMR3_BASE,
|
|
APB_ETMR4_BASE,
|
|
},
|
|
};
|
|
|
|
__WEAK sdrv_recovery_epwm_t recovery_epwm_list = {
|
|
.epwm_num = 4,
|
|
.epwm_base = {
|
|
APB_EPWM1_BASE,
|
|
APB_EPWM2_BASE,
|
|
APB_EPWM3_BASE,
|
|
APB_EPWM4_BASE,
|
|
},
|
|
};
|
|
|
|
__WEAK sdrv_recovery_module_t recovery_module_array = {
|
|
.btm_list = &recovery_btm_list,
|
|
.etimer_list = &recovery_etimer_list,
|
|
.epwm_list = &recovery_epwm_list,
|
|
};
|