232 lines
6.5 KiB
JSON
232 lines
6.5 KiB
JSON
{
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"tag": "0x53465301",
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"init_act_t": [{
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"header": "(((0x1) << 6) | ((0) << 3) | ((0) << 0))",
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"command": 6,
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"addr": "0x0",
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"data0": 0,
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"data1": 0
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},
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{
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"header": "(((0x1) << 6) | ((0x0) << 3) | ((0x1) << 0))",
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"command": "0xc0",
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"addr": "0x0",
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"data0": "0x50",
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"data1": "0"
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},
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{
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"header": "(((0x1) << 6) | ((0) << 3) | ((0) << 0))",
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"command": "0x35",
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"addr": "0x0",
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"data0": "0x0",
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"data1": 0
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}
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],
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"xfer_attr_t": {
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"cmd": "0xEB",
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"cinst_type": 2,
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"caddr_type": 2,
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"cdata_type": 2,
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"caddr_size": 3,
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"cmode": 0,
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"cdummy_size": 10,
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"cflag": "0x0",
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"rsvd": [0, 0, 0, 0, 0, 0, 0, 0]
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},
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"ip_settings_t": {
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"flags": "0x0",
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"rx_delay": "0xf",
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"kunlun": "+++",
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"tx_delay": 0,
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"csda": 0,
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"csdada": 0,
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"cseot": 0,
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"cssot": 0,
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"min_rx_win": 0,
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"rx_training_step": 0,
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"kunlun": "---",
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"ctrl_misc": 0,
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"rsvd": [0, 0, 0, 0, 0]
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},
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"freq": 3,
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"sw_reset_info": 36,
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"training_pattern": ["0x5a", "0xa5", "0xf0", "0x0f", "0x0f", "0xf0", "0xa5", "0x5a"],
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"_comments": {
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"init_act_t": {
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"des": "INIT_ACT array, Initialization action array which includes 10 INIT_ACT at most.",
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"size": "6*10 bytes, below is valid defined",
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"header": "(((act_type) << 6) | ((a_sz) << 3) | ((d_sz) << 0))",
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"command": "1byte",
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"addr": "2bytes",
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"data0": "1byte",
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"data1": "1byte",
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"act_type": {
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"REG_WR(0x01)": "ACT_REG_WR(cmd, a_sz, d_sz, a, d) : (ACT_HDR(1, a_sz, d_sz), cmd, a, (d)&0xff, ((d)>>8)&0xff)); e.g. ACT_REG_WR(0x81, 3, 1, 0, 0xe7)",
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"REG_POLL(0x02)": "ACT_REG_POLL(cmd, bit, v) : (ACT_HDR(2, 0, 1), cmd, 0, bit, v); e.g. ACT_REG_POLL(0x05, 0, 0)",
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"CTL_SYNC(0x03)": "ACT_SYNC(io, edge) : (ACT_HDR(3, 0, 0), 0, 0, io, edge); e.g. ACT_SYNC(2, 0)"
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}
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},
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"xfer_attr_t": {
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"des": "Read XFER Configuration",
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"size": "16 bytes",
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"cmd": {
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"des": "The command code for read",
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"size": "1byte"
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},
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"cinst_type": {
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"des": "IO type of CMD",
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"size": "1byte, below is valid data",
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"0": "Single IO",
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"1": "Dual IO",
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"2": "Quad IO",
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"3": "Octal IO"
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},
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"caddr_type": {
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"des": "IO type of Adress",
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"size": "1byte, below is valid data",
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"0": "Single IO",
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"1": "Dual IO",
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"2": "Quad IO",
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"3": "Octal IO"
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},
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"cdata_type": {
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"des": "IO type of Data",
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"size": "1byte, below is valid data",
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"0": "Single IO",
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"1": "Dual IO",
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"2": "Quad IO",
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"3": "Octal IO"
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},
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"caddr_size": {
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"des": "Address size",
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"size": "1byte, below is valid data",
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"3": "3bytes addressing",
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"4": "4bytes addressing"
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},
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"cmode": {
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"des": "Mode, The Mode value to be sent, Valid only if MODE_VALID set in Flag",
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"size": "1byte"
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},
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"cdummy_size": {
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"des": "Dummy size, The number of the dummy cycles",
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"size": "1byte"
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},
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"cflag": {
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"des": "Flag",
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"size": "1byte, below is valid defined",
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"Bit0": "DDR, indicating this read xfer is in DDR mode",
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"Bit1": "DQS, indicating this read xfer shall use DQS",
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"Bit2": "DTR, indicating this read xfer is in DTR(Double Data Rate) protocol",
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"Bit3": "DUAL_OPCODE_INV",
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"Bit4": "Data Flip",
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"Bit5": "MODE_VALID",
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"Bit6": "ECC_EN,For safety ROM only,If set, Rom code setup ECC_FAIL pad and enbale ECC_FAIL IRQ",
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"Bit7": "CRC_EN,For safety ROM only,If set, Rom code enables CRC feature of OSPI controller and also enable RX_CRC_MASK_IRQ"
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},
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"rsvd": {
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"des": "Reserved",
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"size": "8bytes, Shall be 0"
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}
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},
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"ip_settings_t": {
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"des": "IP(XSPI controller) specific settings",
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"size": "16 bytes",
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"flags": {
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"des": "IPS_FLAG",
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"size": "2bytes, below is valid defined",
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"taishan": {
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"Bit0": "IPS_LPBK,If set, SCLK loopback is desired as sample clock",
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"Bit5": "IPS_RX_DLL_BYPASS,map to (RX DLL Bypass bit) of PHY_CONFIGURATION register"
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},
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"kunlun": {
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"Bit0": "IPS_LPBK",
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"Bit1": "IPS_DLL_BYPASS_MODE",
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"Bit2": "IPS_TAPMODE",
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"Bit3": "IPS_PHY_TRAINING",
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"Bit4": "IPS_PHY_FIFO_POP_DELAY",
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"Bit5": "IPS_RX_DLL_BYPASS",
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"Bit10-8": "IPS_PHY_DLL_PHASE_DETECT_SEL Map to bit[22:20] of register PHY_DLL_MASTER_CONTROL register, Valid for phy mode only",
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"Bit14": "IPS_DEVDLY_VALID",
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"Bit15": "IPS_RXTX_DELAY_VALID. indicating RX delay and TX delay are valid"
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}
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},
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"rx_delay": {
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"des": "RX delay, if non-zero, used to override DLL_CTRL and DLL1_CTRL SLV_TARGET",
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"size": "1byte"
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},
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"kunlun": {
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"tx_delay": {
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"des": "TX delay, Valid if IPS_RXTX_DELAY_VALID set",
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"size": "1byte"
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},
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"csda": {
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"des": "CSDA, Mapped to OSPI device delay register CSDA field,Valid if IPS_DEVDLY_VALID set",
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"size": "1byte"
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},
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"csdada": {
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"des": "CSDADA, Mapped to OSPI device delay register CSDADA field,Valid if IPS_DEVDLY_VALID set",
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"size": "1byte"
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},
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"cseot": {
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"des": "CSEOT, Mapped to OSPI device delay register CSEOT field,Valid if IPS_DEVDLY_VALID set",
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"size": "1byte"
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},
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"cssot": {
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"des": "CSSOT, Mapped to OSPI device delay register CSSOT field,Valid if IPS_DEVDLY_VALID set",
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"size": "1byte"
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},
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"min_rx_win": {
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"des": "Mininum RX Delay valid window size for PHY training",
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"size": "1byte"
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},
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"rx_training_step": {
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"des": "RX DLY Training Step, The step used for phy training, Shall <=4, if 0, ROM set traning step as 1",
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"size": "1byte"
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}
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},
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"ctrl_misc": {
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"des": "Valid if LPS_LPBK of IPS_FLAG set",
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"size": "1byte",
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"0": "SCLK loopback",
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"2": "DQS loopback"
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},
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"rsvd": {
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"des": "Reserved",
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"size": "5byte, Shall be 0"
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}
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},
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"freq": {
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"des": "Freq, The SCLK frequency desired",
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"size": "1byte, below is valid data",
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"taishan": {
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"0": "Freq0,25MHz on Taishan",
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"1": "Freq1,50MHz on Taishan",
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"2": "Freq2,66MHz on Taishan",
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"3": "Freq3,100MHz on Taishan",
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"4": "Freq4,125MHz on Taishan"
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},
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"kunlun": {
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"0": "Freq0,25MHz",
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"1": "Freq1,50MHz",
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"2": "Freq2,100MHz",
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"3": "Freq3,133MHz"
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}
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},
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"reserved": "reserved 6 bytes",
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"sw_reset_info": "1byte, if valid, Boot ROM write this value info Boot ROM Flag resgister and Boot ROM will issue SW reset to NOR flash if (HW reset) fuse was not blown",
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"training_pattern": "8bytes, 0x5AA5F00F_0FF0A55A is recommended",
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"normal_iamge_addr": "4bytes, shall be 4KB aligned",
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"backup_image_addr": "4bytes, shall be 4KB aligned",
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"third_image_addr": "4bytes, shall be 4KB aligned, just for taishan",
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"crc": "4bytes, bytes, automatic calculation"
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}
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}
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