//***************************************************************************** // // WARNING: Automatically generated file, don't modify anymore!!! // // Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved. // Software License Agreement // //***************************************************************************** #ifndef IRQ_NUM_H #define IRQ_NUM_H #define MB_MU_MESSAGE_READY_INTR_NUM 0 #define MB_MU_WAKEUP_INTR_NUM 1 #define MB_SEMAPHORE_LOCK_FAIL_INTR_NUM 2 #define MB_SEMAPHORE_LOCK_STATUS_CHANGE_INTR_NUM 3 #define GPIO_SF_SYNC_DGPIO_INTR_NUM 4 #define GPIO_SF_ASYNC_DGPIO_INTR_NUM 4 #define GPIO_SF_SYNC_GRP_0_INTR_NUM 5 #define GPIO_SF_ASYNC_GRP_0_INTR_NUM 5 #define GPIO_SF_SYNC_GRP_1_INTR_NUM 6 #define GPIO_SF_ASYNC_GRP_1_INTR_NUM 6 #define GPIO_SF_SYNC_GRP_2_INTR_NUM 7 #define GPIO_SF_ASYNC_GRP_2_INTR_NUM 7 #define GPIO_SF_SYNC_GRP_3_INTR_NUM 8 #define GPIO_SF_ASYNC_GRP_3_INTR_NUM 8 #define GPIO_SF_SYNC_GRP_4_INTR_NUM 9 #define GPIO_SF_ASYNC_GRP_4_INTR_NUM 9 #define CR5_SF_NPMUIRQ0_INTR_NUM 10 #define GPIO_AP_SYNC_DGPIO_INTR_NUM 11 #define GPIO_AP_ASYNC_DGPIO_INTR_NUM 11 #define GPIO_AP_SYNC_GRP_0_INTR_NUM 12 #define GPIO_AP_ASYNC_GRP_0_INTR_NUM 12 #define GPIO_AP_SYNC_GRP_1_INTR_NUM 13 #define GPIO_AP_ASYNC_GRP_1_INTR_NUM 13 #define GPIO_AP_SYNC_GRP_2_INTR_NUM 14 #define GPIO_AP_ASYNC_GRP_2_INTR_NUM 14 #define SMC_SMC_WAKEUP_0_INTR_NUM 15 #define WDT1_WDT_INTR_NUM 16 #define WDT2_WDT_INTR_NUM 17 #define WDT3_WDT_INTR_NUM 18 #define WDT4_WDT_INTR_NUM 19 #define WDT5_WDT_INTR_NUM 20 #define WDT6_WDT_INTR_NUM 21 #define WDT8_WDT_INTR_NUM 22 #define DMA_SF_DMA0_CH_0_INTR_NUM 23 #define DMA_SF_DMA0_CH_1_INTR_NUM 24 #define DMA_SF_DMA0_CH_2_INTR_NUM 25 #define DMA_SF_DMA0_CH_3_INTR_NUM 26 #define DMA_SF_DMA0_CH_4_INTR_NUM 27 #define DMA_SF_DMA0_CH_5_INTR_NUM 28 #define DMA_SF_DMA0_CH_6_INTR_NUM 29 #define DMA_SF_DMA0_CH_7_INTR_NUM 30 #define DMA_SF_DMA0_CH_8_INTR_NUM 31 #define DMA_SF_DMA0_CH_9_INTR_NUM 32 #define DMA_SF_DMA0_CH_10_INTR_NUM 33 #define DMA_SF_DMA0_CH_11_INTR_NUM 34 #define DMA_SF_DMA0_CH_12_INTR_NUM 35 #define DMA_SF_DMA0_CH_13_INTR_NUM 36 #define DMA_SF_DMA0_CH_14_INTR_NUM 37 #define DMA_SF_DMA0_CH_15_INTR_NUM 38 #define DMA_SF_DMA0_CH_16_INTR_NUM 39 #define DMA_SF_DMA0_CH_17_INTR_NUM 40 #define DMA_SF_DMA0_CH_18_INTR_NUM 41 #define DMA_SF_DMA0_CH_19_INTR_NUM 42 #define DMA_SF_DMA0_CH_20_INTR_NUM 43 #define DMA_SF_DMA0_CH_21_INTR_NUM 44 #define DMA_SF_DMA0_CH_22_INTR_NUM 45 #define DMA_SF_DMA0_CH_23_INTR_NUM 46 #define DMA_SF_DMA0_INTR_NUM 47 #define DMA_SF_DMA1_CH_0_INTR_NUM 48 #define DMA_SF_DMA1_CH_1_INTR_NUM 49 #define DMA_SF_DMA1_CH_2_INTR_NUM 50 #define DMA_SF_DMA1_CH_3_INTR_NUM 51 #define DMA_SF_DMA1_CH_4_INTR_NUM 52 #define DMA_SF_DMA1_CH_5_INTR_NUM 53 #define DMA_SF_DMA1_CH_6_INTR_NUM 54 #define DMA_SF_DMA1_CH_7_INTR_NUM 55 #define DMA_SF_DMA1_CH_8_INTR_NUM 56 #define DMA_SF_DMA1_CH_9_INTR_NUM 57 #define DMA_SF_DMA1_CH_10_INTR_NUM 58 #define DMA_SF_DMA1_CH_11_INTR_NUM 59 #define DMA_SF_DMA1_CH_12_INTR_NUM 60 #define DMA_SF_DMA1_CH_13_INTR_NUM 61 #define DMA_SF_DMA1_CH_14_INTR_NUM 62 #define DMA_SF_DMA1_CH_15_INTR_NUM 63 #define DMA_SF_DMA1_CH_16_INTR_NUM 64 #define DMA_SF_DMA1_CH_17_INTR_NUM 65 #define DMA_SF_DMA1_CH_18_INTR_NUM 66 #define DMA_SF_DMA1_CH_19_INTR_NUM 67 #define DMA_SF_DMA1_CH_20_INTR_NUM 68 #define DMA_SF_DMA1_CH_21_INTR_NUM 69 #define DMA_SF_DMA1_CH_22_INTR_NUM 70 #define DMA_SF_DMA1_CH_23_INTR_NUM 71 #define DMA_SF_DMA1_INTR_NUM 72 #define DMA_AP_DMA_CH_0_INTR_NUM 73 #define DMA_AP_DMA_CH_1_INTR_NUM 74 #define DMA_AP_DMA_CH_2_INTR_NUM 75 #define DMA_AP_DMA_CH_3_INTR_NUM 76 #define DMA_AP_DMA_CH_4_INTR_NUM 77 #define DMA_AP_DMA_CH_5_INTR_NUM 78 #define DMA_AP_DMA_CH_6_INTR_NUM 79 #define DMA_AP_DMA_CH_7_INTR_NUM 80 #define DMA_AP_DMA_INTR_NUM 81 #define DMA_AP_DMA_AP_UNCERR_INTR_NUM 82 #define SEM1_O_SEM_CPU_INTR_NUM 84 #define SEM2_O_SEM_CPU_INTR_NUM 85 #define UART1_INTR_NUM 86 #define UART2_INTR_NUM 87 #define UART3_INTR_NUM 88 #define UART4_INTR_NUM 89 #define UART5_INTR_NUM 90 #define UART6_INTR_NUM 91 #define UART7_INTR_NUM 92 #define UART8_INTR_NUM 93 #define UART9_INTR_NUM 94 #define UART10_INTR_NUM 95 #define UART11_INTR_NUM 96 #define UART12_INTR_NUM 97 #define UART13_INTR_NUM 98 #define UART14_INTR_NUM 99 #define UART15_INTR_NUM 100 #define UART16_INTR_NUM 101 #define I2C1_INTR_NUM 102 #define I2C2_INTR_NUM 103 #define I2C3_INTR_NUM 104 #define I2C4_INTR_NUM 105 #define I2C5_INTR_NUM 106 #define I2C6_INTR_NUM 107 #define I2C7_INTR_NUM 108 #define I2C8_INTR_NUM 109 #define SPI1_SPI_INTR_NUM 110 #define SPI2_SPI_INTR_NUM 111 #define SPI3_SPI_INTR_NUM 112 #define SPI4_SPI_INTR_NUM 113 #define SPI5_SPI_INTR_NUM 114 #define SPI6_SPI_INTR_NUM 115 #define SPI7_SPI_INTR_NUM 116 #define SPI8_SPI_INTR_NUM 117 #define XSPI1_IRQ0_INTR_NUM 118 #define XSPI1_IRQ1_INTR_NUM 119 #define XSPI2_IRQ0_INTR_NUM 120 #define XSPI2_IRQ1_INTR_NUM 121 #define XSPI_SLV_INTR_NUM 122 #define SACI1_I2S_INTR_NUM 123 #define SACI1_PDM_INTR_NUM 124 #define SACI2_I2S_INTR_NUM 125 #define SACI2_PDM_INTR_NUM 126 #define USB_INTR_NUM 127 #define ENET1_SBD_INTR_NUM 128 #define ENET1_SBD_PERCH_TX_O0_INTR_NUM 129 #define ENET1_SBD_PERCH_TX_O1_INTR_NUM 129 #define ENET1_SBD_PERCH_TX_O2_INTR_NUM 129 #define ENET1_SBD_PERCH_TX_O3_INTR_NUM 129 #define ENET1_SBD_PERCH_TX_O4_INTR_NUM 129 #define ENET1_SBD_PERCH_RX_O0_INTR_NUM 129 #define ENET1_SBD_PERCH_RX_O1_INTR_NUM 129 #define ENET1_SBD_PERCH_RX_O2_INTR_NUM 129 #define ENET1_SBD_PERCH_RX_O3_INTR_NUM 129 #define ENET1_SBD_PERCH_RX_O4_INTR_NUM 129 #define ENET1_LPI_INTR_NUM 130 #define ENET1_PMT_INTR_NUM 130 #define ENET2_SBD_INTR_NUM 131 #define ENET2_SBD_PERCH_TX_O0_INTR_NUM 132 #define ENET2_SBD_PERCH_TX_O1_INTR_NUM 132 #define ENET2_SBD_PERCH_TX_O2_INTR_NUM 132 #define ENET2_SBD_PERCH_TX_O3_INTR_NUM 132 #define ENET2_SBD_PERCH_TX_O4_INTR_NUM 132 #define ENET2_SBD_PERCH_RX_O0_INTR_NUM 132 #define ENET2_SBD_PERCH_RX_O1_INTR_NUM 132 #define ENET2_SBD_PERCH_RX_O2_INTR_NUM 132 #define ENET2_SBD_PERCH_RX_O3_INTR_NUM 132 #define ENET2_SBD_PERCH_RX_O4_INTR_NUM 132 #define ENET2_LPI_INTR_NUM 133 #define ENET2_PMT_INTR_NUM 133 #define SEHC1_SEHC_INTR_NUM 136 #define SEHC1_SEHC_WAKEUP_INTR_NUM 137 #define SEHC2_SEHC_INTR_NUM 138 #define SEHC2_SEHC_WAKEUP_INTR_NUM 139 #define CANFD3_CANFD_INTR_NUM 146 #define CANFD4_CANFD_INTR_NUM 147 #define CANFD5_CANFD_INTR_NUM 148 #define CANFD6_CANFD_INTR_NUM 149 #define CANFD7_CANFD_INTR_NUM 150 #define CANFD8_CANFD_INTR_NUM 151 #define CANFD9_CANFD_INTR_NUM 152 #define CANFD10_CANFD_INTR_NUM 153 #define CANFD11_CANFD_INTR_NUM 154 #define CANFD12_CANFD_INTR_NUM 155 #define CANFD13_CANFD_INTR_NUM 156 #define CANFD14_CANFD_INTR_NUM 157 #define CANFD15_CANFD_INTR_NUM 158 #define CANFD16_CANFD_INTR_NUM 159 #define CANFD21_CANFD_INTR_NUM 164 #define CANFD23_CANFD_INTR_NUM 166 #define FLEXRAY1_IPI_GLOB_INTR_NUM 168 #define FLEXRAY1_IPI_RXB_INTR_NUM 169 #define FLEXRAY1_IPI_TXB_INTR_NUM 170 #define FLEXRAY1_IPI_CHI_INTR_NUM 171 #define FLEXRAY1_IPI_PE_INTR_NUM 171 #define FLEXRAY1_IPI_WU_INTR_NUM 172 #define FLEXRAY1_IPI_FIFO_A_NE_INTR_NUM 173 #define FLEXRAY1_IPI_FIFO_B_NE_INTR_NUM 174 #define FLEXRAY2_IPI_GLOB_INTR_NUM 175 #define FLEXRAY2_IPI_RXB_INTR_NUM 176 #define FLEXRAY2_IPI_TXB_INTR_NUM 177 #define FLEXRAY2_IPI_CHI_INTR_NUM 178 #define FLEXRAY2_IPI_PE_INTR_NUM 178 #define FLEXRAY2_IPI_WU_INTR_NUM 179 #define FLEXRAY2_IPI_FIFO_A_NE_INTR_NUM 180 #define FLEXRAY2_IPI_FIFO_B_NE_INTR_NUM 181 #define SEIP_PKE_INTR_NUM 182 #define SEIP_SKE_INTR_NUM 183 #define SEIP_HASH_INTR_NUM 184 #define SEIP_TRNG_INTR_NUM 185 #define SEIP_KEY_CHK_INTR_NUM 186 #define SEIP_SOC_INTR_NUM 187 #define SEIP_UART_INTR_NUM 188 #define SEIP_SENSOR_INTR_NUM 189 #define SEIP_O_INTR_SE2SOC_MBOX_INTR_NUM 190 #define SEIP_SEIP_ERR_INTR_NUM 191 #define BTM1_O_BTM_INTR_NUM 193 #define BTM2_O_BTM_INTR_NUM 194 #define BTM3_O_BTM_INTR_NUM 195 #define BTM4_O_BTM_INTR_NUM 196 #define BTM5_O_BTM_INTR_NUM 197 #define BTM6_O_BTM_INTR_NUM 198 #define ETMR1_CHN_A_INTR_NUM 199 #define ETMR1_CHN_B_INTR_NUM 199 #define ETMR1_CHN_C_INTR_NUM 199 #define ETMR1_CHN_D_INTR_NUM 199 #define ETMR1_CNT_OVF_INTR_NUM 200 #define ETMR2_CHN_A_INTR_NUM 201 #define ETMR2_CHN_B_INTR_NUM 201 #define ETMR2_CHN_C_INTR_NUM 201 #define ETMR2_CHN_D_INTR_NUM 201 #define ETMR2_CNT_OVF_INTR_NUM 202 #define ETMR3_CHN_A_INTR_NUM 203 #define ETMR3_CHN_B_INTR_NUM 203 #define ETMR3_CHN_C_INTR_NUM 203 #define ETMR3_CHN_D_INTR_NUM 203 #define ETMR3_CNT_OVF_INTR_NUM 204 #define ETMR4_CHN_A_INTR_NUM 205 #define ETMR4_CHN_B_INTR_NUM 205 #define ETMR4_CHN_C_INTR_NUM 205 #define ETMR4_CHN_D_INTR_NUM 205 #define ETMR4_CNT_OVF_INTR_NUM 206 #define EPWM1_CHN_A_INTR_NUM 207 #define EPWM1_CHN_B_INTR_NUM 207 #define EPWM1_CHN_C_INTR_NUM 207 #define EPWM1_CHN_D_INTR_NUM 207 #define EPWM1_CNT_OVF_INTR_NUM 208 #define EPWM2_CHN_A_INTR_NUM 209 #define EPWM2_CHN_B_INTR_NUM 209 #define EPWM2_CHN_C_INTR_NUM 209 #define EPWM2_CHN_D_INTR_NUM 209 #define EPWM2_CNT_OVF_INTR_NUM 210 #define EPWM3_CHN_A_INTR_NUM 211 #define EPWM3_CHN_B_INTR_NUM 211 #define EPWM3_CHN_C_INTR_NUM 211 #define EPWM3_CHN_D_INTR_NUM 211 #define EPWM3_CNT_OVF_INTR_NUM 212 #define EPWM4_CHN_A_INTR_NUM 213 #define EPWM4_CHN_B_INTR_NUM 213 #define EPWM4_CHN_C_INTR_NUM 213 #define EPWM4_CHN_D_INTR_NUM 213 #define EPWM4_CNT_OVF_INTR_NUM 214 #define XTRG_FUNC_INTR_NUM 215 #define IOC_GPIO_SYNC_INTR_NUM 216 #define IOC_GPIO_ASYNC_INTR_NUM 216 #define RTC1_RTC_WAKEUP_INTR_NUM 217 #define RTC1_RTC_PERIODICAL_INTR_NUM 218 #define RTC1_VIOLATION_INTR_NUM 219 #define RTC2_RTC_WAKEUP_INTR_NUM 220 #define RTC2_RTC_PERIODICAL_INTR_NUM 221 #define RTC2_VIOLATION_INTR_NUM 222 #define TM_VIOLATION_INTR_NUM 223 #define VD_AP_O_VDC_FUNC_INTR_NUM 224 #define VD_SF_DIG_O_VDC_FUNC_INTR_NUM 225 #define PT_SNS_AP_PVT_0_INTR_NUM 226 #define PT_SNS_AP_PVT_1_INTR_NUM 227 #define PT_SNS_SF_DIG_PVT_0_INTR_NUM 228 #define PT_SNS_SF_DIG_PVT_1_INTR_NUM 229 #define SCR_SF_SCR_APB_PSLVERR_INTR_NUM 230 #define SCR_AP_SCR_INTR_NUM 231 #define PMU_CORE_PMU_INTR_NUM 232 #define RSTGEN_SF_RSTGEN_INTR_NUM 233 #define U_CKGEN_SF_CKGEN_INTR_NUM 234 #define RSTGEN_AP_RSTGEN_INTR_NUM 235 #define U_CKGEN_AP_CKGEN_INTR_NUM 236 #define SMC_SMC_INTR_NUM 237 #define SADC1_O_SADC_INTR_NUM 238 #define SADC2_O_SADC_INTR_NUM 239 #define SADC3_O_SADC_INTR_NUM 240 #define ACMP1_O_ACMP_INTR_NUM 241 #define ACMP2_O_ACMP_INTR_NUM 242 #define ACMP3_O_ACMP_INTR_NUM 243 #define ACMP4_O_ACMP_INTR_NUM 244 #define DCDC1_O_DCDC_FUNC_INTR_NUM 245 #define LDO_DIG_O_LDO_FUNC_INTR_NUM 246 #define FS_32K_FS_32K_INTR_NUM 247 #define ISTC_INTR_NUM 249 #define MPC_XSPI1A_FUNC_INTR_NUM 250 #define MPC_XSPI1B_FUNC_INTR_NUM 250 #define MPC_XSPI2A_FUNC_INTR_NUM 250 #define MPC_XSPI2B_FUNC_INTR_NUM 250 #define MPC_R5SX_S0_FUNC_INTR_NUM 250 #define MPC_R5SX_S1_FUNC_INTR_NUM 250 #define MPC_VIC3A_FUNC_INTR_NUM 250 #define MPC_VIC3B_FUNC_INTR_NUM 250 #define MPC_R5SF_S_FUNC_INTR_NUM 250 #define MPC_MB_FUNC_INTR_NUM 250 #define MPC_ROMC_FUNC_INTR_NUM 250 #define MPC_IRAMC1_FUNC_INTR_NUM 250 #define MPC_IRAMC2_FUNC_INTR_NUM 250 #define MPC_IRAMC3_FUNC_INTR_NUM 250 #define MPC_IRAMC4_FUNC_INTR_NUM 250 #define MPC_VIC1_FUNC_INTR_NUM 250 #define MAC_FUNC_INTR_NUM 250 #define PPC_APBMUX2_FUNC_INTR_NUM 250 #define PPC_APBMUX3_FUNC_INTR_NUM 250 #define PPC_APBMUX4_FUNC_INTR_NUM 250 #define MPC_CR5_SP0_FUNC_INTR_NUM 250 #define MPC_CR5_SP1_FUNC_INTR_NUM 250 #define MPC_GAMA1_FUNC_INTR_NUM 250 #define MPC_VIC2A_FUNC_INTR_NUM 250 #define MPC_VIC2B_FUNC_INTR_NUM 250 #define PPC_APBMUX5_FUNC_INTR_NUM 250 #define MPC_SDRAMC_FUNC_INTR_NUM 250 #define MPC_SEIP_FUNC_INTR_NUM 250 #define PPC_APBMUX1_FUNC_INTR_NUM 250 #define PPC_APBMUX6_FUNC_INTR_NUM 250 #define PPC_APBMUX7_FUNC_INTR_NUM 250 #define GPIO_SF_SGPIO_INTR_NUM 251 #define IRQ_MAX_INTR_NUM 252 #endif /* IRQ_NUM_H */