/**
 * @file device_init.c
 * @brief Semidrive device ealryinit.
 *
 * @copyright Copyright (c) 2022  Semidrive Semiconductor.
 *            All rights reserved.
 */

#include <common.h>
#include <sdrv_ckgen.h>
#include <sdrv_power.h>
#include <regs_base.h>
#include <reg.h>
#include <param.h>

extern const sdrv_ckgen_node_t **g_ckgen_unused[];

static const sdrv_ckgen_xcg_set_t g_xcg_info[] = {
    {APB_CKGEN_SF_BASE, CKGEN_PCG_TYPE, 207},
    {APB_CKGEN_SF_BASE, CKGEN_BCG_TYPE, 8},
    {APB_CKGEN_SF_BASE, CKGEN_CCG_TYPE, 1},
};

static int mcu_unused_ip_cglist_mask(const sdrv_ckgen_node_t *ckgen_ip[], bool mask)
{
    sdrv_ckgen_node_t *node;
    uint32_t i = 0;
    int ret = 0;

    while (ckgen_ip[i] && !ret) {
        node = (sdrv_ckgen_node_t *)ckgen_ip[i];
        ret = sdrv_ckgen_cg_mask(node, mask);
        i++;
    }

    return ret;
}

static int mcu_unused_ip_config(void)
{
    uint32_t i = 0;
    int ret = 0;

    while (g_ckgen_unused[i]) {
        ret = sdrv_ckgen_ip_clock_enable(g_ckgen_unused[i], CKGEN_HIB_MODE, false);
        ret = sdrv_ckgen_ip_clock_enable(g_ckgen_unused[i], CKGEN_SLP_MODE, false);
        ret = sdrv_ckgen_ip_clock_enable(g_ckgen_unused[i], CKGEN_RUN_MODE, false);
        ret = mcu_unused_ip_cglist_mask(g_ckgen_unused[i], true);
        i++;
    }

    return ret;
}

static void sdrv_xcg_runmode_active(const sdrv_ckgen_xcg_set_t *infos, uint32_t size)
{
    for (uint32_t i = 0; i < size; i++) {
        sdrv_ckgen_xcg_type_set((sdrv_ckgen_xcg_set_t *)&infos[i], CKGEN_RUN_MODE, false);
    }
}

/**
 * @brief initializes the device.
 *
 * This function initializes the device before call main function.
 */
void device_init(void)
{
    /* Set rtc_lbist bypass when do offline-bist */
    RMWREG32(APB_PMU_CORE_BASE + 0x70U, 2, 1, 1);
    RMWREG32(APB_PMU_CORE_BASE + 0x70U, 3, 1, 1);

    sdrv_xcg_runmode_active(g_xcg_info, ARRAY_SIZE(g_xcg_info));

    mcu_unused_ip_config();
}