/** * @brief Unique ID of the peripheral for DMA in SF domain . * * For peripheral transactions,DMA channel should set corresponding * mux id to select peripheral. */ typedef enum { SDRV_DMA_MUX_ID_CANFD1, SDRV_DMA_MUX_ID_CANFD2, SDRV_DMA_MUX_ID_CANFD3, SDRV_DMA_MUX_ID_CANFD4, SDRV_DMA_MUX_ID_CANFD5, SDRV_DMA_MUX_ID_CANFD6, SDRV_DMA_MUX_ID_CANFD7, SDRV_DMA_MUX_ID_CANFD8, SDRV_DMA_MUX_ID_CANFD9, SDRV_DMA_MUX_ID_CANFD10, SDRV_DMA_MUX_ID_CANFD11, SDRV_DMA_MUX_ID_CANFD12, SDRV_DMA_MUX_ID_CANFD13, SDRV_DMA_MUX_ID_CANFD14, SDRV_DMA_MUX_ID_CANFD15, SDRV_DMA_MUX_ID_CANFD16, SDRV_DMA_MUX_ID_CANFD17, SDRV_DMA_MUX_ID_CANFD18, SDRV_DMA_MUX_ID_CANFD19, SDRV_DMA_MUX_ID_CANFD20, SDRV_DMA_MUX_ID_CANFD21, SDRV_DMA_MUX_ID_CANFD22, SDRV_DMA_MUX_ID_CANFD23, SDRV_DMA_MUX_ID_CANFD24, SDRV_DMA_MUX_ID_ENET1_REQ_0, SDRV_DMA_MUX_ID_ENET1_REQ_1, SDRV_DMA_MUX_ID_ENET1_REQ_2, SDRV_DMA_MUX_ID_ENET1_REQ_3, SDRV_DMA_MUX_ID_ENET2_REQ_0, SDRV_DMA_MUX_ID_ENET2_REQ_1, SDRV_DMA_MUX_ID_ENET2_REQ_2, SDRV_DMA_MUX_ID_ENET2_REQ_3, SDRV_DMA_MUX_ID_I2C1, SDRV_DMA_MUX_ID_I2C2, SDRV_DMA_MUX_ID_I2C3, SDRV_DMA_MUX_ID_I2C4, SDRV_DMA_MUX_ID_I2C5, SDRV_DMA_MUX_ID_I2C6, SDRV_DMA_MUX_ID_I2C7, SDRV_DMA_MUX_ID_I2C8, SDRV_DMA_MUX_ID_XSPI1_A_RD, SDRV_DMA_MUX_ID_XSPI1_A_WR, SDRV_DMA_MUX_ID_XSPI1_B_RD, SDRV_DMA_MUX_ID_XSPI1_B_WR, SDRV_DMA_MUX_ID_XSPI2_A_RD, SDRV_DMA_MUX_ID_XSPI2_A_WR, SDRV_DMA_MUX_ID_XSPI2_B_RD, SDRV_DMA_MUX_ID_XSPI2_B_WR, SDRV_DMA_MUX_ID_SPI1_RX, SDRV_DMA_MUX_ID_SPI1_TX, SDRV_DMA_MUX_ID_SPI2_RX, SDRV_DMA_MUX_ID_SPI2_TX, SDRV_DMA_MUX_ID_SPI3_RX, SDRV_DMA_MUX_ID_SPI3_TX, SDRV_DMA_MUX_ID_SPI4_RX, SDRV_DMA_MUX_ID_SPI4_TX, SDRV_DMA_MUX_ID_SPI5_RX, SDRV_DMA_MUX_ID_SPI5_TX, SDRV_DMA_MUX_ID_SPI6_RX, SDRV_DMA_MUX_ID_SPI6_TX, SDRV_DMA_MUX_ID_SPI7_RX, SDRV_DMA_MUX_ID_SPI7_TX, SDRV_DMA_MUX_ID_SPI8_RX, SDRV_DMA_MUX_ID_SPI8_TX, SDRV_DMA_MUX_ID_EPWM1_A, SDRV_DMA_MUX_ID_EPWM1_B, SDRV_DMA_MUX_ID_EPWM1_C, SDRV_DMA_MUX_ID_EPWM1_D, SDRV_DMA_MUX_ID_EPWM1_OVF, SDRV_DMA_MUX_ID_EPWM2_A, SDRV_DMA_MUX_ID_EPWM2_B, SDRV_DMA_MUX_ID_EPWM2_C, SDRV_DMA_MUX_ID_EPWM2_D, SDRV_DMA_MUX_ID_EPWM2_OVF, SDRV_DMA_MUX_ID_EPWM3_A, SDRV_DMA_MUX_ID_EPWM3_B, SDRV_DMA_MUX_ID_EPWM3_C, SDRV_DMA_MUX_ID_EPWM3_D, SDRV_DMA_MUX_ID_EPWM3_OVF, SDRV_DMA_MUX_ID_EPWM4_A, SDRV_DMA_MUX_ID_EPWM4_B, SDRV_DMA_MUX_ID_EPWM4_C, SDRV_DMA_MUX_ID_EPWM4_D, SDRV_DMA_MUX_ID_EPWM4_OVF, SDRV_DMA_MUX_ID_ETMR1_A, SDRV_DMA_MUX_ID_ETMR1_B, SDRV_DMA_MUX_ID_ETMR1_C, SDRV_DMA_MUX_ID_ETMR1_D, SDRV_DMA_MUX_ID_ETMR1_OVF, SDRV_DMA_MUX_ID_ETMR2_A, SDRV_DMA_MUX_ID_ETMR2_B, SDRV_DMA_MUX_ID_ETMR2_C, SDRV_DMA_MUX_ID_ETMR2_D, SDRV_DMA_MUX_ID_ETMR2_OVF, SDRV_DMA_MUX_ID_ETMR3_A, SDRV_DMA_MUX_ID_ETMR3_B, SDRV_DMA_MUX_ID_ETMR3_C, SDRV_DMA_MUX_ID_ETMR3_D, SDRV_DMA_MUX_ID_ETMR3_OVF, SDRV_DMA_MUX_ID_ETMR4_A, SDRV_DMA_MUX_ID_ETMR4_B, SDRV_DMA_MUX_ID_ETMR4_C, SDRV_DMA_MUX_ID_ETMR4_D, SDRV_DMA_MUX_ID_ETMR4_OVF, SDRV_DMA_MUX_ID_XTRG_0, SDRV_DMA_MUX_ID_XTRG_1, SDRV_DMA_MUX_ID_UART1_TX, SDRV_DMA_MUX_ID_UART1_RX, SDRV_DMA_MUX_ID_UART2_TX, SDRV_DMA_MUX_ID_UART2_RX, SDRV_DMA_MUX_ID_UART3_TX, SDRV_DMA_MUX_ID_UART3_RX, SDRV_DMA_MUX_ID_UART4_TX, SDRV_DMA_MUX_ID_UART4_RX, SDRV_DMA_MUX_ID_UART5_TX, SDRV_DMA_MUX_ID_UART5_RX, SDRV_DMA_MUX_ID_UART6_TX, SDRV_DMA_MUX_ID_UART6_RX, SDRV_DMA_MUX_ID_UART7_TX, SDRV_DMA_MUX_ID_UART7_RX, SDRV_DMA_MUX_ID_UART8_TX, SDRV_DMA_MUX_ID_UART8_RX, SDRV_DMA_MUX_ID_UART9_TX, SDRV_DMA_MUX_ID_UART9_RX, SDRV_DMA_MUX_ID_UART10_TX, SDRV_DMA_MUX_ID_UART10_RX, SDRV_DMA_MUX_ID_UART11_TX, SDRV_DMA_MUX_ID_UART11_RX, SDRV_DMA_MUX_ID_UART12_TX, SDRV_DMA_MUX_ID_UART12_RX, SDRV_DMA_MUX_ID_UART13_TX, SDRV_DMA_MUX_ID_UART13_RX, SDRV_DMA_MUX_ID_UART14_TX, SDRV_DMA_MUX_ID_UART14_RX, SDRV_DMA_MUX_ID_UART15_TX, SDRV_DMA_MUX_ID_UART15_RX, SDRV_DMA_MUX_ID_UART16_TX, SDRV_DMA_MUX_ID_UART16_RX, SDRV_DMA_MUX_ID_ADC1_0, SDRV_DMA_MUX_ID_ADC1_1, SDRV_DMA_MUX_ID_ADC2_0, SDRV_DMA_MUX_ID_ADC2_1, SDRV_DMA_MUX_ID_ADC3_0, SDRV_DMA_MUX_ID_ADC3_1, SDRV_DMA_MUX_ID_ISTC, } sdrv_dma_sf_mux_id_e; /** * @brief Unique ID of the peripheral for DMA in AP domain . * * For peripheral transactions,DMA channel should set corresponding * mux id to select peripheral. */ typedef enum { SDRV_DMA_MUX_ID_SACI1_TX, SDRV_DMA_MUX_ID_SACI1_RX, SDRV_DMA_MUX_ID_SACI1_PDM, SDRV_DMA_MUX_ID_SACI2_TX, SDRV_DMA_MUX_ID_SACI2_RX, SDRV_DMA_MUX_ID_SACI2_PDM, SDRV_DMA_MUX_ID_DC, } sdrv_dma_ap_mux_id_e; #define DMA_SF_PERIPHERALS_MUX_MAP \ {SDRV_DMA_MUX_ID_CANFD3, APB_CANFD3_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_CANFD4, APB_CANFD4_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_CANFD16, APB_CANFD16_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_CANFD21, APB_CANFD21_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_I2C3, APB_I2C3_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_I2C4, APB_I2C4_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_I2C5, APB_I2C5_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_I2C6, APB_I2C6_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_I2C3, APB_I2C3_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_I2C4, APB_I2C4_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_I2C5, APB_I2C5_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_I2C6, APB_I2C6_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_XSPI1_A_RD, APB_XSPI1PORTA_BASE, 0x380, \ SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_XSPI1_A_WR, APB_XSPI1PORTA_BASE, 0x280, \ SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_XSPI1_B_RD, APB_XSPI1PORTB_BASE, 0x380, \ SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_XSPI1_B_WR, APB_XSPI1PORTB_BASE, 0x280, \ SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_XSPI2_A_RD, APB_XSPI2PORTA_BASE, 0x380, \ SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_XSPI2_A_WR, APB_XSPI2PORTA_BASE, 0x280, \ SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_XSPI2_B_RD, APB_XSPI2PORTB_BASE, 0x380, \ SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_XSPI2_B_WR, APB_XSPI2PORTB_BASE, 0x280, \ SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_SPI1_RX, APB_SPI1_BASE, 0x3000, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_SPI1_TX, APB_SPI1_BASE, 0x2000, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_SPI2_RX, APB_SPI2_BASE, 0x3000, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_SPI2_TX, APB_SPI2_BASE, 0x2000, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_SPI3_RX, APB_SPI3_BASE, 0x3000, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_SPI3_TX, APB_SPI3_BASE, 0x2000, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_SPI4_RX, APB_SPI4_BASE, 0x3000, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_SPI4_TX, APB_SPI4_BASE, 0x2000, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_SPI5_RX, APB_SPI5_BASE, 0x3000, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_SPI5_TX, APB_SPI5_BASE, 0x2000, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_SPI6_RX, APB_SPI6_BASE, 0x3000, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_SPI6_TX, APB_SPI6_BASE, 0x2000, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_EPWM1_A, APB_EPWM1_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM1_B, APB_EPWM1_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM1_C, APB_EPWM1_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM1_D, APB_EPWM1_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM1_OVF, APB_EPWM1_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM2_A, APB_EPWM2_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM2_B, APB_EPWM2_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM2_C, APB_EPWM2_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM2_D, APB_EPWM2_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM2_OVF, APB_EPWM2_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM3_A, APB_EPWM3_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM3_B, APB_EPWM3_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM3_C, APB_EPWM3_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM3_D, APB_EPWM3_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM3_OVF, APB_EPWM3_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM4_A, APB_EPWM4_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM4_B, APB_EPWM4_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM4_C, APB_EPWM4_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM4_D, APB_EPWM4_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_EPWM4_OVF, APB_EPWM4_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR1_A, APB_ETMR1_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR1_B, APB_ETMR1_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR1_C, APB_ETMR1_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR1_D, APB_ETMR1_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR1_OVF, APB_ETMR1_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR2_A, APB_ETMR2_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR2_B, APB_ETMR2_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR2_C, APB_ETMR2_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR2_D, APB_ETMR2_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR2_OVF, APB_ETMR2_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR3_A, APB_ETMR3_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR3_B, APB_ETMR3_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR3_C, APB_ETMR3_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR3_D, APB_ETMR3_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR3_OVF, APB_ETMR3_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR4_A, APB_ETMR4_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR4_B, APB_ETMR4_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR4_C, APB_ETMR4_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR4_D, APB_ETMR4_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ETMR4_OVF, APB_ETMR4_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_UART1_TX, APB_UART1_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_UART1_RX, APB_UART1_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_UART2_TX, APB_UART2_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_UART2_RX, APB_UART2_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_UART3_TX, APB_UART3_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_UART3_RX, APB_UART3_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_UART4_TX, APB_UART4_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_UART4_RX, APB_UART4_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_UART5_TX, APB_UART5_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_UART5_RX, APB_UART5_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_UART6_TX, APB_UART6_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_UART6_RX, APB_UART6_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_UART7_TX, APB_UART7_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_UART7_RX, APB_UART7_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_UART8_TX, APB_UART8_BASE, 0x200, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_UART8_RX, APB_UART8_BASE, 0x300, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_ADC1_0, APB_ADC1_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ADC1_1, APB_ADC1_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ADC2_0, APB_ADC2_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ADC2_1, APB_ADC2_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ADC3_0, APB_ADC3_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ADC3_1, APB_ADC3_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \ {SDRV_DMA_MUX_ID_ISTC, APB_ISTC_BASE, 0xffff, SDRV_DMA_MUX_BOTH}, #define DMA_AP_PERIPHERALS_MUX_MAP \ {SDRV_DMA_MUX_ID_SACI1_TX, APB_SACI1_BASE, 0x2000, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_SACI1_RX, APB_SACI1_BASE, 0x4000, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_SACI1_PDM, APB_SACI1_BASE, 0x6000, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_SACI2_TX, APB_SACI2_BASE, 0x2000, SDRV_DMA_MUX_WR}, \ {SDRV_DMA_MUX_ID_SACI2_RX, APB_SACI2_BASE, 0x4000, SDRV_DMA_MUX_RD}, \ {SDRV_DMA_MUX_ID_SACI2_PDM, APB_SACI2_BASE, 0x6000, SDRV_DMA_MUX_RD}, #define SDRV_DMA_SF_MAX_CHANNEL (24) /* SF DMA channel number */ #define SDRV_DMA_AP_MAX_CHANNEL (8) /* AP DMA channel number */