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liumin
2026-01-12 18:46:01 +08:00
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5676
20250218-ETH-CAN_loadV1.3/e3_176_ref/middleware/usb/uC-USBH/HCD/EHCI/usbh_hcd_ehci.c Normal file
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20250218-ETH-CAN_loadV1.3/e3_176_ref/middleware/usb/uC-USBH/HCD/EHCI/usbh_hcd_ehci.h Normal file
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/*
*********************************************************************************************************
* uC/USB-Host
* The Embedded USB Host Stack
*
* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
*
* SPDX-License-Identifier: APACHE-2.0
*
* This software is subject to an open source license and is distributed by
* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* GENERIC EHCI DRIVER
*
* Filename : usbh_ehci.h
* Version : V3.42.01
*********************************************************************************************************
*/
#ifndef USBH_EHCI_H
#define USBH_EHCI_H
/*
*********************************************************************************************************
* INCLUDE HEADER FILES
*********************************************************************************************************
*/
#include "../../Source/usbh_core.h"
/*
*********************************************************************************************************
* CONSTANTS
*********************************************************************************************************
*/
#define EHCI_MAX_ITD 10u /* Max nbr of iTD per EP for HS isoc xfer */
#define EHCI_MAX_SITD 10u /* Max nbr of siTD per EP for FS isoc xfer */
#define EHCI_MAX_PERIODIC_BW 90u
#define EHCI_PORT_POWERED_ALWAYS 0u
#define EHCI_PORT_POWERED_INDIVIDUAL 1u
#define EHCI_MAX_PERIODIC_LIST_SIZE (256u * 2u)
#define EHCI_TIMESTAMP_MICROSEC 1u
#define EHCI_TIMESTAMP_MILLISEC 2u
/* ----------- EHCI QH LIST NUMBER DEFINES ------------ */
#define EHCI_QH_LIST_256MS 0u
#define EHCI_QH_LIST_128MS 256u
#define EHCI_QH_LIST_64MS 384u
#define EHCI_QH_LIST_32MS 448u
#define EHCI_QH_LIST_16MS 480u
#define EHCI_QH_LIST_08MS 496u
#define EHCI_QH_LIST_04MS 504u
#define EHCI_QH_LIST_02MS 508u
#define EHCI_QH_LIST_01MS 510u
#define EHCI_INTR_QH_LIST_SIZE (EHCI_QH_LIST_01MS + 1u)
#define EHCI_MAX_BW_PER_MICRO_FRAME 3072u
#define EHCI_BW_FLAG_CONSUME 1u
#define EHCI_BW_FLAG_PRODUCE 2u
/*
*********************************************************************************************************
* LOCAL DEFINES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL DATA TYPES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL GLOBAL VARIABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MACROS
*********************************************************************************************************
*/
#ifndef EHCI_CFG_ONRESET_EN /* En callback to setup auxiliary registers on reset. */
#define EHCI_CFG_ONRESET_EN DEF_DISABLED
#endif
#define USBH_EHCI_CFG_PERIODIC_EN DEF_ENABLED
/*
*********************************************************************************************************
* MAXIMUM PACKET SIZES
*********************************************************************************************************
*/
#define MPS_HS 1024u /* Maximum Packet Size for High Speed device */
#define MPS_FS 1023u /* Maximum Packet Size for Full Speed device */
#define MPS_LS 64u /* Maximum Packet Size for Low Speed device */
/*
*********************************************************************************************************
* TYPE DEFINITIONS
*********************************************************************************************************
*/
typedef struct ehci_isoc_ep_desc EHCI_ISOC_EP_DESC;
typedef struct ehci_isoc_ep_urb EHCI_ISOC_EP_URB;
typedef struct ehci_intr_info EHCI_INTR_INFO;
typedef struct ehci_qh {
CPU_REG32 QHHorLinkPtr;
CPU_REG32 QHEpCapChar[2];
CPU_REG32 QHCurQTDPtr;
CPU_REG32 QHNxtQTDPtr;
CPU_REG32 QHAltNxtQTDPtr;
CPU_REG32 QHToken;
CPU_REG32 QHBufPagePtrList[5];
/* Fields not part of qH struct defined in EHCI spec */
USBH_EP *EPPtr;
CPU_INT32U QTDHead;
CPU_INT08U SMask;
CPU_INT08U BWStartFrame;
CPU_INT16U FrameInterval;
CPU_INT08U Rsvd[4]; /* Padding to align the struct on a 32-byte boundary */
} EHCI_QH;
typedef struct ehci_qtd {
CPU_REG32 QTDNxtPtr;
CPU_REG32 QTDAltNxtPtr;
CPU_REG32 QTDToken;
CPU_REG32 QTDBufPagePtrList[5];
} EHCI_QTD;
typedef struct ehci_sitd {
CPU_REG32 SITDNxtLinkPtr;
CPU_REG32 SITDEpCapChar[2];
CPU_REG32 SITDStsCtrl;
CPU_REG32 SITDBufPagePtrList[2];
CPU_REG32 SITDBackLinkPtr;
} EHCI_SITD;
typedef struct ehci_itd {
CPU_REG32 ITDNxtLinkPtr;
CPU_REG32 ITDStsAndCntrl[8];
CPU_REG32 ITDBufPagePtrList[7];
} EHCI_ITD;
struct ehci_isoc_ep_desc {
void *TDTailPtr;
USBH_EP *EPPtr;
CPU_INT08U SMask;
CPU_INT08U CMask;
CPU_INT08U TCnt;
CPU_INT08U AppStartFrame;
CPU_INT08U NbrFrame;
CPU_INT16U FrameInterval;
EHCI_ISOC_EP_DESC *NxtEPDesc;
};
struct ehci_isoc_ep_urb {
CPU_INT32U iTD_Addr;
CPU_INT08U AppStartFrame;
CPU_INT08U NbrFrame;
};
typedef struct ehci_cap {
CPU_INT08U CapLen;
CPU_INT16U HCIVersion;
CPU_INT32U HCSParams;
CPU_INT32U HCCParams;
CPU_INT08U HCSPPortRoute[15];
} EHCI_CAP;
typedef struct ehci_cap_reg {
CPU_REG32 CapLen_HCIVersion;
CPU_REG32 HCSParams;
CPU_REG32 HCCParams;
CPU_REG08 HCSPPortRoute[15];
} EHCI_CAP_REG;
typedef struct ehci_oper_reg {
CPU_REG32 USBCmd;
CPU_REG32 USBSts;
CPU_REG32 USBIntr;
CPU_REG32 FrameIx;
CPU_REG32 CtrlDSSeg;
CPU_REG32 PeriodicListBase;
CPU_REG32 AsyncListAddr;
CPU_REG32 Rsvd[9];
CPU_REG32 CfgFlag;
CPU_REG32 PortSC[1];
} EHCI_OPER_REG;
typedef struct ehci_dma {
EHCI_QTD *QTDPtr; /* DMA memory CTRL,BULK and INTR QTD */
EHCI_QH *QHPtr; /* DMA memory for Queue Head (QH) */
EHCI_ITD *ITDPtr;
CPU_INT08U *BufPtr;
} EHCI_DMA;
#if (USBH_EHCI_CFG_PERIODIC_EN == DEF_ENABLED)
struct ehci_intr_info {
CPU_INT08U IntrPlaceholderIx; /* Index of Intr placeholder in QHLists array. */
CPU_INT16U FrameInterval;
USBH_EP *EpPtr;
EHCI_INTR_INFO *NxtIntrInfo;
};
#endif
typedef struct ehci_dev { /* -------------------- EHCI Device ------------------- */
EHCI_CAP HcCap; /* Pointer to Capability structure */
EHCI_DMA DMA_EHCI;
CPU_INT08U EHCI_HubBuf[sizeof(USBH_HUB_DESC)];
EHCI_QH *AsyncQHHead; /* Asynchronous list head */
CPU_INT08U NbrPorts; /* Number of Ports in RootHub */
MEM_POOL HC_QHPool; /* Memory pool for allocating HC QHs */
MEM_POOL HC_QTDPool; /* Memory pool for allocating HC QTDs */
MEM_POOL BufPool;
CPU_INT32U PortResetChng; /* Port Reset Change status variable */
EHCI_CAP_REG *HcCapReg; /* Pointer to Host Controller Capability Registers */
EHCI_OPER_REG *HcOperReg; /* Pointer to Host Controller Operational Registers */
#if (USBH_EHCI_CFG_PERIODIC_EN == DEF_ENABLED)
CPU_INT32U *PeriodicListBase;
EHCI_QH *QHLists[EHCI_INTR_QH_LIST_SIZE]; /* HCD qH placeholder array for Intr ep. */
MEM_POOL HC_ITDPool; /* Memory pool for allocating HC iTDs */
MEM_POOL IntrInfoPool; /* Memory pool for allocating Intr info struct. */
MEM_POOL HC_Isoc_EP_DescPool; /* Memory pool for allocating HCD Isoc EP struct */
MEM_POOL HC_Isoc_EP_URBPool;
CPU_INT16U MaxPeriodicBWArr[256][8]; /* Maximum Periodic Bandwidth */
EHCI_ISOC_EP_DESC *HeadIsocEPDesc; /* Isochronous list head pointer */
EHCI_INTR_INFO *HeadIntrInfo; /* Intr info list head pointer. */
#endif
CPU_INT32U FNOCnt; /* Counter for Frame List Rollover */
CPU_BOOLEAN HC_Started; /* Indicate if EHCI HC is started. */
CPU_INT08U DrvType; /* Indicate which EHCI drv type. */
} EHCI_DEV;
/*
*********************************************************************************************************
* GLOBAL VARIABLES
*********************************************************************************************************
*/
#ifdef USBH_EHCI_MODULE
#define USBH_EHCI_EXT
#else
#define USBH_EHCI_EXT extern
#endif
USBH_EHCI_EXT USBH_HC_DRV_API EHCI_DrvAPI;
USBH_EHCI_EXT USBH_HC_DRV_API EHCI_DrvAPI_Synopsys;
USBH_EHCI_EXT USBH_HC_RH_API EHCI_RH_API;
/*
*********************************************************************************************************
* FUNCTION PROTOTYPES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* CONFIGURATION ERRORS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif

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20250218-ETH-CAN_loadV1.3/e3_176_ref/middleware/usb/uC-USBH/HCD/OHCI/usbh_hcd_ohci.c Normal file
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/*
*********************************************************************************************************
* uC/USB-Host
* The Embedded USB Host Stack
*
* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
*
* SPDX-License-Identifier: APACHE-2.0
*
* This software is subject to an open source license and is distributed by
* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* NOTICE
*
* Semidrive modified this file to adapt it for ssdk platform.
* The modifications are only intended for use with Semidrive chips.
* Copyright of all the modifications belongs to Semidrive Semiconductor.
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* STANDARD OHCI DRIVER
*
* Filename : usbh_ohci.h
* Version : V3.42.01
*********************************************************************************************************
*/
#ifndef USBH_OHCI_MODULE_PRESENT
#define USBH_OHCI_MODULE_PRESENT
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#include "../../Source/usbh_core.h"
/*
*********************************************************************************************************
* EXTERNS
*********************************************************************************************************
*/
#ifdef USBH_OHCI_MODULE
#define USBH_OHCI_EXT
#else
#define USBH_OHCI_EXT extern
#endif
/*
*********************************************************************************************************
* DEFINES
*********************************************************************************************************
*/
/* ----------- OHCI ED LIST NUMBER DEFINES ------------ */
#define OHCI_ED_LIST_32MS 0u
#define OHCI_ED_LIST_16MS 32u
#define OHCI_ED_LIST_08MS 48u
#define OHCI_ED_LIST_04MS 56u
#define OHCI_ED_LIST_02MS 60u
#define OHCI_ED_LIST_01MS 62u
#define OHCI_ED_LIST_CTRL 63u
#define OHCI_ED_LIST_BULK 64u
#define OHCI_ED_LIST_SIZE (OHCI_ED_LIST_BULK + 1u)
#define OHCI_MAX_PERIODIC_BW 90u
/*
*********************************************************************************************************
* DATA TYPES
*********************************************************************************************************
*/
typedef struct ohci_hcd_td OHCI_HCD_TD;
typedef struct ohci_hcd_ed OHCI_HCD_ED;
typedef struct ohci_oper_reg {
CPU_REG32 Revision;
CPU_REG32 Control;
CPU_REG32 CommandStatus;
CPU_REG32 InterruptStatus;
CPU_REG32 InterruptEnable;
CPU_REG32 InterruptDisable;
CPU_REG32 HCCA;
CPU_REG32 PeriodCurrentED;
CPU_REG32 ControlHeadED;
CPU_REG32 ControlCurrentED;
CPU_REG32 BulkHeadED;
CPU_REG32 BulkCurrentED;
CPU_REG32 DoneHead;
CPU_REG32 FmInterval;
CPU_REG32 FmRemaining;
CPU_REG32 FmNumber;
CPU_REG32 PeriodicStart;
CPU_REG32 LSThreshold;
CPU_REG32 RhDescriptorA;
CPU_REG32 RhDescriptorB;
CPU_REG32 RhStatus;
CPU_REG32 RhPortStatus[1];
} OHCI_OPER_REG;
/* --- HOST CONTROLLER COMMUNICATION AREA DATA TYPE --- */
typedef struct ohci_hcca {
CPU_REG32 IntTbl[32]; /* Interrupt Table */
CPU_REG32 FrameNbr; /* Frame Number */
CPU_REG32 DoneHead; /* Done Head */
CPU_REG08 Rsvd[116]; /* Reserved for future use */
CPU_REG08 Unknown[4]; /* Unused */
} OHCI_HCCA;
/* --- HOST CONTROLLER ENDPOINT DESCRIPTOR DATA TYPE -- */
typedef struct ohci_hc_ed {
CPU_REG32 Ctrl; /* Endpoint descriptor control */
CPU_REG32 TailTD; /* Physical address of tail in Transfer descriptor list */
CPU_REG32 HeadTD; /* Physcial address of head in Transfer descriptor list */
CPU_REG32 Next; /* Physical address of next Endpoint descriptor */
#if CONFIG_ARCH_CACHE_LINE > 16
CPU_REG08 Rsvd[CONFIG_ARCH_CACHE_LINE - 16];
#endif
} OHCI_HC_ED;
/* --- HOST CONTROLLER TRANSFER DESCRIPTOR DATA TYPE -- */
typedef struct ohci_hc_td {
CPU_REG32 Ctrl; /* Transfer descriptor control */
CPU_REG32 CurBuf; /* Physical address of current buffer pointer */
CPU_REG32 Next; /* Physical pointer to next Transfer Descriptor */
CPU_REG32 BufEnd; /* Physical address of end of buffer */
CPU_REG32 Offsets[4]; /* Isochronous offsets */
} OHCI_HC_TD;
/* --- HOST CONTROLLER ENDPOINT TRANSFER DESCRIPTOR --- */
struct ohci_hcd_ed {
OHCI_HC_ED *HC_EDPtr;
CPU_INT32U DMA_HC_ED;
OHCI_HCD_TD *Head_HCD_TDPtr;
OHCI_HCD_TD *Tail_HCD_TDPtr;
OHCI_HCD_ED *NextPtr;
CPU_INT32U ListInterval;
CPU_INT32U BW;
CPU_BOOLEAN IsHalt;
};
/* HOST CONTROLLER DRIVER TRANSFER DESCRIPTOR DATA TYPE */
struct ohci_hcd_td {
OHCI_HC_TD *HC_TdPtr;
CPU_INT32U DMA_HC_TD;
OHCI_HCD_TD *NextPtr;
USBH_URB *URBPtr; /* URB associated with this TD */
CPU_REG08 State;
};
/* -------------- OHCI DMA Structure ------------------ */
typedef struct ohci_dma {
OHCI_HCCA *HCCAPtr; /* DMA memory HCCA descriptor */
OHCI_HC_TD *TDPtr; /* DMA memory CTRL,BULK and INTR endpoint TD */
OHCI_HC_ED *EDPtr; /* DMA memory for Endpoint Descriptors (ED) */
CPU_INT08U *BufPtr;
} OHCI_DMA;
/* -------------- OHCI DEVICE DATA TYPE --------------- */
typedef struct ohci_dev {
OHCI_DMA DMA_OHCI;
CPU_INT08U OHCI_HubBuf[sizeof(USBH_HUB_DESC)];
OHCI_HCD_ED *EDLists[OHCI_ED_LIST_SIZE]; /* OHCI EndPoint Descriptor Lists */
CPU_INT08U CanWakeUp; /* Port Power */
CPU_INT08U NbrPorts; /* Number of Ports in RootHub */
CPU_INT32U TotBW; /* Periodic list parameters */
CPU_INT32U Branch[32]; /* Bandwidth of branches */
MEM_POOL HC_EDPool; /* Memory pool for allocating DMA ednpoint descriptor */
MEM_POOL HC_TDPool; /* Memory pool for allocating DMA general TDs */
OHCI_HCD_ED *HCD_ED;
MEM_POOL HCD_EDPool; /* Memory pool for allocating OHCI driver EDs */
OHCI_HCD_TD *HCD_TD;
MEM_POOL HCD_TDPool; /* Memory pool for allocating OHCI driver TDs */
MEM_POOL BufPool;
CPU_INT32U FrameNbr;
OHCI_HCD_TD **OHCI_Lookup;
} OHCI_DEV;
/*
*********************************************************************************************************
* GLOBAL VARIABLES
*********************************************************************************************************
*/
USBH_OHCI_EXT USBH_HC_DRV_API OHCI_DrvAPI;
USBH_OHCI_EXT USBH_HC_RH_API OHCI_RH_API;
/*
*********************************************************************************************************
* MACROS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* FUNCTION PROTOTYPES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* CONFIGURATION ERRORS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif