570 lines
15 KiB
C
570 lines
15 KiB
C
/**
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* @file sdrv_xspi.h
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* @brief Semidrive xspi master controller register header
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*
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* @copyright Copyright (c) 2021 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_XSPI_H_
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#define SDRV_XSPI_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <debug.h>
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#include <sdrv_spi_nor.h>
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#include <reg.h>
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#include <types.h>
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#define INDIRECT_READ_FLAG (0)
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#define INDIRECT_WRITE_FLAG (1)
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#define XSPI_DLL_USE_OVERRIDE_MODE (1)
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#undef BIT
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#define BIT(nr) ((uint32_t)1u << (nr))
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#define XSPI_NS_2_TICKS(hz, ns) (((hz) / 1000u * (ns) + 1000000u) / 1000000u)
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#define XSPI_US_2_TICKS(hz, us) (((hz) / 1000u * (us) + 1000u) / 1000u)
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#define XSPI_MS_2_TICKS(hz, ms) ((hz) / 1000u * (ms) + 1u)
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extern volatile int g_xspi_debug;
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// #define WITH_XSPI_DEBUG
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#ifdef WITH_XSPI_DEBUG
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#define xspi_readl(reg) \
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readl(reg); \
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if (g_xspi_debug) { \
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ssdk_printf(SSDK_EMERG, "r(0x%x, r(0x%08x)\r\n", (reg), readl(reg));}
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#define sdrv_xspi_writel(val, reg) \
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writel(val, reg); \
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if (g_xspi_debug) { \
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ssdk_printf(SSDK_EMERG, "w(0x%x, 0x%08x), r(0x%08x)\r\n", (reg), (val), \
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readl(reg)); }
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#else
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#define sdrv_xspi_writel(val, reg) writel((val), (reg))
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#define xspi_readl(reg) readl(reg)
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#endif
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enum xspi_access_mode {
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XSPI_DIRECT_ACCESS_MODE,
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XSPI_INDIRECT_ACCESS_MODE
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};
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typedef union {
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struct {
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// command phase
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uint8_t c_line:2;
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uint8_t c_rate:1;
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uint8_t c_size:2;
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uint8_t c_en:1;
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uint8_t reseved1:2;
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// address phase
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uint8_t a_line:2;
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uint8_t a_rate:1;
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uint8_t a_size:2;
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uint8_t a_en:1; // only indirect
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uint16_t reseved2:2;
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// mode phase (only read)
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uint8_t m_line:2;
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uint8_t m_rate:1;
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uint8_t m_size:2;
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uint8_t m_en:1;
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uint16_t reseved3:2;
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// data phase
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uint8_t d_line:2;
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uint8_t d_rate:1;
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uint8_t d_en:1;
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uint8_t reseved4:4;
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} ph_ctrl;
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uint32_t data;
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} ph_ctrl_t;
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#define XSPI_C_LINE(x) ((x) << 0)
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#define XSPI_C_RATE(x) ((x) << 2)
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#define XSPI_C_SIZE(x) ((x) << 3)
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#define XSPI_C_EN (1u << 5)
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#define XSPI_A_LINE(x) ((x) << 8)
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#define XSPI_A_RATE(x) ((x) << 10)
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#define XSPI_A_SIZE(x) ((x) << 11)
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#define XSPI_A_EN (1u << 13)
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#define XSPI_D_LINE(x) ((x) << 24)
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#define XSPI_D_RATE(x) ((x) << 26)
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#define XSPI_D_EN (1u << 27)
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/** @brief Operation timeout value */
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#define XSPI_IDLE_TIMEOUT_CYCLES (10000u)
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#define XSPI_MODE_CTRL (0x0u)
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#define XSPI_MODE_CTRL_SW_RST BIT(31)
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#define XSPI_MODE_CTRL_IDLE BIT(30)
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#define XSPI_MODE_CTRL_XIP BIT(9)
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#define XSPI_MODE_CTRL_RX_MODE BIT(8)
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#define XSPI_DEV_SIZE (0x4u)
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#define XSPI_DEV_SIZE_SIZE_LSB (8u)
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#define XSPI_DEV_SIZE_SIZE_MASK (0x1Fu)
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#define XSPI_INT_ST_FUC (0x10u)
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#define XSPI_INT_ST_FUC_INDIRECT_DMA_RD_DONE BIT(10u)
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#define XSPI_INT_ST_FUC_TX_FRE_EMPTY BIT(9u)
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#define XSPI_INT_ST_FUC_RX_FRE_FULL BIT(8u)
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#define XSPI_INT_ST_FUC_FIFO_LEVEL_TRIG (XSPI_INT_ST_FUC_RX_FRE_FULL | XSPI_INT_ST_FUC_TX_FRE_EMPTY)
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#define XSPI_INT_ST_FUC_DIRECT_RD_DONE BIT(3u)
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#define XSPI_INT_ST_FUC_DIRECT_WR_DONE BIT(2u)
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#define XSPI_INT_ST_FUC_INDIRECT_RD_DONE BIT(1u)
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#define XSPI_INT_ST_FUC_INDIRECT_WR_DONE BIT(0u)
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#define XSPI_INT_ST_FUC_IND_COMP \
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(XSPI_INT_ST_FUC_INDIRECT_DMA_RD_DONE | XSPI_INT_ST_FUC_INDIRECT_WR_DONE)
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#define XSPI_INT_EN_FUC (0x14u)
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#define XSPI_INT_ST_ERR (0x18u)
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#define XSPI_INT_EN_ERR (0x1Cu)
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#define XSPI_INT_EN_ERR_FUC (0x20u)
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#define XSPI_DATA_INIEGRITY (0x30u)
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#define XSPI_IO_FMUX1 (0x40u)
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#define XSPI_IO_FMUX2 (0x44u)
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#define XSPI_IO1_FMUX1 (0x48u)
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#define XSPI_IO1_FMUX2 (0x4Cu)
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#define XSPI_IO_CTRL (0x60u)
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#define XSPI_ADDR_OFFSET (0x70u)
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#define XSPI_MISC (0x80u)
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#define XSPI_MISC_INDIRECT_AXI_RD_EN BIT(11u)
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#define XSPI_MISC_INDIRECT_AXI_WR_EN BIT(10u)
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#define XSPI_AXI_CTRL (0x84u)
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#define XSPI_SCLK_CTRL (0xC0u)
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#define XSPI_SCLK_CTRL_RX_SEL_MASK (3u)
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#define XSPI_SCLK_CTRL_RX_SEL_LSB (2u)
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#define XSPI_CS_CTRL (0xC4u)
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#define XSPI_CS_CTRL_SEL_MASK (0xFu)
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#define XSPI_CS_CTRL_HW_SEL_MASK (0x3u)
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#define XSPI_CS_CTRL_HW_SEL_DEV1 (0x2u)
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#define XSPI_CS_CTRL_HW_SEL_DEV2 (0x1u)
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#define XSPI_CS_CTRL_HW_SEL_AUTO (0x3u)
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#define XSPI_CS_CTRL_HW_SEL_LSB (27u)
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#define XSPI_CS_CTRL_SW_SEL_MASK (0x3u)
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#define XSPI_CS_CTRL_SW_SEL_DEV1 (0x2u)
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#define XSPI_CS_CTRL_SW_SEL_DEV2 (0x1u
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#define XSPI_CS_CTRL_SW_SEL_LSB (25u)
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#define XSPI_CS_CTRL_SW BIT(24)
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#define XSPI_CS_CTRL_TIME_DELAY_MASK (0xFu)
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#define XSPI_CS_CTRL_TIME_SHSL_DELAY_MASK (0x1Fu)
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#define XSPI_CS_CTRL_TSLCH_LSB (16u)
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#define XSPI_CS_CTRL_TSHSL_LSB (8u)
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#define XSPI_CS_CTRL_TCHSH_LSB (0u)
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#define XSPI_HYPERBUS_CTRL (0xD0u)
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#define XSPI_DLL_CTRL (0xE0u)
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#define XSPI_STATUS (0xE4u)
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#define XSPI_DLL1_CTRL (0xE8u)
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#define XSPI_DLL1_STATUS (0xECu)
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#define XSPI_DIRECT_RD_PH_CTRL (0x100u)
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#define XSPI_DIRECT_WR_PH_CTRL (0x104u)
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#define XSPI_DIRECT_DATA_DDR_RATE BIT(26)
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#define XSPI_DIRECT_DATA_LINE_MASK (0x3u)
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#define XSPI_DIRECT_DATA_LINE_LSB (24u)
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#define XSPI_DIRECT_MODE_EN BIT(21)
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#define XSPI_DIRECT_MODE_SIZE_MASK (0x3u)
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#define XSPI_DIRECT_MODE_SIZE_LSB (19u)
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#define XSPI_DIRECT_MODE_DDR_RATE BIT(18)
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#define XSPI_DIRECT_MODE_LINE_MASK (0x3u)
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#define XSPI_DIRECT_MODE_LINE_LSB (16u)
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#define XSPI_DIRECT_ADDR_SIZE_MASK (0x3u)
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#define XSPI_DIRECT_ADDR_SIZE_LSB (11u)
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#define XSPI_DIRECT_ADDR_DDR_RATE BIT(10)
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#define XSPI_DIRECT_ADDR_LINE_MASK (0x3u)
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#define XSPI_DIRECT_ADDR_LINE_LSB (8u)
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#define XSPI_DIRECT_CMD_EN BIT(5)
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#define XSPI_DIRECT_CMD_SIZE_MASK (0x3u)
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#define XSPI_DIRECT_CMD_SIZE_LSB (3u)
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#define XSPI_DIRECT_CMD_DDR_RATE BIT(2)
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#define XSPI_DIRECT_CMD_LINE_MASK (0x3u)
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#define XSPI_DIRECT_CMD_LINE_LSB (0u)
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#define XSPI_DIRECT_C_CODE (0x114u)
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#define XSPI_DIRECT_C_CODE_MASK (0xFFu)
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#define XSPI_DIRECT_WREN (0x118u)
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#define XSPI_DIRECT_M_CODE (0x11Cu)
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#define XSPI_DIRECT_D_CYC (0x120u)
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#define XSPI_DIRECT_D_CYC_RD_LSB (0u)
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#define XSPI_DIRECT_D_CYC_RD_MASK (0x1Fu)
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#define XSPI_DIRECT_D_CYC_WR_LSB (8u)
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#define XSPI_DIRECT_D_CYC_WR_MASK (0x1Fu)
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#define XSPI_INDIRECT_WR_CTRL (0x200u)
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#define XSPI_INDIRECT_WR_PH_CTRL (0x204u)
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#define XSPI_INDIRECT_RD_PH_CTRL (0x304u)
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#define XSPI_INDIRECT_DATA_EN BIT(27)
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#define XSPI_INDIRECT_DATA_DDR_RATE BIT(26)
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#define XSPI_INDIRECT_DATA_LINE_MASK (0x3u)
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#define XSPI_INDIRECT_DATA_LINE_LSB (24u)
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#define XSPI_INDIRECT_ADDR_EN BIT(13)
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#define XSPI_INDIRECT_ADDR_SIZE_MASK (0x3u)
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#define XSPI_INDIRECT_ADDR_SIZE_LSB (11u)
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#define XSPI_INDIRECT_ADDR_DDR_RATE BIT(10)
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#define XSPI_INDIRECT_ADDR_LINE_MASK (0x3u)
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#define XSPI_INDIRECT_ADDR_LINE_LSB (8u)
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#define XSPI_INDIRECT_CMD_EN BIT(5)
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#define XSPI_INDIRECT_CMD_SIZE_2_BYTES BIT(3u)
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#define XSPI_INDIRECT_CMD_DDR_RATE BIT(2)
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#define XSPI_INDIRECT_CMD_LINE_MASK (0x3u)
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#define XSPI_INDIRECT_CMD_LINE_LSB (0u)
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#define XSPI_INDIRECT_WR_CMD_CODE (0x208u)
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#define XSPI_INDIRECT_WR_CMD_CODE_MASK (0xFFu)
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#define XSPI_INDIRECT_WR_ADDR (0x20Cu)
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#define XSPI_INDIRECT_WR_SIZE (0x210u)
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#define XSPI_INDIRECT_WR_CYC (0x214u)
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#define XSPI_INDIRECT_WR_DMA (0x220u)
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#define XSPI_INDIRECT_RD_DMA (0x320u)
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#define XSPI_INDIRECT_DMA_TRIG_WML_MASK (0x1Fu)
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#define XSPI_INDIRECT_DMA_TRIG_WML_LSB (8u)
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#define XSPI_INDIRECT_DMA_SW_ACK BIT(2)
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#define XSPI_INDIRECT_DMA_SINGLE_EN BIT(1)
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#define XSPI_INDIRECT_DMA_REQ_EN BIT(0)
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#define XSPI_INDIRECT_TX_BUF (0x240u)
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#define XSPI_INDIRECT_TX_BUF_ENTRY_MASK (0xFFu)
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#define XSPI_INDIRECT_TX_BUF_ENTRY_LSB (16)
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#define XSPI_INDIRECT_TX_BUF_LEVEL_MASK (0xFFu)
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#define XSPI_INDIRECT_TX_BUF_LEVEL_LSB (8)
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#define XSPI_INDIRECT_WDATA (0x280u)
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#define XSPI_INDIRECT_RD_CTRL (0x300u)
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#define XSPI_INDIRECT_RD_CMD_CODE (0x308u)
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#define XSPI_INDIRECT_RD_CMD_CODE_MASK (0xFFu)
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#define XSPI_INDIRECT_RD_ADDR (0x30Cu)
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#define XSPI_INDIRECT_RD_SIZE (0x310u)
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#define XSPI_INDIRECT_RD_CYC (0x314u)
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#define XSPI_INDIRECT_RD_CYC_MASK (0x1fu)
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#define XSPI_INDIRECT_RD_M_CODE (0x318u)
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#define XSPI_INDIRECT_P_VALUE (0x330u)
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#define XSPI_INDIRECT_P_MASK (0x334u)
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#define XSPI_INDIRECT_P_TIME (0x338u)
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#define XSPI_INDIRECT_RX_BUF (0x340u)
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#define XSPI_INDIRECT_RX_BUF_ENTRY_MASK (0xFFu)
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#define XSPI_INDIRECT_RX_BUF_ENTRY_LSB (16)
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#define XSPI_INDIRECT_RX_BUF_LEVEL_MASK (0xFFu)
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#define XSPI_INDIRECT_RX_BUF_LEVEL_LSB (8)
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#define XSPI_INDIRECT_RDATA (0x380u)
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#define XSPI_RBUF_HIT_CNTR (0x390u)
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#define XSPI_RBUF_MISS_CNTR (0x394u)
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#define XSPI_GROUP_MERGE (0x3A0u)
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#define XSPI_RBUF_CTRL (0x400u)
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#define XSPI_GID_MASK (0x404u)
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#define XSPI_GID_MATCH (0x408u)
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#define XSPI_IMG_REGION_START (0x500u)
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#define XSPI_IMG_REGION_END_ADDR (0x504u)
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#define XSPI_IMG_REGION_CTRL (0x508u)
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#define XSPI_IMG_REGION_NONCE0 (0x510u)
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#define XSPI_IMG_REGION_NONCE1 (0x514u)
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#define XSPI_IMG_REGION_NONCE2 (0x518u)
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#define XSPI_IMG_REGION_NONCE3 (0x51Cu)
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#define XSPI_IMG_RFD (0x590u)
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#define XSPI_MON_OP_TIME (0x600u)
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#define XSPI_CMD_MON_CTRL (0x610u)
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#define XSPI_MON_REGION_START_ADDR (0x614u)
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#define XSPI_MON_REGION_END_ADDR (0x618u)
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#define XSPI_MON_CMD_VALUE (0x654u)
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#define XSPI_MS_CTRL (0x800u)
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#define XSPI_MS_WAIT_TIME (0x810u)
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#define XSPI_MS_TIMEOUT (0x81Cu)
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#define XSPI_MS_INT_ST (0x820u)
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#define XSPI_MS_INT_EN (0x828u)
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#define XSPI_INDR_WR_PTC (0x900u)
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#define XSPI_INDR_RD_PTC (0x904u)
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#define XSPI_DIRECT_WR_PTC (0x908u)
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#define XSPI_DIRECT_RD_PTC (0x90Cu)
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#define XSPI_INDR_WR_PTA (0x920u)
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#define XSPI_INDR_WR_PTD (0x924u)
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#define XSPI_INDR_RD_PTA (0x928u)
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#define XSPI_INDR_RD_PTD (0x92Cu)
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#define XSPI_DIRECT_WR_PTA (0x930)
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#define XSPI_DIRECT_WR_PTD (0x934)
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#define XSPI_DIRECT_RD_PTA (0x938)
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#define XSPI_DIRECT_RD_PTD (0x93C)
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#define XSPI_ERR_INJ_EN (0xC00)
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#define XSPI_INJ_DATA (0xC04)
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#define XSPI_INJ_CODE (0xC08)
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#define XSPI_FATAL_ERR_ST (0xC20)
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#define XSPI_FATAL_ERR_EN (0xC28)
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#define XSPI_CORE_ERR_ST (0xC30)
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#define XSPI_AXI_UNC_ERR_ST (0xC34)
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#define XSPI_APB_UNC_ERR_ST (0xC38)
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#define XSPI_DMA_ERR_ST (0xC3C)
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#define XSPI_COR_ERR_EN (0xC50)
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#define XSPI_AXI_UNC_ERR_EN (0xC54)
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#define XSPI_APB_UNC_ERR_EN (0xC58)
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#define XSPI_DMA_ERR_EN (0xC5C)
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#define XSPI_CTRL_ERR_ST (0xC60)
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#define XSPI_CTRL_ERR_EN (0xC68)
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#define XSPI_LSP_ERR_INJ_EN (0x1000)
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#define XSPI_LSP_CMP_ERR_INJ (0x1004)
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#define XSPI_LSP_ERR_ST (0x1010)
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#define XSPI_LSP_ERR_EN (0x1014)
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/**
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* @brief xspi indirect read or write prepare trans clean interface
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* @param[in] nor xspi norflash instance contex handle.
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*/
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static inline void sdrv_xspi_indr_pre_trans_clean(struct spi_nor *nor)
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{
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struct xspi_pdata *xspi = nor->host->priv_data;
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/* Config indirect read pre-transaction to 0 */
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sdrv_xspi_writel(0, xspi->apb_base + XSPI_INDR_RD_PTC);
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/* Config direct write pre-transaction to 0 */
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sdrv_xspi_writel(0, xspi->apb_base + XSPI_INDR_WR_PTC);
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}
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/**
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* @brief xspi init interface
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* @param[in] xspi xspi norflash private data
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*/
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void *sdrv_xspi_init(struct xspi_pdata *xspi);
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/**
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* @brief xspi proto setup mode interface
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* @param[in] nor xspi norflash instance contex handle.
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* @param[in] cmd spi nor command info
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* @param[in] access_mode xspi direct or indirect access mode
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* @param[in] ops write or read op
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*/
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void sdrv_xspi_nor_setup(struct spi_nor *nor, enum spi_nor_ops ops);
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/**
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* @brief xspi interrupt unmask interface
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* @param[in] xspi xspi norflash private data
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* @param[in] addr xspi host address
|
|
* @param[in] mask interrupt mask type
|
|
*/
|
|
void sdrv_xspi_proto_setup(struct spi_nor *nor, struct spi_nor_cmd *cmd,
|
|
enum xspi_access_mode access_mode,
|
|
enum spi_nor_ops ops);
|
|
|
|
/**
|
|
* @brief xspi interrupt unmask interface
|
|
* @param[in] xspi xspi norflash private data
|
|
* @param[in] addr xspi host address
|
|
* @param[in] mask interrupt mask type
|
|
*/
|
|
void sdrv_xspi_int_unmask(struct xspi_pdata *xspi, addr_t addr, uint32_t mask);
|
|
|
|
/**
|
|
* @brief xspi indirect trigger interface.
|
|
* @param[in] xspi xspi norflash private data
|
|
* @param[in] addr indirect trans flash address
|
|
* @param[in] size indirect trans flash length
|
|
* @param[in] indirect read or write trans flag
|
|
*/
|
|
void sdrv_xspi_indirect_trigger(const struct xspi_pdata *xspi, uint32_t addr,
|
|
uint32_t size, int flag);
|
|
|
|
|
|
/**
|
|
* @brief xspi setup xfer interface.
|
|
* @param[in] nor xspi norflash instance contex handle.
|
|
* @param[in] opt record flash opt
|
|
* @param[in] addr record flash address
|
|
* @param[in] buf record buf ptr
|
|
* @param[in] size record size
|
|
*/
|
|
void sdrv_xspi_setup_xfer(struct spi_nor *nor, enum flash_opt opt,
|
|
flash_addr_t addr, uint8_t *buf, flash_size_t size);
|
|
|
|
/**
|
|
* @brief xspi rx write fifo interface.
|
|
* @param[in] xspi xspi norflash private data
|
|
* @param[in] write buf to fifo address
|
|
* @param[in] size write bytes select MIN(size, sram_size)
|
|
* @return uint32_t
|
|
* @retval 0: success
|
|
* @retval other: failed
|
|
*/
|
|
uint32_t sdrv_xspi_write_fifo(struct xspi_pdata *xspi, const uint8_t *buf,
|
|
flash_size_t size);
|
|
|
|
/**
|
|
* @brief xspi rx polling mode interface.
|
|
* @param[in] nor xspi norflash instance contex handle.
|
|
* @return int
|
|
* @retval 0: success
|
|
* @retval other: failed
|
|
*/
|
|
int sdrv_xspi_rx_polling(struct spi_nor *nor);
|
|
|
|
|
|
/**
|
|
* @brief xspi tx polling mode interface.
|
|
* @param[in] nor xspi norflash instance contex handle.
|
|
* @return int
|
|
* @retval 0: success
|
|
* @retval other: failed
|
|
*/
|
|
int sdrv_xspi_tx_polling(struct spi_nor *nor);
|
|
|
|
|
|
/**
|
|
* @brief xspi dma enable interface.
|
|
* @details Used for xspi dma enable in indirect write or read mode
|
|
* @param[in] xspi xspi norflash private data
|
|
*/
|
|
void sdrv_xspi_dma_enable(struct xspi_pdata *xspi);
|
|
|
|
/**
|
|
* @brief xspi dma disable interface.
|
|
* @details Used for xspi dma disable in indirect write or read mode
|
|
* @param[in] xspi xspi norflash private data
|
|
*/
|
|
void sdrv_xspi_dma_disable(struct xspi_pdata *xspi);
|
|
|
|
|
|
/**
|
|
* @brief xspi dll enable interface.
|
|
* @details Used for xspi dll config and enable dll
|
|
* @param[in] xspi spi norflash private data
|
|
* @param[in] dll_num select dll num
|
|
* @param[in] value config dll value
|
|
* @param[in] enable enable or not
|
|
*/
|
|
void sdrv_xspi_dll_enable(struct xspi_pdata *xspi, int dll_num, int value,
|
|
bool enable);
|
|
|
|
/**
|
|
* @brief xspi hyperram enable interface.
|
|
* @details Used for config direct read/write and write read dummy cycle
|
|
* @param[in] nor spi norflash instance contex handle.
|
|
* @param[in] cs spi norflash cs.
|
|
* @param[in] read_dummy spi norflash read dummy cycle.
|
|
* @param[in] write_dummy spi norflash write dummy cycle
|
|
*/
|
|
void sdrv_xspi_hyperram_enable(struct spi_nor *nor, uint8_t cs,
|
|
uint8_t read_dummy, uint8_t write_dummy);
|
|
|
|
/**
|
|
* @brief xspi host init
|
|
*
|
|
* @param[in] host spi nor host
|
|
* @param[in] xspi xspi private info
|
|
* @param[in] config xspi config info
|
|
* @return int
|
|
* @retval 0: success
|
|
* @retval other: failed
|
|
*/
|
|
int sdrv_xspi_host_init(struct spi_nor_host *host, struct xspi_pdata *xspi,
|
|
struct xspi_config *config);
|
|
|
|
/**
|
|
* @brief xspi host deinit
|
|
*
|
|
* @param[in] host spi nor host
|
|
* @return
|
|
*/
|
|
void sdrv_spi_nor_drv_deinit(struct spi_nor *nor);
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* SDRV_XSPI_H_ */
|