sdrv_spi_nor.h

Go to the documentation of this file.

 
#ifndef SDRV_SPI_NOR_H_
#define SDRV_SPI_NOR_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdbool.h>
#include <types.h>
#include <sdrv_ckgen.h>
#include <sdrv_common.h>
 
#undef BIT
#define BIT(nr) (1u << (nr))
 
#define SNOR_READID_DUMMY_LSB (24u)
#define SNOR_OPCODE_PROTO_LSB (24u)
#define SNOR_DTR_PROTO       BIT(16)
 
#define SNOR_INST_LANS_PROTO_LSB  (8u)
#define SNOR_INST_LANS_PROTO_MASK (0xFu)
#define SNOR_INST_SINGLE_LANS     (0u << SNOR_INST_LANS_PROTO_LSB)
#define SNOR_INST_DUAL_LANS       (1u << SNOR_INST_LANS_PROTO_LSB)
#define SNOR_INST_QUAD_LANS       (2u << SNOR_INST_LANS_PROTO_LSB)
#define SNOR_INST_OCTAL_LANS      (3u << SNOR_INST_LANS_PROTO_LSB)
#define SNOR_INST_LANS(x)         (((x) >> SNOR_INST_LANS_PROTO_LSB) & \
                                        (SNOR_INST_LANS_PROTO_MASK))
 
#define SNOR_ADDR_LANS_PROTO_LSB  (4u)
#define SNOR_ADDR_LANS_PROTO_MASK (0xFu)
#define SNOR_ADDR_SINGLE_LANS     (0u << SNOR_ADDR_LANS_PROTO_LSB)
#define SNOR_ADDR_DUAL_LANS       (1u << SNOR_ADDR_LANS_PROTO_LSB)
#define SNOR_ADDR_QUAD_LANS       (2u << SNOR_ADDR_LANS_PROTO_LSB)
#define SNOR_ADDR_OCTAL_LANS      (3u << SNOR_ADDR_LANS_PROTO_LSB)
#define SNOR_ADDR_LANS(x)         (((x) >> SNOR_ADDR_LANS_PROTO_LSB) & \
                                        (SNOR_ADDR_LANS_PROTO_MASK))
 
 
#define SNOR_DATA_LANS_PROTO_LSB  (0u)
#define SNOR_DATA_LANS_PROTO_MASK (0xFu)
#define SNOR_DATA_SINGLE_LANS     (0u << SNOR_DATA_LANS_PROTO_LSB)
#define SNOR_DATA_DUAL_LANS       (1u << SNOR_DATA_LANS_PROTO_LSB)
#define SNOR_DATA_QUAD_LANS       (2u << SNOR_DATA_LANS_PROTO_LSB)
#define SNOR_DATA_OCTAL_LANS      (3u << SNOR_DATA_LANS_PROTO_LSB)
#define SNOR_DATA_LANS(x)         (((x) >> SNOR_DATA_LANS_PROTO_LSB) & \
                                        (SNOR_DATA_LANS_PROTO_MASK))
 
#define SNOR_PROTO_1_1_1                                                       \
    (SNOR_INST_SINGLE_LANS | SNOR_ADDR_SINGLE_LANS | SNOR_DATA_SINGLE_LANS)
#define SNOR_PROTO_1_1_2                                                       \
    (SNOR_INST_SINGLE_LANS | SNOR_ADDR_SINGLE_LANS | SNOR_DATA_DUAL_LANS)
#define SNOR_PROTO_1_1_4                                                       \
    (SNOR_INST_SINGLE_LANS | SNOR_ADDR_SINGLE_LANS | SNOR_DATA_QUAD_LANS)
#define SNOR_PROTO_1_1_8                                                       \
    (SNOR_INST_SINGLE_LANS | SNOR_ADDR_SINGLE_LANS | SNOR_DATA_OCTAL_LANS)
#define SNOR_PROTO_1_2_2                                                       \
    (SNOR_INST_SINGLE_LANS | SNOR_ADDR_DUAL_LANS | SNOR_DATA_DUAL_LANS)
#define SNOR_PROTO_1_4_4                                                       \
    (SNOR_INST_SINGLE_LANS | SNOR_ADDR_QUAD_LANS | SNOR_DATA_QUAD_LANS)
#define SNOR_PROTO_1_8_8                                                       \
    (SNOR_INST_SINGLE_LANS | SNOR_ADDR_OCTAL_LANS | SNOR_DATA_OCTAL_LANS)
#define SNOR_PROTO_2_2_2                                                       \
    (SNOR_INST_DUAL_LANS | SNOR_ADDR_DUAL_LANS | SNOR_DATA_DUAL_LANS)
#define SNOR_PROTO_4_4_4                                                       \
    (SNOR_INST_QUAD_LANS | SNOR_ADDR_QUAD_LANS | SNOR_DATA_QUAD_LANS)
#define SNOR_PROTO_8_8_8                                                       \
    (SNOR_INST_OCTAL_LANS | SNOR_ADDR_OCTAL_LANS | SNOR_DATA_OCTAL_LANS)
#define SNOR_PROTO_1_1_1_DTR (SNOR_PROTO_1_1_1 | SNOR_DTR_PROTO)
#define SNOR_PROTO_1_2_2_DTR (SNOR_PROTO_1_2_2 | SNOR_DTR_PROTO)
#define SNOR_PROTO_1_4_4_DTR (SNOR_PROTO_1_4_4 | SNOR_DTR_PROTO)
#define SNOR_PROTO_4_4_4_DTR (SNOR_PROTO_4_4_4 | SNOR_DTR_PROTO)
#define SNOR_PROTO_1_1_8_DTR (SNOR_PROTO_1_1_8 | SNOR_DTR_PROTO)
#define SNOR_PROTO_1_8_8_DTR (SNOR_PROTO_1_8_8 | SNOR_DTR_PROTO)
#define SNOR_PROTO_8_8_8_DTR (SNOR_PROTO_8_8_8 | SNOR_DTR_PROTO)
 
#define SNOR_PROTO_DTR_MASK 0x1ffffu
#define SNOR_PROTO_MASK     0xffffu
#define SNOR_PROTO_DTR(x) ((x) & SNOR_PROTO_DTR_MASK)
#define SNOR_PROTO(x) ((x) & SNOR_PROTO_MASK)
 
#define SPI_NOR_MAX_ID_LEN 6
 
#define SECTOR_4K_POST      (12)
#define SECTOR_32K_POST     (15)
#define SECTOR_64K_POST     (16)
#define SECTOR_128K_POST    (17)
#define SECTOR_256K_POST    (18)
#define SECTOR_POST_TO_SIZE(n) (1U << (n))
 
#define SPINOR_SECTOR_4K_SIZE (0x1000)
#define SPINOR_SECTOR_32K_SIZE (0x8000)
#define SPINOR_SECTOR_64K_SIZE (0x10000)
#define SPINOR_SECTOR_128K_SIZE (0x20000)
#define SPINOR_SECTOR_256K_SIZE (0x40000)
 
#define SWITCH_DEVICE_MAX_NUM (4u)
 
typedef enum {
    SPI_NOR_SECTOR_4KB = 0,
    SPI_NOR_SECTOR_32KB,
    SPI_NOR_SECTOR_64KB,
    SPI_NOR_SECTOR_128KB,
    SPI_NOR_SECTOR_256KB,
    SPI_NOR_SECTOR_TYPE_MAX,
} spi_nor_sector_type;
#define SECTOR_TYPE_TO_POST(type)   ((type) ? (14 + (type)) : 12)
#define SECTOR_TYPE_TO_SIZE(type)   SECTOR_POST_TO_SIZE(SECTOR_TYPE_TO_POST(type))
 
typedef uint64_t flash_addr_t;
typedef uint64_t flash_size_t;
 
enum flash_opt {
    FLASH_OPT_NONE, 
    FLASH_OPT_READ, 
    FLASH_OPT_WRITE,    
    FLASH_OPT_ERASE,    
    FLASH_OPT_MAX,
};
 
enum flash_opt_result {
    FLASH_OPT_COMPLETE = 0,    
    FLASH_OPT_FAILED,          
    FLASH_OPT_PENDING,         
    FLASH_OPT_INCONSISTENT,    
    FLASH_OPT_INVALID,         
    FLASH_OPT_RESULET_MAX,
};
 
struct flash_xfer_info {
    enum flash_opt opt_type;          
    enum flash_opt_result opt_result; 
    flash_addr_t addr;                
    uint8_t *buf;                     
    flash_size_t size;                
};
 
typedef void (*flash_notification)(enum flash_opt type,
                                   enum flash_opt_result result);
 
enum xspi_xfer_mode {
    XSPI_XFER_NONE = 0,
    XSPI_XFER_READ,
    XSPI_XFER_WRITE,
};
 
enum xspi_bus_event_mode {
    SPI_NOR_XFER_CLEAR,
    SPI_NOR_XFER_COMPLETE = 1,
    SPI_NOR_XFER_WAIT,
};
 
struct xspi_config {
    uint8_t id;             
    addr_t apb_base;        
    addr_t direct_base;     
    unsigned int irq;       
    unsigned long ref_clk;  
    bool xip_mode;          
};
 
struct xspi_pdata {
    uint8_t id;               
    addr_t apb_base;          
    addr_t direct_base;       
    unsigned int irq;         
    unsigned long ref_clk_hz; 
    unsigned int sclk;        
    uint8_t dma_bus_width;    
    uint32_t dma_burst_size;  
    bool cs_decoded;          
    uint8_t current_cs;       
    bool dqs_en;              
    uint8_t fifo_depth;       
    uint8_t fifo_width;       
    uint32_t direct_range_size; 
};
 
struct spi_nor;
 
typedef enum {
    SPI_NOR_COMMON = 0, // ret = OK
    SPI_NOR_INIT,
    SPI_NOR_ERASE,
    SPI_NOR_WRITE,
    SPI_NOR_READ,
    SPI_NOR_CANCEL,
} spi_nor_error_group_t;
 
typedef enum {
    SPI_NOR_OK = 0,
    SPI_NOR_FAIL,
    SPI_NOR_BUSY,
    SPI_NOR_TIMEOUT,
    SPI_NOR_UNSUPPORT,
    SPI_NOR_UNREACHABLE,
    SPI_NOR_ADDRESS_INVALID,
    SPI_NOR_LENGTH_INVALID,
    SPI_NOR_COMMON_CODE_MAX,
} spi_nor_common_error_code_t;
 
typedef enum {
    SPI_NOR_INIT_TRAIN_E = SPI_NOR_COMMON_CODE_MAX,
} spi_nor_init_error_code_t;
 
#define SPI_NOR_OK_STATUS                     SDRV_STATUS_OK
#define SPI_NOR_ERR_CODE(g, c)                (((((g) & 0xF) << 5) | ((c) & 0x1F)) * !!(c))
#define SPI_NOR_ERR_STATUS(g, c)              (int)(SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_XSPI, SPI_NOR_ERR_CODE((g), (c)))  * !!(c))
 
enum spi_nor_xfer_mode {
    SPI_NOR_XFER_POLLING_MODE = 0,
    SPI_NOR_XFER_INTERRUPT_MODE,
    SPI_NOR_XFER_DMA_MODE,
};
 
enum spi_nor_device_mode {
    SPI_NOR_DEV_SINGLE_MODE = 0,
    SPI_NOR_DEV_LOCKSTEP_MODE,
    SPI_NOR_DEV_PARALLEL_MODE,
};
 
enum spi_nor_proto_type {
    SPI_NOR_PROTO_TYPE_READ = 0,
    SPI_NOR_PROTO_TYPE_WRITE,
    SPI_NOR_PROTO_TYPE_ERASE,
};
 
enum spi_memory_type {
    SPI_AUTO_DETECT = 0,
    SPI_NOR_FLASH,
    SPI_NAND_FLASH,
    SPI_HYPERFLASH,
    SPI_HYPERRAM,
    SPI_HYPERBUS_MCP,
};
 
struct spi_nor_cmd {
    uint8_t opcode;      
    uint8_t inst_type;   
    uint8_t dummy;       
    uint8_t addr_bytes;  
};
 
struct hyperbus_ca {
    uint16_t addr;
    uint16_t data;
};
 
struct hyperflash_cmd {
    char *name;       
    bool is_read;     
    uint32_t num;     
    struct hyperbus_ca ca[7];
};
 
enum spi_nor_ops {
    SPI_NOR_OPS_READ = 1,
    SPI_NOR_OPS_WRITE,
    SPI_NOR_OPS_ERASE,
    SPI_NOR_OPS_LOCK,
    SPI_NOR_OPS_UNLOCK,
};
 
enum spi_nor_rw_para {
    SPI_NOR_DIRECT_READ = 0,
    SPI_NOR_INDIRECT_READ,
    SPI_NOR_DIRECT_WRITE,
    SPI_NOR_INDIRECT_WRITE,
};
 
struct spi_nor_config {
    uint8_t id;                        
    uint8_t cs;                        
    uint32_t baudrate;                 
    enum spi_nor_xfer_mode xfer_mode;  
    enum spi_nor_device_mode dev_mode; 
    enum spi_memory_type mem_type;     
    bool async_mode;                   
    bool hyperbus_mode;                
    bool sw_rst;                       
    uint32_t force_size;               
};
 
struct spi_nor_erase_map {
    uint32_t erase_proto;
    uint32_t erase_size; // in bytes
    uint32_t post;
};
 
struct spi_nor_erase_cmd {
    flash_addr_t addr;
    const struct spi_nor_erase_map *map;
};
 
struct flash_info {
    const char *name;                     
    uint8_t flash_id[SPI_NOR_MAX_ID_LEN]; 
    uint32_t read_proto;  
    uint32_t write_proto; 
    uint32_t erase_proto; 
    uint32_t erase_proto_list[SPI_NOR_SECTOR_TYPE_MAX]; 
    uint8_t read_dummy;   
    uint8_t write_dummy;  
    uint8_t status_dummy; 
    uint32_t sector_size; 
    uint16_t page_size;   
    flash_size_t size;    
    struct spi_nor_erase_map erase_map[SPI_NOR_SECTOR_TYPE_MAX];   
    int (*default_init)(struct spi_nor *nor); 
    int (*octal_dtr_enable)(struct spi_nor *nor,  bool enable); 
    int (*quad_enable)(struct spi_nor *nor, bool enable); 
    int (*enter_quad)(struct spi_nor *nor, bool enable); 
    int (*set_4byte_addr_mode)(struct spi_nor *nor,
                               bool enable);               
};
 
struct spi_nor_host_ops {
    int (*prepare)(struct spi_nor *flash_handle, enum spi_nor_ops ops); 
    void (*unprepare)(struct spi_nor *flash_handle, enum spi_nor_ops ops); 
    int (*reg_read)(struct spi_nor *flash_handle, struct spi_nor_cmd *cmd,
                    flash_addr_t addr, uint8_t *buf, flash_size_t length); 
    int (*reg_write)(struct spi_nor *flash_handle, struct spi_nor_cmd *cmd,
                     flash_addr_t addr, const uint8_t *buf,
                     flash_size_t length); 
    int (*read)(struct spi_nor *flash_handle, flash_addr_t addr, uint8_t *buf,
                flash_size_t length); 
    int (*write)(struct spi_nor *flash_handle, flash_addr_t addr,
                 const uint8_t *buf, flash_size_t length); 
    int (*erase)(struct spi_nor *flash_handle, flash_addr_t offset); 
    int (*complex_erase)(struct spi_nor *nor, struct spi_nor_erase_cmd *cmd); 
    int (*training)(struct spi_nor *flash_handle, flash_addr_t addr,
                    uint8_t *buf, const uint8_t *pattern, flash_size_t length); 
    int (*cancel)(struct spi_nor *flash_handle); 
    void (*cache_flush)(struct spi_nor *flash_handle, flash_addr_t addr, flash_size_t length); 
    int (*enable_rfd)(struct spi_nor *flash_handle, uint8_t mask);  
    void (*xip_proto_setup)(struct spi_nor *flash_handle);  
};
 
struct hyperbus_host_ops {
    int (*read16)(struct spi_nor *flash_handle, flash_addr_t addr, uint16_t *buf); 
    int (*write16)(struct spi_nor *flash_handle, flash_addr_t addr, uint16_t *buf); 
    void (*set_pre_transaction)(struct spi_nor *flash_handle, bool is_read,
                                bool is_direct, uint32_t num, struct hyperbus_ca **ca_array); 
    void (*hyperram_en)(struct spi_nor *flash_handle, uint8_t cs,
                        uint8_t read_dummy, uint8_t write_dummy); 
    int (*read)(struct spi_nor *flash_handle, flash_addr_t addr, uint8_t *buf,
                flash_size_t length); 
    int (*write)(struct spi_nor *flash_handle, flash_addr_t addr,
                 const uint8_t *buf, flash_size_t length); 
    void (*cache_flush)(struct spi_nor *flash_handle, flash_addr_t addr, flash_size_t length); 
};
 
struct spi_nor_host {
    uint8_t id;                          
    addr_t base;                         
    unsigned int irq;                    
    sdrv_ckgen_node_t *clk;              
    unsigned long ref_clk_hz;            
    bool xip_mode;                     
    struct spi_nor_host_ops *ops;        
    struct hyperbus_host_ops *hyper_ops; 
    struct spi_nor *dev;                 
    void *priv_data;                     
    struct spi_nor *nor_tab[SWITCH_DEVICE_MAX_NUM];  
    flash_size_t total_size;             
};
 
typedef void (*flash_dma_config)(struct spi_nor *nor, flash_addr_t addr, uint8_t *buf,
                     uint32_t len, bool is_read_flag, uint32_t burst_len);
typedef void (*flash_dma_stop)(void);
typedef void (*flash_dma_stop_signal)(struct spi_nor *nor);
 
struct spi_nor {
    uint8_t id;                        
    uint8_t cs;                        
    uint32_t baudrate;                 
    uint32_t offset_address;           
    enum spi_memory_type
    mem_type;                          
    enum spi_nor_device_mode dev_mode; 
    struct flash_info info;           
    bool phy_en;                       
    bool dqs_en;                       
    bool octal_dtr_en;                 
    bool async_mode;                   
    bool hyperbus_mode;                
    bool sw_rst;                       
    uint32_t reg_proto;                
    uint8_t addr_width;                
    enum spi_nor_xfer_mode xfer_mode; 
    struct flash_xfer_info xfer_info;  
    struct flash_xfer_info xfer_info_bottom; 
    flash_notification event_handler;  
    flash_dma_config dma_xfer_config;  
    flash_dma_stop dma_xfer_stop;  
    flash_dma_stop_signal dma_stop;           
    struct spi_nor_host *host;         
    void    *ops;                       
    void *parent;                      
};
 
typedef struct {
    int (*fls_wait_idle)(struct spi_nor *nor);
    int (*fls_write_enable)(struct spi_nor *nor, bool enable);
    int (*fls_init)(struct spi_nor *nor, struct spi_nor_host *host,
                    const struct spi_nor_config *flash_config);
    void (*fls_deinit)(struct spi_nor *nor);
    int (*fls_read)(struct spi_nor *nor, flash_addr_t addr, uint8_t *buf,
                    flash_size_t size);
    int (*fls_write)(struct spi_nor *nor, flash_addr_t addr,
                    const uint8_t *buf, flash_size_t size);
    int (*fls_erase)(struct spi_nor *nor, flash_addr_t addr,
                    flash_size_t size);
    int (*fls_cancel)(struct spi_nor *nor);
    void (*fls_main_function)(struct spi_nor *nor);
    const struct flash_info*(*fls_get_flash_table)(uint32_t *num);
} flash_ops_t;
#if !(CONFIG_DISABLE_SPIBUS_COMPILE)
extern flash_ops_t spi_nor_ops;
#endif
#if !(CONFIG_DISABLE_HYPERBUS_COMPILE)
extern flash_ops_t hyperbus_ops;
#endif
 
static inline int sdrv_spi_nor_wait_idle(struct spi_nor *nor) {
    if (nor && nor->ops) {
        return ((flash_ops_t*)(nor->ops))->fls_wait_idle(nor);
    }
    return SDRV_STATUS_INVALID_PARAM;
}
 
static inline int sdrv_spi_nor_write_enable(struct spi_nor *nor, bool enable) {
    if (nor && nor->ops) {
        return ((flash_ops_t*)(nor->ops))->fls_write_enable(nor, enable);
    }
    return SDRV_STATUS_INVALID_PARAM;
}
 
//void *spi_nor_host_init(const struct spi_nor_host_config *host_config);
 
static inline int sdrv_spi_nor_init(struct spi_nor *flash_handle, struct spi_nor_host *host,
                      const struct spi_nor_config *flash_config) {
    int ret = -1;
    if (flash_config->hyperbus_mode) {
#if !(CONFIG_DISABLE_HYPERBUS_COMPILE)
        ret = hyperbus_ops.fls_init(flash_handle, host, flash_config);
#endif
    } else {
#if !(CONFIG_DISABLE_SPIBUS_COMPILE)
        ret = spi_nor_ops.fls_init(flash_handle, host, flash_config);
#endif
    }
    return ret;
}
 
static inline void sdrv_spi_nor_deinit(struct spi_nor *flash_handle) {
    if (flash_handle && flash_handle->ops) {
        ((flash_ops_t*)(flash_handle->ops))->fls_deinit(flash_handle);
    }
}
 
static inline int sdrv_spi_nor_read(struct spi_nor *flash_handle, flash_addr_t addr,
                      uint8_t *buf,
                      flash_size_t size) {
    if (flash_handle && flash_handle->ops) {
        return ((flash_ops_t*)(flash_handle->ops))->fls_read(flash_handle, addr, buf, size);
    }
    return SDRV_STATUS_INVALID_PARAM;
}
 
static inline int sdrv_spi_nor_write(struct spi_nor *flash_handle, flash_addr_t addr,
                       const uint8_t *buf, flash_size_t size) {
    if (flash_handle && flash_handle->ops) {
        return ((flash_ops_t*)(flash_handle->ops))->fls_write(flash_handle, addr, buf, size);
    }
    return SDRV_STATUS_INVALID_PARAM;
}
static inline int sdrv_spi_nor_erase(struct spi_nor *flash_handle, flash_addr_t addr,
                       flash_size_t size) {
    if (flash_handle && flash_handle->ops) {
        return ((flash_ops_t*)(flash_handle->ops))->fls_erase(flash_handle, addr, size);
    }
    return SDRV_STATUS_INVALID_PARAM;
}
 
static inline int sdrv_spi_nor_cancel(struct spi_nor *flash_handle) {
    if (flash_handle && flash_handle->ops) {
        return ((flash_ops_t*)(flash_handle->ops))->fls_cancel(flash_handle);
    }
    return SDRV_STATUS_INVALID_PARAM;
}
 
static inline void sdrv_spi_nor_main_function(struct spi_nor *flash_handle) {
    if (flash_handle && flash_handle->ops) {
        ((flash_ops_t*)(flash_handle->ops))->fls_main_function(flash_handle);
    }
}
 
static inline void sdrv_spi_nor_setup_handler(struct spi_nor *flash_handle,
        flash_notification handler)
{
    flash_handle->event_handler = handler;
    return;
}
 
static inline enum flash_opt_result sdrv_spi_nor_get_result(
    struct spi_nor *flash_handle)
{
    if (flash_handle) {
        return flash_handle->xfer_info.opt_result;
    }
    else {
        return FLASH_OPT_INVALID;
    }
}
 
static inline struct flash_info *sdrv_spi_nor_get_info(struct spi_nor
        *flash_handle)
{
    if (flash_handle) {
        return &(flash_handle->info);
    }
    else {
        return NULL;
    }
}
 
static inline int sdrv_spi_nor_enable_rfd(struct spi_nor *flash_handle, uint8_t mask) {
    int ret;
    if (flash_handle && flash_handle->host->ops->enable_rfd) {
        flash_handle->host->ops->prepare(flash_handle, SPI_NOR_OPS_LOCK);
        ret = flash_handle->host->ops->enable_rfd(flash_handle, mask);
        flash_handle->host->ops->unprepare(flash_handle, SPI_NOR_OPS_LOCK);
        if (ret) {
            return SDRV_STATUS_FAIL;
        }
    } else {
        return SDRV_STATUS_INVALID_PARAM;
    }
    return SDRV_STATUS_OK;
}
 
static inline const struct flash_info *sdrv_spi_nor_get_flash_table(
    bool is_hyperbus, uint32_t *num) {
    const struct flash_info *ret = NULL;
    if (!num) {
        return NULL;
    }
    if (is_hyperbus) {
#if !(CONFIG_DISABLE_HYPERBUS_COMPILE)
        ret = hyperbus_ops.fls_get_flash_table(num);
#endif
    } else {
#if !(CONFIG_DISABLE_SPIBUS_COMPILE)
        ret = spi_nor_ops.fls_get_flash_table(num);
#endif
    }
    return ret;
}
 
static inline struct spi_nor *sdrv_get_flash_handle(struct spi_nor_host *host,
        flash_addr_t addr, flash_size_t size) {
    struct spi_nor *nor;
    for (uint8_t i = 0; i < SWITCH_DEVICE_MAX_NUM ; i++) {
        nor = host->nor_tab[i];
        if (!nor) {
            continue;
        }
        if ((addr >= nor->offset_address) &&
             (addr + size) <= (nor->offset_address + nor->info.size)) {
            return nor;
        }
    }
    return NULL;
}
 
static inline int sdrv_host_read(struct spi_nor_host *host, flash_addr_t addr,
                        uint8_t *buf, flash_size_t size) {
    struct spi_nor *flash_handle = sdrv_get_flash_handle(host, addr, size);
    if (flash_handle) {
        addr -= flash_handle->offset_address;
        return sdrv_spi_nor_read(flash_handle, addr, buf, size);
    }
    return SDRV_STATUS_FAIL;
}
 
static inline int sdrv_host_erase(struct spi_nor_host *host, flash_addr_t addr,
                        flash_size_t size) {
    struct spi_nor *flash_handle = sdrv_get_flash_handle(host, addr, size);
    if (flash_handle) {
        addr -= flash_handle->offset_address;
        return sdrv_spi_nor_erase(flash_handle, addr, size);
    }
    return SDRV_STATUS_FAIL;
}
 
static inline int sdrv_host_write(struct spi_nor_host *host, flash_addr_t addr,
                       const uint8_t *buf, flash_size_t size) {
    struct spi_nor *flash_handle = sdrv_get_flash_handle(host, addr, size);
    if (flash_handle) {
        addr -= flash_handle->offset_address;
        return sdrv_spi_nor_write(flash_handle, addr, buf, size);
    }
    return SDRV_STATUS_FAIL;
}
 
#ifdef __cplusplus
}
#endif
#endif /* SDRV_SPI_NOR_H_ */