sdrv_pmu.h

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#ifndef SDRV_PMU_DRV_H_
#define SDRV_PMU_DRV_H_
 
#include <sdrv_common.h>
#include <types.h>
#include <part.h>
 
#define SDRV_PMU_WAKEUP_PIN0_MASK  (0X1U)
#define SDRV_PMU_WAKEUP_PIN1_MASK  (0X2U)
#define SDRV_PMU_WAKEUP_RTC_MASK   (0X4U)
#define SDRV_PMU_WAKEUP_BC_MASK    (0X8U)
 
enum sdrv_pmu_error {
    SDRV_PMU_CONFIG_TYPE_WRONG = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_PMU, 0),
    SDRV_PMU_CONFIG_NOT_SUPPORT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_PMU, 1),
};
 
#if CONFIG_E3 || CONFIG_D3
enum srcs_bit {
    SRCS_RSTGEN_SF_I_IST_EN_RTC_OVRD = 0U,
    SRCS_RSTGEN_SF_I_IST_EN_RTC_OVVAL = 1U,
    SRCS_ISTC_RTC_SS_POST_EN_OVVAL = 2U,
    SRCS_ISTC_RTC_SS_POST_EN_OVRD = 3U,
    SRCS_ISTC_PLL_CFG_POST_EN_OVVAL = 4U,
    SRCS_ISTC_PLL_CFG_POST_EN_OVRD = 8U,
    SRCS_ISTC_POWER_CFG_POST_EN_OVVAL = 9U,
    SRCS_ISTC_POWER_CFG_POST_EN_OVRD = 13U,
    SRCS_PT_SNS_SF_PT_SNS_AP_CVEN33_FORCE_OFF = 14U,
    SRCS_ANA_SF_ANALOG_IP_CVEN33_FORCE_OFF = 15U,
    SRCS_DCDC_ISO_EN_B = 16U,
    SRCS_LDO_ISO_EN_B = 17U,
    SRCS_BGR_LDO_AUTO_DISABLE_BY_PMU_EN = 18U,
    SRCS_BGR_SF_AUTO_DISABLE_BY_SMC_EN = 19U,
    SRCS_WAKEUP0_FALL_EDGE_TO_PULSE_EN = 20U,
    SRCS_POR_SF_PU33_B = 21U,
    SRCS_RC24M_PU33_B = 22U,
    SRCS_VD_SF_PU33_B = 23U,
    SRCS_BGR_ANA_PU33_B = 24U,
    SRCS_BGR_SF_PU33_B = 25U,
    SRCS_BGR_LDO_PU33_B = 26U,
    SRCS_POR_AP_PU33_B = 27U,
    SRCS_VD_AP_PU33_B = 28U,
    SRCS_BGR_AP_PU33_B = 29U,
    SRCS_BGR_DISP_PU33_B = 30U,
    SRCS_WAKEUP0_RISE_EDGE_TO_PULSE_EN = 31U,
};
#endif
 
#if CONFIG_E3L
enum srcs_bit {
    SRCS_RSTGEN_SF_I_IST_EN_RTC_OVRD = 0U,
    SRCS_RSTGEN_SF_I_IST_EN_RTC_OVVAL = 1U,
    SRCS_ISTC_RTC_SS_POST_EN_OVVAL = 2U,
    SRCS_ISTC_RTC_SS_POST_EN_OVRD = 3U,
    SRCS_ISTC_PLL_CFG_POST_EN_OVVAL = 4U,
    SRCS_ISTC_PLL_CFG_POST_EN_OVRD = 8U,
    SRCS_ISTC_POWER_CFG_POST_EN_OVVAL = 9U,
    SRCS_ISTC_POWER_CFG_POST_EN_OVRD = 13U,
    SRCS_DCDC_ISO_EN_B = 16U,
    SRCS_SCR_CFG_LATCH_EN = 17U,
    SRCS_BGR_SF_AUTO_DISABLE_BY_SMC_EN = 19U,
    SRCS_WAKEUP0_FALL_EDGE_TO_PULSE_EN = 20U,
    SRCS_POR_SF_PU33_B = 21U,
    SRCS_RC24M_PU33_B = 22U,
    SRCS_VD_SF_PU33_B = 23U,
    SRCS_BGR_ANA_PU33_B = 24U,
    SRCS_BGR_SF_PU33_B = 25U,
    SRCS_SADC1_CVEN33 = 26U,
    SRCS_SACMP1_CVEN33 = 27U,
    SRCS_APAD_CVEN33_B0_B1 = 28U,
    SRCS_APAD_CVEN33_B2_B8 = 29U,
    SRCS_OTHER_CVEN33 = 30U,
    SRCS_WAKEUP0_RISE_EDGE_TO_PULSE_EN = 31U,
};
#endif
 
typedef enum sdrv_pmu_polarity {
    SDRV_PMU_HIGH_LEVEL = 0,
    SDRV_PMU_LOW_LEVEL,
    SDRV_PMU_RISING_EDGE,
    SDRV_PMU_FALLING_EDGE,
} sdrv_pmu_polarity_e;
 
typedef enum sdrv_pmu_edge_filter_enum {
    SDRV_PMU_FILTER_RISING = 0,
    SDRV_PMU_FILTER_FALLING,
    SDRV_PMU_FILTER_BOTH_EDGE,
} sdrv_pmu_edge_filter_e;
 
typedef enum sdrv_pmu_wakeup_pin {
    SDRV_PMU_WAKEUP_PIN_0 = 0,
    SDRV_PMU_WAKEUP_PIN_1,
} sdrv_pmu_wakeup_pin_e;
 
typedef enum sdrv_pmu_wakeup_glitch {
    SDRV_PMU_GLITCH_NONE    = 0,
    SDRV_PMU_GLITCH_RISING  = 1,
    SDRV_PMU_GLITCH_FALLING = 2,
    SDRV_PMU_GLITCH_BOTH    = 3,
} sdrv_pmu_wakeup_glitch_e;
 
typedef enum sdrv_pmu_wakeup_pin_logic {
    SDRV_PMU_WAKEUP_PIN_OR = 0,  
    SDRV_PMU_WAKEUP_PIN_AND,  
} sdrv_pmu_wakeup_pin_logic_e;
 
typedef enum sdrv_pmu_wakeup_in_rtc {
    SDRV_PMU_WAKEUP_IN_RTC_IGNORE = 0,  
    SDRV_PMU_WAKEUP_IN_RTC_LATCH,  
} sdrv_pmu_wakeup_in_rtc_e;
 
typedef enum sdrv_pmu_mode {
    SDRV_PMU_RUN = 0,
    SDRV_PMU_SLEEP,
    SDRV_PMU_HIBERNATE,
    SDRV_PMU_RTC,
} sdrv_pmu_mode_e;
 
typedef enum sdrv_pmu_delay_period {
    SDRV_PMU_PWRUP_DELAY = 0,
    SDRV_PMU_RUN_DELAY,
    SDRV_PMU_SLEEP_DELAY,
    SDRV_PMU_HIB_DELAY,
    SDRV_PMU_RTC_DELAY,
} sdrv_pmu_delay_period_e;
 
typedef enum sdrv_pmu_state {
    SDRV_PMU_STATE_PWR_ON = 0,
    SDRV_PMU_STATE_PWRUP_RUN,
    SDRV_PMU_STATE_SLEEP_RUN,
    SDRV_PMU_STATE_HIBERNATE_RUN,
} sdrv_pmu_state_e;
 
typedef enum sdrv_pmu_ctrl {
    SDRV_PMU_CTRL_OFF = 0,
    SDRV_PMU_CTRL_ON,
} sdrv_pmu_ctrl_e;
 
typedef enum sdrv_pmu_operate {
    SDRV_PMU_MANUAL = 0,
    SDRV_PMU_AUTO,
} sdrv_pmu_operate_e;
 
typedef enum sdrv_pmu_pwr_ctrl_polarity {
    SDRV_PMU_PWR_CTRL_HIGH_ACTIVE = 0,
    SDRV_PMU_PWR_CTRL_LOW_ACTIVE,
} sdrv_pmu_pwr_ctrl_polarity_e;
 
typedef enum sdrv_pmu_pwr_ctrl {
    SDRV_PMU_PWR_CTRL_0 = 0,
    SDRV_PMU_PWR_CTRL_1,
    SDRV_PMU_PWR_CTRL_2,
    SDRV_PMU_PWR_CTRL_3,
} sdrv_pmu_pwr_ctrl_e;
 
typedef enum sdrv_pmu_pwr_on {
    SDRV_PMU_PWR_ON_0 = 0,
    SDRV_PMU_PWR_ON_1,
    SDRV_PMU_PWR_ON_2,
    SDRV_PMU_PWR_ON_3,
} sdrv_pmu_pwr_on_e;
 
typedef enum sdrv_pmu_target {
    SDRV_PMU_SAF = 0,
    SDRV_PMU_AP,
    SDRV_PMU_OTHER,
} sdrv_pmu_target_e;
 
typedef enum sdrv_pmu_pg {
    SDRV_PMU_POWER_GOOD_ENABLE = 0,
    SDRV_PMU_POWER_GOOD_DISABLE,
} sdrv_pmu_pg_e;
 
typedef enum sdrv_pmu_wakeup_src {
    SDRV_PMU_WAKEUP_BY_BC = 0x1U,
    SDRV_PMU_WAKEUP_BY_RTC = 0x2U,
    SDRV_PMU_WAKEUP_BY_PIN = 0x4U,
    SDRV_PMU_WAKEUP_BY_HW_RESET = 0x8U,
} sdrv_pmu_wakeup_src_e;
 
typedef enum sdrv_pmu_hw_power_down_req {
    SDRV_PMU_SEM_INT_POWER_DOWN_REQ = 0x1U,
    SDRV_PMU_RESERVED_POWER_DOWN_REQ = 0x2U,
    SDRV_PMU_FS32K_LVPG_POWER_DOWN_REQ = 0x4U,
    SDRV_PMU_VD_SF_INT_POWER_DOWN_REQ = 0x8U,
    SDRV_PMU_VD_AP_INT_POWER_DOWN_REQ = 0x10U,
    SDRV_PMU_SF_PT_SENSOR_INT_POWER_DOWN_REQ = 0x20U,
    SDRV_PMU_AP_PT_SENSOR_INT_POWER_DOWN_REQ = 0x40U,
    SDRV_PMU_EFUSE_VIO_POWER_DOWN_REQ = 0x80U,
} sdrv_pmu_hw_power_down_req_e;
 
typedef enum sdrv_pmu_power_down_reason {
    SDRV_PMU_POWER_DOWN_SMC_CHECK_FAIL = 0U,
    SDRV_PMU_POWER_DOWN_RESERVED,
    SDRV_PMU_POWER_DOWN_SEM_INT,
    SDRV_PMU_POWER_DOWN_RESERVED_1,
    SDRV_PMU_POWER_DOWN_FS32K_LVPG,
    SDRV_PMU_POWER_DOWN_VD_SF_INT,
    SDRV_PMU_POWER_DOWN_VD_AP_INT,
    SDRV_PMU_POWER_DOWN_SF_PT_SENSOR_INT,
    SDRV_PMU_POWER_DOWN_AP_PT_SENSOR_INT,
    SDRV_PMU_POWER_DOWN_EFUSE_VIO,
    SDRV_PMU_POWER_DOWN_SOFTWARE,
    SDRV_PMU_POWER_DOWN_BC,
} sdrv_pmu_power_down_reason_e;
 
typedef enum sdrv_pmu_int_type {
    SDRV_PMU_INT_PWRON0_RDY_TIMEOUT   = 1U << 0U,
    SDRV_PMU_INT_PWRON2_RDY_TIMEOUT   = 1U << 2U,
    SDRV_PMU_INT_PWRUP_TO_RUN_TIMEOUT = 1U << 4U,
    SDRV_PMU_INT_SLEEP_TO_RUN_TIMEOUT = 1U << 5U,
    SDRV_PMU_INT_HIBERNATE_TO_RUN_TIMEOUT = 1U << 6U,
    SDRV_PMU_INT_LOCKSTEP_ERR             = 1U << 7U,
    SDRV_PMU_INT_SWM_WARN                 = 1U << 10U,
    SDRV_PMU_INT_SWM_FATAL                = 1U << 11U,
    SDRV_PMU_INT_POWER_DOWN_REQ           = 1U << 12U,
} sdrv_pmu_int_type_e;
 
typedef struct sdrv_pmu_edge_filter {
    bool enable_filter;          
    uint8_t filter_sample_interval; 
    uint8_t filter_count;        
    sdrv_pmu_edge_filter_e filter_type; 
} sdrv_pmu_edge_filter_t;
 
typedef struct sdrv_pmu_level_filter {
    uint8_t min_window_for_on;
    uint8_t max_window_for_on;
    uint8_t min_window_for_off;
    uint8_t max_window_for_off;
} sdrv_pmu_level_filter_t;
 
typedef struct sdrv_pmu_level_filter_enable {
    uint8_t bc_cnt_unit;  
    bool max_window_for_on_en;
    bool max_window_for_off_en;
} sdrv_pmu_level_filter_enable_t;
 
typedef struct sdrv_pmu_bc_config {
    sdrv_pmu_polarity_e bc_off_pol;     
    sdrv_pmu_polarity_e bc_on_pol;      
} sdrv_pmu_bc_config_t;
 
typedef struct sdrv_pmu_wakeup_pin_config {
    sdrv_pmu_polarity_e pin_pol; 
} sdrv_pmu_wakeup_pin_config_t;
 
typedef struct sdrv_pmu_wakeuppins_config {
    sdrv_pmu_wakeup_pin_logic_e logic;
    sdrv_pmu_wakeup_in_rtc_e latch;
 
    bool wakepin0_en;
    sdrv_pmu_wakeup_glitch_e wakepin0_glitch;
    sdrv_pmu_polarity_e wakepin0_pol;
    sdrv_pmu_edge_filter_t wakepin0_filter;
 
    bool wakepin1_en;
    sdrv_pmu_polarity_e wakepin1_pol;
    sdrv_pmu_edge_filter_t wakepin1_filter;
} sdrv_pmu_wakeuppins_config_t;
 
typedef struct sdrv_pmu_buttonctrl_config {
    sdrv_pmu_bc_config_t polarity;
    sdrv_pmu_edge_filter_t edge_filter;
    sdrv_pmu_level_filter_enable_t level_filter_en;
    sdrv_pmu_level_filter_t level_filter_para;
    bool fsm_enable;
} sdrv_pmu_buttonctrl_config_t;
 
typedef struct sdrv_pmu_pwron_wdt_config {
    uint8_t por_tw; 
    uint8_t por_tw_adj; 
    uint8_t wdt_div; 
} sdrv_pmu_pwron_wdt_config_t;
 
typedef struct sdrv_pmu_pwron_wdt_enable {
    bool pwron_wdt_en; 
    uint8_t wdt_counter; 
} sdrv_pmu_pwron_wdt_enable_t;
 
typedef struct sdrv_pmu_pwrctrl_config {
    sdrv_pmu_ctrl_e ctrl_status;  
    sdrv_pmu_operate_e ctrl_operate;  
} sdrv_pmu_pwrctrl_config_t;
 
typedef struct sdrv_pmu_pwrctrl_min_delay_config {
    bool pwrup_run_min_delay_en;
    bool sleep_run_min_delay_en;
    bool hibernate_run_min_delay_en;
} sdrv_pmu_pwrctrl_min_delay_config_t;
 
typedef struct sdrv_pmu_pwron_config {
    sdrv_pmu_ctrl_e ctrl_status;  
    sdrv_pmu_operate_e ctrl_operate;  
} sdrv_pmu_pwron_config_t;
 
status_t sdrv_pmu_wakeup_enable(uint32_t enable_bitmap);
 
status_t sdrv_pmu_wakeup_disable(uint32_t disable_bitmap);
 
status_t sdrv_pmu_button_control_init(sdrv_pmu_bc_config_t *bc_config);
 
status_t sdrv_pmu_button_control_edge_filter_config(sdrv_pmu_edge_filter_t *filter_config);
 
status_t sdrv_pmu_button_control_level_filter_para(sdrv_pmu_level_filter_t *filter_config);
 
status_t sdrv_pmu_button_control_level_filter_config(sdrv_pmu_level_filter_enable_t *filter_config);
 
status_t sdrv_pmu_hardware_power_down_request_enable(uint32_t enable_bitmap, bool enable);
 
status_t sdrv_pmu_button_control_enable(bool enable);
 
status_t sdrv_pmu_button_control_fsm_enable(bool enable);
 
status_t sdrv_pmu_button_control_config(sdrv_pmu_buttonctrl_config_t *config);
 
status_t sdrv_pmu_wakeup_pin_init(sdrv_pmu_wakeup_pin_e wakeup_pin, sdrv_pmu_wakeup_pin_config_t *pin_config);
 
status_t sdrv_pmu_wakeup_pin_filter_config(sdrv_pmu_wakeup_pin_e wakeup_pin, sdrv_pmu_edge_filter_t *filter_config);
 
status_t sdrv_pmu_wakeup_pin_enable(sdrv_pmu_wakeup_pin_e wakeup_pin, bool enable);
 
status_t sdrv_pmu_wakeup_pin_logic_set(sdrv_pmu_wakeup_pin_logic_e logic);
 
status_t sdrv_pmu_wakeup_latch_set(sdrv_pmu_wakeup_in_rtc_e latch);
 
status_t sdrv_pmu_wakeup_pins_config(sdrv_pmu_wakeuppins_config_t *config);
 
status_t sdrv_pmu_power_down(void);
 
status_t sdrv_pmu_pwron_watchdog_config(sdrv_pmu_pwron_wdt_config_t *wdt_config);
 
status_t sdrv_pmu_pwron_watchdog_enable(sdrv_pmu_pwr_on_e pwron, sdrv_pmu_pwron_wdt_enable_t *enable_config);
 
status_t sdrv_pmu_pwrctrl_config(sdrv_pmu_pwr_ctrl_e ctrl, sdrv_pmu_mode_e mode, sdrv_pmu_pwrctrl_config_t *config);
 
status_t sdrv_pmu_pwrctrl_min_delay_config(sdrv_pmu_pwrctrl_min_delay_config_t *config);
 
status_t sdrv_pmu_pwrctrl_polarity_config(sdrv_pmu_pwr_ctrl_e ctrl, sdrv_pmu_pwr_ctrl_polarity_e pol);
 
status_t sdrv_pmu_pwrctrl_software_override_enable(sdrv_pmu_pwr_ctrl_e ctrl, bool enable);
 
status_t sdrv_pmu_pwrctrl_software_override_value(sdrv_pmu_pwr_ctrl_e ctrl, bool value);
 
status_t sdrv_pmu_pwrctrl_delay_config(sdrv_pmu_delay_period_e period, sdrv_pmu_pwr_ctrl_e ctrl, uint8_t delay, uint8_t delay_adj);
 
status_t sdrv_pmu_pwron_config(sdrv_pmu_pwr_on_e ctrl, sdrv_pmu_mode_e mode, sdrv_pmu_pwron_config_t *config);
 
status_t sdrv_pmu_pwron_target_config_with_mode(sdrv_pmu_pwr_on_e ctrl, sdrv_pmu_mode_e mode, sdrv_pmu_target_e target);
 
status_t sdrv_pmu_pwron_target_config(sdrv_pmu_pwr_on_e ctrl, sdrv_pmu_target_e target);
 
status_t sdrv_pmu_target_power_on_config(sdrv_pmu_target_e target, sdrv_pmu_mode_e mode, bool powered);
 
status_t sdrv_pmu_pwron_delay_config(sdrv_pmu_delay_period_e period, sdrv_pmu_pwr_on_e ctrl, uint8_t delay, uint8_t delay_adj);
 
status_t sdrv_pmu_pwron_software_override_enable(sdrv_pmu_pwr_on_e ctrl, bool enable);
 
status_t sdrv_pmu_pwron_software_override_value(sdrv_pmu_pwr_on_e ctrl, bool value);
 
status_t sdrv_pmu_minimal_delay_for_state_transition(sdrv_pmu_state_e state, uint8_t delay, uint8_t delay_adj);
 
status_t sdrv_pmu_interrupt_enable(uint32_t bitmap, bool enable);
 
uint32_t sdrv_pmu_get_interrupt_status(void);
 
status_t sdrv_pmu_clear_interrupt_status(uint32_t bitmap);
 
status_t sdrv_pmu_srcs_set(uint32_t bitmap);
 
status_t sdrv_pmu_srcs_clear(uint32_t bitmap);
 
status_t sdrv_pmu_vd_sf_ana_enable(bool enable);
 
status_t sdrv_pmu_por_sf_enable(bool enable);
 
status_t sdrv_pmu_rc24m_enable(bool enable);
 
status_t sdrv_pmu_bgr_sf_enable(bool enable);
 
status_t sdrv_pmu_bgr_ldo_enable(bool enable);
 
status_t sdrv_pmu_bgr_ana_sf1_sf2_enable(bool enable);
 
status_t sdrv_pmu_vd_ap_enable(bool enable);
 
status_t sdrv_pmu_por_ap_enable(bool enable);
 
status_t sdrv_pmu_bgr_ap_enable(bool enable);
 
status_t sdrv_pmu_bgr_disp_enable(bool enable);
 
status_t sdrv_pmu_analog_cven33_enable(bool enable);
 
status_t sdrv_pmu_pt_sns_enable(bool enable);
 
status_t sdrv_pmu_ana_sf_analog_enable(bool enable);
 
status_t sdrv_pmu_bgr_ldo_auto_disable(bool enable);
 
status_t sdrv_pmu_bgr_sf_auto_disable(bool enable);
 
status_t sdrv_pmu_wakeup0_glitch_enable(uint32_t mask);
 
status_t sdrv_pmu_wakeup0_glitch_disable(uint32_t mask);
 
status_t sdrv_pmu_saf_domain_power_good_monitor(sdrv_pmu_pg_e cfg);
 
status_t sdrv_pmu_ap_domain_power_good_monitor(sdrv_pmu_pg_e cfg);
 
status_t sdrv_pmu_rtc_to_off_saf_domain_power_good(sdrv_pmu_pg_e cfg);
 
status_t sdrv_pmu_rtc_to_off_ap_domain_power_good(sdrv_pmu_pg_e cfg);
 
uint32_t sdrv_pmu_get_wakeup_source(void);
 
status_t sdrv_pmu_clear_wakeup_source(void);
 
uint32_t sdrv_pmu_get_power_down_reason(void);
 
status_t sdrv_pmu_clear_power_down_reason(void);
 
uint32_t sdrv_pmu_get_state(void);
 
#endif /* SDRV_PMU_DRV_H_ */