/******************************************************** * Copyright(c) 2021 Semidrive * ********************************************************/ /* Generated by tool. Do not modify manually. */ #ifndef __FUSE_CTRL_REG_H__ #define __FUSE_CTRL_REG_H__ #define FUSE_CTRL_OFF 0x0U #define FM_FUSE_CTRL_PROG_KEY (0xffffU << 16U) #define FV_FUSE_CTRL_PROG_KEY(v) (((v) << 16U) & FM_FUSE_CTRL_PROG_KEY) #define GFV_FUSE_CTRL_PROG_KEY(v) (((v)&FM_FUSE_CTRL_PROG_KEY) >> 16U) #define BM_FUSE_CTRL_RED_COR (0x01U << 12U) #define BM_FUSE_CTRL_ERROR (0x01U << 11U) #define BM_FUSE_CTRL_BUSY (0x01U << 10U) #define BM_FUSE_CTRL_PECCFG (0x01U << 9U) #define BM_FUSE_CTRL_PECCB (0x01U << 8U) #define FM_FUSE_CTRL_ADDR (0xffU << 0U) #define FV_FUSE_CTRL_ADDR(v) (((v) << 0U) & FM_FUSE_CTRL_ADDR) #define GFV_FUSE_CTRL_ADDR(v) (((v)&FM_FUSE_CTRL_ADDR) >> 0U) #define PROG_DATA_OFF 0x4U #define FM_PROG_DATA_DATA (0xffffffffU << 0U) #define FV_PROG_DATA_DATA(v) (((v) << 0U) & FM_PROG_DATA_DATA) #define GFV_PROG_DATA_DATA(v) (((v)&FM_PROG_DATA_DATA) >> 0U) #define FUSE_TRIG_OFF 0x8U #define BM_FUSE_TRIG_BURST_RD (0x01U << 6U) #define BM_FUSE_TRIG_REPAIR_PROGRAM (0x01U << 5U) #define BM_FUSE_TRIG_REPAIR_CHECK (0x01U << 4U) #define BM_FUSE_TRIG_REPAIR_MARGIN_READ (0x01U << 3U) #define BM_FUSE_TRIG_LOAD (0x01U << 2U) #define BM_FUSE_TRIG_PROG (0x01U << 1U) #define BM_FUSE_TRIG_READ (0x01U << 0U) #define READ_FUSE_DATA_OFF 0xcU #define FM_READ_FUSE_DATA_DATA (0xffffffffU << 0U) #define FV_READ_FUSE_DATA_DATA(v) (((v) << 0U) & FM_READ_FUSE_DATA_DATA) #define GFV_READ_FUSE_DATA_DATA(v) (((v)&FM_READ_FUSE_DATA_DATA) >> 0U) #define FUSE_TEST_CFG_OFF 0x10U #define BM_FUSE_TEST_CFG_PTC (0x01U << 5U) #define BM_FUSE_TEST_CFG_PTR (0x01U << 4U) #define FM_FUSE_TEST_CFG_PTM (0xfU << 0U) #define FV_FUSE_TEST_CFG_PTM(v) (((v) << 0U) & FM_FUSE_TEST_CFG_PTM) #define GFV_FUSE_TEST_CFG_PTM(v) (((v)&FM_FUSE_TEST_CFG_PTM) >> 0U) #define FUSE_PWR_UP_TIMING_OFF 0x20U #define FM_FUSE_PWR_UP_TIMING_TSAS_CNT (0x3ffU << 20U) #define FV_FUSE_PWR_UP_TIMING_TSAS_CNT(v) \ (((v) << 20U) & FM_FUSE_PWR_UP_TIMING_TSAS_CNT) #define GFV_FUSE_PWR_UP_TIMING_TSAS_CNT(v) \ (((v)&FM_FUSE_PWR_UP_TIMING_TSAS_CNT) >> 20U) #define FM_FUSE_PWR_UP_TIMING_TPLS_CNT (0xfffU << 8U) #define FV_FUSE_PWR_UP_TIMING_TPLS_CNT(v) \ (((v) << 8U) & FM_FUSE_PWR_UP_TIMING_TPLS_CNT) #define GFV_FUSE_PWR_UP_TIMING_TPLS_CNT(v) \ (((v)&FM_FUSE_PWR_UP_TIMING_TPLS_CNT) >> 8U) #define FM_FUSE_PWR_UP_TIMING_TPENS_CNT (0xffU << 0U) #define FV_FUSE_PWR_UP_TIMING_TPENS_CNT(v) \ (((v) << 0U) & FM_FUSE_PWR_UP_TIMING_TPENS_CNT) #define GFV_FUSE_PWR_UP_TIMING_TPENS_CNT(v) \ (((v)&FM_FUSE_PWR_UP_TIMING_TPENS_CNT) >> 0U) #define FUSE_STB_TIMING_OFF 0x24U #define FM_FUSE_STB_TIMING_TSTB_CNT (0xffffffffU << 0U) #define FV_FUSE_STB_TIMING_TSTB_CNT(v) \ (((v) << 0U) & FM_FUSE_STB_TIMING_TSTB_CNT) #define GFV_FUSE_STB_TIMING_TSTB_CNT(v) \ (((v)&FM_FUSE_STB_TIMING_TSTB_CNT) >> 0U) #define FUSE_IPEN_RD_TIMING_OFF 0x28U #define FM_FUSE_IPEN_RD_TIMING_TIPEN_CNT (0x3ffU << 22U) #define FV_FUSE_IPEN_RD_TIMING_TIPEN_CNT(v) \ (((v) << 22U) & FM_FUSE_IPEN_RD_TIMING_TIPEN_CNT) #define GFV_FUSE_IPEN_RD_TIMING_TIPEN_CNT(v) \ (((v)&FM_FUSE_IPEN_RD_TIMING_TIPEN_CNT) >> 22U) #define FM_FUSE_IPEN_RD_TIMING_TASH_CNT (0x3U << 20U) #define FV_FUSE_IPEN_RD_TIMING_TASH_CNT(v) \ (((v) << 20U) & FM_FUSE_IPEN_RD_TIMING_TASH_CNT) #define GFV_FUSE_IPEN_RD_TIMING_TASH_CNT(v) \ (((v)&FM_FUSE_IPEN_RD_TIMING_TASH_CNT) >> 20U) #define FM_FUSE_IPEN_RD_TIMING_TASP_CNT (0x3U << 18U) #define FV_FUSE_IPEN_RD_TIMING_TASP_CNT(v) \ (((v) << 18U) & FM_FUSE_IPEN_RD_TIMING_TASP_CNT) #define GFV_FUSE_IPEN_RD_TIMING_TASP_CNT(v) \ (((v)&FM_FUSE_IPEN_RD_TIMING_TASP_CNT) >> 18U) #define FM_FUSE_IPEN_RD_TIMING_TAS_CNT (0x3U << 16U) #define FV_FUSE_IPEN_RD_TIMING_TAS_CNT(v) \ (((v) << 16U) & FM_FUSE_IPEN_RD_TIMING_TAS_CNT) #define GFV_FUSE_IPEN_RD_TIMING_TAS_CNT(v) \ (((v)&FM_FUSE_IPEN_RD_TIMING_TAS_CNT) >> 16U) #define FM_FUSE_IPEN_RD_TIMING_TCS_CNT (0xfffU << 4U) #define FV_FUSE_IPEN_RD_TIMING_TCS_CNT(v) \ (((v) << 4U) & FM_FUSE_IPEN_RD_TIMING_TCS_CNT) #define GFV_FUSE_IPEN_RD_TIMING_TCS_CNT(v) \ (((v)&FM_FUSE_IPEN_RD_TIMING_TCS_CNT) >> 4U) #define FM_FUSE_IPEN_RD_TIMING_TRD_CNT (0xfU << 0U) #define FV_FUSE_IPEN_RD_TIMING_TRD_CNT(v) \ (((v) << 0U) & FM_FUSE_IPEN_RD_TIMING_TRD_CNT) #define GFV_FUSE_IPEN_RD_TIMING_TRD_CNT(v) \ (((v)&FM_FUSE_IPEN_RD_TIMING_TRD_CNT) >> 0U) #define FUSE_PG_TIMING_OFF 0x2cU #define FM_FUSE_PG_TIMING_TPWI_CNT (0xffU << 24U) #define FV_FUSE_PG_TIMING_TPWI_CNT(v) \ (((v) << 24U) & FM_FUSE_PG_TIMING_TPWI_CNT) #define GFV_FUSE_PG_TIMING_TPWI_CNT(v) (((v)&FM_FUSE_PG_TIMING_TPWI_CNT) >> 24U) #define FM_FUSE_PG_TIMING_TPM_CNT (0x7ffU << 13U) #define FV_FUSE_PG_TIMING_TPM_CNT(v) (((v) << 13U) & FM_FUSE_PG_TIMING_TPM_CNT) #define GFV_FUSE_PG_TIMING_TPM_CNT(v) (((v)&FM_FUSE_PG_TIMING_TPM_CNT) >> 13U) #define FM_FUSE_PG_TIMING_TPW_CNT (0x1fffU << 0U) #define FV_FUSE_PG_TIMING_TPW_CNT(v) (((v) << 0U) & FM_FUSE_PG_TIMING_TPW_CNT) #define GFV_FUSE_PG_TIMING_TPW_CNT(v) (((v)&FM_FUSE_PG_TIMING_TPW_CNT) >> 0U) #define FUSE_REPAIR_TIMING_OFF 0x30U #define FM_FUSE_REPAIR_TIMING_TTAH_CNT (0x3U << 14U) #define FV_FUSE_REPAIR_TIMING_TTAH_CNT(v) \ (((v) << 14U) & FM_FUSE_REPAIR_TIMING_TTAH_CNT) #define GFV_FUSE_REPAIR_TIMING_TTAH_CNT(v) \ (((v)&FM_FUSE_REPAIR_TIMING_TTAH_CNT) >> 14U) #define FM_FUSE_REPAIR_TIMING_TTAS_CNT (0x3fffU << 0U) #define FV_FUSE_REPAIR_TIMING_TTAS_CNT(v) \ (((v) << 0U) & FM_FUSE_REPAIR_TIMING_TTAS_CNT) #define GFV_FUSE_REPAIR_TIMING_TTAS_CNT(v) \ (((v)&FM_FUSE_REPAIR_TIMING_TTAS_CNT) >> 0U) #define HUK_READY_OFF 0x38U #define BM_HUK_READY_READY (0x01U << 0U) #define FUSA_ERR_INT_STA_OFF 0x80U #define BM_FUSA_ERR_INT_STA_REG_ECC_UNC_ERR (0x01U << 11U) #define BM_FUSA_ERR_INT_STA_REG_ECC_COR_ERR (0x01U << 10U) #define BM_FUSA_ERR_INT_STA_MEM_ECC_UNC_ERR (0x01U << 9U) #define BM_FUSA_ERR_INT_STA_MEM_ECC_COR_ERR (0x01U << 8U) #define BM_FUSA_ERR_INT_STA_LSP_HW_FUSE_CMP_ERR (0x01U << 7U) #define BM_FUSA_ERR_INT_STA_LSP_CMP_ERR (0x01U << 6U) #define BM_FUSA_ERR_INT_STA_INPUT_ERR (0x01U << 5U) #define BM_FUSA_ERR_INT_STA_PUSER_UNC_ERR (0x01U << 4U) #define BM_FUSA_ERR_INT_STA_PCTL_UNC_ERR (0x01U << 3U) #define BM_FUSA_ERR_INT_STA_PADDR_UNC_ERR (0x01U << 2U) #define BM_FUSA_ERR_INT_STA_PWDATA_UNC_ERR (0x01U << 1U) #define BM_FUSA_ERR_INT_STA_PWDATA_COR_ERR (0x01U << 0U) #define FUSA_ERR_INT_STA_EN_OFF 0x84U #define BM_FUSA_ERR_INT_STA_EN_REG_ECC_UNC_ERR (0x01U << 11U) #define BM_FUSA_ERR_INT_STA_EN_REG_ECC_COR_ERR (0x01U << 10U) #define BM_FUSA_ERR_INT_STA_EN_MEM_ECC_UNC_ERR (0x01U << 9U) #define BM_FUSA_ERR_INT_STA_EN_MEM_ECC_COR_ERR (0x01U << 8U) #define BM_FUSA_ERR_INT_STA_EN_LSP_HW_FUSE_CMP_ERR (0x01U << 7U) #define BM_FUSA_ERR_INT_STA_EN_LSP_CMP_ERR (0x01U << 6U) #define BM_FUSA_ERR_INT_STA_EN_INPUT_ERR (0x01U << 5U) #define BM_FUSA_ERR_INT_STA_EN_PUSER_UNC_ERR (0x01U << 4U) #define BM_FUSA_ERR_INT_STA_EN_PCTL_UNC_ERR (0x01U << 3U) #define BM_FUSA_ERR_INT_STA_EN_PADDR_UNC_ERR (0x01U << 2U) #define BM_FUSA_ERR_INT_STA_EN_PWDATA_UNC_ERR (0x01U << 1U) #define BM_FUSA_ERR_INT_STA_EN_PWDATA_COR_ERR (0x01U << 0U) #define FUSA_ERR_INT_SIG_EN_OFF 0x88U #define BM_FUSA_ERR_INT_SIG_EN_REG_ECC_UNC_ERR (0x01U << 11U) #define BM_FUSA_ERR_INT_SIG_EN_REG_ECC_COR_ERR (0x01U << 10U) #define BM_FUSA_ERR_INT_SIG_EN_MEM_ECC_UNC_ERR (0x01U << 9U) #define BM_FUSA_ERR_INT_SIG_EN_MEM_ECC_COR_ERR (0x01U << 8U) #define BM_FUSA_ERR_INT_SIG_EN_LSP_HW_FUSE_CMP_ERR (0x01U << 7U) #define BM_FUSA_ERR_INT_SIG_EN_LSP_CMP_ERR (0x01U << 6U) #define BM_FUSA_ERR_INT_SIG_EN_INPUT_ERR (0x01U << 5U) #define BM_FUSA_ERR_INT_SIG_EN_PUSER_UNC_ERR (0x01U << 4U) #define BM_FUSA_ERR_INT_SIG_EN_PCTL_UNC_ERR (0x01U << 3U) #define BM_FUSA_ERR_INT_SIG_EN_PADDR_UNC_ERR (0x01U << 2U) #define BM_FUSA_ERR_INT_SIG_EN_PWDATA_UNC_ERR (0x01U << 1U) #define BM_FUSA_ERR_INT_SIG_EN_PWDATA_COR_ERR (0x01U << 0U) #define ERR_INJ_OFF 0xa0U #define BM_ERR_INJ_FUSE_READY (0x01U << 5U) #define BM_ERR_INJ_FUSE_LATCHED_PARTIAL (0x01U << 4U) #define FM_ERR_INJ_VIO_O (0x3U << 2U) #define FV_ERR_INJ_VIO_O(v) (((v) << 2U) & FM_ERR_INJ_VIO_O) #define GFV_ERR_INJ_VIO_O(v) (((v)&FM_ERR_INJ_VIO_O) >> 2U) #define BM_ERR_INJ_UNCERR (0x01U << 1U) #define BM_ERR_INJ_CORERR (0x01U << 0U) #define FUSE_OUTPUT_ERR_INJ_OFF 0xa4U #define FM_FUSE_OUTPUT_ERR_INJ_ERR_INJ_BITS (0xffU << 8U) #define FV_FUSE_OUTPUT_ERR_INJ_ERR_INJ_BITS(v) \ (((v) << 8U) & FM_FUSE_OUTPUT_ERR_INJ_ERR_INJ_BITS) #define GFV_FUSE_OUTPUT_ERR_INJ_ERR_INJ_BITS(v) \ (((v)&FM_FUSE_OUTPUT_ERR_INJ_ERR_INJ_BITS) >> 8U) #define FM_FUSE_OUTPUT_ERR_INJ_ERR_INJ_SEL (0x1fU << 0U) #define FV_FUSE_OUTPUT_ERR_INJ_ERR_INJ_SEL(v) \ (((v) << 0U) & FM_FUSE_OUTPUT_ERR_INJ_ERR_INJ_SEL) #define GFV_FUSE_OUTPUT_ERR_INJ_ERR_INJ_SEL(v) \ (((v)&FM_FUSE_OUTPUT_ERR_INJ_ERR_INJ_SEL) >> 0U) #define LSP_CMP_INJ_OFF 0xa8U #define FM_LSP_CMP_INJ_ERR_INJ_BIT (0x7ffU << 2U) #define FV_LSP_CMP_INJ_ERR_INJ_BIT(v) (((v) << 2U) & FM_LSP_CMP_INJ_ERR_INJ_BIT) #define GFV_LSP_CMP_INJ_ERR_INJ_BIT(v) (((v)&FM_LSP_CMP_INJ_ERR_INJ_BIT) >> 2U) #define BM_LSP_CMP_INJ_ERR_INJ_SEL (0x01U << 1U) #define BM_LSP_CMP_INJ_ERR_INJ_EN (0x01U << 0U) #define MEM_RDATA_ERR_INJ_OFF 0xc0U #define FM_MEM_RDATA_ERR_INJ_ERR_INJ (0xffffffffU << 0U) #define FV_MEM_RDATA_ERR_INJ_ERR_INJ(v) \ (((v) << 0U) & FM_MEM_RDATA_ERR_INJ_ERR_INJ) #define GFV_MEM_RDATA_ERR_INJ_ERR_INJ(v) \ (((v)&FM_MEM_RDATA_ERR_INJ_ERR_INJ) >> 0U) #define MEM_RECC_ERR_INJ_OFF 0xc4U #define FM_MEM_RECC_ERR_INJ_ERR_INJ (0x7fU << 0U) #define FV_MEM_RECC_ERR_INJ_ERR_INJ(v) \ (((v) << 0U) & FM_MEM_RECC_ERR_INJ_ERR_INJ) #define GFV_MEM_RECC_ERR_INJ_ERR_INJ(v) \ (((v)&FM_MEM_RECC_ERR_INJ_ERR_INJ) >> 0U) #define MEM_ERR_ADDR_OFF 0xc8U #define FM_MEM_ERR_ADDR_ERR_ADDR (0xffU << 0U) #define FV_MEM_ERR_ADDR_ERR_ADDR(v) (((v) << 0U) & FM_MEM_ERR_ADDR_ERR_ADDR) #define GFV_MEM_ERR_ADDR_ERR_ADDR(v) (((v)&FM_MEM_ERR_ADDR_ERR_ADDR) >> 0U) #define GLB_LOCK_OFF 0x100U #define BM_GLB_LOCK_LOCK (0x01U << 0U) #define BANK_LOCK0_OFF 0x104U #define BM_BANK_LOCK0_HLOCK8 (0x01U << 31U) #define BM_BANK_LOCK0_OLOCK8 (0x01U << 30U) #define BM_BANK_LOCK0_RLOCK8 (0x01U << 29U) #define BM_BANK_LOCK0_PLOCK8 (0x01U << 28U) #define BM_BANK_LOCK0_HLOCK7 (0x01U << 27U) #define BM_BANK_LOCK0_OLOCK7 (0x01U << 26U) #define BM_BANK_LOCK0_RLOCK7 (0x01U << 25U) #define BM_BANK_LOCK0_PLOCK7 (0x01U << 24U) #define BM_BANK_LOCK0_HLOCK6 (0x01U << 23U) #define BM_BANK_LOCK0_OLOCK6 (0x01U << 22U) #define BM_BANK_LOCK0_RLOCK6 (0x01U << 21U) #define BM_BANK_LOCK0_PLOCK6 (0x01U << 20U) #define BM_BANK_LOCK0_HLOCK5 (0x01U << 19U) #define BM_BANK_LOCK0_OLOCK5 (0x01U << 18U) #define BM_BANK_LOCK0_RLOCK5 (0x01U << 17U) #define BM_BANK_LOCK0_PLOCK5 (0x01U << 16U) #define BM_BANK_LOCK0_HLOCK4 (0x01U << 15U) #define BM_BANK_LOCK0_OLOCK4 (0x01U << 14U) #define BM_BANK_LOCK0_RLOCK4 (0x01U << 13U) #define BM_BANK_LOCK0_PLOCK4 (0x01U << 12U) #define BM_BANK_LOCK0_HLOCK3 (0x01U << 11U) #define BM_BANK_LOCK0_OLOCK3 (0x01U << 10U) #define BM_BANK_LOCK0_RLOCK3 (0x01U << 9U) #define BM_BANK_LOCK0_PLOCK3 (0x01U << 8U) #define BM_BANK_LOCK0_HLOCK2 (0x01U << 7U) #define BM_BANK_LOCK0_OLOCK2 (0x01U << 6U) #define BM_BANK_LOCK0_RLOCK2 (0x01U << 5U) #define BM_BANK_LOCK0_PLOCK2 (0x01U << 4U) #define BM_BANK_LOCK0_HLOCK1 (0x01U << 3U) #define BM_BANK_LOCK0_OLOCK1 (0x01U << 2U) #define BM_BANK_LOCK0_RLOCK1 (0x01U << 1U) #define BM_BANK_LOCK0_PLOCK1 (0x01U << 0U) #define BANK_LOCK1_OFF 0x108U #define BM_BANK_LOCK1_HLOCK16 (0x01U << 31U) #define BM_BANK_LOCK1_OLOCK16 (0x01U << 30U) #define BM_BANK_LOCK1_RLOCK16 (0x01U << 29U) #define BM_BANK_LOCK1_PLOCK16 (0x01U << 28U) #define BM_BANK_LOCK1_HLOCK15 (0x01U << 27U) #define BM_BANK_LOCK1_OLOCK15 (0x01U << 26U) #define BM_BANK_LOCK1_RLOCK15 (0x01U << 25U) #define BM_BANK_LOCK1_PLOCK15 (0x01U << 24U) #define BM_BANK_LOCK1_HLOCK14 (0x01U << 23U) #define BM_BANK_LOCK1_OLOCK14 (0x01U << 22U) #define BM_BANK_LOCK1_RLOCK14 (0x01U << 21U) #define BM_BANK_LOCK1_PLOCK14 (0x01U << 20U) #define BM_BANK_LOCK1_HLOCK13 (0x01U << 19U) #define BM_BANK_LOCK1_OLOCK13 (0x01U << 18U) #define BM_BANK_LOCK1_RLOCK13 (0x01U << 17U) #define BM_BANK_LOCK1_PLOCK13 (0x01U << 16U) #define BM_BANK_LOCK1_HLOCK12 (0x01U << 15U) #define BM_BANK_LOCK1_OLOCK12 (0x01U << 14U) #define BM_BANK_LOCK1_RLOCK12 (0x01U << 13U) #define BM_BANK_LOCK1_PLOCK12 (0x01U << 12U) #define BM_BANK_LOCK1_HLOCK11 (0x01U << 11U) #define BM_BANK_LOCK1_OLOCK11 (0x01U << 10U) #define BM_BANK_LOCK1_RLOCK11 (0x01U << 9U) #define BM_BANK_LOCK1_PLOCK11 (0x01U << 8U) #define BM_BANK_LOCK1_HLOCK10 (0x01U << 7U) #define BM_BANK_LOCK1_OLOCK10 (0x01U << 6U) #define BM_BANK_LOCK1_RLOCK10 (0x01U << 5U) #define BM_BANK_LOCK1_PLOCK10 (0x01U << 4U) #define BM_BANK_LOCK1_HLOCK9 (0x01U << 3U) #define BM_BANK_LOCK1_OLOCK9 (0x01U << 2U) #define BM_BANK_LOCK1_RLOCK9 (0x01U << 1U) #define BM_BANK_LOCK1_PLOCK9 (0x01U << 0U) #define BANK_LOCK2_OFF 0x10cU #define BM_BANK_LOCK2_HLOCK24 (0x01U << 31U) #define BM_BANK_LOCK2_OLOCK24 (0x01U << 30U) #define BM_BANK_LOCK2_RLOCK24 (0x01U << 29U) #define BM_BANK_LOCK2_PLOCK24 (0x01U << 28U) #define BM_BANK_LOCK2_HLOCK23 (0x01U << 27U) #define BM_BANK_LOCK2_OLOCK23 (0x01U << 26U) #define BM_BANK_LOCK2_RLOCK23 (0x01U << 25U) #define BM_BANK_LOCK2_PLOCK23 (0x01U << 24U) #define BM_BANK_LOCK2_HLOCK22 (0x01U << 23U) #define BM_BANK_LOCK2_OLOCK22 (0x01U << 22U) #define BM_BANK_LOCK2_RLOCK22 (0x01U << 21U) #define BM_BANK_LOCK2_PLOCK22 (0x01U << 20U) #define BM_BANK_LOCK2_HLOCK21 (0x01U << 19U) #define BM_BANK_LOCK2_OLOCK21 (0x01U << 18U) #define BM_BANK_LOCK2_RLOCK21 (0x01U << 17U) #define BM_BANK_LOCK2_PLOCK21 (0x01U << 16U) #define BM_BANK_LOCK2_HLOCK20 (0x01U << 15U) #define BM_BANK_LOCK2_OLOCK20 (0x01U << 14U) #define BM_BANK_LOCK2_RLOCK20 (0x01U << 13U) #define BM_BANK_LOCK2_PLOCK20 (0x01U << 12U) #define BM_BANK_LOCK2_HLOCK19 (0x01U << 11U) #define BM_BANK_LOCK2_OLOCK19 (0x01U << 10U) #define BM_BANK_LOCK2_RLOCK19 (0x01U << 9U) #define BM_BANK_LOCK2_PLOCK19 (0x01U << 8U) #define BM_BANK_LOCK2_HLOCK18 (0x01U << 7U) #define BM_BANK_LOCK2_OLOCK18 (0x01U << 6U) #define BM_BANK_LOCK2_RLOCK18 (0x01U << 5U) #define BM_BANK_LOCK2_PLOCK18 (0x01U << 4U) #define BM_BANK_LOCK2_HLOCK17 (0x01U << 3U) #define BM_BANK_LOCK2_OLOCK17 (0x01U << 2U) #define BM_BANK_LOCK2_RLOCK17 (0x01U << 1U) #define BM_BANK_LOCK2_PLOCK17 (0x01U << 0U) #define BANK_LOCK3_OFF 0x110U #define BM_BANK_LOCK3_HLOCK32 (0x01U << 31U) #define BM_BANK_LOCK3_OLOCK32 (0x01U << 30U) #define BM_BANK_LOCK3_RLOCK32 (0x01U << 29U) #define BM_BANK_LOCK3_PLOCK32 (0x01U << 28U) #define BM_BANK_LOCK3_HLOCK31 (0x01U << 27U) #define BM_BANK_LOCK3_OLOCK31 (0x01U << 26U) #define BM_BANK_LOCK3_RLOCK31 (0x01U << 25U) #define BM_BANK_LOCK3_PLOCK31 (0x01U << 24U) #define BM_BANK_LOCK3_HLOCK30 (0x01U << 23U) #define BM_BANK_LOCK3_OLOCK30 (0x01U << 22U) #define BM_BANK_LOCK3_RLOCK30 (0x01U << 21U) #define BM_BANK_LOCK3_PLOCK30 (0x01U << 20U) #define BM_BANK_LOCK3_HLOCK29 (0x01U << 19U) #define BM_BANK_LOCK3_OLOCK29 (0x01U << 18U) #define BM_BANK_LOCK3_RLOCK29 (0x01U << 17U) #define BM_BANK_LOCK3_PLOCK29 (0x01U << 16U) #define BM_BANK_LOCK3_HLOCK28 (0x01U << 15U) #define BM_BANK_LOCK3_OLOCK28 (0x01U << 14U) #define BM_BANK_LOCK3_RLOCK28 (0x01U << 13U) #define BM_BANK_LOCK3_PLOCK28 (0x01U << 12U) #define BM_BANK_LOCK3_HLOCK27 (0x01U << 11U) #define BM_BANK_LOCK3_OLOCK27 (0x01U << 10U) #define BM_BANK_LOCK3_RLOCK27 (0x01U << 9U) #define BM_BANK_LOCK3_PLOCK27 (0x01U << 8U) #define BM_BANK_LOCK3_HLOCK26 (0x01U << 7U) #define BM_BANK_LOCK3_OLOCK26 (0x01U << 6U) #define BM_BANK_LOCK3_RLOCK26 (0x01U << 5U) #define BM_BANK_LOCK3_PLOCK26 (0x01U << 4U) #define BM_BANK_LOCK3_HLOCK25 (0x01U << 3U) #define BM_BANK_LOCK3_OLOCK25 (0x01U << 2U) #define BM_BANK_LOCK3_RLOCK25 (0x01U << 1U) #define BM_BANK_LOCK3_PLOCK25 (0x01U << 0U) #define SW_STICKY_OFF 0x140U #define BM_SW_STICKY_BIT31 (0x01U << 31U) #define BM_SW_STICKY_BIT30 (0x01U << 30U) #define BM_SW_STICKY_BIT29 (0x01U << 29U) #define BM_SW_STICKY_BIT28 (0x01U << 28U) #define BM_SW_STICKY_BIT27 (0x01U << 27U) #define BM_SW_STICKY_BIT26 (0x01U << 26U) #define BM_SW_STICKY_BIT25 (0x01U << 25U) #define BM_SW_STICKY_BIT24 (0x01U << 24U) #define BM_SW_STICKY_BIT23 (0x01U << 23U) #define BM_SW_STICKY_BIT22 (0x01U << 22U) #define BM_SW_STICKY_BIT21 (0x01U << 21U) #define BM_SW_STICKY_BIT20 (0x01U << 20U) #define BM_SW_STICKY_BIT19 (0x01U << 19U) #define BM_SW_STICKY_BIT18 (0x01U << 18U) #define BM_SW_STICKY_BIT17 (0x01U << 17U) #define BM_SW_STICKY_BIT16 (0x01U << 16U) #define BM_SW_STICKY_BIT15 (0x01U << 15U) #define BM_SW_STICKY_BIT14 (0x01U << 14U) #define BM_SW_STICKY_BIT13 (0x01U << 13U) #define BM_SW_STICKY_BIT12 (0x01U << 12U) #define BM_SW_STICKY_BIT11 (0x01U << 11U) #define BM_SW_STICKY_BIT10 (0x01U << 10U) #define BM_SW_STICKY_BIT9 (0x01U << 9U) #define BM_SW_STICKY_BIT8 (0x01U << 8U) #define BM_SW_STICKY_BIT7 (0x01U << 7U) #define BM_SW_STICKY_BIT6 (0x01U << 6U) #define BM_SW_STICKY_BIT5 (0x01U << 5U) #define BM_SW_STICKY_BIT4 (0x01U << 4U) #define BM_SW_STICKY_BIT3 (0x01U << 3U) #define BM_SW_STICKY_BIT2 (0x01U << 2U) #define BM_SW_STICKY_BIT1 (0x01U << 1U) #define BM_SW_STICKY_BIT0 (0x01U << 0U) #define VIO0_CFG_OFF 0x200U #define BM_VIO0_CFG_LOCK (0x01U << 31U) #define FM_VIO0_CFG_VIO_POL (0x7fffU << 16U) #define FV_VIO0_CFG_VIO_POL(v) (((v) << 16U) & FM_VIO0_CFG_VIO_POL) #define GFV_VIO0_CFG_VIO_POL(v) (((v)&FM_VIO0_CFG_VIO_POL) >> 16U) #define FM_VIO0_CFG_VIO_EN (0xffffU << 0U) #define FV_VIO0_CFG_VIO_EN(v) (((v) << 0U) & FM_VIO0_CFG_VIO_EN) #define GFV_VIO0_CFG_VIO_EN(v) (((v)&FM_VIO0_CFG_VIO_EN) >> 0U) #define VIO1_CFG_OFF 0x204U #define BM_VIO1_CFG_LOCK (0x01U << 31U) #define FM_VIO1_CFG_VIO_POL (0x7fffU << 16U) #define FV_VIO1_CFG_VIO_POL(v) (((v) << 16U) & FM_VIO1_CFG_VIO_POL) #define GFV_VIO1_CFG_VIO_POL(v) (((v)&FM_VIO1_CFG_VIO_POL) >> 16U) #define FM_VIO1_CFG_VIO_EN (0xffffU << 0U) #define FV_VIO1_CFG_VIO_EN(v) (((v) << 0U) & FM_VIO1_CFG_VIO_EN) #define GFV_VIO1_CFG_VIO_EN(v) (((v)&FM_VIO1_CFG_VIO_EN) >> 0U) #define SW_TRIG_VIO_OFF 0x208U #define FM_SW_TRIG_VIO_SW_TRIG (0x3U << 0U) #define FV_SW_TRIG_VIO_SW_TRIG(v) (((v) << 0U) & FM_SW_TRIG_VIO_SW_TRIG) #define GFV_SW_TRIG_VIO_SW_TRIG(v) (((v)&FM_SW_TRIG_VIO_SW_TRIG) >> 0U) #define LOCK_FUSE_OFF(n) (0x1000U + 4U * (n)) #define FM_LOCK_FUSE_LOCK (0xffffffffU << 0U) #define FV_LOCK_FUSE_LOCK(v) (((v) << 0U) & FM_LOCK_FUSE_LOCK) #define GFV_LOCK_FUSE_LOCK(v) (((v)&FM_LOCK_FUSE_LOCK) >> 0U) #define SHA_REG0_OFF(n) (0x1010U + 4U * (n)) #define FM_SHA_REG0_DATA (0xffffffffU << 0U) #define FV_SHA_REG0_DATA(v) (((v) << 0U) & FM_SHA_REG0_DATA) #define GFV_SHA_REG0_DATA(v) (((v)&FM_SHA_REG0_DATA) >> 0U) #define SHA_MEM0_OFF(n) (0x1080U + 4U * (n)) #define FM_SHA_MEM0_DATA (0xffffffffU << 0U) #define FV_SHA_MEM0_DATA(v) (((v) << 0U) & FM_SHA_MEM0_DATA) #define GFV_SHA_MEM0_DATA(v) (((v)&FM_SHA_MEM0_DATA) >> 0U) #define SHA_REG1_OFF(n) (0x1120U + 4U * (n)) #define FM_SHA_REG1_DATA (0xffffffffU << 0U) #define FV_SHA_REG1_DATA(v) (((v) << 0U) & FM_SHA_REG1_DATA) #define GFV_SHA_REG1_DATA(v) (((v)&FM_SHA_REG1_DATA) >> 0U) #define SHA_MEM1_OFF(n) (0x1140U + 4U * (n)) #define FM_SHA_MEM1_DATA (0xffffffffU << 0U) #define FV_SHA_MEM1_DATA(v) (((v) << 0U) & FM_SHA_MEM1_DATA) #define GFV_SHA_MEM1_DATA(v) (((v)&FM_SHA_MEM1_DATA) >> 0U) #define SHA_REG2_OFF(n) (0x11a0U + 4U * (n)) #define FM_SHA_REG2_DATA (0xffffffffU << 0U) #define FV_SHA_REG2_DATA(v) (((v) << 0U) & FM_SHA_REG2_DATA) #define GFV_SHA_REG2_DATA(v) (((v)&FM_SHA_REG2_DATA) >> 0U) #define SHA_MEM2_OFF(n) (0x11c0U + 4U * (n)) #define FM_SHA_MEM2_DATA (0xffffffffU << 0U) #define FV_SHA_MEM2_DATA(v) (((v) << 0U) & FM_SHA_MEM2_DATA) #define GFV_SHA_MEM2_DATA(v) (((v)&FM_SHA_MEM2_DATA) >> 0U) #define SHA_REG3_OFF(n) (0x1280U + 4U * (n)) #define FM_SHA_REG3_DATA (0xffffffffU << 0U) #define FV_SHA_REG3_DATA(v) (((v) << 0U) & FM_SHA_REG3_DATA) #define GFV_SHA_REG3_DATA(v) (((v)&FM_SHA_REG3_DATA) >> 0U) #define SHA_MEM3_OFF(n) (0x12a0U + 4U * (n)) #define FM_SHA_MEM3_DATA (0xffffffffU << 0U) #define FV_SHA_MEM3_DATA(v) (((v) << 0U) & FM_SHA_MEM3_DATA) #define GFV_SHA_MEM3_DATA(v) (((v)&FM_SHA_MEM3_DATA) >> 0U) #define SHA_REG4_OFF(n) (0x12c0U + 4U * (n)) #define FM_SHA_REG4_DATA (0xffffffffU << 0U) #define FV_SHA_REG4_DATA(v) (((v) << 0U) & FM_SHA_REG4_DATA) #define GFV_SHA_REG4_DATA(v) (((v)&FM_SHA_REG4_DATA) >> 0U) #define SHA_MEM4_OFF(n) (0x12d0U + 4U * (n)) #define FM_SHA_MEM4_DATA (0xffffffffU << 0U) #define FV_SHA_MEM4_DATA(v) (((v) << 0U) & FM_SHA_MEM4_DATA) #define GFV_SHA_MEM4_DATA(v) (((v)&FM_SHA_MEM4_DATA) >> 0U) #define SHA_REG5_OFF(n) (0x12e0U + 4U * (n)) #define FM_SHA_REG5_DATA (0xffffffffU << 0U) #define FV_SHA_REG5_DATA(v) (((v) << 0U) & FM_SHA_REG5_DATA) #define GFV_SHA_REG5_DATA(v) (((v)&FM_SHA_REG5_DATA) >> 0U) #define SHA_MEM5_OFF(n) (0x1300U + 4U * (n)) #define FM_SHA_MEM5_DATA (0xffffffffU << 0U) #define FV_SHA_MEM5_DATA(v) (((v) << 0U) & FM_SHA_MEM5_DATA) #define GFV_SHA_MEM5_DATA(v) (((v)&FM_SHA_MEM5_DATA) >> 0U) #endif /* __FUSE_CTRL_REG_H__ */