sdrv_uart.h

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#ifndef INCLUDE_DRV_SDRV_UART_H
#define INCLUDE_DRV_SDRV_UART_H
 
#include <compiler.h>
#include <sdrv_common.h>
#if CONFIG_UART_ENABLE_DMA
#include <sdrv_dma.h>
#endif
#include <types.h>
 
#ifndef ASSEMBLY
 
__BEGIN_CDECLS
 
/* The default count of timeout */
#define WaitForever 0xFFFFFFFFU
 
/* The operation's timeout period of register. */
#define SDRV_UART_OPERATION_TIMEOUT 0x500000U
 
/* Auto baud detect param */
#define UART_ABR_PATTERN 0U
#define SDRV_UART_ABR_PATTERN_CHAR 0x55U
#define SDRV_UART_MAX_ABR_NUM 8U
 
#if CONFIG_UART_ENABLE_DMA
/* Linklist config. */
#ifdef CONFIG_NUM_LINKLIST_ITEMS
/* User linklist length. */
#define NUM_LINKLIST_ITEMS CONFIG_NUM_LINKLIST_ITEMS
#else
/* Default linklist length. */
#define NUM_LINKLIST_ITEMS 8
#endif
/* Default mad length. */
#define DMA_BURST16_MAD_SIZE_MAX (4000U * 16U)
#define DMA_BURST1_MAD_SIZE_MAX (4000U * 1U)
#endif
 
#define SDRV_UART_INTR_TX_FWE 1U 
#define SDRV_UART_INTR_RX_FWF                                                  \
    (1U << 1) 
#define SDRV_UART_INTR_RX_FUDF                                                 \
    (1U << 3) 
#define SDRV_UART_INTR_TX_FOVF                                                 \
    (1U << 4) 
#define SDRV_UART_INTR_RX_FOVF                                                 \
    (1U << 5) 
#define SDRV_UART_INTR_PARITYERR                                               \
    (1U << 8) 
#define SDRV_UART_INTR_FRAMEERR                                                \
    (1U << 9) 
#define SDRV_UART_INTR_BAUDRATEERR                                             \
    (1U << 10) 
#define SDRV_UART_INTR_NOISERERR                                               \
    (1U << 11) 
#define SDRV_UART_INTR_RXBREAK                                                 \
    (1U << 13) 
#define SDRV_UART_INTR_RXIDLE                                                  \
    (1U << 14) 
#define SDRV_UART_INTR_TX_COMPLETED                                            \
    (1U << 17) 
#define SDRV_UART_INTR_ABRPASS                                                 \
    (1U << 18) 
#define SDRV_UART_INTR_ABRFAIL                                                 \
    (1U << 19) 
/* Uart receive error interrupt bitmask. */
#define SDRV_UART_INTR_RX_ERROR                                                \
    (SDRV_UART_INTR_RX_FOVF | SDRV_UART_INTR_RX_FUDF |                         \
     SDRV_UART_INTR_PARITYERR | SDRV_UART_INTR_FRAMEERR |                      \
     SDRV_UART_INTR_BAUDRATEERR | SDRV_UART_INTR_NOISERERR)
 
/* Uart transmit error interrupt bitmask. */
#define SDRV_UART_INTR_TX_ERROR (SDRV_UART_INTR_TX_FOVF)
 
/* Uart abr interrupt bitmask. */
#define SDRV_UART_INTR_ABR (SDRV_UART_INTR_ABRPASS | SDRV_UART_INTR_ABRFAIL)
 
/* Uart tx/rx fifo base offset. */
#define SDRV_UART_TX_FIFO_OFFSET 0x200U
#define SDRV_UART_RX_FIFO_OFFSET 0x300U
 
typedef union {
    struct {
        uint32_t MODEN : 1;
        uint32_t MODRST : 1;
        uint32_t CGC : 2;
        uint32_t OPMOD : 4;
        uint32_t QCHCTL : 1;
        uint32_t SELFTESTMODEEN : 1;
        uint32_t RESERVED : 22;
    };
    uint32_t v;
} MCR0_Type;
 
typedef union {
    struct {
        uint32_t PRESALE : 5;
        uint32_t TXEN : 1;
        uint32_t RXEN : 1;
        uint32_t BITORDER : 1;
        uint32_t DATABIT : 3;
        uint32_t STOPBIT : 2;
        uint32_t PARITYBIT : 3;
        uint32_t ADDRBIT : 1;
        uint32_t ABREN : 1;
        uint32_t ABRCTL0 : 4;
        uint32_t ABRCTL1 : 3;
        uint32_t FCM : 3;
        uint32_t TRANSFERMODE : 1;
        uint32_t RXMUTECTL : 3;
    };
    uint32_t v;
} PCR0_Type;
 
typedef union {
    struct {
        uint32_t BAUDRATE : 24;
        uint32_t SAMPLERATE : 2;
        uint32_t RXBREAKCTL : 3;
        uint32_t RXIDLECTL : 3;
    };
    uint32_t v;
} PCR1_Type;
 
typedef union {
    struct {
        uint32_t CHAR1 : 8;
        uint32_t CHAR2 : 8;
        uint32_t ADDRCHAR : 8;
        uint32_t ADDRMSK : 8;
    };
    uint32_t v;
} PCR2_Type;
 
typedef union {
    struct {
        uint32_t DE2RE : 8;
        uint32_t RE2DE : 8;
        uint32_t DEAT : 8;
        uint32_t DEDT : 8;
    };
    uint32_t v;
} PCR3_Type;
 
typedef union {
    struct {
        uint32_t TXADDR : 1;
        uint32_t TXBREAK : 1;
        uint32_t TXIDLE : 1;
        uint32_t RESERVED1 : 5;
        uint32_t TXBREAKCTL : 4;
        uint32_t TXIDLECTL : 4;
        uint32_t CHARMATCHCTL : 3;
        uint32_t BCLKOE : 1;
        uint32_t RXTOCTL : 3;
        uint32_t RESERVED2 : 9;
    };
    uint32_t v;
} PCR4_Type;
 
typedef union {
    struct {
        uint32_t TXCHARINT : 8;
        uint32_t RESERVED1 : 8;
        uint32_t SIRTXPUL : 8;
        uint32_t SIRRXPUL : 8;
    };
    uint32_t v;
} PCR5_Type;
 
typedef union {
    struct {
        uint32_t LINBREAKDEL : 3;
        uint32_t CHKSUMTYP : 1;
        uint32_t RESERVED : 28;
    };
    uint32_t v;
} PCR6_Type;
 
typedef union {
    struct {
        uint32_t PCMDTO : 5;
        uint32_t RESERVED : 27;
    };
    uint32_t v;
} PCR7_Type;
 
typedef union {
    struct {
        uint32_t TXSEL : 4;
        uint32_t TXMODE : 3;
        uint32_t TXPOL : 1;
        uint32_t RXSEL : 4;
        uint32_t RXMODE : 2;
        uint32_t RXEDGESEL : 2;
        uint32_t RXPOL : 1;
        uint32_t RXSYNCEN : 1;
        uint32_t RXFILTCTL : 3;
        uint32_t RESERVED : 11;
    };
    uint32_t v;
} PCR8_Type;
 
typedef union {
    struct {
        uint32_t TXSEL : 4;
        uint32_t TXMODE : 3;
        uint32_t TXPOL : 1;
        uint32_t RXSEL : 4;
        uint32_t RXMODE : 2;
        uint32_t RXEDGESEL : 2;
        uint32_t RXPOL : 1;
        uint32_t RXSYNCEN : 1;
        uint32_t RXFILTCTL : 3;
        uint32_t RESERVED : 11;
    };
    uint32_t v;
} PCR11_Type;
 
typedef union {
    struct {
        uint32_t WMLVL : 8;
        uint32_t RESERVED1 : 8;
        uint32_t CLR : 1;
        uint32_t RESERVED2 : 15;
    };
    uint32_t v;
} FCR_Type;
 
typedef union {
    struct {
        uint32_t FILLLVL : 8;
        uint32_t EMPTYLVL : 8;
        uint32_t FIFOSZ : 8;
        uint32_t EMPTY : 1;
        uint32_t FULL : 1;
        uint32_t RESERVED : 6;
    };
    uint32_t v;
} FSR_Type;
 
typedef union {
    struct {
        uint32_t TXFWE : 1;
        uint32_t RXFWF : 1;
        uint32_t TXFUDF : 1;
        uint32_t RXFUDF : 1;
        uint32_t TXFOVF : 1;
        uint32_t RXFOVF : 1;
        uint32_t TXFABT : 1;
        uint32_t RXFABT : 1;
        uint32_t PARITYERR : 1;
        uint32_t FRAMEERR : 1;
        uint32_t BAUDRATEERR : 1;
        uint32_t NOISEERR : 1;
        uint32_t RXTO : 1;
        uint32_t RXBREAK : 1;
        uint32_t RXIDLE : 1;
        uint32_t RXADDR : 1;
        uint32_t CHARMATCH : 1;
        uint32_t TC : 1;
        uint32_t ABRPASS : 1;
        uint32_t ABRFAIL : 1;
        uint32_t STARTERR : 1;
        uint32_t APBCMDDONE : 1;
        uint32_t APBCMDABORT : 1;
        uint32_t RXPIDPASS : 1;
        uint32_t RXPIDERR : 1;
        uint32_t RXCHKSUMPASS : 1;
        uint32_t RXCHKSUMERR : 1;
        uint32_t RESERVED : 1;
        uint32_t IO0EDGE : 1;
        uint32_t IO1EDGE : 1;
        uint32_t IO2EDGE : 1;
        uint32_t IO3EDGE : 1;
    };
    uint32_t v;
} INTR0_Type;
 
typedef union {
    struct {
        uint32_t FC_STATE : 4;
        uint32_t LIN_STATE : 4;
        uint32_t IORX_STATE : 4;
        uint32_t IOTX_STATE : 4;
        uint32_t RXBREAK_STATE : 2;
        uint32_t ABR_STATE : 3;
        uint32_t MUTEMODE : 1;
        uint32_t PCMD_STATE : 2;
        uint32_t LIN_CHECKSUM : 8;
    };
    uint32_t v;
} PSR0_Type;
 
typedef union {
    struct {
        uint32_t AUTOBAUDRATE : 24;
        uint32_t ABRCHAR : 4;
    };
    uint32_t v;
} PSR1_Type;
 
typedef union {
    struct {
        uint32_t DOORBELL : 16;
        uint32_t RESERVED : 16;
    };
    uint32_t v;
} CMDCSR0_Type;
 
typedef union {
    struct {
        uint32_t TXBYTENUM : 8;
        uint32_t RXBYTENUM : 8;
        uint32_t PID : 8;
        uint32_t RESERVED : 8;
    };
    uint32_t v;
} CMDCSR1_Type;
 
typedef union {
    struct {
        uint32_t TXDMAE : 1;
        uint32_t RXDMAE : 1;
        uint32_t TXDMARST : 1;
        uint32_t RXDMARST : 1;
        uint32_t RESERVED : 28;
    };
    uint32_t v;
} DMACR_Type;
 
typedef union {
    struct {
        uint32_t TXDMA_STATE : 2;
        uint32_t RXDMA_STATE : 2;
        uint32_t TXDMAREQ : 1;
        uint32_t RXDMAREQ : 1;
        uint32_t RESERVED : 26;
    };
    uint32_t v;
} DMASR_Type;
 
typedef struct sdrv_uart_regs {
    volatile MCR0_Type MCR0;          /* 0x0 */
    volatile uint32_t PRDATAINJ;      /* 0x4 */
    volatile uint32_t MCR2;           /* 0x8 */
    volatile uint32_t MCR3;           /* 0xC */
    volatile uint32_t MCR4;           /* 0x10 */
    volatile uint32_t RESERVED1;      /* 0x14 */
    volatile uint32_t MSR0;           /* 0x18 */
    volatile uint32_t MSR1;           /* 0x1C */
    volatile INTR0_Type INTR0;        /* 0x20 */
    volatile uint32_t RESERVED2[2];   /* 0x24 ~ 0x28 */
    volatile uint32_t INTR3;          /* 0x2C */
    volatile INTR0_Type INTEN0;       /* 0x30 */
    volatile uint32_t RESERVED3[2];   /* 0x34 ~ 0x38 */
    volatile uint32_t INTEN3;         /* 0x3C */
    volatile CMDCSR0_Type CMDCSR0;    /* 0x40 */
    volatile CMDCSR1_Type CMDCSR1;    /* 0x44 */
    volatile uint32_t RESERVED4[2];   /* 0x48 ~ 0x4C */
    volatile FCR_Type FCR0;           /* 0x50 */
    volatile FCR_Type FCR1;           /* 0x54 */
    volatile uint32_t RESERVED5[2];   /* 0x58 ~ 0x5C */
    volatile FSR_Type FSR0;           /* 0x60 */
    volatile FSR_Type FSR1;           /* 0x64 */
    volatile uint32_t RESERVED6[2];   /* 0x68 ~ 0x6C */
    volatile DMACR_Type DMACR;        /* 0x70 */
    volatile DMASR_Type DMASR;        /* 0x74 */
    volatile uint32_t RESERVED7[2];   /* 0x78 ~ 0x7C */
    volatile PCR0_Type PCR0;          /* 0x80 */
    volatile PCR1_Type PCR1;          /* 0x84 */
    volatile PCR2_Type PCR2;          /* 0x88 */
    volatile PCR3_Type PCR3;          /* 0x8C */
    volatile PCR4_Type PCR4;          /* 0x90 */
    volatile PCR5_Type PCR5;          /* 0x94 */
    volatile PCR6_Type PCR6;          /* 0x98 */
    volatile PCR7_Type PCR7;          /* 0x9C */
    volatile PCR8_Type PCR8;          /* 0xA0 */
    volatile uint32_t PCR9;           /* 0xA4 */
    volatile uint32_t PCR10;          /* 0xA8 */
    volatile PCR11_Type PCR11;        /* 0xAC */
    volatile uint32_t PCR12;          /* 0xB0 */
    volatile uint32_t PCR13;          /* 0xB4 */
    volatile uint32_t PCR14;          /* 0xB8 */
    volatile uint32_t PCR15;          /* 0xBC */
    volatile uint32_t RESERVED8[8];   /* 0xC0 ~ 0xDC */
    volatile uint32_t INT_STA;        /* 0xE0 */
    volatile uint32_t INT_STA_EN;     /* 0xE4 */
    volatile uint32_t INT_SIG_EN;     /* 0xE8 */
    volatile uint32_t RESERVED9[5];   /* 0xEC ~ 0xFC */
    volatile PSR0_Type PSR0;          /* 0x100 */
    volatile PSR1_Type PSR1;          /* 0x104 */
    volatile uint32_t PSR2;           /* 0x108 */
    volatile uint32_t PSR3;           /* 0x10C */
    volatile uint32_t PSR4;           /* 0x110 */
    volatile uint32_t PSR5;           /* 0x114 */
    volatile uint32_t PSR6;           /* 0x118 */
    volatile uint32_t PSR7;           /* 0x11C */
    volatile uint32_t RESERVED10[56]; /* 0x120 ~ 0x1FC */
    volatile uint32_t TXDR;           /* 0x200 */
    volatile uint32_t RESERVED11[63]; /* 0x204 ~ 0x2FC */
    volatile uint32_t RXDR;           /* 0x300 */
} sdrv_uart_regs_t;
 
enum sdrv_uart_callback_status {
    SDRV_UART_NoEvent = 0U,         
    SDRV_UART_TxCompleted = 1U,     
    SDRV_UART_RxFWF = 2U,           
    SDRV_UART_RxCompleted = 3U,     
    SDRV_UART_TxFifoOverFlow = 4U,  
    SDRV_UART_RxFifoOverFlow = 5U,  
    SDRV_UART_RxFifoUnderFlow = 6U, 
    SDRV_UART_FramingError = 7U,    
    SDRV_UART_ParityError = 8U,     
    SDRV_UART_NoiseError = 9U,      
    SDRV_UART_BaudrateError = 10U,  
    SDRV_UART_AbrPass = 11U,        
    SDRV_UART_AbrFail = 12U,        
    SDRV_UART_TxDmaDone = 13U,      
    SDRV_UART_TxDmaError = 14U,     
    SDRV_UART_RxDmaDone = 15U,      
    SDRV_UART_RxDmaError = 16U,     
    SDRV_UART_RxIdle = 17U,         
    SDRV_UART_RxBufferFull = 18U,   
};
 
typedef struct sdrv_uart sdrv_uart_t;
typedef enum sdrv_uart_callback_status sdrv_uart_callback_status_e;
 
typedef void (*uart_callback_t)(sdrv_uart_t *ctrl,
                                sdrv_uart_callback_status_e status,
                                void *userData);
 
typedef enum sdrv_uart_op_mode {
    SDRV_UART_SERIAL_MODE = 0U,
} sdrv_uart_op_mode_e;
 
typedef enum sdrv_uart_transfer_mode {
    SDRV_UART_FULL_DUPLEX = 0U,
} sdrv_uart_transfer_mode_e;
 
typedef enum sdrv_uart_dls {
    SDRV_UART_CHAR_8_BITS = 0U, 
    SDRV_UART_CHAR_7_BITS = 1U, 
    SDRV_UART_CHAR_6_BITS = 2U, 
    SDRV_UART_CHAR_5_BITS = 3U, 
} sdrv_uart_dls_e;
 
typedef enum sdrv_uart_stop {
    SDRV_UART_STOP_1_BIT = 0U,   
    SDRV_UART_STOP_1_5_BIT = 1U, 
    SDRV_UART_STOP_2_BIT = 2U,   
    SDRV_UART_STOP_0_5_BIT = 3U, 
} sdrv_uart_stop_e;
 
typedef enum sdrv_uart_parity {
    SDRV_UART_NO_PARITY = 0U,   
    SDRV_UART_EVEN_PARITY = 1U, 
    SDRV_UART_ODD_PARITY = 2U,  
} sdrv_uart_parity_e;
 
typedef enum sdrv_uart_fcm {
    SDRV_UART_NO_FC = 0U, 
} sdrv_uart_fcm_e;
 
typedef struct sdrv_uart_rs485_fcm {
    uint8_t deat_cycle;  
    uint8_t dedt_cycle;  
    uint8_t de2re_cycle; 
    uint8_t re2de_cycle; 
} sdrv_uart_rs485_fcm_t;
 
typedef struct sdrv_uart_fcm_config {
    sdrv_uart_fcm_e fcm_type; 
    sdrv_uart_rs485_fcm_t
        rs485_fcm; 
} sdrv_uart_fcm_config_t;
 
typedef enum sdrv_abr_max {
    SDRV_ABR_CHAR1 = 0U,  
    SDRV_ABR_CHAR2 = 1U,  
    SDRV_ABR_CHAR4 = 2U,  
    SDRV_ABR_CHAR8 = 3U,  
    SDRV_ABR_CHAR16 = 4U, 
    SDRV_ABR_CHAR32 = 5U, 
    SDRV_ABR_CHAR64 = 6U, 
    SDRV_ABR_CHAR128 = 7U, 
} sdrv_abr_max_e;
 
typedef enum sdrv_rxidle_ctl {
    SDRV_IDLE_DETECT_DISABLE = 0U, 
    SDRV_IDLE_DETECT_16CYCLE =
        1U, 
    SDRV_IDLE_DETECT_32CYCLE =
        2U, 
    SDRV_IDLE_DETECT_64CYCLE =
        3U, 
    SDRV_IDLE_DETECT_128CYCLE =
        4U, 
    SDRV_IDLE_DETECT_256CYCLE =
        5U, 
    SDRV_IDLE_DETECT_512CYCLE =
        6U, 
    SDRV_IDLE_DETECT_1024CYCLE =
        7U, 
} sdrv_rxidle_ctl_e;
 
typedef enum sdrv_uart_transfer_type {
    SDRV_TRANSFER_NO_MODE = 0U,        
    SDRV_TRANSFER_SYNC_MODE = 1U,      
    SDRV_TRANSFER_ASYNC_MODE = 2U,     
    SDRV_TRANSFER_REALTIME_MODE = 3U,  
    SDRV_TRANSFER_DMA_ASYNC_MODE = 4U, 
    SDRV_TRANSFER_DMA_REALTIME_MODE =
        5U, 
} sdrv_uart_transfer_type_e;
 
typedef enum sdrv_uart_transfer_status {
    Transfer_TxIdle = 0U,     
    Transfer_TxBusy = 1U,     
    Transfer_RxIdle = 2U,     
    Transfer_RxBusy = 3U,     
    Transfer_RxFail = 4U,     
    Transfer_TxFail = 5U,     
    Transfer_RxAbrBusy = 6U,  
    Transfer_RxAbrReady = 7U, 
    Transfer_RxAbrFail = 8U,  
} sdrv_uart_transfer_status_e;
 
typedef enum sdrv_uart_error_status {
    Status_Success = SDRV_STATUS_OK,      
    Status_Timeout = SDRV_STATUS_TIMEOUT, 
    Status_Busy = SDRV_STATUS_BUSY,       
    Status_Fail = SDRV_STATUS_FAIL,       
    Status_Invalid_Param =
        SDRV_STATUS_INVALID_PARAM, 
    Status_Abr_Not_Ready = SDRV_ERROR_STATUS(
        SDRV_STATUS_GROUP_UART, 0U), 
    Status_Rxfovf = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_UART,
                                      1U), 
    Status_Parity_Err = SDRV_ERROR_STATUS(
        SDRV_STATUS_GROUP_UART, 2U), 
    Status_Frame_Err = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_UART,
                                         3U), 
    Status_Baudrate_Err = SDRV_ERROR_STATUS(
        SDRV_STATUS_GROUP_UART, 4U), 
    Status_Noise_Err = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_UART,
                                         5U), 
    Status_dma_channel_config_Err =
        SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_UART,
                          6U), 
} sdrv_uart_error_status_e;
 
struct sdrv_uart {
    uint32_t base; 
    uint32_t irq;  
    uint32_t baud;     
    uint32_t clk_freq; 
    volatile sdrv_uart_transfer_type_e
        rxtransfer_type; 
    volatile sdrv_uart_transfer_type_e
        txtransfer_type; 
    const uint8_t *tx_ptr;       
    volatile uint32_t tx_remain; 
    uart_callback_t tx_async_cb; 
    void *tx_userparam; 
    uint8_t *rx_ptr;             
    volatile uint32_t rx_remain; 
    uart_callback_t rx_async_cb; 
    void *rx_userparam; 
    uart_callback_t callback; 
    void *userData;           
    volatile sdrv_uart_transfer_status_e tx_state; 
    volatile sdrv_uart_transfer_status_e rx_state; 
    volatile uint8_t abr_count; 
    volatile sdrv_uart_transfer_status_e
        abr_state; 
#if CONFIG_UART_ENABLE_DMA
    sdrv_dma_t *dma_instance;
    sdrv_dma_channel_t *rx_dmachannel; 
    sdrv_dma_channel_t *tx_dmachannel; 
    sdrv_rxidle_ctl_e
        rx_idle; 
    uint32_t bytes_rxcarried; /* The number of carried bytes by dma, only for
                               dma mode. */
    /* Uart rx dma linklist. */
    sdrv_dma_linklist_descriptor_t rx_dma_linklist[NUM_LINKLIST_ITEMS]
        __attribute__((__aligned__(CONFIG_ARCH_CACHE_LINE)));
    /* Uart tx dma linklist. */
    sdrv_dma_linklist_descriptor_t tx_dma_linklist[NUM_LINKLIST_ITEMS]
        __attribute__((__aligned__(CONFIG_ARCH_CACHE_LINE)));
 
#endif
};
 
typedef struct sdrv_uart_config {
    uint32_t base; 
    uint32_t irq;  
    uint32_t
        baud;          
    uint32_t clk_freq; 
    sdrv_uart_dls_e data_bits;  
    sdrv_uart_stop_e stop_bits; 
    sdrv_uart_parity_e parity;  
    sdrv_uart_fcm_config_t fcm; 
    uint8_t abr_en;             
    sdrv_abr_max_e
        match_num; 
    uint8_t txwmlvl; 
    /* SDRV_UART_INTR_RX_FWF interrupt will be setted when the number of data in
     * rx fifo more than rxwmlvl + 1.
     */
    uint8_t rxwmlvl; 
    bool dma_en; 
#if CONFIG_UART_ENABLE_DMA
    sdrv_rxidle_ctl_e
        rx_idle; 
#endif
} sdrv_uart_config_t;
 
sdrv_uart_error_status_e
sdrv_uart_controller_init(sdrv_uart_t *ctrl, const sdrv_uart_config_t *cfg,
                          uart_callback_t callback, void *userData);
 
sdrv_uart_error_status_e sdrv_uart_deinit(sdrv_uart_t *ctrl);
 
sdrv_uart_error_status_e sdrv_uart_set_baudrate(sdrv_uart_t *ctrl,
                                                uint32_t baud);
 
sdrv_uart_error_status_e sdrv_uart_abr_start(sdrv_uart_t *ctrl,
                                             sdrv_abr_max_e num);
 
uint32_t sdrv_uart_get_rxfifodata(sdrv_uart_t *ctrl, uint8_t *data,
                                  uint32_t maxlen);
 
sdrv_uart_error_status_e sdrv_uart_start_realtime_receive(sdrv_uart_t *ctrl);
 
sdrv_uart_error_status_e sdrv_uart_stop_realtime_receive(sdrv_uart_t *ctrl);
 
sdrv_uart_error_status_e sdrv_uart_sync_receive(sdrv_uart_t *ctrl,
                                                uint8_t *data, uint32_t size,
                                                uint32_t *received_bytes,
                                                uint32_t times);
 
bool sdrv_uart_txfifo_empty(sdrv_uart_t *ctrl);
 
sdrv_uart_error_status_e
sdrv_uart_sync_transmit(sdrv_uart_t *ctrl, const uint8_t *data, uint32_t size,
                        uint32_t *transmitted_bytes, uint32_t times);
 
sdrv_uart_error_status_e sdrv_uart_async_receive(sdrv_uart_t *ctrl,
                                                 uint8_t *data, uint32_t size,
                                                 uart_callback_t rx_cb,
                                                 void *rx_userparam);
 
sdrv_uart_error_status_e sdrv_uart_async_receive_abort(sdrv_uart_t *ctrl);
 
sdrv_uart_error_status_e
sdrv_uart_async_transmit(sdrv_uart_t *ctrl, const uint8_t *data, uint32_t size,
                         uart_callback_t tx_cb, void *tx_userparam);
 
sdrv_uart_error_status_e sdrv_uart_async_transmit_abort(sdrv_uart_t *ctrl);
 
#if CONFIG_UART_ENABLE_DMA
sdrv_uart_error_status_e
sdrv_uart_dma_receive(sdrv_uart_t *ctrl, uint8_t *data, uint32_t size,
                      uart_callback_t rx_cb, void *rx_userparam,
                      sdrv_dma_t *dma_ctrl, sdrv_dma_channel_t *dma_channel,
                      sdrv_dma_channel_id_e channel_id);
 
sdrv_uart_error_status_e sdrv_uart_dma_receive_abort(sdrv_uart_t *ctrl);
 
sdrv_uart_error_status_e
sdrv_uart_dma_transmit(sdrv_uart_t *ctrl, const uint8_t *data, uint32_t size,
                       uart_callback_t tx_cb, void *tx_userparam,
                       sdrv_dma_t *dma_ctrl, sdrv_dma_channel_t *dma_channel,
                       sdrv_dma_channel_id_e channel_id);
 
sdrv_uart_error_status_e sdrv_uart_dma_transmit_abort(sdrv_uart_t *ctrl);
 
sdrv_uart_error_status_e sdrv_uart_dma_receive_start(
    sdrv_uart_t *ctrl, uint8_t *data, uint32_t size, uart_callback_t rx_cb,
    void *rx_userparam, sdrv_dma_t *dma_ctrl, sdrv_dma_channel_t *dma_channel,
    sdrv_dma_channel_id_e channel_id);
 
uint32_t sdrv_uart_dma_bytes_received(sdrv_uart_t *ctrl);
 
#endif
 
sdrv_uart_error_status_e sdrv_uart_intr_ctrl(sdrv_uart_t *ctrl, uint32_t mask,
                                             bool value);
 
uint32_t sdrv_uart_intr_get(sdrv_uart_t *ctrl);
 
uint32_t sdrv_uart_intr_status_get(sdrv_uart_t *ctrl);
 
sdrv_uart_error_status_e sdrv_uart_intr_status_clear(sdrv_uart_t *ctrl,
                                                     uint32_t mask);
 
int sdrv_uart_irq_handler(uint32_t irq, void *ctrl);
 
__END_CDECLS
 
#endif
 
#endif